AD7538JRZ-REEL1 [ADI]
LC2MOS Microprocessor-Compatible 14-Bit DAC; LC2MOS微处理器兼容14位DAC
| 型号： | AD7538JRZ-REEL1 |
| 厂家： | 
ADI |
| 描述： | LC2MOS Microprocessor-Compatible 14-Bit DAC |
| 文件： | 总16页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
Microprocessor-Compatible 14-Bit DAC
AD7538
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
DD
All grades 14-bit monotonic over the full temperature range
Low cost, 14-bit upgrade for 12-bit systems
14-bit parallel load with double buffered inputs
Small 24-pin, 0.30” DIP and SOIC
23
AD7538
2
3
R
I
FB
14-BIT DAC
1
V
REF
OUT
Low output leakage (<20 nA) over the full temperature range
4
AGND
LDAC
APPLICATIONS
20
DAC REGISTER
Microprocessor-based control systems
Digital audio
Precision servo control
21
22
CS
INPUT
REGISTER
WR
14
Control and measurement in high temperature environments
5
24
6
19
V
DB13 TO DB0
DGND
SS
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7538 is a 14-bit monolithic CMOS digital-to-analog
converter (DAC) that uses laser trimmed thin-film resistors to
achieve excellent linearity.
1. Guaranteed Monotonicity.
The AD7538 is guaranteed monotonic to 14-bits over the
full temperature range for all grades.
2. Low Cost.
The DAC is loaded by a single 14-bit wide word using standard
chip select and memory write logic. Double buffering, which is
The AD7538, with its 14-bit dynamic range, affords a low
cost solution for 12-bit system upgrades.
3. Small Package Size.
The AD7538 is packaged in a small 24-pin, 0.3" DIP and a
24-pin SOIC.
4. Low Output Leakage.
By tying VSS (Pin 24) to a negative voltage, it is possible to
achieve a low output leakage current at high temperatures.
5. Wide Power Supply Tolerance.
LDAC
optional using
, allows simultaneous updates in a system
containing multiple AD7538s.
A novel low leakage configuration enables the AD7538 to
exhibit excellent output leakage current characteristics over
the specified temperature range.
The AD7538 is manufactured using the linear-compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL or CMOS logic level inputs.
The device operates on a +12 V to +15 V VDD, with a 5ꢀ
tolerance on this nominal figure. All specifications are
guaranteed over this range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD7538
TABLE OF CONTENTS
Features .............................................................................................. 1
Equivalent Circuit Analysis ...................................................... 10
Digital Section ............................................................................ 10
Unipolar Binary Operation (2-Quadrant Multiplication).... 10
Bipolar Operation (4-Quadrant Multiplication).................... 11
Low Leakage Configuration...................................................... 11
Programmable Gain Amplifier................................................. 12
Application Hints ........................................................................... 13
Output Offset.............................................................................. 13
General Ground Management.................................................. 13
Microprocessor Interfacing....................................................... 13
AD7538-to-8086 Interface........................................................ 13
AD7538-to-MC68000 Interface ............................................... 13
Digital Feedthrough................................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 4
Timing Characteristics ................................................................ 4
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
DAC Section...................................................................................... 9
Circuit Information........................................................................ 10
REVISION HISTORY
1/09—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 15
5/87—Rev. 0 to Rev. A
Rev. B | Page 2 of 16
AD7538
SPECIFICATIONS
VDD = 11.4 V to 15.75 V1, VREF = 10 V; VPIN3 = VPIN4 = 0 V, VSS = −300 mV; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A, J
Versions
B, K
Versions
Parameter2
ACCURACY
S Version
T Version
Unit
Test Conditions/Comments
Resolution
Relative Accuracy
14
±2
14
±1
14
±2
14
±1
Bits
LSB max
All grades guaranteed
monotonic
Differential Nonlinearity
Full-Scale Error
+25°C
TMIN to TMAX
Gain Temperature Coefficient3;
ΔGain/ΔTemperature
±1
±1
±1
±1
LSB max
Over temperature
Measured using internal RFB DAC
Registers loaded with all 1s
±4
±±
±2
±4
±5
±2
±4
±1ꢀ
±2
±4
±6
±2
LSB max
LSB max
ppm/°C typ
Output Leakage Current
IOUT (Pin 3)
25°C
TMIN to TMAX
TMIN to TMAX
±5
±1ꢀ
±25
±5
±1ꢀ
±25
±5
±2ꢀ
±15ꢀ
±5
±2ꢀ
±15ꢀ
nA max
nA max
nA max
All digital inputs ꢀ V
VSS = –3ꢀꢀ mV
VSS = ꢀ V
REFERENCE INPUT
Input Resistance (Pin 1)
3.5
1ꢀ
3.5
1ꢀ
3.5
1ꢀ
3.5
1ꢀ
kΩ min
kΩ max
Typical input resistance = 6 kΩ
DIGITAL INPUTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN (Input Current)
25°C
2.4
ꢀ.±
2.4
ꢀ.±
2.4
ꢀ.±
2.4
ꢀ.±
V min
V max
±1
±1ꢀ
7
±1
±1ꢀ
7
±1
±1ꢀ
7
±1
±1ꢀ
7
μA max
μA max
pF max
VIN = ꢀ V or VDD
TMIN to TMAX
CIN (Input Capacitance)3
POWER SUPPLY
VDD Range
11.4/15.75 11.4/15.75 11.4/15.75
−2ꢀꢀ/−5ꢀꢀ −2ꢀꢀ/−5ꢀꢀ −2ꢀꢀ/−5ꢀꢀ
11.4/15.75
V min/V max Specification guaranteed over
this range
VSS Range
IDD
−2ꢀꢀ/−5ꢀꢀ mV min/
mV max
4
Specification guaranteed over
this range
All digital inputs are VIL or VIH
All digital inputs are ꢀ V or VDD
4
5ꢀꢀ
4
5ꢀꢀ
4
5ꢀꢀ
mA max
μA max
5ꢀꢀ
1 Specifications are guaranteed for a VDD of 11.4 V to 15.75 V. At VDD = 5 V, the device is fully functional with degraded specifications.
2 Temperature range as follows: J, K Versions: ꢀ°C to +7ꢀ°C
A, B Versions: −25°C to +±5°C
S, T Versions: −55°C to +125°C
3 Sample tested to ensure compliance.
Rev. B | Page 3 of 16
AD7538
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not subject to test. VDD = 11.4 V to 15.75 V, VREF = 10 V, VPIN3 = VPIN4
0 V, VSS = 0 V or −300 mV, output amplifier is AD711 except where noted.
=
Table 2.
TA = 25°C
TA = TMIN, TMAX
Parameter
Unit
Test Conditions/Comments
Output Current Settling Time
1.5
μs max
To ꢀ.ꢀꢀ3% of full-scale range
IOUT load= 1ꢀꢀ Ω, CEXT = 13 pF DAC register alternately loaded
with all 1s and all ꢀs; typical value of settling time is ꢀ.± μs
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
2ꢀ
nV-sec typ
mV p-p typ
Measured with VREF = ꢀ V. IOUT load = 1ꢀꢀ Ω, CEXT = 13 pF; DAC
register alternately loaded with all 1s and all ꢀs
VREF = ±1ꢀ V, 1ꢀ kHz sine wave DAC
Register loaded with all ꢀs
3
5
Power Supply Rejection
ΔGain/ΔVDD
±ꢀ.ꢀ1
±ꢀ.ꢀ2
% per % max
ΔVDD = ±5%
Output Capacitance
COUT (Pin 3)
COUT (Pin 3)
26ꢀ
13ꢀ
26ꢀ
13ꢀ
pF max
pF max
DAC register loaded with all 1s
DAC register loaded with all ꢀs
Output Noise Voltage Density
(1ꢀ Hz to 1ꢀꢀ kHz)
15
nV√Hz typ
Measured between RFB and IOUT
TIMING CHARACTERISTICS
VDD = 11.4 V to 15.75 V, VREF = 10 V, VPIN3 = VPIN4 = 0 V, VSS = 0 V or −300 mV. All specifications TMIN to TMAX unless otherwise noted. See
Figure 2 for a timing diagram.
Table 3.
Limit at
TA = +25°C
Limit at TA = 0°C to +70°C
TA = −25°C to +85°C
Limit at
TA = −55°C to +125°C
Parameter1
Unit
Test Conditions/Comments
ꢀ
ꢀ
ꢀ
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR setup time
CS to WR hold time
LDAC pulse width
Write pulse width
Data setup time
t1
t2
t3
t4
t5
t6
ꢀ
ꢀ
ꢀ
17ꢀ
17ꢀ
14ꢀ
2ꢀ
2ꢀꢀ
2ꢀꢀ
16ꢀ
2ꢀ
24ꢀ
24ꢀ
1±ꢀ
3ꢀ
Data hold time
1 Temperature range as follows: J, K Versions: ꢀ°C to +7ꢀ°C
A, B Versions: −25°C to +±5°C
S, T Versions: −55°C to +125°C
Rev. B | Page 4 of 16
AD7538
TIMING DIAGRAM
t1
t2
5V
0V
CS
LDAC
WR
t3
5V
0V
t4
5V
0V
t6
t5
5V
0V
DATA
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURES FROM 10%
TO 90% OF 5V, tR
= tF = 20ns.
V
+ V
2
IH
IL
2. TIMING MEASUREMENT REFERENCE LEVEL IS
.
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH.
Figure 2. Timing Diagram
Rev. B | Page 5 of 16
AD7538
ABSOLUTE MAXIMUM RATINGS
TA = +25°C unless, otherwise stated.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD (Pin 23) to DGND
VSS (Pin 24) to AGND
VREF (Pin 1) to AGND
VRFB (Pin 2) to AGND
Digital Input Voltage (Pins 6 to 22)
to DGND
−ꢀ.3 V, +17 V
−15 V, +ꢀ.3 V
±25 V
±25 V
ESD CAUTION
−ꢀ.3 V, VDD +ꢀ.3 V
−ꢀ.3 V, VDD +ꢀ.3 V
−ꢀ.3 V, VDD +ꢀ.3 V
VPIN3 to DGND
AGND to DGND
Power Dissipation (Any Package)
To 75°C
1ꢀꢀꢀ mW
1ꢀ mW/°C
Derates Above 75°C
Operating Temperature Range
Commercial (J, K Versions)
Industrial (A, B Versions)
Extended (S, T Versions)
Storage Temperature
Lead Temperature (Soldering, 1ꢀ sec)
ꢀ°C to +7ꢀ°C
−25°C to +±5°C
−55°C to +125°C
−65°C to +15ꢀ°C
3ꢀꢀ°C
Rev. B | Page 6 of 16
AD7538
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
9
24
23
V
V
REF
SS
DD
R
FB
I
22 WR
OUT
AGND
21 CS
AD7538
TOP VIEW
(Not to Scale)
DGND
(MSB) DB13
DB12
20 LDAC
19 DB0 (LSB)
18 DB1
17 DB2
16 DB3
15 DB4
14 DB5
13 DB6
DB11
DB10
DB9 10
DB8 11
DB7 12
Figure 3. Pin Configuration
Table 5. Pin Function Description
Pin No. Mnemonic Description
Voltage Reference.
1
2
3
4
5
VREF
RFB
IOUT
AGND
DGND
Feedback Resistor. Used to close the loop around an external op amp.
Current Output Terminal.
Analog Ground
Digital Ground.
6 to 19 DB13 to DBꢀ
Data Inputs. Bit DB13 (MSB) to Bit DBꢀ (LSB).
Chip Select Input. Active low.
2ꢀ
21
22
LDAC
CS
Asynchronous Load DAC Input. Active low.
WR
Write Input. Active low.
CS
LDAC
WR
Operation
ꢀ
1
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
Load input register.
X1
Load DAC register from input register.
Input and DAC registers are transparent.
No operation.
ꢀ
X1
1
X1
No operation.
23
24
VDD
VSS
+12 V to +15 V Supply Input.
Bias pin for high temperature low leakage configuration. To implement low leakage system, the pin should be
at a negative voltage. See Figure 6 and Figure ± for recommended circuitry.
1 X = don’t care.
Rev. B | Page 7 of 16
AD7538
TERMINOLOGY
Digital-To-Analog Glitch Impulse
Relative Accuracy
The amount of charge injected from the digital inputs to the
analog output when the inputs change state is called digital-to-
analog glitch impulse. This is normally specified as the area of
the glitch in either pA-secs or nV-secs depending upon whether
the glitch is measured as a current or voltage. It is measured
with VREF = AGND.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in least significant bits or as a percentage of full-
scale reading.
Output Capacitance
This is the capacitance from IOUT to AGND.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
over the operating temperature range ensures monotonicity.
Output Leakage Current
Output leakage current is current which appears at IOUT with the
DAC register loaded to all 0s.
Gain Error
Multiplying Feedthrough Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after the offset error has been adjusted out and is
expressed in least significant bits. Gain error is adjustable to
zero with an external potentiometer.
This is the ac error due to capacitive feedthrough from the VREF
terminal to IOUT with the DAC register loaded to all zeros.
Rev. B | Page ± of 16
AD7538
DAC SECTION
Figure 4 shows a simplified circuit diagram for the AD7538
DAC section. The three MSBs of the 14-bit data word are
decoded to drive the seven switches (A to G). The 11 LSBs
of the data word consist of an R-2R ladder operated in a
current steering configuration.
Switch A to Switch G steer equally weighted currents between
I
OUT and AGND.
Because the input resistance at VREF is constant, it may be driven
by a voltage source or a current source of positive or negative
polarity.
The R-2R ladder current is ⅛ of the total reference input
current. ⅞ current flows in the parallel ladder structure.
R
R
R
V
REF
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
R/4
R
FB
G
F
E
D
C
B
A
S10
S9
S0
I
OUT
AGND
Figure 4. Simplified Circuit Diagram for the AD7538 DAC Section
Rev. B | Page 9 of 16
AD7538
CIRCUIT INFORMATION
R1
20Ω
V
DD
R2
10Ω
EQUIVALENT CIRCUIT ANALYSIS
V
IN
Figure 5 shows an equivalent circuit for the analog section
of the AD7538 DAC. The current source ILEAKAGE is composed
of surface and junction leakages. The RO resistor denotes the
equivalent output resistance of the DAC, which varies with
input code. COUT is the capacitance due to the current steering
switches and varies from about 90 pF to 180 pF (typical values)
depending upon the digital input. g(VREF, N) is the Thevenin
equivalent voltage generator due to the reference input voltage,
1
23
2
C1
33pF
V
V
R
FB
REF
DD
20
21
22
LDAC
LDAC
I
3
OUT
AD7538
CS
CS
A1
AD711
4
AGND
V
WR
WR
O
V
DB13 TO DB0 DGND
SS
24
C2
4.7µF
5
6
19
ANALOG
GND
+
VREF, and the transfer function of the DAC ladder, N.
R3
1kΩ
DIGITAL
GND
INPUT DATA
R/4
R4
47kΩ
R
FB
R
O
–15V
I
OUT
Figure 6. Unipolar Binary Operation
I
C
OUT
g (V
REF
, N)
LEAKAGE
AGND
Table 6. Unipolar Binary Code Table
Figure 5. AD7538 Equivalent Analog Output Circuit
Binary Number In
DAC Register
DIGITAL SECTION
MSB
LSB
Analog Output, VOUT
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close as possible to 0 V and 5 V logic levels.
11 1111 1111 1111
10 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
−VIN(16,383/16,384)
−VIN(8192/16,384) = −½VIN
−VIN(1/16,384)
0 V
UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
For zero offset adjustment, the DAC register is loaded with
all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V.
Adjusting VOUT to 0 V is not necessary in many applications,
but it is recommended that VOS be no greater than (25 × 10−6)
(VREF) to maintain specified DAC accuracy (see the Application
Hints section).
Figure 6 shows the circuit diagram for unipolar binary
operation. With an ac input, the circuit performs 2-quadrant
multiplication. The code table for Figure 6 is given in Table 6.
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
Full-scale trimming is accomplished by loading the DAC
register with all 1s and adjusting R1 so that VOUTA = −VIN
(16,383/16,384). For high temperature operation, resistors
and potentiometers should have a low temperature coefficient.
In many applications, because of the excellent gain TC and
gain error specifications of the AD7538, gain error trimming is
not necessary. In fixed reference applications, full scale can also
be adjusted by omitting R1 and R2 and trimming the reference
voltage magnitude.
Rev. B | Page 10 of 16
AD7538
BIPOLAR OPERATION (4-QUADRANT
MULTIPLICATION)
Table 7. Bipolar Code Table for the Offset Binary Circuit
of Figure 8
The recommended circuit diagram for bipolar operation is
shown in Figure 8. Offset binary coding is used. The code table
for Figure 8 is given in Table 7.
Binary Number In
DAC Register
MSB
LSB
Analog Output VOUT
+VIN(8191/8192)
+VIN(1/8192)
0 V
−VIN(1/8192)
−VIN(8191/8192)
11 1111 1111 1111
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
With the DAC loaded to 10 0000 0000 0000, adjust R1 for VO =
0 V. Alternatively, one can omit R1 and R2 and adjust the ratio
of R5 and R6 for VO = 0 V. Full-scale trimming can be accom-
plished by adjusting the amplitude of VIN or by varying the
value of R7.
The values given for R1, R2 are the minimum necessary to
calibrate the system for Resistors R5, R6, R7 ratio matched to
0.1%. System linearity error is independent of resistor ratio
matching and is affected by DAC linearity error only.
V
= 15V
= 10V
DD
60
50
40
30
20
10
0
V
REF
When operating over a wide temperature range, it is important
that the resistors be of the same type so that their temperature
coefficients match.
V
= 0V
SS
LOW LEAKAGE CONFIGURATION
V
= –0.3V
SS
For CMOS multiplying DAC, as the device is operated at higher
temperatures, the output leakage current increases. For a 14-bit
resolution system, this can be a significant source of error. The
AD7538 features a leakage reduction configuration to keep the
leakage current low over an extended temperature range. One
may operate the device with or without this configuration. If VSS
(Pin 24) is tied to AGND then the DAC exhibits normal output
leakage currents at high temperatures. To use the low leakage
facility, VSS should be tied to a voltage of approximately −0.3 V
as in Figure 6 and Figure 8. A simple resistor divider (R3, R4)
produces approximately −300 mV from −15 V. The C2
capacitor in parallel with R3 is an integral part of the low
leakage configuration and must be 4.7 μF or greater. Figure 7
is a plot of leakage current vs. temperature for both conditions.
It clearly shows the improvement gained by using the low
leakage configuration.
30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
Figure 7. Graph of Typical Leakage Current vs. Temperature for AD7538
V
IN
V
R2
22Ω
DD
R6
20kΩ
R1
50Ω
1
23
2
C1
33pF
R7
20kΩ
V
V
R
FB
REF
DD
20
21
22
LDAC
LDAC
R5
10kΩ
I
3
OUT
AD7538
CS
CS
A1
4
AGND
A2
AD711
WR
WR
AD711
V
O
R8
5kΩ, 10%
V
DB13 TO DB0 DGND
SS
24
C2
4.7µF
5
6
19
+
R3
1kΩ
ANALOG
GND
DIGITAL
GND
INPUT DATA
R4
47kΩ
–15V
Figure 8. Bipolar Operation
Rev. B | Page 11 of 16
AD7538
Substituting this expression into Equation 1 and assuming
zero gain error for the DAC (RIN = RFB), the transfer function
simplifies to
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 9 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
2n
N
VOUT
VIN
= −
(3)
DIGITAL
INPUT
The ratio N/2n is commonly represented by the term, D, and, as
such, is the fractional representation of the digital input word.
N
V
DD
− 2n −1
I
OUT
VOUT
VIN
= −
=
(4)
AD7538
N
D
GND
V
REF
A
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. The all 0s code is never applied. This avoids an open-loop
condition thereby saturating the amplifier. With the all 0s code
excluded there remains (2n – 1) possible input codes allowing a
choice of (2n – 1) output levels. In decibels the dynamic range is
V
DD
R
FB
V
IN
V
OUT
A
V
SS
NOTES
1. RESISTOR R IS ACTUALLY
INCLUDED ON THE DICE.
FB
Figure 9. Programmable Gain Amplifier (PGA)
VOUT
VIN
20 log10
= 20 log10
2n −1
= 84 dB
)
The transfer function of Figure 9 is:
REQ
RFB
VOUT
VIN
Gain =
= −
(1)
(2)
R
V
EQ is the equivalent transfer impedance of the DAC from the
REF pin to the IOUT pin and can be expressed as
2n RIN
REQ
where:
=
N
n is the resolution of the DAC.
N is the DAC input code in decimal.
RIN is the constant input impedance of the DAC (RIN = RLAD).
Rev. B | Page 12 of 16
AD7538
APPLICATION HINTS
In a multiple DAC system, the double buffering of the AD7538
allows the user to simultaneously update all DACs. In Figure 11,
a 14-bit word is loaded to the input registers of each of the DACs
in sequence. Then, with one instruction to the appropriate
OUTPUT OFFSET
CMOS DACs in circuits such as Figure 6 and Figure 8 exhibit
a code dependent output resistance, which in turn can cause a
code dependent error voltage at the output of the amplifier.
The maximum amplitude of this error, which adds to the DAC
nonlinearity, depends on VOS, where VOS is the amplifier input
offset voltage. To maintain specified accuracy with VREF at 10 V,
it is recommended that VOS be no greater than 0.25 mV, or (25 ×
10−6) (VREF), over the temperature range of operation. The AD711 is
a suitable op amp. The op amp has a wide bandwidth and high
slew rate and is recommended for ac and other applications
requiring fast settling.
LDAC
address, CS4 (that is,
DACs simultaneously.
) is brought low, updating all the
ADDRESS BUS
16-BIT
LATCH
ADDRESS
DECODE
CS1
ALE
CS
AD75381
CS4 CS3 CS2
8096
LDAC
WR
WR
DB0 TO DB13
AD0 TO AD15
DATA BUS
GENERAL GROUND MANAGEMENT
Because the AD7538 is specified for high accuracy, it is impor-
tant to use a proper grounding technique. AC or transient
voltages between AGND and DGND can cause noise injection
into the analog output. The simplest method of ensuring that
voltages at AGND and DGND are equal is to tie AGND and
DGND together at the AD7538. In more complex systems
where the AGND and DGND intertie on the backplane, it is
recommended that two diodes be connected in inverse
parallel between the AD7538 AGND and DGND pins
(1N914 or equivalent).
CS
AD75381
LDAC
WR
DB0 TO DB13
CS
AD75381
MICROPROCESSOR INTERFACING
LDAC
WR
The AD7538 is designed for easy interfacing to 16-bit micro-
processors and can be treated as a memory mapped peripheral.
This reduces the amount of external logic needed for interfacing
to a minimal.
DB0 TO DB13
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 11. AD7538-to-8086 Interface: Multiple DAC System
AD7538-TO-8086 INTERFACE
AD7538-TO-MC68000 INTERFACE
Figure 10 shows the 8086 processor interface to a single device.
LDAC
In this setup, the double buffering feature (using
) of the
Figure 12 shows the MC68000 processor interface to a single
device. In this setup, the double buffering feature of the DAC
is not used and the appropriate data is written into the DAC in
one MOVE instruction.
DAC is not used. The 14-bit word is written to the DAC in one
MOVE instruction and the analog output responds
immediately.
ADDRESS BUS
A1 TO A23
MC68000
AS
ADDRESS BUS
16-BIT
LATCH
ADDRESS
DECODE
ALE
CS
ADDRESS
DECODE
CS
LDAC
8096
AD75381
WR
LDAC
DTACK
AD75381
WR
AD13
AD0
WR
R/W
DB0 TO DB13
AD0 TO AD15
DATA BUS
DB0 TO DB13
D0 TO D15
DATA BUS
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 10. AD7538-to-8086 Interface Circuit
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 12. AD7538-to-MC68000 Interface
Rev. B | Page 13 of 16
AD7538
DIGITAL FEEDTHROUGH
ADDRESS
DECODE
A0 TO A15
MICRO-
PROCESSOR
SYSTEM
AD75381
The digital inputs to the AD7538 are directly connected to the
microprocessor bus in the preceding interface configurations.
These inputs are constantly changing even when the device is
not selected. The high frequency logic activity on the bus can
feed through the DAC package capacitance to show up as noise
on the analog output. To minimize this digital feedthrough
isolate the DAC from the noise source. Figure 13 shows an
interface circuit, which uses this technique. All data inputs are
CS
LDAC
WR
EN
WR
16-BIT
LATCH
DB0 TO DB13
D0 TO D15
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 13. AD7538 Interface Circuit Using Latches to Minimize Digital
Feedthrough
CS
latched from the bus by the
signal. One may also use other
means, such as peripheral interface devices, to reduce the digital
feedthrough.
Rev. B | Page 14 of 16
AD7538
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
1
13
12
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 14. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
MAX
0.005 (0.13)
MIN
0.310 (7.87)
0.220 (5.59)
24
13
12
1
PIN 1
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.200 (5.08)
1.280 (32.51) MAX
MAX
0.290 (7.37)
0.150 (3.81)
MIN
0.015 (0.38)
0.008 (0.20)
15°
0°
0.200 (5.08)
0.125 (3.18)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 15. 24-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-24-1)
Dimensions shown in inches and (millimeters)
Rev. B | Page 15 of 16
AD7538
15.60 (0.6142)
15.20 (0.5984)
24
1
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
BSC
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD753±JN
Temperature Range
ꢀ°C to +7ꢀ°C
Relative Accuracy
±2 LSB
±2 LSB
±1 LSB
±1 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
Full-Scale Error
±± LSB
±± LSB
±5 LSB
±5 LSB
±± LSB
±± LSB
±± LSB
±± LSB
±5 LSB
±5 LSB
±5 LSB
±5 LSB
±± LSB
±5 LSB
±1ꢀ LSB
±6 LSB
Package Description
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead CERDIP
24-Lead CERDIP
24-Lead CERDIP
24-Lead CERDIP
Package Option
N-24-1
N-24-1
N-24-1
N-24-1
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
Q-24-1
Q-24-1
Q-24-1
Q-24-1
AD753±JNZ1
ꢀ°C to +7ꢀ°C
AD753±KN
ꢀ°C to +7ꢀ°C
AD753±KNZ1
AD753±JR
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
AD753±JR-REEL
AD753±JRZ1
AD753±JRZ-REEL1
AD753±KR
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
AD753±KR-REEL
AD753±KRZ1
AD753±KRZ-REEL1
AD753±AQ
AD753±BQ
AD753±SQ
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
ꢀ°C to +7ꢀ°C
−25°C to +±5°C
−25°C to +±5°C
−55°C to +125°C
−55°C to +125°C
AD753±TQ
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01139-0-1/09(B)
Rev. B | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明