AD7568BP-REEL [ADI]
LC2MOS Octal 12-Bit DAC; LC2MOS八通道12位DAC
| 型号： | AD7568BP-REEL |
| 厂家： | 
ADI |
| 描述： | LC2MOS Octal 12-Bit DAC |
| 文件： | 总14页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
Octal 12-Bit DAC
a
AD7568
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
V
V
D
V
C
V
B
V
A
R
A
FB
AGND DGND
DD
REF
REF
REF
REF
AD7568
I
I
A
A
INPUT
DAC A
LATCH
OUT1
OUT2
12
12
12
DAC A
DAC B
DAC C
LATCH A
Low Pow er: 1 m W
R
B
FB
Versatile Serial Interface
Sim ultaneous Update Capability
Reset Function
I
I
B
B
DAC B
LATCH
OUT1
OUT2
INPUT
12
12
12
12
12
12
LATCH B
R
C
FB
44-Pin PQFP and PLCC
I
I
C
OUT1
INPUT
DAC C
LATCH
12
12
12
12
12
LATCH C
C
OUT2
APPLICATIONS
Process Control
Autom atic Test Equipm ent
General Purpose Instrum entation
R
D
FB
I
I
D
INPUT
DAC D
LATCH
OUT1
OUT2
DAC D
DAC E
DAC F
DAC G
DAC H
LATCH D
D
R
E
FB
I
I
E
INPUT
DAC E
LATCH
OUT1
LATCH E
E
OUT2
GENERAL D ESCRIP TIO N
T he AD7568 contains eight 12-bit DACs in one monolithic de-
vice. T he DACs are standard current output with separate VREF
R
F
FB
DAC F
I
F
F
INPUT
OUT1
OUT2
LATCH
LATCH F
I
,
R
G
FB
I
OUT 1, IOUT 2 and RFB terminals.
I
G
INPUT
DAC G
LATCH
OUT1
OUT2
LATCH G
T he AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de-
vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.
I
G
R
I
H
FB
H
INPUT
DAC H
LATCH
OUT1
12
12
LATCH H
I
H
OUT2
All DACs can be simultaneously updated using the asynchro-
nous LDAC input and they can be cleared by asserting the
asynchronous CLR input.
CONTROL LOGIC
+
FSIN
CLKIN
INPUT SHIFT
REGISTER
SDIN
T he AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.
V
REF
E
V G
V
REF
REF
V
F
H
A0
SDOUT
REF
LDAC CLR
P IN CO NFIGURATIO NS
P lastic Quad Flatpack
P lastic Leaded Chip Carrier
6
5
4
3
2
1
44 43 42 41 40
7
8
39
38
37
36
35
34
33
32
31
30
29
NC
F
1
2
3
4
5
6
7
8
9
NC
F
NC
33
32
31
30
29
28
27
26
25
24
23
PIN 1 IDENTIFIER
NC
V
C
V
REF
REF
V
V
C
REF
REF
R
C
R
F
F
F
FB
FB
R
C
R
F
F
F
9
FB
FB
I
I
C
I
OUT1
OUT1
AD7568 PQFP
I
10
11
12
13
14
15
16
17
I
I
C
I
C
OUT1
OUT2
OUT1
OUT2
OUT2
OUT2
TOP VIEW
V
B
V
G
G
G
G
I
REF
REF
NottoScale
C
B
AD7568 PLCC
TOP VIEW
(Not to Scale)
R
B
R
FB
FB
V
V
G
G
G
G
H
H
REF
REF
I
I
B
I
I
OUT1
OUT1
R
R
I
B
FB
B
FB
OUT2
OUT2
V
H 10
V
A
I
I
B
B
A
REF
REF
OUT1
OUT2
OUT1
OUT2
R
H
11
R
A
FB
FB
I
V
V
REF
REF
R
R
A
FB
FB
18 19
21 22
24 25 26
28
27
20
23
NC = NO CONNECT
REV. C
NC = NO CONNECT
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
(V = +4.75 V to +5.25 V; IOUT1 = IOUT2 = O V; V = +5 V; T = TMIN to T ,
unless otherwise noted)
DD
REF
A
MAX
1
AD7568–SPECIFICATIONS
P aram eter
AD 7568B2
Units
Test Conditions/Com m ents
ACCURACY
Resolution
12
Bits
1 LSB = VREF/212 = 1.22 mV when VREF = 5 V
Relative Accuracy
Differential Nonlinearity
Gain Error
±0.5
±0.9
LSB max
LSB max
All Grades Guaranteed Monotonic over T emperature
+25°C
TMIN to TMAX
Gain T emperature Coefficient
±4
±5
2
LSBs max
LSBs max
ppm FSR/°C typ
ppm FSR/°C max
5
Output Leakage Current
IOUT 1
@ +25°C
TMIN to TMAX
10
200
nA max
nA max
See T erminology Section
REFERENCE INPUT
Input Resistance
5
9
2
kΩ min
kΩ max
% max
T ypical Input Resistance = 7 kΩ
Ladder Resistance Mismatch
DIGIT AL INPUT S
T ypically 0.6%
V
V
INH, Input High Voltage
INL, Input Low Voltage
2.4
0.8
±1
10
V min
V max
µA max
pF max
I
INH, Input Current
CIN, Input Capacitance
POWER REQUIREMENT S
VDD Range
4.75/5.25
V min/V max
Power Supply Sensitivity
∆Gain/∆VDD
IDD
–75
300
3.5
dB typ
µA max
mA max
VINH = 4.0 V min, VINL = 0.4 V max
VINH = 2.4 V min, VINL = 0.8 V max
(These characteristics are included for Design Guidance and are not subject
to test. DAC output op amp is AD843.)
AC PERFORMANCE CHARACTERISTICS
P aram eter
AD 7568B2
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE
Output Voltage Settling T ime
500
ns typ
T o 0.01% of Full-Scale Range. DAC Latch Alternately
Loaded with All 0s and All 1s.
Digital to Analog Glitch Impulse 40
nV–s typ
dB max
Measured with VREF = 0 V. DAC Register Alternately
Loaded with All 0s and All 1s.
VREF = 20 V pk-pk, 10 kHz Sine Wave. DAC Latch
Loaded with All 0s.
All 1s Loaded to DAC.
All 0s Loaded to DAC.
Feedthrough from Any One Reference to the Others
with 20 V pk-pk, 10 kHz Sine Wave Applied.
Effect of all 0s to all 1s Code T ransition on
Nonselected DACs.
Feedthrough to Any DAC Output with FSIN High
and Square Wave Applied to SDIN and SCLK.
VREF = 6 V rms, 1 kHz Sine Wave.
Multiplying Feedthrough Error
Output Capacitance
–66
60
pF max
pF max
dB typ
30
Channel-to-Channel Isolation
Digital Crosstalk
–76
40
nV–s typ
nV–s typ
dB typ
Digital Feedthrough
40
T otal Harmonic Distortion
Output Noise Spectral Density
@ 1 kHz
–83
20
nV/√Hz
All 1s Loaded to the DAC. VREF = 0 V. Output Op
Amp is AD OP07.
NOT ES
1T emperature range as follows: B Version: –40°C to +85°C.
2All specifications also apply for VREF = +10 V, except relative accuracy which degrades to ±1 LSB.
Specifications subject to change without notice.
REV. C
–2–
AD7568
TIMING SPECIFICATIONS (V = +5 V ؎ 5%; IOUT1 = IOUT2 = 0 V; T = TMIN to T , unless otherwise noted)
DD
A
MAX
Lim it at
Lim it at
P aram eter
TA = +25؇C
TA = –40؇C to +85؇C
Units
D escription
t1
t2
t3
t4
t5
t6
t72
t8
t9
100
40
40
30
30
5
90
70
40
100
40
40
30
30
5
90
70
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
CLKIN Cycle T ime
CLKIN High T ime
CLKIN Low T ime
FSIN Setup T ime
Data Setup T ime
Data Hold T ime
FSIN Hold T ime
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR Pulse Width
NOT ES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t1
CLKIN (I)
t3
t2
t4
t7
FSIN (I)
t5
t6
DB15
DB0
SDIN (I)
t8
SDOUT (O)
LDAC, CLR
DB0
DB15
t9
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Tim ing Diagram
1.6mA
I
OL
TO OUTPUT
PIN
+2.1V
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output
Tim ing Specifications
REV. C
–3–
AD7568
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to DGND
IOUT1 to DGND
IOUT2 to DGND
Digital Input Voltage to DGND
−0.3 V to +6 V
−0.3 V to VDD +0.3 V
−0.3 V to VDD +0.3 V
−0.3 V to VDD +0.3 V
1ꢀ V
VRFB, VREF to DGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial Plastic (B Versions)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Power Dissipation (Any Package) to 7ꢀ°C
Derates above 7ꢀ°C by
10 mA
ESD CAUTION
−40°C to +8ꢀ°C
−6ꢀ°C to +1ꢀ0°C
300°C
2ꢀ0 mW
10 mW/°C
1 Transient currents of up to 100 mA will not cause SCR latch-up.
PIN DESCRIPTION
Mnemonic Description
VDD
DGND
AGND
Positive Power Supply. This is ꢀ V ꢀ5.
Digital Ground.
Analog Ground
VREFA to VREFH DAC Reference Inputs.
RFBA to RFBH DAC Feedback Resistor Pins.
IOUTA to IOUTH DAC Current Output Terminals.
AGND
CLKIN
This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.
FSIN
SDIN
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it
enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low.
Serial Data Input. The device accepts a 16-bit word. The first bit (DB1ꢀ) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally
comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT
A0
This shift register output allows multiple devices to be connected in a daisy-chain configuration.
Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the
data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC
CLR
Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the
input latches.
Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.
– 4 –
REV. C
AD7568
TERMINO LO GY
O utput Voltage Settling Tim e
Relative Accur acy
T his is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage or full-scale
reading.
D igital to Analog Glitch Im pulse
T his is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
D iffer ential Nonlinear ity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
AC Feedthr ough Er r or
T his is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT terminal, when all 0s are
loaded in the DAC.
Gain Er r or
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
O utput Leakage Cur r ent
D igital Cr osstalk
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT 1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT 1 current. Minimum current will flow in the IOUT 2 line
when the DAC is loaded with all 1s. T his is a combination of
the switch leakage current and the ladder termination resistor
current. T he IOUT 2 leakage current is typically equal to that in
T he glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
D igital Feedthr ough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de-
vice to show up as noise on the IOUT pin and subsequently on
the op amp output. T his noise is digital feedthrough.
IOUT 1
.
O utput Capacitance
T his is the capacitance from the IOUT 1 pin to AGND.
Table I. AD 7568 Loading Sequence
D B15
D B0
D B11 D B10 D B9 D B8 D B7 D B6 D B5 D B4 D B3 D B2 D B1 D B0
A0
D S2 D S1 D S0
Table II. D AC Selection
D S2
D S1
D S0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Selected
DAC B Selected
DAC C Selected
DAC D Selected
DAC E Sclected
DAC F Selected
DAC G Sclected
DAC H Selected
REV. C
–5–
AD7568–Typical Performance Curves
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2
1.0
0.9
V
= +5V
= +25°C
DD
V
= +5V
V
T
= +5V
= +25°C
DD
DD
T
A
A
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= +2.4V
IH
1
V
= +4V
IH
0
0.0
1.0
2.0
3.0
4.0
5.0
–40
–15
10
35
60
85
2.0
4.0
6.0
– Volts
8.0
10.0
DIGITAL INPUT – Volts
TEMPERATURE – °C
V
REF
Figure 3. Supply Current vs. Logic
Input Voltage
Figure 4. Supply Current vs.
Tem perature
Figure 5. Differential Nonlinearity
Error vs. VREF
1.0
1.0
0.8
0.6
0.4
0.2
0.0
–50
V
T
= +5V
= +25°C
DD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
V
T
= +5V
= +25°C
DD
A
V
V
T
= +10V
= +5V
= +25°C
REF
A
DD
V
= 6V rms
IN
A
OP AMP = AD713
2
3
4
5
10
2.0
4.0
6.0
– Volts
8.0
10.0
0
2048
DIGITAL CODE
4095
10
10
10
V
FREQUENCY – Hz
REF
Figure 6. Integral Nonlinearity Error
vs. VREF
Figure 7. Typical DAC to DAC
Linearity Matching
Figure 8. Total Harm onic Distortion
vs. Frequency
0
0
V
C = 20V pk-pk SINE WAVE
V
B GROUNDED
REF
REF
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ALL OTHER REFERENCE INPUTS GROUNDED
DAC C LOADED WITH ALL 1s
ALL OTHER REFERENCE INPUTS =
20V pk-pk SINE WAVE
200ns
5V
ALL OTHER DACs LOADED WITH ALL 0s
DAC B LOADED WITH ALL 0s
ALL OTHER DACs LOADED WITH ALL 1s
100
90
DIGITAL INPUTS
V
T
= +5V
DD
= +25°C
A
V
= +10V
REF
OP AMP = AD713
AD713 OUTPUT
10
0%
50mV
200ns
3
3
4
4
5
6
5
6
10
10
10
10
10
10
10
10
FREQUENCY – Hz
FREQUENCY – Hz
Figure 10. Channel-to-Channel
Isolation (1 DAC to 1 DAC)
Figure 11. Channel-to-Channel
Isolation (1 DAC to All Other DACs)
Figure 9. Digital-to-Analog Glitch
Im pulse
REV. C
–6–
AD7568
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Inter face Section
DAC LOADED WITH ALL 1s
T he AD7568 is a serial input device. T hree lines control the se-
rial interface, FSIN, CLKIN and SDIN. T he timing diagram is
shown in Figure 1.
V
T
= +5V
= +25°C
DD
A
V
= 20V pk-pk
IN
When the FSIN input goes low, data appearing on the SDIN
line is clocked into the input shift register on each falling edge of
CLKIN. When sixteen bits have been received, the register
loading is automatically disabled until the next falling edge of
FSIN detected. Also, the received data is clocked out on the
next rising edge of CLKIN and appears on the SDOUT pin.
T his feature allows several devices to be connected together in a
daisy chain fashion.
OP AMP = AD713
DAC LOADED WITH ALL 0s
3
4
5
6
7
10
10
10
10
10
When the sixteen bits have been received in the input shift regis-
ter, DB3 (A0) is checked to see if it corresponds to the state of
pin A0. If it does, then the word is accepted. Otherwise, it is dis-
regarded. T his allows the user to address one of two AD7568s
in a very simple fashion. DB0 to DB2 of the 16-bit word deter-
mine which of the eight DAC input latches is to be loaded.
When the LDAC line goes low, all eight DAC latches in the de-
vice are simultaneously loaded with the contents of their respec-
tive input latches, and the outputs change accordingly.
Figure 12. Multiplying Frequency Response vs.
Digital Code
GENERAL D ESCRIP TIO N
D /A Section
T he AD7568 contains eight 12-bit current-output D/A convert-
ers. A simplified circuit diagram for one of the D/A converters is
shown in Figure 13.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A, B and C.
T he remaining 10 bits of the data word drive the switches S0 to
S9 in a standard R–2R ladder configuration.
Bringing the CLR line low resets the DAC latches to all 0s. T he
input latches are not affected, so that the user can revert to the
previous analog output if desired.
CLKIN
Each of the switches A to C steers 1/4 of the total reference cur-
rent with the remaining current passing through the R–2R
section.
16-BIT INPUT SHIFT REGISTER
FSIN
SDIN
SDOUT
Each DAC in the device has separate VREF, IOUT 1, IOUT 2 and
RFB pins. T his makes the device extremely versatile and allows
DACs in the same device to be configured differently.
Figure 14. Input Logic
When an output amplifier is connected in the standard configu-
ration of Figure 15, the output voltage is given by:
VOUT = –D•VREF
where D is the fractional representation of the digital word
loaded to the DAC. T hus, in the AD7568, D can be set from
0 to 4095/4096.
V
REF
R
R
R
2R
2R
2R
2R
2R
2R
2R
S9
C
B
A
S8
S9
R/2
R
I
FB
OUT1
OUT2
I
SHOWN FOR ALL 1s ON DAC
Figure 13. Sim plified D/A Circuit Diagram
REV. C
–7–
AD7568
R4
UNIP O LAR BINARY O P ERATIO N
(2-Q uadr ant Multiplication)
R2 10Ω
20kΩ
R5
R
A
Figure 15 shows the standard unipolar binary connection dia-
gram for one of the DACs in the AD7568. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication. Resistors
R1 and R2 allow the user to adjust the DAC gain error. Offset
can be removed by adjusting the output amplifier offset voltage.
FB
C1
R1 20Ω
20kΩ
I
A
A
OUT1
V
R3
IN
V
DAC A
A1
OUT
10kΩ
A2
V
A
REF
I
OUT2
AD7568
SIGNAL
GND
A1 should be chosen to suit the application. For example, the
AD OP07 or OP177 are ideal for very low bandwidth applica-
tions while the AD843 and AD845 offer very fast settling time
in wide bandwidth applications. Appropriate multiple versions
of these amplifiers can be used with the AD7568 to reduce
board space requirements.
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 16. Bipolar Operation (4-Quadrant Multiplication)
T he code table for Figure 15 is shown in T able III.
Table IV. Bipolar (O ffset Binary) Code Table
R2 10Ω
R
A
FB
D igital Input
MSB . . . . . LSB
Analog O utput
(VO UT As Shown in Figure 16)
C1
R1 20Ω
I
I
A
A
OUT1
V
V
IN
OUT
DAC A
A1
V
A
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
+VREF (2047/2048)
+VREF (1/2048)
+VREF (0/2048) = 0
–VREF (1/2048)
–VREF (2047/2048)
–VREF (2048/2048) = –VREF
REF
OUT2
A1: OP-177
AD7568
SIGNAL
GND
ADOP-07
AD711
AD843
AD845
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
NOT E
Nominal LSB size for the circuit of Figure 16 is given by:
VREF (1/2048).
Figure 15. Unipolar Binary Operation
Table III. Unipolar Binary Code Table
SINGLE SUP P LY CIRCUITS
T he AD7568 operates from a single +5 V supply, and this
makes it ideal for single supply systems. When operating in such
a system, it is not possible to use the standard circuits of Figures
15 and 16 since these invert the analog input, VIN. T here are
two alternatives. One of these continues to operate the DAC as
a current-mode device, while the other uses the voltage switch-
ing mode.
D igital Input
MSB………LSB
Analog O utput
(VO UT As Shown in Figure 15)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
–VREF (4095/4096)
–VREF (2049/4096)
–VREF (2048/4096)
–VREF (2047/4096)
–VREF (1/4096)
R
A
FB
–VREF (0/4096) = 0
I
I
A
A
OUT1
OUT2
V
V
IN
OUT
DAC A
AD7568
A1
NOT E
V
A
Nominal LSB size for the circuit of Figure 15 is given by:
VREF (1/4096).
REF
BIP O LAR O P ERATIO N
(4-Q uadr ant Multiplication)
V
BIAS
Figure 16 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7568. T he coding is
offset binary as shown in T able IV. When VIN is an ac signal,
the circuit performs 4-quadrant multiplication. T o maintain the
gain error specifications, resistors R3, R4 and R5 should be ra-
tio matched to 0.01%.
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 17. Single Supply Current-Mode Operation
REV. C
–8–
AD7568
R1
R2
Cur r ent Mode Cir cuit
In the current mode circuit of Figure 17, IOUT 2, and hence
R
A
FB
I
OUT 1, is biased positive by an amount VBIAS. For the circuit to
V
OUT
V
I
A
A
V
A
REF
A1
IN
OUT1
OUT2
operate correctly, the DAC ladder termination resistor must be
connected internally to IOUT 2. T his is the case with the AD7568.
T he output voltage is given by:
DAC A
I
AD7568
RFB
VOUT = D
V
(
BIAS −VIN +VBIAS
)
{
}
RDAC
NOTES
1) ONLY ONE DAC IS SHOWN FOR CLARITY.
2) DIGITAL INPUT CONNECTIONS ARE OMITTED.
3) C1 PHASE COMPENSATION (5–15pF) MAY BE
As D varies from 0 to 4095/4096, the output voltage varies from
VOUT = VBIAS to VOUT = 2 VBIAS – VIN. VBIAS should be a low
impedance source capable of sinking and sourcing all possible
variations in current at the IOUT 2 terminal without any
problems.
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 18. Single Supply Voltage Switching
Mode Operation
Voltage Mode Cir cuit
Figure 18 shows DAC A of the AD7568 operating in the
voltage-switching mode. T he reference voltage, VIN is applied to
the IOUT 1 pin, IOUT 2 is connected to AGND and the output volt-
age is available at the VREF terminal. In this configuration, a
positive reference voltage results in a positive output voltage
making single supply operation possible. T he output from the
DAC is a voltage at a constant impedance (the DAC ladder re-
sistance). T hus, an op amp is necessary to buffer the output
voltage. T he reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt-
age input should be driven from a low impedance source.
AP P LICATIO NS
P r ogr am m able State Var iable Filter
T he AD7568 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
T he circuit of Figure 19 shows its use in a state variable filter
design. T his type of filter has three outputs: low pass, high pass
and bandpass. T he particular version shown in Figure 19 uses
one half of an AD7568 to control the critical parameters f0, Q
and A0. Instead of several fixed resistors, the circuit uses the
DAC equivalent resistances as circuit elements. T hus, R1 in
Figure 19 is controlled by the 12-bit digital word loaded to
DAC A of the AD7568. T his is also the case with R2, R3 and
R4. T he fixed resistor R5 is the feedback resistor, RFBB.
It is important to note that VIN is limited to low voltages be-
cause the switches in the DAC no longer have the same source-
drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, VIN must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. T his means that the
full-range multiplying capability of the DAC is lost.
DAC Equivalent Resistance, REQ = (RLADDER ϫ 4096)/N
where:
RLADDER is the DAC ladder resistance.
N is the DAC Digital Code in Decimal (0 < N < 4096).
C3 10pF
C1 1000pF
A2
C1 1000pF
A3
R8 30kΩ
R7 30kΩ
HIGH
PASS
LOW
PASS
A1
R6
OUTPUT
OUTPUT
10kΩ
A1
BAND
PASS
I
A
R
B
V
B
V
C
I
V
D
OUTPUT
I
B
OUT1
C
I
D
OUT1
FB
REF
REF
OUT1
REF
OUT1
V
IN
DAC A
(R1)
DAC B
(R2)
DAC C
(R3)
DAC D
(R4)
V
A
REF
1/2 x AD7568
I
D
I
A
I
C
OUT2
I
B
OUT2
OUT2
OUT2
NOTES
1. A1, A2, A3, A4: 1/4 x AD713
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE
Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN
BANDWIDTH LIMITATIONS.
Figure 19. Program m able 2nd Order State Variable Filter
REV. C
–9–
AD7568
In the circuit of Figure 19:
the data word transmitted to the AD7568 corresponds to the
loading sequence shown in T able I. When data is to be trans-
mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of T XD. T he 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. T o load data to the AD7568, P3.3 is left low af-
ter the first eight bits are transferred, and a second byte of data
is then transferred serially to the AD7568. When the second se-
rial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. T he AD7568 expects the MSB first. T he 80C51
transmit routine should take this into account.
C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to
each DAC).
Resonant frequency, f0 = 1/(2πR3C1).
Quality Factor, Q = (R6/R8)•(R2/R5).
Bandpass Gain, A0 = –R2/R1.
Using the values shown in Figure 19, the Q range is 0.3 to 5,
and the f0 range is 0 to 12 kHz.
AP P LICATIO N H INTS
O utput O ffset
CMOS D/A converters in circuits such as Figures 15, 16 and 17
exhibit a code dependent output resistance which in turn can
cause a code dependent error voltage at the output of the ampli-
fier. T he maximum amplitude of this error, which adds to the
D/A converter nonlinearity, depends on VOS, where VOS is the
amplifier input offset voltage. For the AD7568 to maintain
specified accuracy with VREF at 10 V, it is recommended that
VOS be no greater than 500 µV, or (50 ϫ 10–6)•(VREF), over the
temperature range of operation. Suitable amplifiers include the
AD OP07, AD OP27, OP177, AD711, AD845 or multiple ver-
sions of these.
80C51*
AD7568*
CLR
P3.5
P3.4
P3.3
TXD
RXD
LDAC
FSIN
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Tem per atur e Coefficients
T he gain temperature coefficient of the AD7568 has a maxi-
mum value of 5 ppm/°C and a typical value of 2 ppm/°C. T his
corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively
over a 100°C temperature range. When trim resistors R1 and
R2 are used to adjust full-scale in Figures 15 and 16, their tem-
perature coefficients should be taken into account. For further
information see “Gain Error and Gain T emperature Coefficient
of CMOS Multiplying DACs,” Application Note, Publication
Number E630c–5–3/86, available from Analog Devices.
Figure 20. AD7568 to 80C51 Interface
LDAC and CLR on the AD7568 are also controlled by 80C51
port outputs. T he user can bring LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.
AD 7568–68H C11 Inter face
Figure 21 shows a serial interface between the AD7568 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7568, while the MOSI output drives the serial data line
of the AD7568. T he FSIN signal is derived from a port line
(PC7 shown).
H igh Fr equency Consider ations
T he output capacitances of the AD7568 DACs work in con-
junction with the amplifier feedback resistance to add a pole to
the open loop response. T his can cause ringing or oscillation.
Stability can be restored by adding a phase compensation ca-
pacitor in parallel with the feedback resistor. T his is shown as
C1 in Figures 15, 16 and 17.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. T he 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. T o load data to the
AD7568, PC7 is left low after the first eight bits are transferred,
and a second byte of data is then transferred serially to the
AD7568. When the second serial transfer is complete, the PC7
line is taken high.
MICRO P RO CESSO R INTERFACING
AD 7568–80C51 Inter face
A serial interface between the AD7568 and the 80C51 micro-
controller is shown in Figure 20. T XD of the 80C51 drives
SCLK of the AD7568 while RXD drives the serial data line of
the part. T he FSIN signal is derived from the port line P3.3.
T he 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. T herefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
REV. C
–10–
AD7568
68HC11*
AD7568*
TMS320C25*
AD7568*
+5V
CLR
PC5
PC6
CLR
LDAC
FSIN
XF
FSX
LDAC
FSIN
PC7
SCK
CLKIN
SDIN
DX
SDIN
CLKIN
MOSI
CLKX
*ADDITIONAL PINS OMITTED FOR CLARITY
CLOCK
GENERATION
Figure 21. AD7568 to 68HC11 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.
AD 7568–AD SP -2101 Inter face
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. T he ADSP-2101 may be
set up to operate in the SPORT T ransmit Normal Internal
Framing Mode. T he following ADSP-2101 conditions are rec-
ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. T ransmission is initiated by writing a word to the
T X register after the SPORT has been enabled. T he data is then
clocked out on every rising edge of SCLK after T FS goes low.
T FS stays low until the next data transfer.
Multiple D AC System s
If there are only two AD7568s in a system, there is a simple way
of programming each. T his is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro-
gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
ADSP-2101*
AD7568*
ADSP-2101*
AD7568*
A0
+5V
+5V
CLR
CLR
FO
LDAC
FO
TFS
LDAC
FSIN
FSIN
TFS
DT
SDIN
CLKIN
DT
SDIN
CLKIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7568*
Figure 22. AD7568 to ADSP-2101 Interface
LDAC
FSIN
SDIN
CLKIN
A0
AD 7568–TMS320C25 Inter face
Figure 23 shows an interface circuit for the T MS320C25
digital signal processor. T he data on the DX pin is clocked
out of the processor’s T ransmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST 1 register to 0. T he transmit operation be-
gins when data is written into the data transmit register of the
T MS320C25. T his data will be transmitted when the FSX line
goes low while CLKX is high or going high. T he data, starting
+5V
CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing ADSP-2101 to Two AD7568s
REV. C
–11–
AD7568
For systems which contain larger numbers of AD7568s and
where the user also wishes to read back the DAC contents for
diagnostic purposes, the SDOUT pin may be used to daisy
chain several devices together and provide the necessary serial
readback. An example with the 68HC11 is shown in Figure 25.
T he routine below shows how four AD7568s would be pro-
grammed in such a system. Data is transmitted at the MOSI pin
of the 68HC11. It flows through the input shift registers of the
AD7568s and finally appears at the SDOUT pin of DAC N. So,
the readback routine can be invoked any time after the first four
words have been transmitted (the four input shift registers in the
chain will now be filled up and further activity on the CLKIN
pin will result in data being read back to the microcomputer
through the MISO pin). System connectivity can be verified in
this manner. For a four-device system (32 DACs) a two-line to
four-line decoder is necessary.
68HC11*
AD7568*
(DAC 1)
MOSI
SDIN
PC7
SCK
PC6
FSIN
SCLK
LDAC
A0
MISO
SDOUT
SDIN
DECODE LOGIC
AD7568*
(DAC 2)
FSIN
SCLK
LDAC
A0
SDOUT
Note that to program the 32 DACs, 35 transmit operations are
needed. In the routine, three words must be retransmitted. T he
first word for DACs # 3, # 2 and # 1 must be transmitted twice in
order to synchronize their arrival at the SDIN pin with A0 going
low.
SDIN
AD7568*
(DAC N)
Table V. Routine for Loading 4 AD 7568s Connected As in
Figure 25
FSIN
SCLK
LDAC
A0
SDOUT
Bring PC7 (FSIN) low to allow writing to the AD7568s.
Enable AD7568 # 4 (Bring A0 low). Disable the others.
T ransmit 1st 16-bit word: Data for DAC H, # 4
. . . .
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Multi-DAC System
. . . .
T ransmit 9th 16-bit word: Data for DAC H, # 3
T ransmit 9th 16-bit word again: Data for DAC H, # 3
T ransmit 10th 16-bit word: Data for DAC G, # 3
T ransmit 11th 16-bit word: Data for DAC F, # 3
Enable AD7568 # 3, Disable the others.
T ransmit 12th 16-bit word: Data for DAC E, # 3
. . . .
. . . .
T ransmit 17th 16-bit word: Data for DAC H, # 2
T ransmit 17th 16-bit word again: Data for DAC H, # 2
T ransmit 18th 16-bit word: Data for DAC G, # 2
Enable AD7568 # 2, Disable the others.
T ransmit 19th 16-bit word: Data for DAC F, # 2
. . . .
. . . .
T ransmit 25th word: Data for DAC H, # 1
Enable AD7568 # 1, Disable the others.
T ransmit 25th word again: Data for DAC H, # 1
T ransmit 26th word: Data for DAC G, # 1
. . . .
. . . .
T ransmit 32nd word: Data for DAC A, # 1
Bring PC7 (FSIN) high to disable writing to the AD7568s.
REV. C
–12–
AD7568
OUTLINE DIMENSIONS
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.020 (0.51)
MIN
6
40
39
0.048 (1.22)
0.042 (1.07)
7
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
0.630 (16.00)
0.590 (14.99)
BOTTOM VIEW
(PINS UP)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.045 (1.14)
0.025 (0.64)
R
0.656 (16.66)
0.650 (16.51)
0.120 (3.05)
0.090 (2.29)
SQ
0.695 (17.65)
0.685 (17.40)
SQ
COMPLIANT TO JEDEC STANDARDS MO-047-AC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 44-Lead Plastic Leaded Chip Carrier [PLCC]
(P-44)
Dimensions shown in inches and (millimeters)
14.15
1.03
0.88
0.73
13.90 SQ
13.65
2.45
MAX
34
44
1.95 REF
1
33
PIN 1
SEATING
PLANE
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
2.20
2.00
1.80
0.23
0.11
23
11
7°
0°
22
12
0.25 MIN
0.10
0.45
0.30
LEAD WIDTH
COPLANARITY
VIEW A
0.80 BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MO-112-AA-1
Figure 27. 44-Lead Metric Quad Flat Package [MQFP]
(S-44-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Linearity Error (LSBs)
Package Description
Package Option
P-44
P-44
P-44
P-44
AD7568BP
AD7568BP-REEL
AD7568BPZ
AD7568BPZ-REEL
AD7568BSZ
AD7568BSZ-REEL
0ꢀ5
0ꢀ5
0ꢀ5
0ꢀ5
0ꢀ5
0ꢀ5
44-Lead Plastic Leaded Chip Carrier [PLCC]
44-Lead Plastic Leaded Chip Carrier [PLCC]
44-Lead Plastic Leaded Chip Carrier [PLCC]
44-Lead Plastic Leaded Chip Carrier [PLCC]
44-Lead Metric Quad Flat Package [MQFP]
44-Lead Metric Quad Flat Package [MQFP]
S-44-2
S-44-2
1 Z = RoHS Compliant Part
REV. C
– 13 –
AD7568
REVISION HISTORY
2/12—Rev. B to Rev. C
Changes to
Description, Pin Description Table...................4
CLR
Updated Outline Dimensions........................................................13
Changes to Ordering Guide...........................................................13
Added Revision History Section ...................................................14
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10541-0-2/12(C)
– 14 –
REV. C
相关型号：
AD7568BS-REEL
IC OCTAL, SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 12-BIT DAC, PQFP44, PLASTIC, QFP-44, Digital to Analog Converter
ADI
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