AD7609 [ADI]
8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC; 8通道差分DAS 18位，双极性，同步采样ADC
| 型号： | AD7609 |
| 厂家： | 
ADI |
| 描述： | 8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC |
| 文件： | 总36页 (文件大小：788K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel Differential DAS with 18-Bit,
Bipolar, Simultaneous Sampling ADC
Data Sheet
AD7609
FEATURES
APPLICATIONS
8 simultaneously sampled inputs
True differential inputs
Power line monitoring and protection systems
Multiphase motor control
True bipolar analog input ranges: 10 V, 5 V
Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
18-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Performance
7 kV ESD rating on analog input channels
98 dB SNR, −107 dB THD
Dynamic range: up to 105 dB typical
Low power: 100 mW
Standby mode: 25 mW
64-lead LQFP package
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
COMPANION PRODUCTS
External References: ADR421, ADR431
Digital Isolators: ADuM1402, ADuM5000, ADuM5402
Power: ADIsimPower, Supervisor Parametric Search
Additional companion products on the AD7609 product page
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Single-
Ended
Inputs
True
Number of
Differential Simultaneous
Inputs
AD76091
Resolution
18 Bits
16 Bits
Sampling Channels
AD7608
AD7606
AD7606-6
AD7606-4
AD7607
8
8
6
4
8
14 Bits
1 Patent pending.
FUNCTIONAL BLOCK DIAGRAM
AVCC
AVCC
REGCAP REGCAP REFCAPB REFCAPA
RFB
1MΩ
V1+
V1–
CLAMP
CLAMP
T/H
SECOND-
ORDER LPF
2.5V
LDO
2.5V
LDO
RFB
RFB
1MΩ
1MΩ
REFIN/REFOUT
V2+
V2–
CLAMP
CLAMP
T/H
T/H
T/H
T/H
T/H
T/H
T/H
SECOND-
ORDER LPF
RFB
RFB
1MΩ
1MΩ
REF SELECT
AGND
2.5V
REF
V3+
V3–
CLAMP
CLAMP
OS 2
OS 1
OS 0
SECOND-
ORDER LPF
RFB
RFB
1MΩ
1MΩ
V4+
V4–
CLAMP
CLAMP
DOUT
A
SECOND-
ORDER LPF
SERIAL
RFB
RFB
1MΩ
1MΩ
DOUTB
8:1
MUX
PARALLEL/
SERIAL
RD/SCLK
CS
DIGITAL
FILTER
18-BIT
SAR
V5+
V5–
CLAMP
CLAMP
INTERFACE
SECOND-
ORDER LPF
RFB
RFB
1MΩ
1MΩ
PAR/SER SEL
VDRIVE
V6+
V6–
CLAMP
CLAMP
SECOND-
ORDER LPF
PARALLEL
DB[15:0]
RFB
RFB
1MΩ
1MΩ
AD7609
V7+
V7–
CLAMP
CLAMP
SECOND-
ORDER LPF
CLK OSC
RFB
RFB
1MΩ
1MΩ
BUSY
CONTROL
INPUTS
V8+
V8–
CLAMP
CLAMP
SECOND-
ORDER LPF
FRSTDATA
RFB
1MΩ
AGND
CONVST A CONVST B RESET RANGE
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD7609
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Details ....................................................................... 21
Analog Input ............................................................................... 21
ADC Transfer Function............................................................. 22
Internal/External Reference...................................................... 23
Typical Connection Diagram ................................................... 24
Power-Down Modes .................................................................. 24
Conversion Control ................................................................... 25
Digital Interface.............................................................................. 26
Applications....................................................................................... 1
Companion Products....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
PAR
/SER SEL = 0)...................................... 26
Parallel Interface (
PAR
Serial Interface (
/SER SEL = 1)......................................... 26
Reading During Conversion..................................................... 27
Digital Filter ................................................................................ 28
Layout Guidelines....................................................................... 32
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
2/12—Rev. 0 to Rev. A
Changes to Analog Input Ranges Section ....................................21
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 36
Data Sheet
AD7609
GENERAL DESCRIPTION
The AD7609 is an 18-bit, 8-channel, true differential,
simultaneous sampling analog-to-digital data acquisition
system (DAS). The part contains analog input clamp protection,
a second-order antialiasing filter, a track-and-hold amplifier, an
18-bit charge redistribution successive approximation analog-
to-digital converter (ADC), a flexible digital filter, a 2.5 V
reference and reference buffer, and high speed serial and
parallel interfaces.
The AD7609 operates from a single 5 V supply and can
accommodate 10 V and 5 V true bipolar differential input
signals while sampling at throughput rates up to 200 kSPS for
all channels. The input clamp protection circuitry can tolerate
voltages up to 16.5 V. T h e AD7609 has 1 MΩ analog input
impedance regardless of sampling frequency. The single supply
operation, on-chip filtering, and high input impedance elimi-
nate the need for driver op amps and external bipolar supplies.
The AD7609 antialiasing filter has a −3 dB cutoff frequency of
32 kHz and provides 40 dB antialias rejection when sampling
at 200 kSPS. The flexible digital filter is pin driven, yields
improvements in SNR, and reduces the −3 dB bandwidth.
Rev. A | Page 3 of 36
AD7609
Data Sheet
SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise
noted.1
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2, 3
fIN = 1 kHz sine wave unless otherwise noted
Oversampling by 16; 10 V range; fIN = 160 Hz
Oversampling by 16; 5 V range; fIN = 160 Hz
No oversampling; 10 V range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
98
101
100
91
90.5
91
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
90
89.5
89.5
89
Signal-to-(Noise + Distortion) (SINAD)2
Dynamic Range
90
91.5
90.5
−107
−110
−108
Total Harmonic Distortion (THD)2, 3
No oversampling; 10 V range
No oversampling; 5 V range
−97
−96
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation2
fa = 1 kHz, fb = 1.1 kHz
−110
−106
−95
dB
dB
dB
fIN on unselected channels up to 160 kHz
ANALOG INPUT FILTER
Full Power Bandwidth
−3 dB, 10 V range
−3 dB, 5 V range
−0.1 dB, 10 V range
−0.1 dB, 5 V range
10 V range
32
23
13
10
7.1
10.2
kHz
kHz
kHz
kHz
µs
tGROUP DELAY
5 V range
µs
DC ACCURACY
Resolution
No missing codes
18
Bits
Differential Nonlinearity2
Integral Nonlinearity2
Total Unadjusted Error (TUE)
0.75
3
10
90
8
40
2
7
−0.99/+2
7.5
LSB4
LSB
LSB
LSB
LSB
10 V range
5 V range
Positive Full-Scale Error2, 5
External reference
Internal reference
External reference
Internal reference
10 V range
140
LSB
Positive Full-Scale Error Drift
Positive Full-Scale Error Matching2
ppm/°C
ppm/°C
LSB
LSB
LSB
12
40
3
80
100
24
5 V range
10 V range
Bipolar Zero Code Error2,
6
5 V range
3
48
LSB
Bipolar Zero Code Error Drift
Bipolar Zero Code Error Matching2
Negative Full-Scale Error2, 5
10 V range
5 V range
10 V range
5 V range
External reference
Internal reference
External reference
Internal reference
10 V range
10
5
2.7
13
8
40
4
8
µV/°C
µV/°C
LSB
LSB
LSB
30
65
140
LSB
Negative Full-Scale Error Drift
Negative Full-Scale Error Matching2
ppm/°C
ppm/°C
LSB
12
40
80
100
5 V range
LSB
Rev. A | Page 4 of 36
Data Sheet
AD7609
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG INPUT
Differential Input Voltage Ranges
VIN = Vx+ − (Vx−)
RANGE = 1; 10 V
RANGE = 0; 5 V
−20
−10
−10
+20
+10
+10
V
V
V
Absolute Voltage Input
10 V range, see the Analog Input Clamp
Protection section
5 V range, see the Analog Input Clamp
Protection section
−5
−4
+5
+4
V
Common-Mode Input Range
CMRR
Analog Input Current
5
−70
5.4
2.5
5
V
dB
µA
µA
pF
MΩ
10 V, see Figure 28
5 V, see Figure 28
Input Capacitance7
Input Impedance
1
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
2.475
2.5
7.5
2.49/
2.505
2.525
1
V
µA
pF
V
Input Capacitance7
REF SELECT = 1
REFIN/REFOUT
Reference Output Voltage
Reference Temperature Coefficient
LOGIC INPUTS
10
ppm/°C
Input High Voltage (VINH
)
0.7 × VDRIVE
V
Input Low Voltage (VINL
Input Current (IIN)
Input Capacitance (CIN)7
LOGIC OUTPUTS
)
0.3 × VDRIVE
2
V
µA
pF
5
Output High Voltage (VOH
)
ISOURCE = 100 µA
ISINK = 100 µA
VDRIVE − 0.2
V
V
µA
pF
Output Low Voltage (VOL
)
0.2
20
Floating-State Leakage Current
Floating-State Output Capacitance7
Output Coding
1
5
Twos complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
All eight channels included
Per channel, all eight channels included
4
1
µs
µs
kSPS
200
POWER REQUIREMENTS
AVCC
VDRIVE
4.75
2.3
5.25
5.25
V
V
ITOTAL
Digital inputs = 0 V or VDRIVE
fSAMPLE = 200 kSPS
Normal Mode (Static)
Normal Mode (Operational)8
Standby Mode
16
20
5
22
28.5
8
mA
mA
mA
µA
Shutdown Mode
2
11
Rev. A | Page 5 of 36
AD7609
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Power Dissipation
Normal Mode (Static)
Normal Mode (Operational)8
Standby Mode
80
100
25
115.5
157
42
mW
mW
mW
µW
fSAMPLE = 200 kSPS
Shutdown Mode
10
60.5
1 Temperature range for B version is −40°C to +85°C.
2 See the Terminology section.
3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with VDRIVE = 5 V, SNR typically reduces
by 1.5 dB and THD by 3 dB.
4 LSB means least significant bit. With 5 V input range, 1 LSB = 76.29 µV. With 10 V input range, 1 LSB = 152.58 µV.
5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from
the external reference.
6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.
7 Sample tested during initial release to ensure compliance.
8 Operational power/current figure includes contribution when running in oversampling mode.
Rev. A | Page 6 of 36
Data Sheet
AD7609
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX
,
unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Parameter
Min
Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE
tCYCLE
1/throughput rate
Parallel mode, reading during; or after conversion VDRIVE = 2.7 V to 5.25 V; or
5
µs
µs
serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUT
A
and DOUTB lines
Parallel mode reading after conversion VDRIVE = 2.3 V
Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
5
4
10.1 µs
11.5 µs
tCONV
3.45
7.87
16.05
33
66
133
257
4.15 µs
9.1
18.8 µs
39
µs
µs
µs
µs
µs
µs
78
158
315
100
tWAKE-UP STANDBY
STBY rising edge to CONVST x rising edge; power-up time from standby mode
tWAKE-UP SHUTDOWN
Internal Reference
30
13
ms
ms
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
50
20
20
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
45
25
25
0
2
t5
0.5
25
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
t6
t7
25
PARALLEL READ OPERATION
t8
0
0
ns
ns
CS to RD setup time
t9
CS to RD hold time
t10
RD low pulse width
19
24
30
37
15
22
ns
ns
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
t11
t12
Rev. A | Page 7 of 36
AD7609
Data Sheet
Limit at TMIN, TMAX
Min Typ Max Unit Description
Parameter
t13
Delay from CS until DB[15:0] three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
19
24
30
37
ns
ns
ns
ns
3
t14
19
24
30
37
ns
ns
ns
ns
ns
ns
ns
t15
t16
t17
6
6
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state enabled
22
SERIAL READ OPERATION
fSCLK
Frequency of serial read clock
20
15
MHz VDRIVE above 4.75 V
MHz VDRIVE above 3.3 V
12.5 MHz VDRIVE above 2.7 V
10
MHz VDRIVE above 2.3 V
t18
Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until
MSB valid
18
23
35
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
SCLK low pulse width
3
t19
20
26
32
39
ns
ns
ns
ns
ns
ns
t20
t21
t22
t23
0.4 tSCLK
0.4 tSCLK
7
SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
CS rising edge to DOUTA/DOUTB three-state enabled
22
ns
FRSTDATA OPERATION
t24
Delay from CS falling edge until FRSTDATA three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Delay from CS falling edge until FRSTDATA high, serial mode
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
18
23
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
t25
18
23
30
35
t26
Delay from RD falling edge to FRSTDATA high
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
19
23
30
35
ns
ns
ns
ns
Rev. A | Page 8 of 36
Data Sheet
AD7609
Limit at TMIN, TMAX
Min Typ Max Unit Description
Parameter
t27
Delay from RD falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from 18th SCLK falling edge to FRSTDATA low
22
29
ns
ns
t28
20
27
29
ns
ns
ns
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from CS rising edge until FRSTDATA three-state enabled
t29
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V.
2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t5
CONVST A/
CONVST B
tCYCLE
t2
CONVST A/
CONVST B
t3
tCONV
t1
BUSY
t4
CS
t7
tRESET
RESET
Figure 2. CONVST x Timing—Reading After a Conversion
t5
CONVST A/
CONVST B
tCYCLE
t2
CONVST A/
CONVST B
t3
tCONV
t1
BUSY
t6
CS
t7
tRESET
RESET
Figure 3. CONVST x Timing—Reading During a Conversion
CS
RD
t9
t8
t13
t11
t10
t16
t17
t14
V2
t15
V8
V1
[17:2]
V1
[1:0]
V2
[1:0]
V8
[1:0]
DATA:
DB[15:0]
INVALID
t24
[17:2]
[17:2]
t26
t27
t29
FRSTDATA
CS
RD
Pulses
Figure 4. Parallel Mode Separate and
Rev. A | Page 9 of 36
AD7609
Data Sheet
t12
CS, RD
t16
t13
V1
t17
V1
[1:0]
V2
[17:2]
V2
[1:0]
V7
[17:2]
V7
[1:0]
V8
[17:2]
V8
[1:0]
DATA:
DB[15:0]
[17:2]
FRSTDATA
CS
RD
Figure 5. and
Linked Parallel Mode
CS
t21
t20
SCLK
t19
t22
DB1
t23
t18
D
D
A,
B
OUT
OUT
DB17
t25
DB14
DB13
DB0
t28
t29
FRSTDATA
Figure 6. Serial Read Operation
Rev. A | Page 10 of 36
Data Sheet
AD7609
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
AVCC to AGND
VDRIVE to AGND
−0.3 V to +7 V
−0.3 V to AVCC + 0.3 V
16.5 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
10 mA
Analog Input Voltage to AGND1
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except
Supplies1
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.
Operating Temperature Range
B Version
Storage Temperature Range
Junction Temperature
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec)
Table 5. Thermal Resistance
Package Type
−40°C to +85°C
−65°C to +150°C
150°C
θJA
θJC
Unit
64-Lead LQFP
45
11
°C/W
240(+0)°C
ESD CAUTION
Pb-Free Temperature, Soldering Reflow 260(+0)°C
ESD (All Pins Except Analog Inputs)
ESD (Analog Input Pins Only)
2 kV
7 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. A | Page 11 of 36
AD7609
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
AV
48
AV
CC
CC
ANALOG INPUT
PIN 1
2
3
47 AGND
46
AGND
OS 0
DECOUPLING CAPACITOR PIN
POWER SUPPLY
REFGND
4
5
45
44
43
42
41
40
39
38
37
36
OS 1
OS 2
REFCAPB
REFCAPA
REFGND
REFIN/REFOUT
AGND
GROUND PIN
6
DATA OUTPUT
PAR/SER SEL
AD7609
7
STBY
TOP VIEW
DIGITAL OUTPUT
DIGITAL INPUT
(Not to Scale)
8
RANGE
9
AGND
CONVST A
CONVST B
RESET
REFERENCE INPUT/OUTPUT
10
11
12
13
REGCAP
AV
CC
AV
CC
RD/SCLK
REGCAP
CS
BUSY 14
35 AGND
FRSTDATA 15
34 REF SELECT
33 DB15
DB0
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Type1 Mnemonic Description
1, 37, 38, 48
P
AVCC
Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.
2, 26, 35,
40, 41, 47
P
AGND
Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7609. All
analog input signals and external reference signals should be referred to these pins. All six of these
AGND pins should connect to the AGND plane of a system.
23
P
VDRIVE
Logic Power Supply Input. The voltage (2.3 V to 5 V) supplied at this pin determines the operating
voltage of the interface. This pin is nominally at the same supply as the supply of the host interface
(that is, DSP, FPGA).
36, 39
P
REGCAP
Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 μF capacitor. The voltage on these output pins is in the
range of 2.5 V to 2.7 V.
49, 51, 53,
55, 57, 59,
61, 63
50, 52, 54,
56, 58, 60,
62, 64
AI+
AI−
REF
V1+ to V8+ Analog Input V1+ to Analog Input V8+. These pins are the positive terminal of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin.
V1− to V8− Analog Input V1− to Analog Input V8−. These are the negative terminals of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin. The signal
on this pin should be 180° out of phase with the corresponding Vx+ pin.
42
REFIN/
REFOUT
Reference Input/ Reference Output. The on-chip reference of 2.5 V is available on this pin for external
use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by
setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this
input. See the Internal/External Reference section. Decoupling is required on this pin for both the
internal or external reference options. A 10 µF capacitor should be applied from this pin to ground
close to the REFGND pins.
34
DI
REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal
reference is selected and is enabled. If this pin is set to logic low, the internal reference is disabled and
an external reference voltage must be applied to the REFIN/REFOUT pin.
44, 45
43, 46
REF
REF
REFCAPA,
REFCAPB
REFGND
Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to
AGND using a low ESR 10 μF ceramic capacitor.
Reference Ground Pins. These pins should be connected to AGND.
Rev. A | Page 12 of 36
Data Sheet
AD7609
Pin No.
Type1 Mnemonic Description
8
DI
DI
DI
RANGE
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the
analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all
channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during a
conversion is not recommended. See the Analog Input section for more details.
Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to a logic high, the serial interface is selected.
In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins
function as serial data outputs.
6
PAR/
SER SEL
When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to AGND.
9, 10
CONVST A,
CONVST B
Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate
conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A
and CONVST B can be shorted together and a single conversion start signal applied. Alternatively,
CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be
used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only
possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions
from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to
hold. This function allows a phase delay to be created inherently between the sets of analog inputs.
13
12
DI
DI
CS
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in
parallel mode, the output bus (DB[15:0]) is enabled and the conversion result is output on the parallel
data bus lines. In serial mode, the CS is used to frame the serial read transfer and clocks out the MSB
of the serial output data.
Parallel Data Read Control Input When Parallel Interface is Selected (RD)/Serial Clock Input When
Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output
bus is enabled. In parallel mode, two RD pulses are required to read the full 18 bits of conversion
results from each channel. The first RD pulse outputs DB[17:2], and the second RD pulses outputs
DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge
takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the
conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data
outputs, DOUTA and DOUTB. For further information, see the Conversion Control section.
RD/SCLK
14
DO
BUSY
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and
indicates that the conversion process has started. The BUSY output remains high until the conversion
process for all channels is complete. The falling edge of BUSY signals that the conversion data is being
latched into the output data registers and will be available to be read after a time, t4. Any data read
while BUSY is high should be complete before the falling edge of BUSY occurs. Rising edges on
CONVST A or CONVST B have no effect while the BUSY signal is high.
11
15
DI
RESET
Reset Input. When set to logic high, the rising edge of RESET resets the AD7609. The part must receive
a RESET pulse after power-up. To achieve the specified performance after the RESET signal, the tWAKE_UP
SHUTDOWN time should elapse between power-on and the RESET pulse. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a
RESET pulse is applied during a read, the contents of the output registers reset to all zeros.
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in
three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling
edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS
as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS
falling edge. See the Conversion Control section for more details.
DO
FRSTDATA
7
DI
STBY
Standby Mode Input. This pin is used to place the AD7609 into one of two power-down modes:
standby mode or shutdown mode. The power-down mode entered depends on the state of the
RANGE pin, as shown in Table 8. When in standby mode, all circuitry except the on-chip reference,
regulators, and regulator buffers is powered down. When in shutdown mode, all circuitry is
powered down.
Rev. A | Page 13 of 36
AD7609
Data Sheet
Pin No.
Type1 Mnemonic Description
DI OS [2:0]
5, 4, 3
Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is
the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for additional details
on the oversampling mode of operation and Table 9 for oversampling bit decoding.
33
DO/DI DB15
DO/DI DB14
Parallel Output Data Bits, Data Bit 15. When PAR/SER SEL = 0, this pin acts as three-state parallel digital
output pin. This pin is used to output DB17 of the conversion result during the first RD pulse and DB1
of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pin should be
tied to AGND.
Parallel Output Data Bits, Data Bit 14. When PAR/SER SEL = 0, this pin acts as three-state parallel digital
output pin. When CS and RD are low, this pin is used to output DB16 of the conversion result during
the first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER
SEL = 1, this pin should be tied to AGND.
32
31 to 27
24
DO
DO
DO
DO
DB[13:9]
Parallel Output Data Bits, Data Bit 13 to Data Bit 9. When PAR/SER SEL = 0, these pins act as three-state
parallel digital input/output pins. When CS and RD are low, these pins are used to output DB15 to
DB11 of the conversion result during the first RD pulse and output 0 during the second RD pulse.
When PAR/SER SEL = 1, these pins should be tied to AGND.
DB7/DOUT
DB8/DOUT
DB[6:0]
A
B
Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER SEL = 0, this
pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to
output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTA and outputs
serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER SEL = 0, this
pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to
output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTB and outputs
serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bits, Data Bit 6 to Data Bit 0. When PAR/SER SEL = 0, these pins act as three-state
parallel digital input/output pins. When CS and RD are low, these pins are used to output DB8 to DB2
of the conversion result during the first RD pulse and output 0 during the second RD pulse. When
PAR/SER SEL = 1, these pins should be tied to AGND.
25
22 to 16
1 Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output.
Rev. A | Page 14 of 36
Data Sheet
AD7609
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
0
AV , V
= 5V
CC DRIVE
INTERNAL REFERENCE
±10V RANGE
fSAMPLE = 200 kSPS
fIN = 1kHz
–20
–40
1
16384 POINT FFT
SNR = 91.52dB
–60
0
THD = –111.05dB
–80
±10V RANGE
–1
–2
–3
AV , V
= 5V
CC DRIVE
= 25°C
–100
–120
–140
–160
T
A
fSAMPLE = 200 kSPS
WCP INL = 1.69 LSB
WCN INL = –1.3 LSB
0
20k
40k
60k
80k
100k
CODE
INPUT FREQUENCY (Hz)
Figure 8. FFT Plot, 10 V Range
Figure 11. Typical INL, 10 V Range
1.0
0.8
±10V RANGE
0
AV , V = 5V
CC DRIVE
T
= 25°C
AV , V
CC DRIVE
INTERNAL REFERENCE
±5V RANGE
fSAMPLE = 200kSPS
f IN = 1kHz
16,384 POINT FFT
= 5V
fSAAMPLE = 200 kSPS
WCP DNL = 0.33 LSB
WCN DNL = –0.32 LSB
0.6
–20
–40
0.4
0.2
–60
SNR = 91.12dB
0
THD = –109.77dB
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
–140
–160
0
20k
40k
60k
80k
100k
INPUT FREQUENCY (Hz)
CODE
Figure 9. FFT Plot, 5 V Range
Figure 12. Typical DNL, 10 V Range
3
2
0
AV , V
CC
= 5V
DRIVE
–20
–40
INTERNAL REFERENCE
±10V RANGE
fSAMPLE = 12.5kSPS
fIN = 1Hz
1
8192 POINT FFT
SNR = 100.71dB
THD: –111.74dB
–60
0
–80
–1
–2
–3
±5V RANGE
AV , V
CC DRIVE
= 5V
–100
–120
–140
–160
T
= 25°C
A
fSAMPLE = 200 kSPS
WCP INL = 1.56 LSB
WCN INL = –1.22 LSB
0
1
2
3
4
5
6
INPUT FREQUENCY (kHz)
CODE
Figure 10. FFT Plot, 10 V Range
Figure 13. Typical INL, 5 V Range
Rev. A | Page 15 of 36
AD7609
Data Sheet
1.0
±5V RANGE
AV , V
= 5V
0.8
CC DRIVE
40
32
T
= 25°C
fSAAMPLE = 200 kSPS
WCP INL = 0.45 LSB
WCN INL = –0.38 LSB
0.6
PFS ERROR
NFS ERROR
0.4
24
0.2
16
0
8
–0.2
–0.4
–0.6
–0.8
–1.0
0
–8
–16
–24
–32
–40
±10V RANGE
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
–40
–25
–10
5
20
35 50 65 80
TEMPERATURE (°C)
CODE
Figure 17. NFS and PFS Error Matching
Figure 14. Typical DNL, 5 V Range
10
8
80
60
40
±10V RANGE
6
20
±5V RANGE
4
0
–20
–40
–60
AV , V
= 5V
2
CC DRIVE
fSAMPLE = 200 kSPS
= 25°C
T
A
EXTERNAL REFERENCE
SOURCE RESISTANCE IS MATCHED ON
THE V– INPUT
0
200kSPS
AV , V
= 5V
CC DRIVE
±10V AND ±5V RANGE
EXTERNAL REFERENCE
35 50 65 80
TEMPERATURE (°C)
–2
–80
–40
0
20k
40k
60k
80k
100k
120k
–25
–10
5
20
SOURCE RESISTANCE (Ω)
Figure 18. PFS and NFS Error vs. Source Resistance
Figure 15. NFS Error vs. Temperature
105
80
60
AV , V
= 5V
fSAMPLE CHANGES WITH OS RATE
= 25°C
CC DRIVE
T
A
100
95
INTERNAL REFERENCE
±10V RANGE
40
20
0
±5V RANGE
±10V RANGE
90
–20
–40
–60
NO OS
OS × 2
OS × 4
OS × 8
OS × 16
OS × 32
OS × 64
85
200kSPS
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
35 50 65 80
TEMPERATURE (°C)
80
–80
–40
10
100
10k
INPUT FREQUENCY (Hz)
10k
100k
–25
–10
5
20
Figure 19. SNR vs. Input Frequency, 10 V Range
Figure 16. PFS Error vs. Temperature
Rev. A | Page 16 of 36
Data Sheet
AD7609
8
6
105
AV , V
= 5V
fSAMPLE CHANGES WITH OS RATE
= 25°C
CC DRIVE
T
A
100
95
INTERNAL REFERENCE
±5V RANGE
4
2
0
90
±5V RANGE
NO OS
OS × 2
OS × 4
OS × 8
OS × 16
OS × 32
OS × 64
–2
–4
–6
±10V RANGE
85
80
200 kSPS
AV ,V
= 5V
CC DRIVE
EXTERNAL REFERENCE
10
100
10k
INPUT FREQUENCY (Hz)
10k
100k
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 23. Bipolar Zero Code Error vs. Temperature
Figure 20. SNR vs. Input Frequency, 5 V Range
–60
–70
±10V RANGE
16
12
8
AV , V
= 5V
CC DRIVE
T
= 25°C
fSAAMPLE = 200 kSPS
±5V RANGE
±10V RANGE
R
MATCHED
SOURCE
ON V +, V – INPUTS
x
x
–80
4
–90
0Ω
10Ω
0
500Ω
1.2kΩ
5kΩ
–100
–110
–120
–4
–8
–12
10kΩ
200kSPS
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
35 50 65 80
TEMPERATURE (°C)
1
10
100
–16
–40
FREQUENCY (kHz)
–25
–10
5
20
Figure 24. Bipolar Zero Code Error Matching Between Channels
Figure 21. THD vs. Input Frequency for Various Source Impedances,
10 V Range
–50
–40
AV , V
CC DRIVE
INTERNAL REFERENCE
AD7609 RECOMMENDED DECOUPLING USED
= 5V
±5V RANGE
–60
–70
AV , V
= 5V
–50
–60
CC DRIVE
T
= 25°C
fSAAMPLE = 200 kSPS
fSAMPLE = 200kSPS
T
= 25°C
A
R
MATCHED
SOURCE
ON V +, V – INPUTS
–80
x
x
±10V RANGE
–70
–90
±5V RANGE
–80
–100
–110
–120
–130
–140
0Ω
10Ω
500Ω
1.2kΩ
5kΩ
–90
–100
–110
–120
10kΩ
0
20
40
60
80
100
120
140
160
1
10
100
NOISE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 25. Channel-to-Channel Isolation
Figure 22. THD vs. Input Frequency for Various Source Impedances,
5 V Range
Rev. A | Page 17 of 36
AD7609
Data Sheet
110
105
100
95
22
20
18
16
14
12
10
8
±10V RANGE
±5V RANGE
90
AV = V
CC DRIVE
= 5V
AV , V
= 5V
CC DRIVE
T
= 25°C
85
80
A
T
= 25°C
A
INTERNAL REFERENCE
INTERNAL REFERENCE
fSAMPLE VARIES WITH OS RATE
fSAMPLE SCALES WITH OS RATIO
NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64
OVERSAMPLING RATIO
NO OS
OS × 2
OS × 4
OS × 8
OS × 16 OS × 32 OS × 64
OVERSAMPLING RATIO
Figure 26. Dynamic Range vs. Oversampling Ratio
Figure 29. Supply Current vs. Oversampling Rate
140
130
120
110
100
90
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
AV
= 5.25V
CC
AV
AV
= 5V
CC
CC
±10V RANGE
±5V RANGE
= 4.75V
80
AV , V
= 5V
CC DRIVE
INTERNAL REFERENCE
AD7609 RECOMMENDED DECOUPLING USED
70
fSAMPLE = 200kSPS
T
= 25°C
A
60
0
100 200 300 400 500 600 700 800 900 1000 1100
–40
–25
–10
5
20
35
50
65
80
AV
NOISE FREQUENCY (kHz)
CC
TEMPERATURE (°C)
Figure 27. Reference Output Voltage vs. Temperature for Different Supply
Voltages
Figure 30. PSRR
10
0
AV , V
CC DRIVE
= 5V
AV , V
= 5V
CC DRIVE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T = 25°C
fSAAMPLE = 200kSPS
fSAMPLE = 200kSPS
INTERNAL REFERENCE
5
0
±5V RANGE
–5
±10V RANGE
+25°C V+
+25°C V–
+85°C V–
+85°C V+
–40°C V–
–40°C V+
–10
–15
–20
10
100
1k
FREQUENCY (Hz)
10k
100k
–15
–10
–5
0
5
10
15
20
DIFFERENTIAL ANALOG INPUT VOLTAGE (Vx+ – (Vx–)) (V)
Figure 28. Analog Input Current vs. Input Voltage Over Temperature
Figure 31. CMRR vs. Common-Mode Ripple Frequency
Rev. A | Page 18 of 36
Data Sheet
AD7609
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
Integral Nonlinearity
The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2, excluding dc). The ratio
depends on the number of quantization levels in the digitization
process: the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a ½ LSB below the first code
transition, and full scale at ½ LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Code Error
The deviation of the midscale transition (all 1s to all 0s) from
the ideal VIN voltage, that is, AGND.
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for an 18-bit converter, this is 110.12 dB.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the harmonics to the fundamental.
For the AD7609, it is defined as
Bipolar Zero Code Error Match
The difference in bipolar zero code error between any two input
channels.
THD (dB) =
Positive Full-Scale Error
2
2
2
2
2
2
2
2
The last transition (from 011 . . . 10 to 011 . . . 11 in twos
complement coding) should occur for an analog voltage 1½
LSB below the nominal full scale (9.99977 V for the 10 V
range and 4.99988 V for the 5 V range). The positive full-scale
error is the deviation of the actual level of the last transition
from the ideal level.
V2 +V3 +V4 +V5 +V6 +V7 +V8 +V9
20log
V1
where:
V1 is the rms amplitude of the fundamental.
V2 to V9 are the rms amplitudes of the second through ninth
harmonics.
Positive Full-Scale Error Match
The difference in positive full-scale error between any two input
channels.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.
Negative Full-Scale Error
The first transition (from 100 . . . 00 to 100 . . . 01 in twos
complement coding) should occur for an analog voltage ½ LSB
above the negative full scale (−9.999923 V for the 10 V range
and −4.9999618 for the 5 V range). The negative full-scale
error is the deviation of the actual level of the first transition
from the ideal level.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m, n = 0,
1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n is equal to 0. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Negative Full-Scale Error Match
The difference in negative full-scale error between any two
input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within 1 LSB, after the end of the conversion.
See the Track-and-Hold Amplifiers section for more details.
The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in decibels (dB).
Rev. A | Page 19 of 36
AD7609
Data Sheet
Power Supply Rejection (PSR)
Channel-to-Channel Isolation
Variations in power supply affect the full-scale transition but
not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. The power
supply rejection ratio is defined as the ratio of the power in
the ADC output at full-scale frequency, f, to the power of a
200 mV p-p sine wave applied to the ADC VDD and VSS supplies
of Frequency fS.
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
10 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 1 kHz signal.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC
common-mode input at full-scale frequency, f, to the power in
the output of a full-scale p-p sine wave applied to the common-
mode voltage of VINX+ and VINX− of frequency, fS,
PSRR (dB) = 10 log (Pf/PfS)
where:
Pf is equal to the power at Frequency f in the ADC output.
PfS is equal to the power at Frequency fS coupled onto the VDD
and VSS supplies.
CMRR (dB) = 20 log (Pf/PfS)
where:
Pf is equal to the power at Frequency f in the ADC input.
PfS is equal to the power at Frequency fS in the ADC output.
Rev. A | Page 20 of 36
Data Sheet
AD7609
THEORY OF OPERATION
Analog Input Clamp Protection
CONVERTER DETAILS
Figure 32 shows the analog input structure of the AD7609.
Each AD7609 analog input contains clamp protection circuitry.
Despite a single 5 V supply operation, this analog input clamp
protection allows for an input overvoltage up to 16.5 V.
The AD7609 is a data acquisition system that employs a high
speed, low power, charge redistribution successive approxima-
tion analog-to-digital converter (ADC) and allows the
simultaneous sampling of eight true differential analog input
channels. The analog inputs on the AD7609 can accept true
bipolar input signals. The RANGE pin is used to select either
10 V or 5 V as the input range. The AD7609 operates from
a single 5 V supply.
R
FB
1MΩ
Vx+
Vx–
CLAMP
CLAMP
1MΩ
SECOND-
ORDER
LPF
The AD7609 contains input clamp protection, input signal
scaling amplifiers, a second-order antialiasing filter, track-and-
hold amplifiers, an on-chip reference, reference buffers, a high
speed ADC, a digital filter, and high speed parallel and serial
interfaces. Sampling on the AD7609 is controlled using
CONVST x signals.
R
FB
Figure 32. Analog Input Circuitry
Figure 33 shows the current vs. voltage characteristic of the
clamp circuit. For input voltages up to 16.5 V, no current flows
in the clamp circuit. For input voltages above 16.5 V, the
AD7609 clamp circuitry turns on and clamps the analog input
to 16.5 V. A series resister should be placed on the analog
input channels to limit the current to 10 mA for input voltages
above 16.5 V. In an application where there is a series resistance
on an analog input channel, VINx+, a corresponding resistance
is required on the VINx− channel (see Figure 34). If there is no
corresponding resister on the Vx− channel, this results in an
offset error on that channel. It is recommended that the input
overvoltage clamp protection circuitry be used to protect the
AD7609 against transient overvoltage events. It is not recom-
mended to leave the AD7609 in a condition where the clamp
protection circuitry is active (in normal or power-down
conditions) for extended periods because this may degrade the
bipolar zero code error performance of the AD7609.
ANALOG INPUT
Analog Input Ranges
The AD7609 can handle true bipolar input voltages. The logic
level on the RANGE pin determines the analog input range of
all analog input channels. If this pin is tied to a logic high, the
analog input range is 10 V for all channels. If this pin is tied
to a logic low, the analog input range is 5 V for all channels.
A logic change on this pin has an immediate effect on the
analog input range; however, there is a settling time of 80 µs
typically, in addition to the normal acquisition time requirement.
The recommended practice is to hardwire the RANGE pin
according to the desired input range for the system signals.
During normal operation, the applied analog input voltage should
remain within the analog input range selected via the RANGE
pin. A RESET pulse must be applied to the part to ensure the
analog input channels are configured for the range selected.
AV , V
CC DRIVE
= 5V
30
20
T
= 25°C
A
10
When in a power-down mode, it is recommended to tie the
analog inputs together or both analog input pins (Vx+, Vx−) to
GND. As per the Analog Input Clamp Protection section, the
overvoltage clamp protection is recommended for use in
transient overvoltage conditions, and should not remain active
for extended periods. Stressing the analog inputs outside of
these conditions may degrade the Bipolar Zero Code error and
THD performance of the AD7609.
0
–10
–20
–30
–40
–50
–20
–15
–10
–5
0
5
10
15
20
Analog Input Impedance
SOURCE VOLTAGE (V)
The analog input impedance of the AD7609 is 1 MΩ. This is a
fixed input impedance and does not vary with the AD7609 sam-
pling frequency. This high analog input impedance eliminates
the need for a driver amplifier in front of the AD7609 allowing
for direct connection to the source or sensor. With the need for
a driver amplifier eliminated, bipolar supplies can be removed
from the signal chain, which are often a source of noise in a system.
Figure 33. Input Protection Clamp Profile
R
FB
AD7609
1MΩ
1MΩ
R
R
+10V
VINx+
VINx–
CLAMP
CLAMP
–10V
+10V
C
–10V
R
FB
Figure 34. Input Resistance Matching on the Analog Input
Rev. A | Page 21 of 36
AD7609
Data Sheet
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 µs on the AD7609. The
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, or serial
interface after BUSY goes low; or, alternatively, data from the
previous conversion can be read while BUSY is high. Reading data
from the AD7609 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. With a VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB
when reading during a conversion.
Analog Input Antialiasing Filter
An analog antialiasing filter is also provided on the AD7609.
The filter is a second-order Butterworth. Figure 35 and
Figure 36 show the frequency and phase response respectively
of the analog antialiasing filter. In the 5 V range, the −3 dB
frequency is typically 23 kHz. In the 10 V range, the −3 dB
frequency is typically 32 kHz.
0
10V DIFF
–5
5V DIFF
–10
–15
–20
–25
ADC TRANSFER FUNCTION
The output coding of the AD7609 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/262,144 for the AD7609. The FSR for the AD7609 is 40 V
for the 10 V range and 20 V for the 5 V range. The ideal
transfer characteristic for the AD7609 is shown in Figure 37.
TEMP
0.1dB
3dB
–40°C 13,354Hz 33,520Hz
10V 25°C 12,769Hz 32,397Hz
85°C 12,427Hz 31,177Hz
–30
–35
–40°C 10,303Hz 24,365Hz
5V
25°C
85°C
9619Hz 23,389Hz
9326Hz 22,607Hz
–40
100
1k
10k
100k
V+ ± (V–)
10V
V+ ± (V–)
5V
REF
2.5V
REF
2.5V
±10V CODE =
× 131,072 ×
FREQUENCY (Hz)
Figure 35. Analog Antialiasing Filter Frequency Response
±5V CODE =
× 131,072 ×
14
13
12
11
10
9
011...111
011...110
+FSR – (–FSR)
218
000...001
000...000
111...111
LSB =
±5V RANGE
±10V RANGE
8
7
100...010
100...001
100...000
6
5
–FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB
4
ANALOG INPUT
3
Figure 37. AD7609 Transfer Characteristic
AV , V
= 5V
fSAMPLE = 200kSPS
= 25°C
CC DRIVE
2
1
The LSB size is dependent on the analog input range selected
(see Table 7).
T
A
0
10
1k
10k
100k
INPUT FREQUENCY (Hz)
Table 7. Output Codes and Ideal Input Values
Figure 36. Analog Antialiasing Filter Phase Response
Analog
Analog Input
(V+ − (V−)
Input
V+ − (V−)
Digital
Output
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7609 allow the ADC to
accurately acquire an input sine wave of full-scale amplitude
to 18-bit resolution. The track-and-hold amplifiers sample
their respective inputs simultaneously on the rising edge of
CONVST x. The aperture time for track-and-hold (that is, the
delay time between the external CONVST x signal and the
track-and-hold actually going into hold) is well matched, by design,
across all eight track-and-holds on one device and from device
to device. This matching allows more than one AD7609 device
to be sampled simultaneously in a system.
Description
FSR − 0.5 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
−FSR + 1 LSB
−FSR
10 V Range
5 V Range
Code (Hex)
+19.99992 V
+152.58 µV
0 V
−152.58 µV
−19.99984 V
−20 V
9.999961 V
76 µV
0 V
−76 µV
−9.99992 V
−10 V
0x1FFFF
0x00001
0x00000
0x3FFFF
0x20001
0x20000
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode and the acquisition time
for the next set of conversions begins.
Rev. A | Page 22 of 36
Data Sheet
AD7609
REFIN/REFOUT
INTERNAL/EXTERNAL REFERENCE
SAR
The AD7609 contains an on-chip 2.5 V band gap reference. The
REFIN/REFOUT pin allows access to the 2.5 V reference that
generates the on-chip 4.5 V reference internally, or it allows an
external reference of 2.5 V to be applied to the AD7609. An
externally applied reference of 2.5 V is also amplified to 4.5 V using
the internal buffer. This 4.5 V buffered reference is the reference
used by the SAR ADC.
REFCAPB
REFCAPA
BUF
10µF
2.5V
REF
Figure 38. Reference Circuitry
The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference and the external reference.
If this pin is set to logic high, the internal reference is selected
and is enabled; if this pin is set to logic low, the internal refer-
ence is disabled and an external reference voltage must be
applied to the REFIN/REFOUT pin. The internal reference
buffer is always enabled. After a reset, the AD7609 operates in
the reference mode selected by the REF SELECT pin. Decoupling
is required on the REFIN/REFOUT pin for both the internal
or external reference options. A 10 µF ceramic capacitor is
required on the REFIN/REFOUT to ground close to the
REFGND pins. The AD7609 contains a reference buffer
configured to amplify the REF voltage up to ~4.5 V, as shown
in Figure 38. The REFCAPA and REFCAPB pins must be
shorted together externally and a ceramic capacitor of 10 μF
applied to REFGND to ensure the reference buffer is in
closed-loop operation. The reference voltage available at the
REFIN/REFOUT pin is 2.5 V.
V
DRIVE
AD7609
AD7609
AD7609
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
+
10µF
100nF
100nF
Figure 39. Single External Reference Driving Multiple AD7609
REFIN/REFOUT Pins
AD7609
AD7609
AD7609
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
100nF
100nF
100nF
When the AD7609 is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin. For
applications using multiple AD7609 devices, the following
configurations are recommended depending on the application
requirements.
ADR421
0.1µF
Figure 40. Internal Reference Driving Multiple AD7609 REFIN Pins
External Reference Mode
One ADR421 external reference can be used to drive the
REFIN/REFOUT pins of all AD7609 devices (see Figure 39). In
this configuration, each AD7609 REFIN/REFOUT pin should
be decoupled with a 100 nF decoupling capacitor.
Internal Reference Mode
One AD7609 device, configured to operate in the internal
reference mode, can be used to drive the remaining AD7609
devices, which are configured to operate in external reference
mode (see Figure 40). The REFIN/REFOUT pin of the AD7609,
configured in internal reference mode, should be decoupled
using a 10 µF ceramic decoupling capacitor. The other AD7609
devices, configured in external reference mode, should use a
100 nF decoupling capacitor on their REFIN/REFOUT pins.
Rev. A | Page 23 of 36
AD7609
Data Sheet
TYPICAL CONNECTION DIAGRAM
POWER-DOWN MODES
Figure 41 shows the typical connection diagram for the
AD7609. There are four AVCC supply pins on the part that
can be tied together and decoupled using a 100 nF capacitor at
each supply pin and a 10 µF capacitor at the supply source. The
AD7609 can operate with the internal reference or an externally
applied reference. In this configuration, the AD7609 is config-
ured to operate with the internal reference. When using a single
AD7609 device on the board, the REFIN/REFOUT pin should
be decoupled with a 10 µF capacitor. In an application with
multiple AD7609 devices, see the Internal/External Reference
section. The REFCAPA and REFCAPB pins are shorted together
and decoupled with a 10 µF ceramic capacitor.
There are two power-down modes available on the AD7609.
STBY
or one of the two power-down modes. The two power-down
modes available are standby mode and shutdown mode. The
power-down mode is selected through the state of the RANGE
The
pin controls whether the AD7609 is in normal mode
STBY
pin when the
pin is low. Table 8 shows the configurations
required to choose the desired power-down mode. When the
AD7609 is placed in standby mode, the current consumption is
8 mA maximum and power-up time is approximately 100 µs
because the capacitor on the REFCAPA/REFCAPB pins must
charge up. In standby mode, the on-chip reference and
regulators remain powered up and the amplifiers and ADC core
are powered down. When the AD7609 is placed in shutdown
mode, the current consumption is 11 µA maximum and power
up time is about 13 ms. In shutdown mode, all circuitry
is powered down. When the AD7609 is powered up from
shutdown mode, a reset signal must be applied to the AD7609
after the required power-up time has elapsed.
The VDRIVE supply is connected to the same supply as the pro-
cessor. The voltage on VDRIVE controls the voltage value of the
output logic signals. For layout, decoupling, and grounding
hints, see the Layout Guidelines section.
After supplies are applied to the AD7609, a reset should be
applied to the AD7609 to ensure that it is configured for the
correct mode of operation.
Table 8. Power-Down Mode Selection
STBY
Power-Down Mode
Standby
Shutdown
RANGE
0
0
1
0
ANALOG SUPPLY
VOLTAGE 5V1
DIGITAL SUPPLY
VOLTAGE +2.3V TO +5V
+
1µF
10µF
100nF
100nF
2
AV
V
DRIVE
REFIN/REFOUT
REGCAP
CC
REFCAPA
PARALLEL
INTERFACE
+
DB0 TO DB15
10µF
REFCAPB
REFGND
CONVST A, B
CS
RD
BUSY
V1+
V1–
V2+
V2–
V3+
V3–
V4+
V4–
V5+
V5–
V6+
V6–
V7+
V7–
V8+
V8–
AD7609
RESET
OS 2
OS 1
OS 0
OVERSAMPLING
EIGHT DIFFERENTIAL
ANALOG INPUT PAIRS
REF SELECT
PAR/SER SEL
V
DRIVE
RANGE
STBY
V
DRIVE
AGND
1
DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).
CC
CC
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV
PIN 37 AND PIN 38.
CC
2
DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
Figure 41. Typical Connection Diagram
Rev. A | Page 24 of 36
Data Sheet
AD7609
Simultaneously Sampling Two Sets of Channels
CONVERSION CONTROL
The AD7609 also allows the analog input channels to be
sampled simultaneously in two sets. This can be used in power
line protection and measurement systems to compensate for
phase differences between PT and CT transformers. In a 50 Hz
system, this allows for up to 9° of phase compensation, and in a
60 Hz system, it allows for up to 10° of phase compensation.
Simultaneous Sampling on All Analog Input Channels
The AD7609 allows simultaneous sampling of all analog input
channels. All channels are sampled simultaneously when both
CONVST x pins (CONVST A, CONVST B) are tied together. A
single CONVST x signal is used to control both CONVST x inputs.
The rising edge of this common CONVST x signal initiates
simultaneous sampling on all analog input channels.
This is accomplished by pulsing the two CONVST x pins inde-
pendently and is only possible if oversampling is not in use.
CONVST A is used to initiate simultaneous sampling of the first
set of channels (V1 to V4). CONVST B is used to initiate
simultaneous sampling on the second set of analog input
channels (V5 to V8), as illustrated in Figure 42. On the rising
edge of CONVST A, the track-and-hold amplifiers for the first
set of channels are placed into hold mode. On the rising edge
of CONVST B, the track-and-hold amplifiers for the second set
of channels are placed into hold mode. The conversion process
begins after both rising edges of CONVST x have occurred;
therefore, BUSY goes high on the rising edge of the later
CONVST x signal. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus or the serial
data lines, DOUTA and DOUTB. There is no change to the data
read process when using two separate CONVST x signals.
The AD7609 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is tCONV. The BUSY signal indicates to the user when
conversions are in progress, so that when the rising edge of
CONVST x is applied, BUSY goes logic high and transitions low
at the end of the entire conversion process. The falling edge of
the BUSY signal is used to place all eight track-and-hold
amplifiers back into track mode. The falling edge of BUSY also
indicates that the new data can now be read from the parallel
bus (DB[15:0]) or the serial data lines, DOUTA and DOUTB.
Connect all unused analog input channel to AGND. The results
for any unused channels are still included in the data read
because all channels are always converted.
V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD
t5
CONVST A
CONVST B
AD7609 CONVERTS
ON ALL 8 CHANNELS
BUSY
tCONV
CS, RD
V1
V2
V8
DATA: DB[15:0]
FRSTDATA
Figure 42. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode
Rev. A | Page 25 of 36
AD7609
Data Sheet
DIGITAL INTERFACE
The AD7609 provides two interface options: a parallel interface
and a high speed serial interface. The required interface mode is
AD7609
INTERRUPT
BUSY 14
PAR
selected via the
/SER SEL pin.
13
CS
RD
12
DIGITAL
HOST
The operation of the interface modes is described in the
following sections.
33:16
DB[15:0]
CS
Figure 43. AD7609 Interface Diagram: One AD7609 Using the Parallel Bus;
RD
PARALLEL INTERFACE (PAR/SER SEL = 0)
and
Shorted Together
Data can be read from the AD7609 via the parallel data bus with
SERIAL INTERFACE (PAR/SER SEL = 1)
CS
RD
standard and
signals. To read the data over the parallel
PAR
CS
RD
and
bus, the
/SER SEL pin should be tied low. The
To read data back from the AD7609 over the serial interface,
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
PAR
CS
the
/SER SEL pin should be tied high. The
and SCLK
signals are used to transfer data from the AD7609. The AD7609
has two serial data output pins, DOUTA and DOUTB. Data can be
read back from the AD7609 using one or both of these DOUT
lines. For the AD7609, conversion results from Channel V1 to
Channel V4 first appear on DOUTA, whereas conversion results
from Channel V5 to Channel V8 first appear on DOUTB.
CS
RD
impedance state when both
and
are logic low.
CS
CS
CS
The rising edge of the
the falling edge of the
high impedance state.
input signal three-states the bus and
input signal takes the bus out of the
is the control signal that enables the
data lines; it is the function that allows multiple AD7609
CS
CS
The
OUTB) out of three-state and clocks out the MSB of the conver-
sion result. The rising edge of SCLK clocks all subsequent data
CS
falling edge takes the data output lines (DOUTA and
devices to share the same parallel data bus. The
signal can
signal can be used to
D
RD
be permanently tied low, and the
access the conversion results, as shown in Figure 4. A read
operation of new data can take place after the BUSY signal
goes low (Figure 2), or, alternatively, a read operation of data
from the previous conversion process can take place while
BUSY is high (Figure 3).
bits onto the serial data outputs, DOUTA and DOUTB. The
input can be held low for the entire serial read or it can be
pulsed to frame each channel read of 18 SCLK cycles.
Figure 44 shows a read of eight simultaneous conversion results
using two DOUT lines on the AD7609. In this case, a 72 SCLK
transfer is used to access data from the AD7609 and
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using only one DOUT line, in which case DOUTA is recom-
mended to access all conversion data, because the channel data
is output in ascending order. For the AD7609 to access all eight
conversion results on one DOUT line, a total of 144 SCLK cycles
are required. These 144 SCLK cycles can be framed by one
signal or each group of 18 SCLK cycles can be individually
RD
The
results register. Two
18-bit conversion result from each channel. Applying a
RD RD
pin clocks the
pin is used to read data from the output conversion
CS
is held
RD
pulses are required to read the full
sequence of 16
conversion results out from each channel onto the parallel
RD
pulses to the AD7609
output bus, DB[15:0], in ascending order. The first
edge after BUSY goes low clocks out DB[17:2] of the V1 result,
RD
falling
CS
the next
falling edge updates the bus with DB[1:0] of the V1
RD
result. It takes 16
pulses to read the eight 18-bit conversion
CS
framed by the
signal. The disadvantage of using only one
th
RD
results from the AD7609. The 16 falling edge of
the DB[1:0] conversion result for Channel V8. When the
clocks out
RD
D
OUT line is that the throughput rate is reduced if reading after
conversion. The unused DOUT line should be left unconnected
in serial mode. For the AD7609, if DOUTB is to be used as a
single DOUT line, the channel results are output in the following
order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA
indicator returns low after V5 is read on DOUTB.
signal is logic low, it enables the data conversion result from
each channel to be transferred to the digital host (DSP, FPGA).
When there is only one AD7609 in a system/board and it
does not share the parallel bus, data can be read using only one
CS
RD
control signal from the digital host. The
can be tied together, as shown in Figure 5. In this case, the data
CS RD
and
signals
bus comes out of three-state on the falling edge of
/
. The
signal allows the data to be clocked out
of the AD7609 and to be read by the digital host. In this case,
CS RD
combined
and
CS
16
is used to frame the data transfer of each data channel and
CS
pulses are required to read the eight channels of data.
Rev. A | Page 26 of 36
Data Sheet
AD7609
Figure 6 shows the timing diagram for reading one channel of
are read on DOUTB, the FRSTDATA output does not go high
CS
when V1 is being output on this serial data output pin. It only
goes high when V1 is available on DOUTA (and this is when V5
is available on DOUTB).
data, framed by the
The SCLK input signal provides the clock source for the serial
CS
signal, from the AD7609 in serial mode.
read operation. goes low to access the data from the AD7609.
CS
The falling edge of
clocks out the MSB of the 18-bit conversion result. This MSB
CS
takes the bus out of three-state and
READING DURING CONVERSION
Data can be read from the AD7609 while BUSY is high
and conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read can be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a VDRIVE of 3.3 V to 5.25 V.
is valid on the first falling edge of the SCLK after the
edge. The subsequent 17 data bits are clocked out of the
falling
AD7609 on the SCLK rising edge. Data is valid on the SCLK
falling edge. Eighteen clock cycles must be provided to the
AD7609 to access each conversion result.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS
CS
takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
Data can be read from the AD7609 at any time other than on
the falling edge of BUSY because this is when the output data
registers are updated with the new conversion data. t6, outlined
in Table 3, should be observed in this condition.
DOUTA output data line. The FRSTDATA output returns to a
logic low following the 18th SCLK falling edge. If all channels
CS
72
SCLK
D
D
A
B
V1
V5
V2
V6
V3
V7
V4
V8
OUT
OUT
Figure 44. AD7609 Serial Interface with Two DOUT Lines
Rev. A | Page 27 of 36
AD7609
Data Sheet
The CONVST A and CONVST B pins must be tied/driven
DIGITAL FILTER
together when oversampling is turned on. When the over-
sampling function is turned on, the BUSY high time for the
conversion process extends. The actual BUSY high time
depends on the oversampling rate selected; the higher the
oversampling rate, the longer the BUSY high, or total
conversion time, see Table 9.
The AD7609 contains an optional digital filter. This digital filter
is a first-order sinc filter. This digital filter should be used in
applications where slower throughput rates are used or where
higher signal-to-noise ratio or dynamic range is desirable. The
oversampling ratio of the digital filter is controlled using the
oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB
control bit and OS 0 is the LSB control bit. Table 9 provides
the oversampling bit decoding to select the different oversample
rates. The OS pins are latched on the falling edge of BUSY.
This sets the oversampling rate for the next conversion (see
Figure 45). In addition to the oversampling function, the output
result is decimated to 18-bit resolution.
Figure 46 shows that the conversion time extends as the over-
sampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 µs. Figure 46 shows OS × 2
and OS × 4; for a 10 kSPS example, there is adequate cycle time
to further increase the oversampling rate and yield greater
improvements in SNR performance. In an application where
the initial sampling or throughput rate is at 200 kSPS, for
example, and oversampling is turned on, the throughput rate
must be reduced to accommodate the longer conversion time
and to allow for the read. To achieve the fastest throughput
rate possible when oversampling is turned on, the read can be
performed during the BUSY high time. The falling edge of BUSY
is used to update the output data registers with the new conver-
sion data; therefore, the reading of conversion data should not
occur on this edge. Figure 47 to Figure 53 illustrate the effect of
oversampling on the code spread in a dc histogram plot. As the
oversample rate is increased, the spread of codes is reduced. (In
Figure 47 to Figure 53, AVCC = VDRIVE = 5 V and the sampling
rate was scaled with OS ratio.)
If the OS pins are set to select an OS ratio of 8, the next
CONVST x rising edge takes the first sample for each channel
and the remaining seven samples for all channels are taken with
an internally generated sampling signal. These samples are then
averaged to yield an improvement in SNR performance. Table 9
shows typical SNR performance for both the 10 V and the
5 V ranges. As Table 9 indicates, there is an improvement in
SNR as the OS ratio increases. As the OS ratio increases, the
3 dB frequency is reduced and the allowed sampling frequency
is also reduced. In an application where the required sampling
frequency is 10 kSPS, an OS ratio of up to 16 can be used. In
this case, the application sees an improvement in SNR but the
input −3 dB bandwidth is limited to ~6 kHz.
CONVST A,
CONVST B
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
CONVERSION N
CONVERSION N + 1
BUSY
OS x
tOS_HOLD
tOS_SETUP
Figure 45. OS Pin Timing
Table 9. Oversampling Bit Decoding (100 Hz Input Signal)
OS
[2:0]
OS
Ratio
SNR 5 V Range SNR 10 V Range −3 dB BW 5 V Range −3 dB BW 10 V
Maximum Throughput
CONVST x Frequency (kHz)
(dB)
90.8
93.3
95.5
98
100.6
101.8
102.7
(dB)
91.5
93.9
96.4
98.9
101
(kHz)
Range (kHz)
000
001
010
011
100
101
110
111
No OS
2
4
8
16
32
64
Invalid
22
22
18.5
11.9
6
33
28.9
21.5
12
6
200
100
50
25
12.5
6.25
3.125
102
3
3
102.9
1.5
1.5
Rev. A | Page 28 of 36
Data Sheet
AD7609
tCYCLE
CONVST A,
CONVST B
tCONV
19µs
9µs
4µs
OS = 0
OS = 2
OS = 4
BUSY
CS
t4
t4
t4
RD
DATA:
DB[15:0]
Figure 46. AD7609—No Oversampling, Oversampling × 4, and Oversampling × 8 Using Read After Conversion
3000
1600
OVERSAMPLING BY 4
NO OVERSAMPLING
1384
1373
1400
1200
1000
800
600
400
200
0
2394
2500
2000
1500
1000
500
2363
1167
1062
840
1340
727
1191
492
450
422
2
210
219
4
341
100
5
83
79
3
49
5
27
32
6
8
4
10
2
11
7
2
1
0
–5
–4
–3
–2
–1
0
1
–9 –8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
8
9
CODE
CODE
Figure 49. Histogram of Codes—OS × 4 (10 Codes)
Figure 47. Histogram of Codes—No OS (19 Codes)
4000
3500
3000
2500
2000
1500
1000
500
2000
1800
1600
1400
1200
1000
800
OVERSAMPLING BY 2
OVERSAMPLING BY 8
3392
1785
1772
1389
2397
1146
1568
788
599
600
400
317
549
214
200
229
105
15
46
41
1
15
3
12
1
2
1
0
0
–4
–3
–2
–1
0
1
2
–7 –6 –5 –4 –3 –2 –1
0
CODE
1
2
3
4
5
6
7
CODE
Figure 50. Histogram of Codes—OS × 8 (Eight Codes)
Figure 48. Histogram Of Codes—OS × 2 (15 Codes)
Rev. A | Page 29 of 36
AD7609
Data Sheet
4500
4000
3500
3000
2500
2000
1500
1000
500
When the oversampling mode is selected, this has the effect
OVERSAMPLING BY 16
of adding a digital filter function after the ADC. The different
oversampling rates and the CONVST x sampling frequency
produces different digital filter frequency profiles.
3833
3279
Figure 54 to Figure 59 show the digital filter frequency profiles
for the different oversampling rates. The combination of the
analog antialiasing filter and the oversampling digital filter can
be used to eliminate or reduce the complexity of the design of
the filter before the AD7609. The digital filtering combines
steep roll-off and linear phase response.
657
406
–2
0
AV
V
= 5V
CC
14
2
3
= 5V
0
DRIVE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–3
–1
0
1
T
= 25°C
A
10V RANGE
OS BY 2
CODE
Figure 51. Histogram of Codes—OS × 16 (Six Codes)
6000
5000
4000
3000
2000
1000
0
OVERSAMPLING BY 32
5090
2716
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 54. Digital Filter Response for OS × 2
341
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
45
–2
AV
= 5V
= 5V
CC
V
DRIVE
= 25°C
–1
0
1
T
A
CODE
10V RANGE
OS BY 4
Figure 52. Histogram of Codes—OS × 32 (Four Codes)
7000
6000
5000
4000
3000
2000
1000
0
OVERSAMPLING BY 64
5871
2245
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 55. Digital Filter Response for OS × 4
75
1
–2
–1
0
1
CODE
Figure 53. Histogram of Codes – OS × 64 (Four Codes)
Rev. A | Page 30 of 36
Data Sheet
AD7609
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AV
= 5V
= 5V
AV
= 5V
= 5V
CC
CC
V
V
DRIVE
= 25°C
DRIVE
T
T = 25°C
A
A
10V RANGE
OS BY 8
10V RANGE
OS BY 32
–100
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 56. Digital Filter Response for OS × 8
Figure 58. Digital Filter Response for OS × 32
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AV
= 5V
= 5V
AV
= 5V
CC
CC
V
V
= 5V
DRIVE
= 25°C
DRIVE
T = 25°C
A
T
A
10V RANGE
OS BY 16
10V RANGE
OS BY 64
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 57. Digital Filter Response for OS × 16
Figure 59. Digital Filter Response for OS × 64
Rev. A | Page 31 of 36
AD7609
Data Sheet
LAYOUT GUIDELINES
The printed circuit board that houses the AD7609 should be
designed so that the analog and digital sections are separated
and confined to different areas of the board.
Use at least one ground plane. It can be common or split
between the digital and analog sections. In the case of the split
plane, the digital and analog ground planes should be joined in
only one place, preferably as close as possible to the AD7609.
If the AD7609 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only one point, a star ground point, which
should be established as close as possible to the AD7609. Good
connections should be made to the ground plane. Avoid sharing
one connection for multiple ground pins. Individual vias or
multiple vias to the ground plane should be used for each
ground pin.
Figure 60. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and
REGCAP Pins
Avoid running digital lines under the devices because doing
so couples noise onto the die. Allow the analog ground plane
to run under the AD7609 to avoid noise coupling. Shield fast-
switching signals like CONVST A, CONVST B, or clocks with
digital ground to avoid radiating noise to other sections of the
board, and they should never run near analog signal paths.
Avoid crossover of digital and analog signals. Run traces on
layers in close proximity on the board at right angles to each
other to reduce the effect of feedthrough through the board.
The power supply lines to the AVCC and VDRIVE pins on the
AD7609 should use as large a trace as possible to provide low
impedance paths and reduce the effect of glitches on the power
supply lines. Where possible, use supply planes. Good connec-
tions should be made between the AD7609 supply pins and the
power tracks on the board; this should involve the use of a single
via or multiple vias for each supply pin.
Figure 61. Bottom Layer Decoupling
Good decoupling is also important to lower the supply imped-
ance presented to the AD7609 and to reduce the magnitude of
the supply spikes. Place the decoupling capacitors close to,
ideally right up against, these pins and their corresponding
ground pins. Place the decoupling capacitors for the REFIN/
REFOUT pin and the REFCAPA and REFCAPB pins as close as
possible to their respective AD7609 pins. Where possible, they
should be placed on the same side of the board as the AD7609
device. Figure 60 shows the recommended decoupling on the
top layer of the AD7609 board. Figure 61 shows bottom layer
decoupling. Bottom layer decoupling is for the four AVCC pins
and the VDRIVE pin.
Rev. A | Page 32 of 36
Data Sheet
AD7609
To ensure good device-to-device performance matching in a
system that contains multiple AD7609 devices, a symmetrical
layout between the AD7609 devices is important. Figure 62
shows a layout with two AD7609 devices. The AVCC supply
plane runs to the right of both devices. The VDRIVE supply track
runs to the left of the two AD7609 devices. The reference chip
is positioned between both AD7609 devices and the reference
voltage track runs north to Pin 42 of U1 and south to Pin 42
to U2. A solid ground plane is used. These symmetrical layout
principles can be applied to a system that contains more than
two AD7609 devices. The AD7609 devices can be placed in a
north-to-south direction with the reference voltage located
midway between the AD7609 devices and the reference track
running in the north-to-south direction similar to Figure 62.
Figure 62. Multiple AD7609 Layout, Top Layer and Supply Plane Layer
Rev. A | Page 33 of 36
AD7609
Data Sheet
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
PLANE
17
32
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7609BSTZ
AD7609BSTZ-RL
EVAL-AD7609EDZ
CED1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board for the AD7609
ST-64-2
ST-64-2
Converter Evaluation Development
1 Z = RoHS Compliant Part.
Rev. A | Page 34 of 36
Data Sheet
NOTES
AD7609
Rev. A | Page 35 of 36
AD7609
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09760-0-2/12(A)
Rev. A | Page 36 of 36
相关型号：
AD7610BCPZ
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48
ROCHESTER
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