AD7621 [ADI]
16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC; 16位， 1 LSB INL ， 3 MSPS PulSAR系列ADC
| 型号： | AD7621 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 文件： | 总26页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
16-Bit, 1 LSB INL, 3 MSPS PulSARTM ADC
a
PreliminaryTechnicalData
AD7621
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16 Bits Resolution with No Missing Codes
No Pipeline Delay ( SAR architecture )
Differential Input Range: ꢀVREF (VREF up to 2.5V)
Throughput:
3 MSPS (Wideband Warp and Warp Mode)
2 MSPS (Normal Mode)
REF
REFGND
TEMP REFBUFIN
DVDD DGND
AGND
AVDD
OVDD
AD7621
SERIAL
PORT
OGND
REF
SER/PAR
1.25 MSPS (Impulse Mode)
16
IN+
IN-
SWITCHED
CAP DAC
D[15:0]
BUSY
INL: ꢀ1 LSB Max (ꢀ0.0015% of Full-Scale)
S/(N+D): 90 dB Typ @ 100 kHz ( VREF = 2.5V )
THD: –100 dB Typ @ 100 kHz
Parallel (16 or 8bits bus) and Serial 5V/3.3V/2.5V Interface
SPI/QSPI/MICROWIRE/DSP Compatible
On-board Low Drift Reference with Buffer and Temperature
sensor
PARALLEL
INTERFACE
RD
CS
PDREF
CLOCK
PDBUF
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OB/2C
BYTESWAP
RESET
Single 2.5 V Supply Operation
WARP IMPULSE
CNVST
Power Dissipation: 100 mW Typ @ 3 MSPS
Power-Down Mode
Package: 48-Lead Quad Flat Pack (LQFP)
48-Lead Frame Chip Scale Package (LFCSP)
Speed Upgrade of the AD7677
PulSAR Selection
500 - 570
Type / kSPS 100 - 250
800 - 1000 >1000
Pseudo
AD7651
AD7650/52 AD7653
APPLICATIONS
Differential AD7660/61 AD7664/66 AD7667
Medical Instruments
High Speed Data Acquisition
Communications
Instrumentation
Spectrum Analysis
ATE
True Bipolar
AD7663
AD7675
AD7665
AD7676
AD7671
True
Differential
AD7677 AD7621
18 Bit
AD7678
AD7679
AD7654
AD7674
AD7655
Multichannel
/
Simultaneous
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. High resolution and Fast Throughput
The AD7621 is a 3 MSPS, charge redistribution,
16-bit SAR ADC ( no latency ).
The AD7621 is a 16-bit, 3 MSPS, charge redistribution
SAR, fully differential analog-to-digital converter that
operates from a single 2.5 V power supply. The part
contains a high-speed 16-bit sampling ADC, an internal
conversion clock, an internal reference buffer, error
correction circuits, and both serial and parallel system
interface ports.
2. Excellent accuracy
The AD7621 has a maximum integral nonlinearity of 1
LSB with no missing 16-bit code.
3. Single-Supply Operation
It features a very high sampling rate mode (Wideband
Warp) for undersampling applications and, for asyn-
chronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced
power mode (Impulse) where the power is scaled with
the throughput.
The AD7621 operates from a single 2.5 V supply and
typically dissipates only 100 mW. In impulse mode,
its power dissipation decreases with the throughput and
it features a power-down mode.
5. Serial or Parallel Interface
Versatile parallel (16 or 8 bits bus) or 2-wire serial
interface arrangement compatible with either 2.5V,
3.3V or 5 V logic.
It is available in a 48-lead LQFP or a 48-lead LFCSP
with operation specified from –40°C to +85°C.
REV. Pr D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
(–40ꢁC to +85ꢁC, VREF = AVDD, AVDD = DVDD = OVDD = 2.5 V, unless otherwise noted.)
AD7621–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
R E S O L U T I O N
1 6
Bits
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
VIN+ – VIN-
-VREF
–0.1
+VREF
AVDD
V
V
dB
µ A
V
IN+, VIN- to AGND
f
IN = TBD kHz
TBD
T B D
TBD MSPS Throughput
Input Impedance
See Analog Input Section
THROUGHPUT
Complete Cycle
Throughput Rate
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
SPEED
In WideBand Warp Mode
In Wideband Warp Mode
In Warp Mode
333
3
3
1
500
2
800
1.25
ns
0.1
0.001
M S P S
M S P S
ms
ns
M S P S
ns
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
0
0
M S P S
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
– 1
– 1
1 6
1
+ 1
+ 1
LSB1
L S B
Bits
Transition Noise
Gain Error, TMIN to TMAX
Gain Error Temperature Drift
Zero Error, TMIN to TMAX
Zero Error Temperature Drift
Power Supply Sensitivity
VREF
=
AVDD
0.7
L S B
% of FSR
ppm/°C
LSB
ppm/°C
L S B
2
TBD
TBD
TBD
2
TBD
TBD
T B D
AVDD = 2.5V
fIN = 100 kHz,
5%
AC ACCURACY
Signal-to-Noise
V
REF=AVDD
8 8
9 0
dB3
d B
d B
d B
d B
VREF=2.048V
fIN = 100 kHz
fIN = 100 kHz
fIN = 100 kHz,
88.3
100
–100
9 0
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
fIN = 100 kHz,–60 dB Input
3 0
5 0
d B
M H z
–3 dB Input Bandwidth
SAMPLING
Aperture Delay
DYNAMICS
1
ns
Aperture Jitter
Transient Response
Overvoltage recovery
TBD
ps rms
ns
ns
Full-Scale Step
R E F
5 0
5 0
R E F E R E N C E
External Reference Voltage Range
REF Current Drain
REF Voltage with reference buffer
Reference Buffer Input Voltage
REFBUFIN Input Current
T B D
2.048
T B D
2.048
1.2
A V D D
V
µ A
V
V
µ A
3
MSPS Throughput
REFBUFIN=1. 2V
R E F B U F I N
2
2.1
T B D
+ 1
T B D
– 1
INTERNAL REFERENCE
Internal Reference Voltage
Internal Reference Temp Drift
Internal Reference Temp Drift
REFBUFIN Line Regulation
REFBUFIN Output Resistance
Power Supply Rejection
@ 25ꢁC
T B D
1.2
T B D
V
–40ꢁC to +85ꢁC
0ꢁC to +70ꢁC
T B D
T B D
T B D
16
ppm/ꢁC
ppm/ꢁC
ppm/V
k⍀
AVDD = 2.5V
@ TBD kHz
1,000 Hours
5%
T B D
T B D
T B D
T B D
T B D
313
d B
µ s
Turn-on Settling Time
Long-term Stability
Hysterisis
ppm
ppm
k⍀
REFBUFIN Output Resistance
Temperature Pin Voltage Output
Temperature Sensitivity
@ 25ꢁC
m V
1
4.3
mV/ꢁC
k⍀
TEMP pin Output Resistance
REV. Pr D
–2–
PRELIMINARY TECHNICAL DATA
AD7621
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL
INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+1.7
– 1
+0.6
5.25
+ 1
V
V
µ A
µ A
IIH
– 1
+ 1
DIGITAL
Data Format
Pipeline Delay
OUTPUTS
Parallel or Serial 16-Bits
Conversion Results Available Immediately
After Completed Conversion
0.4
VOL
VOH
ISINK = 500 µA
ISOURCE = –500 µA
V
V
OVDD – 0.3
POWER SUPPLIES
Specified Performance
AVDD
2.37
2.37
2.3
2.5
2.5
2.63
2.63
3.6
V
V
V
DVDD
OVDD
Operating Current4
AVDD
3 MSPS Throughput
15
4.5
130
mA
mA
µA
DVDD5
OVDD5
Power Dissipation5
PDBUF high @ 3 MSPS4
PDBUF low @ 3 MSPS4
PDBUF high @ 1.25 MSPS6
PDBUF low @ 1.25 MSPS6
In Power-Down Mode7
100
108
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mW
mW
mW
mW
µW
TEMPERATURE RANGE8
Specified Performance
TMIN to TMAX
–40
+85
°C
N O T E S
1LSB means Least Significant Bit. With the 2.5
V input range, one LSB is 76.294 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4In warp mode.
5Tested in parallel reading mode.
6In impulse mode.
7With all digital inputs forced to DVDD or DGND respectively.
8Contact factory for extended temperature range.
Specifications subject to change without notice.
(–40ꢁC to +85ꢁC, AVDD = DVDD = 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 12 AND 13
Convert Pulsewidth
Time Between Conversions
t1
t2
5
ns
ns
333/500/800
Note 1
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read After
t3
t4
30
ns
ns
263/400/750
Convert
Aperture Delay
(Warp Mode/Normal Mode/Impulse Mode)
t5
t6
t7
t8
t9
1
ns
ns
ns
ns
ns
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode)
RESET Pulsewidth
10
263/400/750
263/400/750
70/100/50
10
REFER TO FIGURES 14, 15, AND 16 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
t10
ns
t11
t12
t13
20
2
ns
ns
ns
40
15
REV. Pr D
–3–
PRELIMINARY TECHNICAL DATA
AD7621
TIMING SPECIFICATIONS (continued)
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 18 AND 19 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
t14
t15
t16
t17
TBD
TBD
TBD
ns
ns
ns
ns
CNVST LOW to SYNC Delay
TBD
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
TBD
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
TBD
TBD
TBD
ns
ns
ns
ns
ns
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
See Table I
TBD
t30
TBD
ns
REFER TO FIGURES 20 AND 22 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
2
ns
ns
ns
ns
ns
ns
ns
7
TBD
TBD
12.5
5
External SCLK HIGH
External SCLK LOW
5
NOTES
1Inwarpmodeonly,themaximumtimebetweenconversionsis1ms;otherwise,thereisnorequiredmaximumtime.
2Inserialinterfacemodes,theSYNC,SCLK,andSDOUTtimingsaredefinedwithamaximumloadCLof10pF;otherwise,theloadis60pFmaximum.
3Inserialmasterreadduringconvertmode.SeeTableIforserialmasterreadafterconvertmode.
Specificationssubjecttochangewithoutnotice.
Table I. Serial clock timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
t18
t19
t19
t20
t21
t22
t23
t24
t28
t28
t28
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
T B D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–4–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
ABSOLUTE MAXIMUM RATINGS1
I
500ꢂA
Analog Inputs
OL
IN+2, IN-2, REF, REFBUFIN, TEMP, REFGND to
AGND . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
TO OUTPUT
PIN
1.4V
C
50pF*
L
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . 0.3 V
Supply Voltages
I
500ꢂA
OH
AVDD, DVDD . . . . . . . . . . . . . . . . . . . -0.3V to +2.7 V
OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +3.8 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . 2.5W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Lead Temperature Range
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
*
C
OF 10pF; OTHERWISE, THE LOAD IS 50pF MAXIMUM.
L
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
2V
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
0.8V
N O T E S
tDELAY
tDELAY
1Stresses above those listed under Absolute Maximum Ratings may
2V
2V
0.8V
cause permanent damage to the device. This is
a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
0.8V
Figure 2. Voltage Reference Levels for Timing
2See Analog Input section.
3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC
30°C/W.
=
4Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7621AST
AD7621ASTRL
AD7621ACP
AD7621ACPRL
EVAL-AD7621CB1
EVAL-CONTROL BRD32
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Evaluation Board
ST-48
ST-48
CP-48
CP-48
Controller Board
N O T E S
1This board can be used as
purposes.
a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration
2This board allows
a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7621 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING
ING!
ESD SENSITIVE
DEVICE
REV. Pr D
–5–
PRELIMINARY TECHNICAL DATA
AD7621
PIN CONFIGURATION
48-Lead LQFP and 48-Lead LFCSP
(ST-48 and CP-48)
48
47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
AGND
AVDD
36 AGND
PIN 1
IDENTIFIER
35 CNVST
NC
34
33
32
31
30
29
PD
BYTESWAP
OB/2C
RESET
CS
AD7621
TOP VIEW
WARP
RD
IMPULSE
DGND
BUSY
D15
(Not to Scale)
SER/PAR
8
9
D0
D1
28
27
26
25
10
11
12
D14
D2/DIVSCLK[0]
D3/DIVSCLK[1]
D13
D12
13 14 15 16 17 18
21 22 23 24
19 20
NC = NO CONNECT
–6–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1, 41, 42 AGND
P
P
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 2.5 V.
No Connect.
Parallel Mode Selection (8-bit/16-bit). When LOW, the LSB is output on D[7:0]
and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and
the MSB is output on D[7:0].
2, 44
3, 40
4
AVDD
NC
BYTESWAP DI
5
6
OB/2C
DI
DI
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital
output is straight binary; when LOW, the MSB is inverted resulting in a two’s
complement output from its internal shift register.
Conversion mode selection. When HIGH and IMPULSE LOW, this input selects
the fastest mode, the maximum throughput is achievable, and a minimum conversion
rate must be applied in order to guarantee full specified accuracy. When LOW, full
accuracy is maintained independent of the minimum conversion rate.
Conversion mode selection. When HIGH and WARP LOW, this input selects a
reduced power mode. In this mode, the power dissipation is approximately
proportional to the sampling rate.
WARP
7
8
IMPULSE
DI
DI
SER/PAR
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when
HIGH, the serial interface is selected and some bits of the data bus are used as a
serial port.
9, 10
D[0:1]
D O
Bit 0 and Bit 1 of the parallel port data output bus. When SER/PAR is HIGH, these
outputs are in high impedance.
11,12
D[2:3]or
DIVSCLK[0:1]
DI/O
When SER/PAR is LOW, these pins are Bit 2 and Bit 3 of the Parallel
Port Data Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is
serial master read after convert, these inputs, part of the serial port, are used to slow
down if desired the internal serial clock which clocks the data output. In other serial
modes, these pins are high impedance outputs.
13
14
D4
DI/O
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port
Data Output Bus.
or EXT/INT
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital
select input for choosing the internal or an external data clock. With EXT/INT tied
LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
HIGH, output data is synchronized to an external clock signal connected to the
SCLK input.
D5
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data
Output Bus.
or INVSYNC
When SER/PAR is HIGH, this input, part of the serial port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
15
16
D6
DI/O
DI/O
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data
Output Bus.
or INVSCLK
D7
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the
SCLK signal. It is active in both master and slave mode.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel PortData
Output Bus.
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the serial port, is used as either an
external data input or a read mode selection input depending on the state of
EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain
the conversion results from two or more ADCs onto a single SDOUT line. The
digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods
after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When
RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is
complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply than the supply
REV. Pr D
–7–
PRELIMINARY TECHNICAL DATA
AD7621
Pin No.
Mnemonic
Type
Description
of the host interface (2.5 V or 3 V).
19
20
21
DVDD
DGND
D8
P
P
D O
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel PortData
Output Bus.
or SDOUT
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial
data output synchronized to SCLK. Conversion results are stored in an on-chip
register. The AD7621 provides the conversion result, MSB first, from its internal
shift register. The data format is determined by the logic level of OB/2C.
In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the
next rising edge.
22
23
D9
DI/O
D O
When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data
Output Bus.
or SCLK
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data
clock input or output, dependent upon the logic state of the EXT/INT pin. The
active edge where the data SDOUT is updated depends upon the logic state of the
INVSCLK pin.
When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data
Output Bus.
D10
or SYNC
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital
output frame synchronization for use with the internal data clock (EXT/INT = Logic
LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven
HIGH and remains HIGH while SDOUT output is valid. When a read sequence is
initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
24
D11
D O
When SER/PAR is LOW, this output is used as the Bit 11 of the ParallelPort Data
Output Bus.
or RDERROR
When SER/PAR is HIGH and when EXT/INT is HIGH, this output, part of the
serial port, is used as a incomplete read error flag. In slave mode, when a data
read is started and not complete when the following conversion is complete, the
current data is lost and RDERROR is pulsed high.
25–28
29
D[12:15]
BUSY
D O
D O
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs
regard less of the interface mode.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH
until the conversion is complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
30
31
DGND
RD
P
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output
bus is enabled.
32
33
34
35
CS
DI
DI
DI
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output
bus is enabled. CS is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7621. Current conversion if any
is aborted. If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and
conversions are inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the
hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP
LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the
internal sample/hold is put into the hold state and a conversion is immediately
started.
RESET
PD
CNVST
36
37
AGND
REF
P
AI
Must be tied to analog ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external
reference on this pin if the internal reference buffer is not used. Should be decoupled
effectively with or without the internal buffer.
38
REFGND
AI
Reference Input Analog Ground.
–8–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
Pin No.
Mnemonic
Type
Description
39
43
45
46
IN-
IN+
AI
AI
AO
Differential Negative Analog Input.
Differential Negative Analog Input.
Temperature sensor analog output typically 1mV/°C.
Internal Reference Output and Reference Buffer Input Voltage. The internal reference
buffer has a fixed gain. It outputs 2.048V typically when 1.2V is applied on this pin.
Allows choice of Internal or External voltage reference. When HIGH, the internal
reference is switched off and an external reference must been used. When LOW, the
on-chip reference is turned on.
TEMP
REFBUFIN AI
47
PDREF
PDBUF
DI
DI
48
Allows choice of buffering reference. When LOW, the buffer is selected. When
HIGH, the buffer is switched off.
NOTES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
REV. Pr D
–9–
PRELIMINARY TECHNICAL DATA
AD7621
Signal to (noise + distortion) ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/(N+D) is expressed in
decibels.
DEFINITION OF SPECIFICATIONS
Integral nonlinearity error (INL)
Linearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale”. The point used as “negative full
scale” occurs 1/2 LSB before the first code transition.
“Positive full scale” is defined as a level 1 1/2 LSB be-
yond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
Aperture delay
Aperture delay is a measure of the acquisition perfor-
mance and is measured from the falling edge of the
CNVST input to when the input signal is held for a con-
version.
Differential nonlinearity error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential nonlinearity is the maximum deviation from this
ideal value. It is often specified in terms of resolution for
which no missing codes are guaranteed.
Transient response
The time required for the AD7621 to achieve its rated
accuracy after a full-scale step function is applied to its
input.
Gain error
The first transition (from 000 . . . 00 to 000 . . . 01) should
occur for an analog voltage 1/2 LSB above the nominal –
full scale (-2.047962 V for the 2.048V range). The last
transition (from 111 . . . 10 to 111 . . . 11) should occur for
an analog voltage 1 1/2 LSB below the nominal full scale
(2.047886 V for the 2.048V range). The gain error is the
deviation of the difference between the actual level of the
last transition and the actual level of the first transition
from the difference between the ideal levels.
Reference Voltage Temperature Coefficient
The change of the internal reference output voltage V
over the operating temperature range and normalized by
the output voltage at 25°C, expressed in ppm/°C. The
equation follows:
V(T2 ) −V(T1)
TCV(ppm /°C) =
×106
V(25°C) × (T2 −T1)
where
V(25°C) = V at 25°C
Zero error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
V(T2) = V at Temperature 2
V(T1) = V at Temperature 1
Reference Voltage Long-Term Stability
Spurious free dynamic range (SFDR)
The difference, in decibels (dB), between the rms ampli-
tude of the input signal and the peak spurious signal.
Typical shift of output voltage at 25°C on a sample of
parts subjected to operation life test of 1000 hours at
125°C:
V(t1) −V(t0 )
Effective number of bits (ENOB)
ꢃV(ppm) =
×106
ENOB is a measurement of the resolution with a sine
wave input. It is related to S/(N+D) by the following for-
mula:
V(t0 )
where
V(t0) = V at 25°C at Time 0
V(t1) = V at 25°C after 1,000 hours operation at 125°C
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
Reference Voltage Thermal Hysteresis
Total harmonic distortion (THD)
Thermal hysteresis is defined as the change of output
voltage after the device is cycled through temperature
from +25°C to –40°C to +125°C and back to +25°C.
This is a typical value from a sample of parts put through
such a cycle
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal
and is expressed in decibels.
Dynamic range
VTC −V(25°C)
Dynamic range is the ratio of the rms value of the full
scale to the rms noise measured with the inputs shorted
together. The value for dynamic range is expressed in
decibels.
VHYS (ppm) =
×106
V(25°C)
where
V(25°C) = V at 25°C
VTC = V at 25°C after temperature cycle at +25°C to
–40°C to +125°C and back to +25°C
Signal-to-noise ratio (SNR)
SNR is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value
for SNR is expressed in decibels.
–10–
REV. Pr D
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics- AD7621
To Be Supplied
To Be Supplied
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
To Be Supplied
To Be Supplied
TPC 2. Histogram of 131,072 Conversions of a DC Input
at the Code Transition
TPC 5. Histogram of 131,072 Conversions of a DC Input
at the Code Center
To Be Supplied
To Be Supplied
TPC 3. Typical Positive INL Distribution (TBD Units)
TPC 6. Typical Negative INL Distribution (TBD Units)
REV. Pr D
–11–
PRELIMINARY TECHNICAL DATA
AD7621
To Be Supplied
To Be Supplied
TPC 7. Typical INL and DNL vs Temperature
TPC 10. Typical INL and DNL vs Sampling rate
To Be Supplied
To Be Supplied
TPC 8. FFT
TPC 11. SNR, S/(N+D) and ENOB vs. Frequency
To Be Supplied
To Be Supplied
TPC 9. FFT
TPC 12. THD, SFDR and Harmonics vs. Frequency
–12–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
To Be Supplied
To Be Supplied
TPC 16.Operating Current vs. Sampling Rate
TPC 13. SNR, S/(N+D) and THD vs. Input Level
To Be Supplied
To Be Supplied
TPC 17. Power-Down Operating Currents vs. Temperature
TPC 14. SNR, S/(N+D) and ENOB vs Temperature
To Be Supplied
To Be Supplied
TPC 18. Positive and Negative Full Scale, Offset and Refer-
ence Buffer Gain vs. Temperature
TPC 15. THD, SFDR and Harmonics vs Temperature
REV. Pr D
–13–
PRELIMINARY TECHNICAL DATA
AD7621
To Be Supplied
To Be Supplied
TPC 19.Positive and Negative Full Scale, Offset and
Reference Buffer Gain vs. Supply .
TPC 22. Typical Internal Reference Temperature
Drift Distribution (TBD Units)
To Be Supplied
To Be Supplied
TPC 20.Typical Delay vs. Load Capacitance CL
TPC 23. Typical Internal Reference Hysterisis
Distribution(TBDUnits)
To Be Supplied
TPC 21.Typical Internal Reference voltage vs. Tem-
perature
–14–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
IN+
SWITCHES CONTROL
SW
+
MSB
LSB
32,768C 16,384C
4C
2C
2C
C
C
BUSY
CONTROL
LOGIC
REF
COMP
OUTPUT CODE
REFGND
32,768C
16,384C
MSB
4C
C
C
SW
-
LSB
CNVST
IN -
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
nected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the in-
puts IN+ and IN- captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each
element of the capacitor array between REFGND or REF,
the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . . VREF/65536). The control logic
toggles these switches, starting with the MSB first, in
order to bring the comparator back into a balanced condi-
tion. After the completion of this process, the control
logic generates the ADC output code and brings BUSY
output low.
The AD7621 is a very fast, low-power, single-supply,
precise 16-bit analog-to-digital converter (ADC) using
successive approximation architecture.
The AD7621 features different modes to optimize perfor-
mances according to the applications.
In Warp mode, the AD7621 is capable of converting
3,000,000 samples per second (3 MSPS).
The AD7621 provides the user with an on-chip
track/hold, successive approximation ADC that does not
exhibit any pipeline or latency, making it ideal for mul-
tiple multiplexed channel applications.
Modes of Operation
The AD7621 can be operated from a single 2.5 V supply
and be interfaced to either 5 V or 3.3 V or 2.5 V digital
logic. It is housed in a 48-lead LQFP or a tiny LFCSP
packages that combines space savings and allows flexible
configurations as either serial or parallel interface. The
AD7621 is pin-to-pin-compatible with the AD7674.
The AD7621 features three modes of operations, Warp,
Normal, and Impulse. Each of these modes is more suit-
able for specific applications.
The Warp mode allows the fastest conversion rate up to
3 MSPS. However, in this mode, and this mode only, the
full specified accuracy is guaranteed only when the time
between conversion does not exceed 1 ms. If the time be-
tween two consecutive conversions is longer than 1 ms, for
instance, after power-up, the first conversion result should
be ignored. This mode makes the AD7621 ideal for appli-
cations where fast sample rate are required.
CONVERTER OPERATION
The AD7621 is a successive approximation analog-to-
digital converter based on a charge redistribution DAC.
Figure 3 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 16
binary weighted capacitors which are connected to the two
comparator inputs.
The normal mode is the fastest mode (2 MSPS) without
any limitation about the time between conversions. This
mode makes the AD7621 ideal for asynchronous appli-
cations such as data acquisition systems, where both high
accuracy and fast sample rate are required.
During the acquisition phase, terminals of the array tied to
the comparator’s input are connected to AGND via SW+
and SW-. All independent switches are connected to the
analog inputs. Thus, the capacitor arrays are used as sam-
pling capacitors and acquire the analog signal on IN+ and
IN- inputs. When the acquisition phase is complete and
the CNVST input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SW+ and SW- are
opened first. The two capacitor arrays are then discon-
The impulse mode, the lowest power dissipation mode,
allows power saving between conversions. The maximum
throughput in this mode is 1.25 MSPS. This feature
makes the AD7621 ideal for battery-powered applications.
REV. Pr D
–15–
PRELIMINARY TECHNICAL DATA
AD7621
Transfer Functions
Table III. Output Codes and Ideal Input Voltages
Using the OB/2C digital input, the AD7621 offers two
output codings: straight binary and two’s complement.
The ideal transfer characteristic for the AD7621 is shown
in Figure 4 and Table III.
Digital Output Code
Hexa
Analog
Input
Straight Two’s
Binary Comple-
ment
D
escription
VREF = 2.048V
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB 75.684µV
Midscale 0 V
Midscale – 1 LSB -75.684µV
2.047924 V
2.047849 V
3FFFF1 1FFFF1
3 F F F E
20001
1 F F E
00001
00000
3 F F F F
20001
200002
111...111
111...110
111...101
20000
1 F F F F
–FSR + 1 LSB
–FSR
-2.047924 V 00001
-2.048 V
000002
N O T E S
1This is also the code for overrange analog input (VIN+ – VIN- above
VREF
– VREFGND).
000...010
000...001
000...000
2This is also the code for underrange analog input (VIN+ – VIN- below
-VREF
+ VREFGND).
-FS
-FS+1 LSB
+FS-1 LSB
+FS-1.5 LSB
ANALOG INPUT
-FS+0.5 LSB
Figure 4. ADC Ideal Transfer Function
DVDD
ANALOG
SUPPLY
10ꢄ
DIGITAL SUPPLY
(2.5V OR 3.3V)
note 5
(2.5V)
100nF
100nF
100nF
10ꢂF
10ꢂF
10ꢂF
AVDD AGND
DGND
DVDD
OVDD
OGND
SERIAL
PORT
REFBUFIN
CREF
SCLK
100nF
SDOUT
note 1
REF
BUSY
CREF
ꢂC/ꢂP/DSP
AD7621
50ꢄ
10ꢂF
D
CNVST
note 2
REFGND
IN+
MODE0
MODE1
OB/2C
note 6
15ꢄ
U1
note 3
DVDD
ANALOG INPUT+
1.2nF
AD8021
C
C
note 4
PDREF
PDBUF
CS
CLOCK
RD
15ꢄ
U2
IN-
RESET
PD
note 3
ANALOG INPUT-
1.2nF
AD8021
C
C
note 4
NOTES :
Note 1 : See Voltage Reference Input Section.
Note 2 : C is 10ꢂF ceramic capacitor or low esr tantalum. Ceramic size 1206 Panasonic ECJ-3xB0J106 is recommended. See Voltage Reference Input Section.
REF
Note 3 : The AD8021 is recommended. See Driver Amplifier Choice Section.
Note 4 : See Analog Inputs Section.
Note 5 : Option. See Power Supply Section.
Note 6 : Optional Low jitter CNVST. See Conversion Control Section.
–16–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the
AD7621. Different circuitry shown on this diagram are
optional and are discussed below.
Analog Inputs
Figure 6 shows a simplified analog input section of the
AD7621.
To Be Supplied
To Be Supplied
Figure 7. Analog Input CMRR vs. Frequency
During the acquisition phase, for AC signals, the AD7621
behaves like a one pole RC filter consisted of the equiva-
lent resistance R+ , R- and CS. The resistors R+ and R-
are typically TBD ⍀ and are lumped component made up
of some serial resistor and the on resistance of the switches.
The capacitor CS is typically TBD pF and is mainly the
ADC sampling capacitor. This one pole filter with a typi-
cal -3dB cutoff frequency of 50 MHz reduces undesirable
aliasing effect and limits the noise coming from the in-
puts.
Figure 6. AD7621 simplified Analog Input.
The diodes shown in Figure 6 provide ESD protection for
the inputs. Care must be taken to ensure that the analog
input signal never exceeds the absolute ratings on these
inputs. This will cause these diodes to become forward-
biased and start conducting current. These diodes can
handle a forward-biased current of 150 mA maximum.
This condition could eventually occur when the input
buffer's (U1) or (U2) supplies are different from AVDD.
In such case, an input buffer with a short-circuit current
limitation can be used to protect the part.
Because the input impedance of the AD7621 is very high,
the AD7621 can be driven directly by a low impedance
source without gain error. That allows to put, as shown in
Figure 5, an external one-pole RC filter between the out-
put of the amplifier output and the ADC analog inputs to
even further improve the noise filtering done by the
AD7621 analog input circuit. However, the source imped-
ance has to be kept low because it affects the ac
performances, especially the total harmonic distortion.
The maximum source impedance depends on the amount
of total harmonic distortion (THD) that can be tolerated.
The THD degrades as a function of the source impedance
and the maximum input frequency.
This analog input structure is a true differential structure.
By using these differential inputs, signals common to both
inputs are rejected as shown in Figure 7 which represents
the typical CMRR over frequency.
Driver Amplifier Choice
Although the AD7621 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
•
The driver amplifier and the AD7621 analog input
circuit have to be able together to settle for a full-scale
step the capacitor array at a 16-bit level (0.0015%). In
the amplifier’s datasheet, the settling at 0.1% or 0.01%
is more commonly specified. It could significantly dif-
fer from the settling time at 16 bit level and, therefore,
it should be verified prior to the driver selection. The
tiny op-amp AD8021 which combines ultra low noise
and a high gain bandwidth meets this settling time
requirement.
REV. Pr D
–17–
PRELIMINARY TECHNICAL DATA
AD7621
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR
and transition noise performance of the AD7621. The
noise coming from the driver is filtered by the AD7621
analog input circuit one-pole low-pass filter made by
R+, R- and CS. The SNR degradation due to the ampli-
fier is :
U1
ANALOG INPUT
AD8021
10pF
(UNIPOLAR 0 to 2.048V)
IN+
15ꢄ
15ꢄ
590ꢄ
1.2nF
1.2nF
AD7621
IN-
590ꢄ
U2
1kꢄ
1kꢄ
56
REF
AD8021
10pF
SNRLOSS = 20LOG
,
2
100nF
10ꢂF
3136 + ꢅf -3dB Ne
N
(
)
where :
f-3dB is the -3dB input bandwidth in MHz of the AD7621
(50 MHz) or the cutoff frequency of the input filter if
any used
Figure 8. Single Ended to Differential Driver Circuit (
internal reference buffer used )
N is the noise factor of the amplifiers ( 1 if in buffer con-
figuration )
Voltage Reference
The AD7621 allows the choice of either a very low tem-
perature drift internal voltage reference or an external
reference.
eN is the equivalent input noise voltage of each op-amp in
nV/(Hz)1/2
Unlike many ADC with internal reference, the internal
reference of the AD7621 provides excellent performances
and can be used in almost all applications. It is tempera-
For instance, a driver with an equivalent input noise of
2nV/ΊHz like the AD8021 and configured as a buffer, thus
with a noise gain of +1, the SNR degrades by only 0.17
dB with the filter in figure 5, and 0.8 dB without.
ture compensated to 1.2V
TBD mV with a typical drift
of TBD ppm/°C, a typical long-term stability of TBD
ppm and a typical hysterisis of TBD ppm.
•
The driver needs to have a THD performance suitable
to that of the AD7621.
However, the advantages to use the external reference
voltage directly are :
The AD8021 meets these requirements and is usually
appropriate for almost all applications. The AD8021
needs an external compensation capacitor of 10 pF. This
capacitor should have good linearity as an NPO ceramic
or mica type.
- The power saving of about 8mW typical when the inter-
nal reference and its buffer are powered down ( PDREF
and PDBUF High )
- The SNR and dynamic range improvement of about 1.7
dB resulting of the use of a reference voltage very close to
the supply (2.5V) instead of a typical 2.048V reference
when the internal buffer is used.
The AD8022 could also be used where dual version is
needed and gain of 1 is used.
Single to Differential Driver
To use the internal reference along with the internal
buffer, PDREF and PDBUF should both be LOW. This
will produce a voltage on REFBUFIN of 1.2 V and the
buffer will gain it up, resulting in a 2.048 V reference on
REF pin.
For applications using unipolar analog signals, a single-
ended to differential driver will allow for a differential
input into the part. The schematic is shown in Figure 8.
This configuration, when provided an input signal of 0 to
VREF , will produce a differential ꢀ VREF with midscale at
VREF/2.
It is useful to decouple the REFBUFIN pin with a 100 nF
ceramic capacitor. The output impedance of the
REFBUFIN pin is 16 kꢄ. Thus, the 100 nF capacitor
provides an RC filter for noise reduction.
If the application can tolerate more noise, the AD8138,
differential driver, can be used.
To use an external reference along with the internal
buffer, PDREF should be HIGH and PDBUF should be
low. This powers down the internal reference and allows
for the 1.2 V reference to be applied to REFBUFIN.
To use an external reference directly on REF pin,
PDREF and PDBUF should both be HIGH.
It should be noted that the internal reference and internal
buffer are independent of the power down (PD) pin of the
part. Furthermore, powering up the internal reference and
internal buffer requires time due to the charge of the REF
decoupling.
–18–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
In both cases, the voltage reference input REF has a dy-
namic input impedance and requires, therefore, an
efficient decoupling between REF and REFGND inputs.
When the internal reference buffer is used, this decoupling
consists of a 10 µF ceramic capacitor ( e.g. : Panasonic
ECJ-3xB0J106 1206 size ).
When external reference is used, the decoupling consists
of a low ESR 47 µF tantalum capacitor connected to the
REF and REFGND inputs with minimum parasitic induc-
tance.
To Be Supplied
Temperature Sensor
The TEMP pin, which measures the temperature of the
AD7621, can be used as shown in figure 9. The output of
the TEMP pin is applied to one of the inputs of the ana-
log switch (e.g. : ADG779) and the ADC itself is used to
measure its own temperature. This configuration could be
very useful to improve the calibration accuracy over the
temperature range.
Figure 10. PSRR vs. Frequency
POWER DISSIPATION Vs. THROUGHPUT
In Impulse mode, the AD7621 automatically reduces its
power consumption at the end of each conversion phase.
During the acquisition phase, the operating currents are
very low which allows a significant power saving when the
conversion rate is reduced as shown in Figure 11. This
feature makes the AD7621 ideal for very low-power bat-
tery applications.
To Be Supplied
It should be noted that the digital interface remains active
even during the acquisition phase. To reduce the operat-
ing digital supply currents even further, the digital inputs
need to be driven close to the power rails (i.e., DVDD
and DGND).
Figure 9. Use of the Temperature Sensor
Power Supply
The AD7621 uses three sets of power supply pins: an ana-
log 2.5 V supply AVDD, a digital 2.5 V core supply
DVDD, and a digital input/output interface supply
OVDD. The OVDD supply allows direct interface with
any logic working between 2.3 V and 5.25 V. To reduce
the number of supplies needed, the digital core (DVDD)
can be supplied through a simple RC filter from the ana-
log supply as shown in Figure 5. The AD7621 is
independent of power supply sequencing and thus free
from supply voltage induced latchup. Additionally, it is
very insensitive to power supply variations over a wide
frequency range as shown in Figure 10.
To Be Supplied
Figure 11. Power Dissipation vs. Sample Rate
REV. Pr D
–19–
PRELIMINARY TECHNICAL DATA
AD7621
CONVERSION CONTROL
Figure 12 shows the detailed timing diagrams of the con-
version process. The AD7621 is controlled by the signal
CNVST which initiates conversion. Once initiated, it
cannot be restarted or aborted, even by the power-down
input PD, until the conversion is complete. The CNVST
signal operates independently of CS and RD signals.
t
9
RESET
BUSY
t
2
t
DATA
BUS
1
CNVST
BUSY
t
8
CNVST
t
4
t
t
3
5
t
6
Figure 13. RESET Timing
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
DIGITAL INTERFACE
The AD7621 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or
parallel interface. The serial interface is multiplexed on
the parallel data bus. The AD7621 digital interface also
accommodates both 2.5V, 3.3V or 5V logic with either
OVDD at 2.5V or 3.3V. OVDD defines the logic high out-
put voltage. In most applications, the OVDD supply pin of
the AD7621 is connected to the host system interface 2.5V
or 3.3V digital supply. Finally, by using the OB/2C input
pin, both two’s complement or straight binary coding can
be used.
t
t
8
7
Figure 12. Basic Conversion Timing
Although CNVST is a digital signal, it should be de-
signed with this special care with fast, clean edges and
levels, with minimum overshoot and undershoot or ring-
ing.
For applications where the SNR is critical, the CNVST
signal should have a very low jitter. Some solutions to
achieve that are to use a dedicated oscillator for CNVST
generation or, at least, to clock it with a high frequency
low jitter clock as shown in Figure 5.
The two signals CS and RD control the interface. When
at least one of these signals is high, the interface outputs
are in high impedance. Usually, CS allows the selection of
each AD7621 in multi-circuits applications and is held
low in a single AD7621 design. RD is generally used to
enable the conversion result on the data bus.
In impulse mode, conversions can be automatically initi-
ated. If CNVST is held low when BUSY is low, the
AD7621 controls the acquisition phase and then automati-
cally initiates a new conversion. By keeping CNVST low,
the AD7621 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up, CNVST
should be brought low once to initiate the conversion
process. In this mode, the AD7621 could sometimes run
slightly faster then the guaranteed limits in the impulse
mode. This feature does not exist in warp or normal modes.
CS = RD = 0
t
1
CNVST
BUSY
t
10
t
4
t
3
t
11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
Figure 14. Master Parallel Data Timing for Reading
(Continuous Read)
–20–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
CS = 0
PARALLEL INTERFACE
t1
The AD7621 is configured to use the parallel interface
with either a 16-bit or 8-bit bus width. The data can be
read either after each conversion, which is during the
next acquisition phase, or during the following conversion
as shown, respectively, in Figure 15 and Figure 16. When
the data is read during the conversion, however, it is rec-
ommended that it is read only during the first half of the
conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the
most critical analog conversion circuitry.
CNVST, RD
BUSY
t4
t3
DATA
BUS
PREVIOUS
CONVERSION
t12
t13
CS
Figure 16. Slave Parallel Data Timing for Reading
(Read During Convert)
RD
CS
RD
BUSY
A0, A1
DATA
BUS
CURRENT
CONVERSION
HI-Z
HI-Z
HI-Z
Pins D[15:8]
Pins D[7:0]
t12
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
t13
t
t
t
12
12
13
Figure 15. Slave Parallel Data Timing for Reading
(Read After Convert)
HI-Z
Figure 17. 8-Bit and 16-Bit Parallel Interface
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CS, RD
t3
CNVST
BUSY
t28
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
2
t26
1
3
14
15
16
SCLK
t15
t27
SDOUT
D15
D14
t23
D2
D1
D0
X
t16
t22
Figure 18. Master Serial Data Timing for Reading (Read After Convert)
REV. Pr D
–21–
PRELIMINARY TECHNICAL DATA
AD7621
SERIAL INTERFACE
To accomodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
The AD7621 is configured to use the serial interface when
SER/PAR is held high. The AD7621 outputs 16 bits of
data, MSB first, on the SDOUT pin. This data is syn-
chronized with the 16 clock pulses provided on SCLK
pin. The output data is valid on both the rising and falling
edge of the data clock. That allows a fast serial interface
speed by using the same clock edge to output the data
from the ADC and to sample the previous bit by the digi-
tal host.
SLAVE SERIAL INTERFACE
External Clock
The AD7621 is configured to accept an externally sup-
plied serial data clock on the SCLK pin when the
EXT/INT pin is held high. In this mode, several meth-
ods can be used to read the data. The external serial
clock is gated by CS. When CS and RD are both low,
the data can be read after each conversion or during the
following conversion. The external clock can be either a
continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 20 and Figure 22 show the detailed timing
diagrams of these methods.
MASTER SERIAL INTERFACE
Internal Clock
The AD7621 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low.
The AD7621 also generates a SYNC signal to indicate to
the host when the serial data is valid. The serial clock
SCLK and the SYNC signal can be inverted if desired.
Depending on RDC/SDIN input, the data can be read
after each conversion or during the following conversion.
Figure 18 and Figure 19 show the detailed timing dia-
grams of these two modes.
While the AD7621 is performing a bit decision, it is impor-
tant that voltage transients not occur on digital
input/output pins or degradation of the conversion result
could occur. This is particularly important during the
second half of the conversion phase because the AD7621
provides error correction circuitry that can correct for an
improper bit decision made during the first half of the
conversion phase. For this reason, it is recommended
that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is
low or, more importantly, that it does not transition dur-
ing the latter half of BUSY high.
Usually, because the AD7621 is used with a fast through-
put, the mode master, read during conversion is the most
recommended serial mode when it can be used.
In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical con-
version decisions.
In read-after-conversion mode, it should be noted that,
unlike in other modes, the signal BUSY returns low after
the 16 data bits are pulsed out and not at the end of the
conversion phase which results in a longer BUSY width.
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
t1
CNVST
t3
BUSY
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
14
15
16
t18
t27
SDOUT
X
D15
D14
t23
D2
D1
D0
t16
t22
Figure 19. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
–22–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
External Discontinuous Clock Data Read After Con-
version
Another advantage is to be able to read the data at any
speed up to 80 MHz which accommodates both slow
digital host interface and the fastest serial reading.
Though the maximum throughput cannot be achieved
using this mode, it is the most recommended of the serial
slave modes. Figure 20 shows the detailed timing dia-
grams of this method. After a conversion is complete,
indicated by BUSY returning low, the result of this con-
version can be read while both CS and RD are low. The
data is shifted out, MSB first, with 16 clock pulses and is
valid on both rising and falling edge of the clock.
Finally, in this mode only, the AD7621 provides a
“daisy-chain” feature using the RDC/SDIN input pin for
cascading multiple converters together. This feature is
useful for reducing component count and wiring connec-
tions when desired as, for instance, in isolated
multiconverter applications.
An example of the concatenation of two devices is shown
in Figure 21. Simultaneous sampling is possible by using
a common CNVST signal. It should be noted that the
RDC/SDIN input is latched on the edge of SCLK oppo-
site to the one used to shift out the data on SDOUT.
Hence, the MSB of the “upstream” converter just follows
the LSB of the “downstream” converter on the next
SCLK cycle.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion
process.
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
BUSY
t35
t36 t37
SCLK
1
2
3
15
16
17
18
t31
t32
X
D15
t34
D14
D13
X13
D1
X15
Y15
X14
Y14
SDOUT
D0
X0
t16
SDIN
X15
X14
X
1
t33
Figure 20. Slave Serial Data Timing for Reading (Read After Convert)
RD =0
EXT/INT = 1
INVSCLK = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
3
4
15
16
1
2
t31
t32
D14
X
D15
D15
D1
D0
SDOUT
t16
Figure 22. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
REV. Pr D
–23–
PRELIMINARY TECHNICAL DATA
AD7621
MICROPROCESSOR INTERFACING
The AD7621 is ideally suited for traditional dc measure-
ment applications supporting a microprocessor, and ac
signal processing applications interfacing to a digital sig-
nal processor. The AD7621 is designed to interface either
with a parallel 8-bit or 16-bit wide interface or with a
general purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used
with the AD7621 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of
the AD7621 with an SPI equipped DSP, the ADSP-219x.
BUSY
OUT
BUSY
BUSY
AD7621
#2
(UPSTREAM)
AD7621
#1
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SPI Interface (ADSP-219x)
SCLK
SCLK
Figure 22 shows an interface diagram between the
AD7621 and an SPI-equipped DSP, ADSP219x. To
accommodate the slower speed of the DSP, the AD7621
acts as a slave device and data must be read after conver-
sion. This mode also allows the “daisy chain” feature.
The convert command could be initiated in response to an
internal timer interrupt. The reading process could be
initiated in response to the end-of-conversion signal
(BUSY going low) using an interrupt line of the DSP.
The Serial Peripheral Interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI interrupt enable (TIMOD) =00 by writing to the SPI
Control Register (SPICLTx). It should be noted that to
meet all timing requirements, the SPI clock should be
limited to 17Mbits/s which allow to read an ADC result
in about 1.1 ꢂs. When higher sampling rate is desired, it
is recomended to use one of the parallel interface mode
with the ADSP-219x.
SCLK IN
CS IN
CNVST IN
Figure 21. Two AD7621s in a “Daisy-Chain” Configuration
External Clock Data Read During Conversion
Figure 22 shows the detailed timing diagrams of this
method. During a conversion, while both CS and RD are
both low, the result of the previous conversion can be
read. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the
clock. The 16 bits have to be read before the current con-
version is complete. If that is not done, RDERROR is
pulsed high and can be used to interrupt the host inter-
face to prevent incomplete data reading. There is no
“daisy chain” feature in this mode and RDC/SDIN
input should always be tied either high or low.
To reduce performance degradation due to digital activity,
a fast discontinuous clock of is recommended to ensure that
all the bits are read during the first half of the conversion
phase. It is also possible to begin to read the data after
conversion and continue to read the last bits even after a new
conversion has been initiated.
DVDD
AD7621*
ADSP-219x*
SER/PAR
EXT/INT
PFx
BUSY
SPIxSEL (PFx)
MISOx
CS
SDOUT
SCLK
SCKx
RD
INVSCLK
CNVST
PFx or TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing the AD7621 to SPI Interface
–24–
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
APPLICATION HINTS
ing on the configuration. OGND is connected to the
digital system ground.
Layout
The AD7621 has very good immunity to noise on the
power supplies. However, care should still be taken with
regard to grounding layout.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to
the ADC and connected with short and large traces to
minimize parasitic inductances.
The printed circuit board that houses the AD7621
should be designed so the analog and digital sections
are separated and confined to certain areas of the board.
This facilitates the use of ground planes that can be
easily separated. Digital and analog ground planes
should be joined in only one place, preferably under-
neath the AD7621, or, at least, as close as possible to the
AD7621. If the AD7621 is in a system where multiple
devices require analog to digital ground connections,
the connection should still be made at one point only, a
star ground point, which should be established as close
as possible to the AD7621.
Evaluating the AD7621 Performance
A recommended layout for the AD7621 is outlined in the
documentation of the EVAL-AD7621-CB, evaluation
board for the AD7621. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board
from a PC via the Eval Control Brd3.
It is recommended to avoid running digital lines under the
device as these will couple noise onto the die. The analog
ground plane should be allowed to run under the
AD7621 to avoid noise coupling. Fast switching signals
like CNVST or clocks should be shielded with digital
ground to avoid radiating noise to other sections of the
board, and should never run near analog signal paths.
Crossover of digital and analog signals should be
avoided. Traces on different but close layers of the board
should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power
supply lines to the AD7621 should use as large a trace as
possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decou-
pling is also important to lower the supplies impedance
presented to the AD7621 and reduce the magnitude of
the supply spikes. Decoupling ceramic capacitors, typi-
cally 100 nF, should be placed on each power supplies
pins AVDD, DVDD and OVDD close to, and ideally
right up against these pins and their corresponding
ground pins. Additionally, low ESR 10 µF capacitors
should be located in the vicinity of the ADC to further
reduce low frequency ripple.
The DVDD supply of the AD7621 can be either a
separate supply or come from the analog supply,
AVDD, or from the digital interface supply, OVDD.
When the system digital supply is noisy, or fast switching
digital signals are present, it is recommended if no sepa-
rate supply available, to connect the DVDD digital
supply to the analog supply AVDD through an RC filter
as shown in Figure 5, and connect the system supply to the
interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system sup-
ply, it is useful to insert a bead to further reduce
high-frequency spikes.
The AD7621 has four different ground pins; REFGND,
AGND, DGND, and OGND. REFGND senses the refer-
ence voltage and should be a low impedance return to
the reference because it carries pulsed currents. AGND
is the ground to which most internal ADC analog sig-
nals are referenced. This ground must be connected with
the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depend-
REV. Pr D
–25–
PRELIMINARY TECHNICAL DATA
AD7621
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP)
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
12
25
0ꢁ
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7ꢁ
0ꢁ
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
48-Lead Frame Chip Scale Package (LFCSP)
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.276 (7.0)
BSC SQ
0.017 (0.42)
0.009 (0.24)
37
48
36
1
PIN 1
INDICATOR
0.215 (5.45)
0.209 (5.30) SQ
0.203 (5.15)
TOP
VIEW
0.266 (6.75)
BSC SQ
BOTTOM
VIEW
12
25
24
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
13
0.012 (0.30)
0.009 (0.23)
0.031 (0.80) MAX
0.026 (0.65) NOM
12˚MAX
0.007 (0.18) Paddle connected to AGND
( This connection is not required
to meet electrical performances )
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
0.039 (1.00) MAX
0.033 (0.85) NOM
0.020 (0.50)
BSC
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
–26–
REV. Pr D
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