AD7643BCPZRL [ADI]
18-Bit, 1.25 MSPS PulSAR ADC;
| 型号： | AD7643BCPZRL |
| 厂家： | 
ADI |
| 描述： | 18-Bit, 1.25 MSPS PulSAR ADC |
| 文件： | 总29页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18-Bit, 1.25 MSPS PulSAR® ADC
AD7643
FUNCTIONAL BLOCK DIAGRAM
FEATURES
TEMP REFBUFIN REF REFGND
DVDD DGND
Throughput: 1.25 MSPS
INL: 1.5 LSB typical, 3 LSB maximum ( 11 ppm of full scale)
18-bit resolution with no missing codes
Dynamic range: 95 dB typical
AGND
AVDD
OVDD
OGND
AD7643
REF
REF AMP
SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −113 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
SERIAL
PORT
18
IN+
IN–
SWITCHED
CAP DAC
D[17:0]
MODE0
MODE1
BUSY
RD
PARALLEL
INTERFACE
PDREF
PDBUF
PD
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CS
RESET
D0/OB/2C
Power dissipation
65 mW typical @ 1.25 MSPS with internal REF
2 μW in power-down mode
CNVST
Figure 1.
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with the AD7641 and other PulSAR ADC’s
Table 1. PulSAR 48-Lead Selection
100 to
250
500 to
570
650 to
1000
Type/kSPS
>1000
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
AD7653,
AD7667
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
True Bipolar
AD7610,
AD7663
AD7675
AD7665
AD7612,
AD7671
AD7677
True
Differential
AD7676
AD7621,
AD7622,
AD7623
AD7641,
AD7643
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
AD7634,
AD7674
AD7655
GENERAL DESCRIPTION
The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution
SAR, fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. The part has no
latency and can be used in asynchronous rate applications. The
AD7643 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7643 is only available in Pb-free packages with
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7643 is a 1.25 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7643 has no missing 18-bit code.
3. Internal Reference.
The AD7643 has a 2.048 V internal reference with a typical
drift of 8 ppm/°C and an on-chip TEMP sensor.
4. Single-Supply Operation.
operation specified from −40°C to +85°C.
The AD7643 operates from a 2.5 V single supply.
5. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with 2.5 V, 3.3 V, or
5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7643* PRODUCT PAGE QUICK LINKS
Last Content Update: 04/14/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• AD7643 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7643 Evaluation Kit
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD7643 EngineerZone Discussions.
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
• AD7643: 18-Bit, 1.25 MSPS PulSAR™ ADC Data Sheet
TECHNICAL SUPPORT
REFERENCE MATERIALS
Technical Articles
Submit a technical question or find your regional support
number.
• MS-2210: Designing Power Supplies for High Speed ADC
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD7643
TABLE OF CONTENTS
Features .............................................................................................. 1
Multiplexed Inputs ..................................................................... 17
Driver Amplifier Choice ........................................................... 18
Voltage Reference Input ............................................................ 18
Power Supply............................................................................... 20
Conversion Control ................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial interface ............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7643 Performance...................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Applications Information .............................................................. 15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Transfer Functions...................................................................... 16
Typical Connection Diagram........................................................ 17
Analog Inputs.............................................................................. 17
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7643
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
VIN+, VIN− to AGND
fIN = 100 kHz
−VREF
−0.1
+VREF
AVDD1
V
V
dB
μA
Operating Input Voltage
Analog Input CMRR
Input Current
58
2.5
1.25 MSPS throughput
Input Impedance2
THROUGHPUT SPEED
Complete Cycle
800
ns
Throughput Rate
1.25
MSPS
DC ACCURACY
Integral Linearity Error3
No Missing Codes
Differential Linearity Error
Transition Noise
−3
18
−1
1.5
+3
LSB4
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
+1.25
VREF = 2.5 V
VREF = 2.048 V
1.7
2.0
5
Zero Error, TMIN to TMAX
Zero Error Temperature Drift
Gain Error, TMIN to TMAX
−16
−22
+16
+22
1
5
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Signal-to-Noise
1
16
ppm/°C
LSB
AVDD = 2.5 V 5%
VREF = 2.5 V
95
dB6
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
fIN = 1 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
93.5
93.5
92
93
Spurious-Free Dynamic Range
Total Harmonic Distortion
118
114
111
108
−114
−113
−109
−105
93.5
93.5
91.8
92.5
50
Signal-to-(Noise + Distortion)
−3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
1
5
ns
ps rms
ns
Aperture Jitter
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Full-scale step
250
PDREF = PDBUF = low
REF @ 25°C
−40°C to +85°C
AVDD = 2.5 V 5%
2.038
2.048
8
15
2.058
V
ppm/°C
ppm/V
Rev. 0 | Page 3 of 28
AD7643
Parameter
Conditions
Min
Typ
5
1.19
6.33
Max
Unit
ms
V
Turn-On Settling Time
REFBUFIN Output Voltage
REFBUFIN Output Resistance
EXTERNAL REFERENCE
Voltage Range
Current Drain
CREF = 10 μF
REFBUFIN @ 25°C
kΩ
PDREF = PDBUF = high
REF
1.25 MSPS throughput
PDREF = high, PDBUF = low
REF = 2.048 V typical
REFBUFIN = 1.2 V
1.8
2.5
100
AVDD + 0.1
1.30
V
μA
REFERENCE BUFFER
REFBUFIN Input Voltage Range
REFBUFIN Input Current
TEMPERATURE PIN
Voltage Output
Temperature Sensitivity
Output Resistance
DIGITAL INPUTS
Logic Levels
1.05
1.2
1
V
nA
@ 25°C
278
1
4.7
mV
mV/°C
kΩ
VIL
VIH
IIL
IIH
−0.3
1.7
−1
+0.6
5.25
+1
V
V
μA
μA
−1
+1
DIGITAL OUTPUTS
Data Format7
Pipeline Delay8
VOL
VOH
ISINK = 500 μA
ISOURCE = −500 μA
0.4
V
V
OVDD − 0.3
POWER SUPPLIES
Specified Performance
AVDD
2.37
2.37
2.309
2.5
2.5
2.63
2.63
3.6
V
V
V
DVDD
OVDD
Operating Current10
AVDD11
DVDD
OVDD12
1.25 MSPS throughput
With internal reference
24
1.5
0.5
mA
mA
mA
Power Dissipation10, 11
With Internal Reference
With External Reference
In Power-Down Mode12
TEMPERATURE RANGE13
Specified Performance
1.25 MSPS throughput
1.25 MSPS throughput
PD = high
65
60
2
80
75
mW
mW
μW
TMIN to TMAX
−40
+85
°C
1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF
2 See Analog Inputs section.
.
3 Linearity is tested using endpoints, not best fit.
4 LSB means least significant bit. With the 2.048 V input range, 1 LSB is 15.63 μV.
5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7 Parallel or serial 18-bit.
8 Conversion results are available immediately after completed conversion.
9 See the Absolute Maximum Ratings section.
10 Tested in parallel reading mode.
11 With internal reference, PDREF and PDBUF are low; with external reference, PDREF and PDBUF are high.
12 With all digital inputs forced to OVDD.
13 Consult sales for extended temperature range.
Rev. 0 | Page 4 of 28
AD7643
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION AND RESET (Refer to Figure 30 and Figure 31)
Convert Pulse Width
Time Between Conversions
t1
t2
t3
t4
t5
t6
t7
t8
t9
t38
t39
15
800
701
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNVST
23
Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
RESET Low to BUSY High Delay2
BUSY High Time from RESET Low2
PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )
550
1
10
550
550
250
15
10
500
CNVST
t10
t11
t12
t13
ns
ns
ns
ns
Low to Data Valid Delay
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
2
2
20
15
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 36 and Figure 37)
CS
CS
CS
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Low to SYNC Valid Delay
Low to Internal SCLK Valid Delay
Low to SDOUT Delay
3
CNVST
135
Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period4
Internal SCLK High4
Internal SCLK Low4
SDOUT Valid Setup Time4
SDOUT Valid Hold Time4
SCLK Last Edge to SYNC Delay4
CS
CS
CS
2
8
2
2
1
0
0
20
10
10
10
High to SYNC Hi-Z
High to Internal SCLK Hi-Z
High to SDOUT Hi-Z
BUSY High in Master Serial Read After Convert4
CNVST
See Table 4
508
13
Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)
External SCLK Set-Up Time
External SCLK Active Edge to SDOUT Delay
SDIN Set-Up Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
t31
t32
t33
t34
t35
t36
t37
5
1
5
5
12.5
5
5
ns
ns
ns
ns
ns
ns
ns
8
1 See the Conversion Control section.
2 See the Digital Interface section and the RESET section.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Rev. 0 | Page 5 of 28
AD7643
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
t18
t19
t19
t20
t21
t22
t23
t24
t28
1
8
20
2
2
1
0
0
0.84
3
3
3
16
40
8
8
5
0.5
0.5
1.14
32
70
16
16
5
10
9
1.72
64
135
32
32
5
30
26
2.88
μs
500µA
I
OL
TO OUTPUT
PIN
1.4V
C
L
50pF
2V
0.8V
500µA
I
OH
tDELAY
tDELAY
NOTE
2V
2V
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
0.8V
0.8V
C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
L
Figure 3. Voltage Reference Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
Rev. 0 | Page 6 of 28
AD7643
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs/Outputs
IN+1, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AVDD + 0.3 V to
AGND − 0.3 V
0.3 V
AVDD, DVDD
OVDD
AVDD to DVDD
−0.3 V to +2.7 V
−0.3 V to +3.8 V
2.8 V
AVDD, DVDD to OVDD
Digital Inputs
PDREF, PDBUF2
−3.8 V to +2.8 V
−0.3 V to +5.5 V
20 mA
Internal Power Dissipation3
Internal Power Dissipation4
Junction Temperature
Storage Temperature Range
700 mW
2.5 W
125°C
–65°C to +125°C
1 See Analog Inputs section.
2 See Voltage Reference Input section.
3 Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.
4 Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7643
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
AGND
AGND
PIN 1
AVDD
MODE0
MODE1
D0/OB/2C
DGND
2
3
IDENTIFIER
35 CNVST
34 PD
4
33
RESET
5
32 CS
AD7643
6
31
30
29
28
27
26
25
RD
TOP VIEW
DGND
7
DGND
BUSY
D17
(Not to Scale)
8
D1/A0
9
D2/A1
D3
10
11
12
D16
D4/DIVSCLK[0]
D5/DIVSCLK[1]
D15
D14
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic
Type1 Description
1, 36,
AGND
P
Analog Power Ground Pin.
41, 42
2, 44
3, 4
AVDD
MODE[0:1]
P
DI
Input Analog Power Pins. Nominally 2.5 V.
Data Output Interface Mode Selection.
Interface MODE#
MODE1
MODE0
Description
0
1
2
3
0
0
1
1
0
1
0
1
18-bit interface
16-bit interface
8-bit (byte) interface
Serial interface
5
D0/OB/2C
DI/O
When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight
2C
binary/twos complement. When OB/ is high, the digital output is straight binary; when low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7
8
DGND
D1/A0
P
DI/O
Connect to Digital Ground.
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
9
D2/A1
D3
DI/O
When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
10
DO
11, 12 D[4:5]
or DIVSCLK[0:1]
DI/O
When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read
after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the
internally generated serial clock that clocks the data output. In other serial modes, these pins are
high impedance outputs.
13
D6
or EXT/INT
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the
internally generated (master) or external (slave) serial data clock.
When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,
gated by CS, connected to the SCLK input.
Rev. 0 | Page 8 of 28
AD7643
Pin
No.
Mnemonic
D7
or INVSYNC
Type1 Description
14
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this
input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
16
D8
or INVSCLK
DI/O
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.
D9
When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.
or RDC
When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode
(EXT/INT = low), RDC is used to select the read mode.
When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.
or SDIN
When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode (EXT/INT = high),
SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).
19
20
21
DVDD
DGND
D10
P
P
DO
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT
When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial
data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643
provides the conversion result, MSB first, from its internal shift register. The data format is
determined by the logic level of OB/2C.
In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK.
In slave mode, EXT/INT = high:
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial
data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low),
this output is used as a digital output frame synchronization for use with the internal data clock.
22
23
D11
or SCLK
DI/O
DO
D12
or SYNC
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
24
D13
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR
When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to
28
29
D[14:17]
BUSY
DO
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
30
DGND
P
Digital Power Ground.
Rev. 0 | Page 9 of 28
AD7643
Pin
No.
Mnemonic
Type1 Description
31
RD
DI
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32
33
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS
is also used to gate the external clock in slave serial mode.
RESET
DI
Reset Input. When high, resets the AD7643. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface
section. If not used, this pin can be tied to DGND.
34
35
37
PD
DI
Power-Down Input. When high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
CNVST
REF
DI
AI/O
Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
38
39
40
43
45
REFGND
IN−
NC
IN+
TEMP
AI
AI
Reference Input Analog Ground.
Differential Negative Analog Input.
No Connect.
AI
AO
Differential Positive Analog Input.
Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient
of 1 mV/°C. This pin can be used to measure the temperature of the AD7643. See the
Temperature Sensor section.
46
REFBUFIN
AI/O
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
47
48
PDREF
PDBUF
DI
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
Table 7. Data Bus Interface Definition
MODE MODE1 MODE0
2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
D0/OB/
0
1
1
2
2
2
2
3
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
R[0]
R[1]
R[2]
R[3]
R[3]
R[1]
R[4:9]
R[4:9]
R[10:11]
R[10:11]
R[12:15]
R[12:15]
R[16:17]
R[16:17]
18-Bit Parallel
16-Bit High Word
16-Bit Low Word
8-Bit High Byte
8-Bit Mid Byte
8-Bit Low Byte
8-Bit Low Byte
Serial Interface
2C
2C
2C
2C
2C
2C
2C
A0 = 0 R[2]
A0 = 1 R[0]
A0 = 0 A1 = 0
A0 = 0 A1 = 1
A0 = 1 A1 = 0
A0 = 1 A1 = 1
All Hi-Z
OB/
OB/
OB/
OB/
OB/
OB/
OB/
All Zeros
All Hi-Z
R[10:11]
R[2:3]
R[12:15]
R[4:7]
R[16:17]
R[8:9]
All Hi-Z
All Hi-Z
All Hi-Z
R[0:1]
All Zeros
R[0:1]
All Zeros
Serial Interface
Rev. 0 | Page 10 of 28
AD7643
TERMINOLOGY
Integral Nonlinearity Error (INL)
Total Harmonic Distortion (THD)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal to (Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Gain Error
Effective Number of Bits (ENOB)
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−2.0479922 V for the 2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479766 V for the
2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance and
CNVST
is measured from the falling edge of the
the input signal is held for a conversion.
input to when
Zero Error
Transient Response
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
The time required for the AD7643 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Dynamic Range
It is derived from the typical shift of output voltage at 25°C on a
sample of parts maximum and minimum reference output
voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is
expressed in ppm/°C using
It is the ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
VREF
(
Max
)
−VREF
(Min)
TCVREF
(ppm/°C
)
=
×106
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
VREF
(
25°C
)
×
(
TMAX −TMIN
)
where:
V
V
V
REF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX
REF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX
REF (25°C) = VREF at 25°C
T
MAX = +85°C
MIN = –40°C
T
Rev. 0 | Page 11 of 28
AD7643
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
1.25
1.0
2.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
0
65536
131072
CODE
196608
262144
0
65536
131072
CODE
196608
262144
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
40000
35000
30000
25000
20000
15000
10000
5000
35000
30000
25000
20000
15000
10000
5000
0
σ
REF
= 1.67
= 2.5V
σ
= 2.04
= 2.048V
V
V
REF
33606
28621
24350
26875
23521
18613
16141
15505
17320
13376
10173
6371
5401
4726
4848
3062
3807
2306
1295
488
665
305
297
0
1
3
59
16
3
0
108
228
21 28
3
2
0
CODE IN HEX
CODE IN HEX
Figure 6. Histogram of 131,072 Conversions of a DC Input at
the Code Center (External Reference)
Figure 9. Histogram of 131,072 Conversions of a DC Input at
the Code Center (Internal Reference)
2.0486
12
10
2.0484
2.0482
2.0480
2.0478
2.0476
2.0474
2.0472
2.0470
GAIN ERROR
8
6
4
2
0
ZERO ERROR
–2
–4
–6
–8
–10
–12
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Typical Reference Voltage Output vs. Temperature (2 Units)
Figure 10. Zero Error, Gain Error vs. Temperature
Rev. 0 | Page 12 of 28
AD7643
0
–20
0
–20
fS = 1.25MSPS
fIN = 20.03kHz
SNR = 93.4dB
THD = –113dB
SFDR = 108dB
SINAD = 93.4dB
fS = 1.25MSPS
fIN = 100.03kHz
SNR = 93dB
THD = –106dB
SFDR = 109dB
SINAD = 92.8dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
100
200
300
400
500
600
0
100
200
300
400
500
600
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. FFT 100 kHz
Figure 11. FFT 20 kHz
95
94
93
92
91
19
18
17
16
15
14
95
16.0
15.6
15.2
14.8
14.4
14.0
13.6
13.2
12.8
12.4
12.0
93
91
89
87
85
83
81
79
77
75
SNR
SNR
SINAD
SINAD
ENOB
ENOB
90
–55
1
10
100
1000
–35
–15
5
25
45
65
85
105
125
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 12. SNR, SINAD, and ENOB vs. Frequency
Figure 15. SNR, SINAD, and ENOB vs. Temperature
–70
–80
120
110
100
90
–85
–90
–95
120
110
100
90
SFDR
SFDR
–100
–90
–105
–110
–115
–120
–125
–130
–135
–140
–145
THD
80
–100
–110
–120
–130
–140
THD
70
THIRD
HARMONIC
60
80
50
THIRD HARMONIC
SECOND
HARMONIC
40
SECOND HARMONIC
70
30
20
1000
60
125
1
10
100
–55
–35
–15
5
25
45
65
85
105
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 13. THD, Harmonics, and SFDR vs. Frequency
Figure 16. THD, Harmonics, and SFDR vs. Temperature
Rev. 0 | Page 13 of 28
AD7643
96.0
95.5
95.0
94.5
94.0
93.5
93.0
100k
10k
1k
AVDD
DVDD
SNR
100
10
OVDD = 3.3V
SINAD
1
OVDD = 2.5V
0.1
0.01
PDREF = PDBUF = HIGH
100k 1M 10M
SAMPLING RATE (SPS)
–60
–50
–40
–30
–20
–10
0
10
100
1k
10k
INPUT LEVEL (dB)
Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale)
Figure 19. Operating Current vs. Sampling Rate
16
20
14
12
10
18
16
14
12
10
8
OVDD = 2.5V @ 85°C
OVDD = 2.5V @ 25°C
DVDD
OVDD, 3.3V
OVDD, 2.5V
8
6
4
OVDD = 3.3V @ 25°C
OVDD = 3.3V @ 85°C
2
6
AVDD
0
–55
4
–35
–15
5
25
45
65
85
105
125
0
50
100
150
200
TEMPERATURE (°C)
C
(pF)
L
Figure 20. Typical Delay vs. Load Capacitance CL
Figure 18. Power-Down Operating Currents vs. Temperature
Rev. 0 | Page 14 of 28
AD7643
APPLICATIONS INFORMATION
IN+
AGND
LSB
SWITCHES
CONTROL
SW+
MSB
131,072C
65,536C
65,536C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
REFGND
OUTPUT
CODE
131,072C
MSB
SW–
LSB
CNVST
AGND
IN–
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7643 is a very fast, low power, single-supply, precise
18-bit ADC using successive approximation architecture. The
AD7643 is capable of converting 1,250,000 samples per second
(1.25 MSPS).
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. A
conversion phase is initiated once the acquisition phase is complete
The AD7643 provides the user with an on-chip, track-and-hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
CNVST
and the
input goes low. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the inputs (IN+ and IN−) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4
throughVREF/262144). The control logic toggles these switches,
starting with the MSB first, to bring the comparator back into a
balanced condition. After the completion of this process, the
control logic generates the ADC output code and brings BUSY
output low.
The AD7643 can operate from a single 2.5 V supply and
interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed
in a Pb-free, 48-lead LQFP package or a tiny 48-lead LFCSP
package, which combines space savings with flexibility and
allows the AD7643 to be configured as either a serial or a
parallel interface. The AD7643 is pin-to-pin compatible with
the AD7641 and is a speed upgrade of the AD7674, AD7678,
and AD7679.
CONVERTER OPERATION
The AD7643 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.
Rev. 0 | Page 15 of 28
AD7643
TRANSFER FUNCTIONS
2C
Using the OB/ digital input, except in 18-bit interface mode,
Table 8. Output Codes and Ideal Input Voltages
Digital Output Code (Hex)
the AD7643 offers two output codings: straight binary and twos
complement. The LSB size with VREF = 2.048 V is 2 × VREF
262,144, which is 15.623 μV. Refer to Figure 22 and Table 8 for
the ideal transfer characteristic.
/
Analog Input
VREF = 2.048 V
Straight
Binary
Twos
Complement
Description
FSR −1 LSB
FSR − 2 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
+2.0479844 V
+2.0479688 V
+15.625 μV
0 V
−15.625 μV
−2.0479844 V
−2.048 V
0x3FFFF1
0x3FFFE
0x20001
0x20000
0x1FFFF
0x00001
0x1FFFF1
0x1FFFE
0x00001
0x00000
0x3FFFF
0x20001
111...111
111...110
111...101
0x000002 0x200002
1 This is also the code for overrange analog input (VIN+ − VIN− above
+VREF − VREFGND).
2 This is also the code for underrange analog input (VIN+ − VIN− below
−VREF + VREFGND).
000...010
000...001
000...000
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
–FSR
–FSR + 0.5 LSB
Figure 22. ADC Ideal Transfer Function
DIGITAL
SUPPLY (2.5V)
NOTE 5
10Ω
DIGITAL
INTERFACE
SUPPLY
ANALOG
SUPPLY (2.5V)
(2.5V OR 3.3V)
100nF
10µF
10µF
10µF
100nF
100nF
AVDD AGND DGND
REF
DVDD
OVDD
OGND
SERIAL
PORT
NOTE 3
SCLK
C
REF
10µF
REFBUFIN
REFGND
100nF
NOTE 4
SDOUT
BUSY
NOTE 7
NOTE 2
U1
MICROCONVERTER/
MICROPROCESSOR/
DSP
50Ω
15Ω
D
CNVST
IN+
50pF
ANALOG
INPUT +
AD7643
D0/OB/2C
C
2.7nF
C
MODE0
MODE1
NOTE 1
OVDD
NOTE 2
U2
CS
RD
15Ω
CLOCK
IN–
ANALOG
INPUT –
NOTE 3
C
C
2.7nF
50pF
PDREF
PDBUF
PD
RESET
NOTE 1
10kΩ
NOTE 6
1. SEE ANALOG INPUTS SECTION.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. OPTION, SEE POWER-UP SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 23. Typical Connection Diagram
Rev. 0 | Page 16 of 28
AD7643
TYPICAL CONNECTION DIAGRAM
switches. CIN is typically 12 pF and is mainly the ADC sampling
capacitor. During the conversion phase, when the switches are
opened, the input impedance is limited to CPIN. RIN and CIN
make a 1-pole, low-pass filter that has a typical −3 dB cutoff
frequency of 50 MHz, thereby reducing an undesirable aliasing
effect and limiting the noise coming from the inputs.
Figure 23 shows a typical connection diagram for the AD7643.
Different circuitry shown in this diagram is optional and is
discussed in the following sections.
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of
the AD7643.
Because the input impedance of the AD7643 is very high, the
AD7643 can be driven directly by a low impedance source
without gain error. To further improve the noise filtering achieved
by the AD7643’s analog input circuit, an external 1-pole RC
filter between the amplifier’s outputs and the ADC analog
inputs can be used, as shown in Figure 23. However, large source
impedances significantly affect the ac performance, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 26.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes the diodes to become forward-
biased and to start conducting current. These diodes can handle
a forward-biased current of 100 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
U1 or U2 supplies are different from AVDD. In such a case, an
input buffer with a short-circuit current limitation can be used
to protect the part.
AVDD
–70
D
D
C
1
2
R
IN
IN
IN+ OR IN–
AGND
–75
R
= 500Ω
S
C
PIN
–80
–85
R
= 100Ω
S
Figure 24. AD7643 Simplified Analog Input
–90
The analog input of the AD7643 is a true differential structure.
By using this differential input, small signals common to both
inputs are rejected, as shown in Figure 25, representing the
typical CMRR over frequency with internal and external references.
R
= 50Ω
S
–95
–100
–105
–110
R
= 10Ω
S
65
1
10
100
1000
INPUT FREQUENCY (kHz)
60
Figure 26. THD vs. Analog Input Frequency and Source Resistance
INT REF
MULTIPLEXED INPUTS
EXT REF
55
When using the full 1.25 MSPS throughput in multiplexed
applications for a full-scale step, the RC filter, as shown in
Figure 23, does not settle in the required acquisition time, t8.
These values are chosen to optimize the best SNR performance
of the AD7643. To use the full 1.25 MSPS throughput in
multiplexed applications, the RC should be adjusted to satisfy t8
(which is ~ 8.5 × RC time constant). However, lowering R and C
increases the RC filter bandwidth and allows more noise into the
AD7643, which degrades SNR. To preserve the SNR performance
in these applications using the RC filter shown in Figure 23,
the AD7643 should be run with t8 > 350 ns; or approximately
1/(t7 + t8) ~ 1.12 MSPS.
50
45
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of capacitor CPIN and the network formed by the
series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 175 Ω and is a lumped component
comprised of some serial resistors and the on resistance of the
Rev. 0 | Page 17 of 28
AD7643
The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
DRIVER AMPLIFIER CHOICE
Although the AD7643 is easy to drive, the driver amplifier
needs to meet the following requirements:
•
For multichannel, multiplexed applications, the driver
amplifier and the AD7643 analog input circuit must be
able to settle for a full-scale step of the capacitor array at an
18-bit level (0.0004%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at an 18-bit level
and should be verified prior to driver selection. The
AD8021 op amp, which combines ultralow noise and high
gain bandwidth, meets this settling time requirement even
when used with gains up to 13.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in
applications where high frequency (above 100 kHz) performance is
not required. In applications with a gain of 1, an 82 pF
compensation capacitor is required. The AD8610 is an option
when low bias current is needed in low frequency applications.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver, as shown in Figure 27, allows for a
differential input into the part. This configuration, when
provided an input signal of 0 to VREF, produces a differential
VREF with midscale at VREF/2. The 1-pole filter using R = 15 Ω
and C = 2.7 nF provides a corner frequency of 3.9 MHz.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7643. The noise coming from
the driver is filtered by the AD7643 analog input circuit
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. The SNR degradation due
to the amplifier is
If the application can tolerate more noise, the AD8139
differential driver can be used.
⎛
⎜
⎞
⎟
30
⎜
⎜
⎟
⎟
SNRLOSS = 20log
πf−3dB
2
πf−3dB
2
2
2
U1
⎜
⎜
⎟
⎟
900 +
(
NeN+
)
+
(NeN−
)
AD8021
ANALOG INPUT
⎝
⎠
(UNIPOLAR 0V TO 2.048V)
10pF
590Ω
590Ω
15Ω
where:
IN+
2.7nF
f
–3dB is the input bandwidth of the AD7643 (50 MHz) or
AD7643
the cutoff frequency of the input RC filter shown in Figure 23
(3.9 MHz), if one is used.
15Ω
U2
IN–
5kΩ
5kΩ
REF
AD8021
10pF
2.7nF
N is the noise factor of the amplifier (1 in buffer
configuration).
100nF
10µF
e
N+ and eN− are the equivalent input voltage noise densities
Figure 27. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
of the op amps connected to IN+ and IN−, in nV/√Hz.
This approximation can be used when the resistances used
around the amplifier are small. If larger resistances are
used, their noise contributions should also be root-sum
squared.
VOLTAGE REFERENCE INPUT
The AD7643 allows the choice of either a very low temperature
drift internal voltage reference, an external 1.2 V reference that
can be buffered using the internal reference buffer, or an
external reference.
For instance, when using op amps with an equivalent input
noise density of 2.1 nV/√Hz, such as the AD8021, with a
noise gain of 1 when configured as a buffer, degrades the
SNR by only 0.25 dB when using the RC filter in Figure 23,
and by 2.5 dB without it.
Unlike many ADCs with internal references, the internal
reference of the AD7643 provides excellent performance and
can be used in almost all applications.
•
The driver needs to have a THD performance suitable to
that of the AD7643. Figure 13 gives the THD vs. frequency
that the driver should exceed.
Rev. 0 | Page 18 of 28
AD7643
Internal Reference (PDBUF = Low, PDREF = Low)
occur when the driving voltage is above AVDD (for instance, at
power-up). In this case, a 125 Ω series resistor is recommended.
To use the internal reference, the PDREF and PDBUF inputs
must both be low. This produces a 1.2 V band gap output on
REFBUFIN, which is amplified by the internal buffer and
results in a 2.048 V reference on the REF pin.
Reference Decoupling
Whether using an internal or external reference, the AD7643
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs.
This decoupling depends on the choice of the voltage reference
but usually consists of a low ESR capacitor connected to REF
and REFGND with minimum parasitic inductance.
The internal reference is temperature compensated to 2.048 V
10 mV. The reference is trimmed to provide a typical drift of
8 ppm/°C. This typical drift characteristic is shown in Figure 7.
The output resistance of REFBUFIN is 6.33 kΩ (minimum)
when the internal reference is enabled. It is necessary to
decouple this with a ceramic capacitor greater than 100 nF.
Therefore, the capacitor provides an RC filter for noise reduction.
A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF
tantalum capacitor) is appropriate when using either the
internal reference or one of the recommended reference voltages.
Because the output impedance of REFBUFIN is typically
6.33 kΩ, relative humidity (among other industrial contaminates)
can directly affect the drift characteristics of the reference.
Typically, a guard ring is used to reduce the effects of drift
under such circumstances. However, because the AD7643 has a
fine lead pitch, guarding this node is not practical. Therefore, in
these industrial and other types of applications, it is recommended
to use a conformal coating, such as Dow Corning® 1-2577 or
HumiSeal® 1B73.
The placement of the reference decoupling is also important to
the performance of the AD7643. The decoupling capacitor
should be mounted on the same side as the ADC right at the
REF pin with a thick PCB trace. The REFGND should also connect
to the reference decoupling capacitor with the shortest distance.
For applications that use multiple AD7643 devices, it is more
effective to use an external reference with the internal reference
buffer to buffer the reference voltage. However, because the
reference buffers are not unity gain, ratiometric, simultaneously
sampled designs should use an external reference and external
buffer, such as the AD8031/AD8032; therefore, preserving the
same reference level for all converters.
External 1.2 V Reference and Internal Buffer (PDBUF =
Low, PDREF = High)
To use an external reference along with the internal buffer,
PDREF should be high and PDBUF should be low. This powers
down the internal reference and allows an external 1.2 V
reference to be applied to REFBUFIN, producing 2.048 V
(typically) on the REF pin.
The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance,
a 4 ppm/°C TC of the reference changes full scale by 1 LSB/°C.
External 2.5 V Reference (PDBUF = High, PDREF = High)
To use an external 2.5 V reference directly on the REF pin,
PDREF and PDBUF should both be high.
Note that VREF can be increased to AVDD + 0.1 V. Because the
input range is defined in terms of VREF, this would essentially
increase the range to 0 V to 2.8 V with an AVDD = 2.7 V.
For improved drift performance, an external reference, such as
the AD780 or ADR431, can be used. The advantages of directly
using the external voltage reference are:
Temperature Sensor
The TEMP pin measures the temperature of the AD7643. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as, ADG779), and the ADC itself is
used to measure its own temperature. This configuration is
shown in Figure 28.
•
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (2.5 V) instead of a typical 2.048 V reference
when the internal reference is used. This is calculated by
2.048
2.50
⎛
⎜
⎝
⎞
⎟
⎠
SNR = 20log
TEMP
ADG779
•
The power savings when the internal reference is powered
down (PDREF high).
TEMPERATURE
IN+
ANALOG INPUT
(UNIPOLAR)
SENSOR
AD7643
C
AD8021
C
PDREF and PDBUF power down the internal reference and
the internal reference buffer, respectively. The input current
of PDREF and PDBUF should never exceed 20 mA. This can
Figure 28. Use of the Temperature Sensor
Rev. 0 | Page 19 of 28
AD7643
POWER SUPPLY
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
The AD7643 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in Figure 23.
CONVERSION CONTROL
CNVST
The AD7643 is controlled by the
input. A falling edge
CNVST
on
is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in Figure 30. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
Power Sequencing
The AD7643 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
insensitive to power supply variations over a wide frequency
range, as shown in Figure 29.
CNVST
CS
complete. The
RD
signal operates independently of
and
signals.
t2
65.0
62.5
60.0
t1
CNVST
BUSY
57.5
EXT REF
t4
55.0
t3
t5
t6
52.5
50.0
47.5
45.0
INT REF
MODE
ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
Figure 30. Basic Conversion Timing
1
10
100
1000
10000
CNVST
For optimal performance, the rising edge of should not
occur after the maximum
of conversion.
FREQUENCY (kHz)
CNVST
low time, t1, or until the end
Figure 29. PSRR vs. Frequency
Power-Up
Although
is a digital signal, it should be designed with
CNVST
At power-up, or when returning to operational mode from the
power-down mode (PD = high), the AD7643 engages an
initialization process. During this time, the first 128 conversions
should be ignored or the RESET input could be pulsed to
engage a faster initialization process. Refer to the Digital
Interface section for RESET and timing details.
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The
trace should be shielded with ground and a low
CNVST
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 23.
A simple power-on reset circuit, as shown in Figure 23, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7643 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
For applications where SNR is critical, the
signal should
CNVST
have very low jitter. This can be achieved by using a dedicated
oscillator for generation, or by clocking with a
CNVST
CNVST
high frequency, low jitter clock, as shown in Figure 23.
Rev. 0 | Page 20 of 28
AD7643
INTERFACES
CS = RD = 0
CNVST
DIGITAL INTERFACE
t1
The AD7643 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7643
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic
with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic
high output voltage. In most applications, the OVDD supply pin
of the AD7643 is connected to the host system interface 2.5 V
t10
BUSY
t4
t3
t11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
2C
or 3.3 V digital supply. By using the D0/OB/ input pin, either
Figure 32. Master Parallel Data Timing for Reading (Continuous Read)
twos complement or straight binary coding can be used.
Slave Parallel Interface
CS
RD
control the interface. When at least
The two signals
one of these signals is high, the interface outputs are in high
CS
and
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 33 and
Figure 34, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
impedance. Usually,
multicircuit applications and is held low in a single AD7643
RD
allows the selection of each AD7643 in
design.
the data bus.
is generally used to enable the conversion result on
RESET
The RESET input is used to reset the AD7643 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to Figure 31 for the RESET
timing details.
CS
RD
t9
BUSY
RESET
CNVST
DATA
DATA
BUS
CURRENT
CONVERSION
t12
t13
Figure 33. Slave Parallel Data Timing for Reading (Read After Convert)
BUSY
t38
t39
t8
CS = 0
Figure 31. RESET Timing
CNVST,
RD
t1
PARALLEL INTERFACE
BUSY
t4
The AD7643 is configured to use the parallel interface for an
18-bit, 16-bit, or 8-bit bus width according to Table 7.
t3
Master Parallel Interface
DATA
BUS
PREVIOUS
CONVERSION
CS
RD
low, thus
Data can be continuously read by tying
and
t12
t13
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications, unless the device is held in RESET.
Figure 32 details the timing for this mode.
Figure 34. Slave Parallel Data Timing for Reading (Read During Convert)
Rev. 0 | Page 21 of 28
AD7643
16-Bit and 8-Bit Interface (Master or Slave)
MASTER SERIAL INTERFACE
Internal Clock
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35. By connecting A0/A1 to an
address line(s), the data can be read in two words for a 16-bit
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer
to Table 7 for the full details of the interface.
The AD7643 is configured to generate and provide the serial
data clock SCLK when the EXT/
pin is held low. The
INT
AD7643 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion. Figure 36 and
Figure 37 show detailed timing diagrams of these two modes.
CS, RD
Usually, because the AD7643 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.
A1
A0
HI-Z
HI-Z
HI-Z
HIGH
WORD
LOW
WORD
D[17:2]
HI-Z
t13
HIGH
BYTE
LOW
BYTE
MID
BYTE
D[17:10]
In read after conversion mode, it should be noted that unlike
other modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.
t12
t12
t12
Figure 35. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7643 is configured to use the serial interface when
MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.
In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing
details when using these inputs.
Rev. 0 | Page 22 of 28
AD7643
INVSCLK = INVSYNC = 0
DIVSCLK[1:0] = 0
EXT/INT = 0
RDC/SDIN = 0
CS, RD
CNVST
t3
t28
BUSY
SYNC
t30
t29
t25
t18
t19
t21
t14
t24
t20
t26
1
2
3
16
17
18
SCLK
t15
t27
SDOUT
D17
D16
t23
D2
D1
D0
X
t16
t22
Figure 36. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
CNVST
t1
t3
BUSY
SYNC
t17
t25
t19
t20 t21
t14
t24
t26
t15
SCLK
1
2
3
16
17
18
t18
t27
SDOUT
X
D17
D16
t23
D2
D1
D0
t16
t22
Figure 37. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. 0 | Page 23 of 28
AD7643
SLAVE SERIAL INTERFACE
External Clock
Finally, in this mode only, the AD7643 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple converters
together. This feature is useful for reducing component count
and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
The AD7643 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
pin is
INT
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by . When and
CS
CS
are both low, the data can be read after each conversion or
RD
An example of the concatenation of two devices is shown in
Figure 38. Simultaneous sampling is possible by using a
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 39 and Figure 40 show the detailed timing
diagrams of these methods.
CNVST
common
signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Therefore, the MSB of the
upstream converter just follows the LSB of the downstream
converter on the next SCLK cycle.
While the AD7643 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7643 provides error correction circuitry
that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided,
a discontinuous clock is toggled only when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
BUSY
OUT
BUSY
BUSY
AD7643
AD7643
#2
#1
(UPSTREAM)
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
External Discontinuous Clock Data Read After Conversion
SCLK IN
CS IN
Figure 39 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
CNVST IN
Figure 38. Two AD7643 Devices in a Daisy-Chain Configuration
low, the conversion result can be read while both
low. Data is shifted out MSB first with 18 clock pulses and is
valid on the rising and falling edges of the clock.
and
are
CS
RD
External Clock Data Read During Previous Conversion
Figure 40 shows the detailed timing diagrams of this method.
CS
RD
During a conversion, while
and
are both low, the result
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 80 MHz, which accommodates both the slow digital host
interface and the fast serial reading.
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and the RDC/SDIN input should always
be tied either high or low.
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
In this reading mode, it is recommended to pause digital
activity just prior to initiating a conversion (SCLK should be
held high or low). Once the conversion has begun, the reading
can continue. Also, in this mode, the use of a slower clock speed
can be used to read the data because the total reading time is the
acquisition time, t8 + half of the conversion time, t7 (t8 + ½ × t7, see
the External Clock Data Read During Previous Conversion
section).
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 67 MHz is recommended to
ensure that all the bits are read during the first half of the SAR
conversion phase, t7, because the ADC can correct for errors
introduced by digital activity during this time.
Rev. 0 | Page 24 of 28
AD7643
RD = 0
EXT/INT = 1
INVSCLK = 0
CS
BUSY
SCLK
t35
t36 t37
1
2
3
16
17
18
19
20
t31
t32
X
D17
D16
D15
X15
D1
X1
X17
Y17
X16
Y16
SDOUT
SDIN
D0
t16
t34
X17
X16
X0
t33
Figure 39. Slave Serial Data Timing for Reading (Read After Convert)
t31
RD = 0
EXT/INT = 1
INVSCLK = 0
CS
t3
CNVST
BUSY
t35
t36
t37
SCLK
16
4
17
18
2
3
1
t32
SDOUT
X
D1
D2
D17
D16
D15
D0
t16
Figure 40. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. 0 | Page 25 of 28
AD7643
SPI Interface (ADSP-219x)
MICROPROCESSOR INTERFACING
Figure 41 shows an interface diagram between the AD7643 and
an SPI-equipped DSP, the ADSP-219x. To accommodate the
slower speed of the DSP, the AD7643 acts as a slave device and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with three SPI byte access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
peripheral interface (SPI) on the ADSP-219x is configured for
master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock
phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) =
00 by writing to the SPI control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, allowing it to read an ADC result in less
than 1 μs. When a higher sampling rate is desired, it is
The AD7643 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The
AD7643 is designed to interface with a parallel 8-bit or 16-bit
wide interface or with a general-purpose serial port or I/O ports
on a microcontroller. A variety of external buffers can be used
with the AD7643 to prevent digital noise from coupling into the
ADC. The SPI Interface (ADSP-219x) section illustrates the use
of the AD7643 with the ADSP-219x SPI-equipped DSP.
recommended to use one of the parallel interface modes.
DVDD
AD7643
ADSP-219x1
MODE0
MODE1
BUSY
CS
PFx
EXT/INT
SPIxSEL (PFx)
MISOx
SDOUT
SCLK
CNVST
RD
SCKx
PFx OR TFSx
INVSCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 41. Interfacing the AD7643 to ADSP-219x
Rev. 0 | Page 26 of 28
AD7643
APPLICATION HINTS
LAYOUT
The DVDD supply of the AD7643 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, and no
separate supply is available, it is recommended to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. Refer
to Figure 23 for an example of this configuration. When DVDD
is powered from the system supply, it is useful to insert a bead
to further reduce high frequency spikes.
While the AD7643 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To
facilitate the use of ground planes that can be easily separated,
design the printed circuit board that houses the AD7643 so that
the analog and digital sections are separated and confined to
certain areas of the board. Digital and analog ground planes
should be joined in only one place, preferably underneath the
AD7643, or as close as possible to the AD7643. If the AD7643 is
in a system where multiple devices require analog-to-digital
ground connections, the connections should still be made at
one point only, a star ground point, established as close as
possible to the AD7643.
The AD7643 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and,
because it carries pulsed currents, should have a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be connected
with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.
To prevent coupling noise onto the die, avoid radiating noise,
and reduce feedthrough:
• Do not run digital lines under the device.
• Run the analog ground plane under the AD7643.
• Shield fast switching signals, like
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
or clocks, with
CNVST
The layout of the decoupling of the reference voltage is
important. To minimize parasitic inductances, place the
decoupling capacitor close to the ADC and connect it with
short, thick traces.
• Avoid crossover of digital and analog signals.
EVALUATING THE AD7643 PERFORMANCE
• Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough
through the board.
A recommended layout for the AD7643 is outlined in the
documentation of the EVAL-AD7643-CB evaluation board for
the AD7643. The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the EVAL-
CONTROL BRD3.
The power supply lines to the AD7643 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the impedance of the supplies presented
to the AD7643, and to reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should
be placed on each of the power supplies pins, AVDD, DVDD,
and OVDD. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding
ground pins. Additionally, low ESR 10 μF capacitors should be
located in the vicinity of the ADC to further reduce low
frequency ripple.
Rev. 0 | Page 27 of 28
AD7643
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
ELECTRICAL PERFORMANCES.
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
36
48
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
24
12
0.15
0.05
13
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 43. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
CP-48-1
CP-48-1
ST-48
ST-48
AD7643BCPZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
AD7643BCPZRL1
AD7643BSTZ1
AD7643BSTZRL1
EVAL-AD7643CB2
EVAL-CONTROL BRD33
Controller Board
1 Z = Pb-free part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06024–0–4/06(0)
Rev. 0 | Page 28 of 28
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