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AD7656A_17 [ADI]

250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC;
AD7656A_17
型号： AD7656A_17
厂家： ADI    ADI
描述：

250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
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250 kSPS, 6-Channel, Simultaneous  
Sampling, Bipolar 16-Bit ADC  
Data Sheet  
AD7656A  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CONVST A  
CONVST B CONVST C AV  
DV  
CC  
DD  
CC  
6 independent analog-to-digital converters (ADCs)  
True bipolar analog inputs  
CS  
Pin-/software-selectable ranges: ±10 V or ±± V  
Fast throughput rate: 2±0 kSPS  
iCMOS® process technology  
Low power: 140 mW at 2±0 kSPS with ± V supplies  
Wide input bandwidth  
86.± dB SNR at ±0 kHz input frequency  
On-chip reference and reference buffers  
Parallel, serial, and daisy-chain interface modes  
High speed serial interface  
Serial peripheral interface (SPI)/QSPI™/MICROWIRE®/DSP  
compatible  
Power-down mode: 100 mW maximum  
64-lead LQFP  
CLK  
OSC  
REF  
SER/PAR/SEL  
CONTROL  
LOGIC  
V
DRIVE  
STBY  
BUF  
BUF  
BUF  
OUTPUT  
DRIVERS  
DB8/DOUT A  
16-BIT SAR  
V1  
V2  
V3  
V4  
V5  
V6  
T/H  
SCLK  
16-BIT SAR  
16-BIT SAR  
T/H  
T/H  
T/H  
T/H  
OUTPUT  
DRIVERS  
DB9/DOUT B  
OUTPUT  
DRIVERS  
DB10/DOUT C  
16-BIT SAR  
16-BIT SAR  
16-BIT SAR  
DATA/  
CONTROL  
LINES  
OUTPUT  
DRIVERS  
RD  
Improved power supply sequencing (PSS) robustness  
WR/REF  
EN/DIS  
T/H  
V
AD7656A  
APPLICATIONS  
AGND  
DGND  
SS  
Power line monitoring systems  
Instrumentation and control systems  
Multi-axis positioning systems  
Figure 1.  
GENERAL DESCRIPTION  
The AD7656A1 contains six 16-bit, fast, low power, successive  
approximation analog-to-digital converters (ADCs) all in the  
one package that is designed on the iCMOS® process (industrial  
CMOS). iCMOS is a process combining high voltage silicon  
with submicron CMOS and complementary bipolar technologies.  
It enables the development of a wide range of high performance  
analog ICs, capable of 33 V operation in a footprint that no  
previous generation of high voltage devices could achieve. Unlike  
analog ICs using conventional CMOS processes, iCMOS  
components can accept bipolar input signals while providing  
increased performance, which dramatically reduces power  
consumption and package size.  
The conversion process and data acquisition are controlled  
using CONVST x signals and an internal oscillator. Three  
CONVST x pins (CONVST A, CONVST B, and CONVST C)  
allow independent, simultaneous sampling of the three ADC  
pairs. The AD7656A has a high speed parallel and serial interface,  
allowing the device to interface with microprocessors or digital  
signal processors (DSPs). In serial interface mode, the AD7656A  
has a daisy-chain feature that allows multiple ADCs to connect  
to a single serial interface. The AD7656A can accommodate  
true bipolar input signals in the 4 × VREF range and 2 × VREF  
range. The AD7656A also contains an on-chip 2.5 V reference.  
Multifunction pin names may be referenced by their relevant  
function only.  
The AD7656A features throughput rates of up to 250 kSPS. It  
contains wide bandwidth (12 MHz), track-and-hold amplifiers  
that can handle input frequencies up to 12 MHz.  
PRODUCT HIGHLIGHTS  
1. Six 16-bit, 250 kSPS ADCs on board.  
2. Six true bipolar, high impedance analog inputs.  
3. Parallel and high speed serial interfaces.  
1 Protected by U.S. Patent No. 6,731,232.  
Rev. 0  
Document Feedback  
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
 
AD7656A* PRODUCT PAGE QUICK LINKS  
Last Content Update: 04/14/2017  
COMPARABLE PARTS  
View a parametric search of comparable parts.  
DESIGN RESOURCES  
• AD7656A Material Declaration  
• PCN-PDN Information  
DOCUMENTATION  
Application Notes  
• Quality And Reliability  
• Symbols and Footprints  
• AN-893: Configuring the AD7656/AD7657/AD7658 for  
Serial and Daisy-Chain Interface Modes of Operation  
DISCUSSIONS  
View all AD7656A EngineerZone Discussions.  
• AN-931: Understanding PulSAR ADC Support Circuitry  
Data Sheet  
• AD7656A: 250 kSPS, 6-Channel, Simultaneous Sampling,  
Bipolar 16-Bit ADC Data Sheet  
SAMPLE AND BUY  
Visit the product page to see pricing options.  
User Guides  
• UG-535: Evaluating the AD7656/AD7657/AD7658, 250  
kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/  
12-Bit ADCs  
TECHNICAL SUPPORT  
Submit a technical question or find your regional support  
number.  
REFERENCE MATERIALS  
Solutions Bulletins & Brochures  
DOCUMENT FEEDBACK  
Submit feedback for this data sheet.  
• Emerging Energy Applications Solutions Bulletin, Volume  
10, Issue 4  
Technical Articles  
• MS-2210: Designing Power Supplies for High Speed ADC  
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AD7656A  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Theory of Operation ...................................................................... 15  
Converter Details ....................................................................... 15  
ADC Transfer Function............................................................. 16  
Reference Section ....................................................................... 16  
Typical Connection Diagram ................................................... 16  
Driving the Analog Inputs ........................................................ 17  
Interface Section......................................................................... 17  
Software Selection of ADCs...................................................... 19  
Serial Read Operation................................................................ 21  
Applications....................................................................................... 1  
Functional Block Diagram .............................................................. 1  
General Description......................................................................... 1  
Product Highlights ........................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Timing Specifications .................................................................. 5  
Absolute Maximum Ratings............................................................ 6  
Power Supply Sequencing ........................................................... 6  
Thermal Resistance ...................................................................... 6  
ESD Caution.................................................................................. 6  
Pin Configuration and Function Descriptions............................. 7  
Typical Performance Characteristics ........................................... 10  
Terminology .................................................................................... 13  
Daisy-Chain Mode (DCEN = 1, SER/  
/SEL = 1)............. 21  
PAR  
Application Hints ........................................................................... 24  
Layout .......................................................................................... 24  
Outline Dimensions....................................................................... 25  
Ordering Guide .......................................................................... 25  
REVISION HISTORY  
12/13—Revision 0: Initial Version  
Rev. 0 | Page 2 of 28  
 
Data Sheet  
AD7656A  
SPECIFICATIONS  
VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, and VDRIVE = 2.7 V to 5.25 V. For the 4 × VREF range,  
V
DD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the 2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. fSAMPLE =  
250 kSPS, and TA = TMIN to TMAX, unless otherwise noted.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE  
Signal-to-Noise + Distortion (SINAD)1  
Signal-to-Noise Ratio (SNR)1  
Total Harmonic Distortion (THD)1  
RANGE Pin = 0  
fIN = 50 kHz sine wave  
84  
85  
85.5  
86.5  
dB  
dB  
dB  
dB  
dB  
dB  
−90  
−92  
−100  
−100  
VDD/VSS = 6 V to 11 V  
VDD/VSS = 12 V to 16.5 V  
RANGE Pin = 1  
Peak Harmonic or Spurious Noise (SFDR)1  
Intermodulation Distortion (IMD)1  
Second-Order Terms  
fa = 50 kHz, fb = 49 kHz  
−112  
−107  
dB  
dB  
Third-Order Terms  
Aperture Delay  
10  
4
ns  
ns  
ps  
dB  
MHz  
MHz  
Aperture Delay Matching  
Aperture Jitter  
Channel-to-Channel Isolation1  
35  
−100  
12  
fIN on unselected channels up to 100 kHz  
At −3 dB  
At −0.1 dB  
Full Power Bandwidth  
2
DC ACCURACY  
Resolution  
16  
Bits  
No Missing Codes  
15  
16  
Bits  
Bits  
LSB  
At 25°C  
Integral Nonlinearity1  
3
1
LSB  
Positive Full-Scale Error1  
Positive Full-Scale Error Matching1  
Bipolar Zero-Scale Error1  
Bipolar Zero-Scale Error Matching1  
Negative Full-Scale Error1  
Negative Full-Scale Error Matching1  
0.22%  
0.75  
0.35  
0.023  
0.038  
0.75  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
0.004%  
0.22%  
0.35  
ANALOG INPUT  
See Table 6 for the minimum VDD/VSS  
for each range  
Input Voltage Ranges  
−4 × VREF  
−2 × VREF  
+4 × VREF  
+2 × VREF  
1
V
V
µA  
pF  
pF  
RANGE pin = 0  
RANGE pin = 1  
DC Leakage Current  
Input Capacitance2  
10  
14  
4 × VREF range when in track mode  
2 × VREF range when in track mode  
REFERENCE INPUT/OUTPUT  
Reference Input Voltage Range  
DC Leakage Current  
2.5  
3
1
V
µA  
pF  
Input Capacitance2  
18.5  
150  
6
REFEN/DIS = 13  
1000 hours  
Reference Output Voltage  
Long-Term Stability  
Reference Temperature Coefficient  
2.49  
2.51  
25  
V
ppm  
ppm/°C  
ppm/°C  
Rev. 0 | Page 3 of 28  
 
AD7656A  
Data Sheet  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
LOGIC INPUTS  
Input High Voltage (VINH  
)
0.7 × VDRIVE  
V
Input Low Voltage (VINL  
Input Current (IIN)  
)
0.3 × VDRIVE  
1
10  
V
µA  
pF  
Typically 10 nA, VIN = 0 V or VDRIVE  
Input Capacitance (CIN)2  
LOGIC OUTPUTS  
Output High Voltage (VOH)  
Output Low Voltage (VOL)  
Floating State Leakage Current  
Floating State Output Capacitance2  
Output Coding  
VDRIVE − 0.2  
V
V
µA  
pF  
ISOURCE = 200 µA  
ISINK = 200 µA  
0.2  
1
10  
CONVERSION RATE  
Conversion Time  
3.1  
µs  
Track-and-Hold Acquisition Time1, 2  
Throughput Rate  
POWER REQUIREMENTS  
VDD Range  
VSS Range  
AVCC  
550  
250  
ns  
kSPS  
Parallel interface mode only  
6
−6  
4.75  
4.75  
2.7  
16.5  
−16.5  
5.25  
5.25  
5.25  
V
V
V
V
V
For the 4 × VREF range, VDD = 11 V to 16.5 V  
For the 4 × VREF range, VSS = −11 V to −16.5 V  
DVCC  
VDRIVE  
4
ITOTAL  
Digital inputs = 0 V or VDRIVE  
AVCC = DVCC = VDRIVE = 5.25 V,  
Normal Mode (Static)  
28  
26  
mA  
mA  
V
DD = 16.5 V, VSS = −16.5 V  
Normal Mode (Operational)  
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE  
5.25 V, VDD = 16.5 V, VSS = −16.5 V  
=
ISS (Operational)  
IDD (Operational)  
Partial Power-Down Mode  
0.25  
0.25  
7
mA  
mA  
mA  
VSS = −16.5 V, fSAMPLE = 250 kSPS  
VDD = 16.5 V, fSAMPLE = 250 kSPS  
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,  
VSS = −16.5 V  
Full Power-Down Mode (STBY Pin)  
Power Dissipation  
80  
mA  
SCLK on or off, AVCC = DVCC = VDRIVE  
5.25 V, VDD = 16.5 V, VSS = −16.5 V  
AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V,  
VSS = −16.5 V  
=
Normal Mode (Static)  
143  
140  
35  
mW  
mW  
mW  
mW  
Normal Mode (Operational)  
Partial Power-Down Mode  
Full Power-Down Mode (STBY Pin)  
fSAMPLE = 250 kSPS  
100  
1 See the Terminology section.  
2 Sample tested during initial release to ensure compliance.  
3 Multifunction pin names may be referenced by their relevant function only.  
4 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC  
.
Rev. 0 | Page 4 of 28  
 
 
Data Sheet  
AD7656A  
TIMING SPECIFICATIONS  
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the  
4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V, and for the 2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to  
−16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and  
timed from a voltage level of 1.6 V.  
Table 2.  
Limit at TMIN, TMAX  
Parameter  
VDRIVE < 4.7± V VDRIVE = 4.7± V to ±.2± V Unit  
Description1  
PARALLEL INTERFACE MODE  
tCONVERT  
tQUIET  
3
150  
3
150  
µs typ  
ns min  
Conversion time, internal clock  
Minimum quiet time required between bus relinquish  
and start of next conversion  
tACQ  
t1  
t10  
550  
60  
25  
2
550  
60  
25  
2
ns min  
ns min  
ns min  
ms max  
Acquisition time  
CONVST x high to BUSY high  
Minimum CONVST x low pulse  
STBY rising edge to CONVST x rising edge, not  
shown in figures  
tWAKE-UP  
25  
25  
µs max  
Partial power-down mode  
PARALLEL WRITE OPERATION  
t11  
t12  
t13  
t14  
t15  
15  
0
15  
0
ns min  
ns min  
ns min  
ns min  
ns min  
WR pulse width  
CS to WR setup time  
5
5
CS to WR hold time  
5
5
Data setup time before WR rising edge  
Data hold after WR rising edge  
5
5
PARALLEL READ OPERATION  
t2  
0
0
ns min  
ns min  
ns min  
ns min  
ns max  
ns min  
ns max  
ns min  
BUSY to RD delay  
t3  
0
0
CS to RD setup time  
t4  
0
0
CS to RD hold time  
t5  
45  
45  
10  
12  
6
36  
36  
10  
12  
6
RD pulse width  
t6  
Data access time after RD falling edge  
Data hold time after RD rising edge  
Bus relinquish time after RD rising edge  
Minimum time between reads  
t7  
t8  
t9  
SERIAL INTERFACE MODE  
fSCLK  
t16  
18  
12  
18  
12  
MHz max Frequency of serial read clock  
ns max  
ns max  
ns min  
ns min  
ns min  
ns max  
Delay from CS until SDATA three-state disabled  
2
t17  
22  
22  
Data access time after SCLK rising edge/CS falling edge  
SCLK low pulse width  
SCLK high pulse width  
SCLK to data valid hold time after SCLK falling edge  
CS rising edge to SDATA high impedance  
t18  
t19  
t20  
t21  
0.4 × tSCLK  
0.4 × tSCLK  
10  
0.4 × tSCLK  
0.4 × tSCLK  
10  
18  
18  
1 Multifunction pin names may be referenced by their relevant function only.  
2 A buffer is used on the data output pins for this measurement.  
200µA  
I
OL  
TO OUTPUT  
PIN  
1.6V  
C
L
25pF  
200µA  
I
OH  
Figure 2. Load Circuit for Digital Output Timing Specifications  
Rev. 0 | Page 5 of 28  
 
 
 
AD7656A  
Data Sheet  
ABSOLUTE MAXIMUM RATINGS  
POWER SUPPLY SEQUENCING  
TA = 25°C, unless otherwise noted.  
Simultaneous application of VDD and VSS is necessary to  
guarantee reliability of the device. In the cases where  
simultaneous application cannot be guaranteed, VDD must power  
up before VSS. When a negative voltage is applied to the analog  
inputs before VDD and VSS are fully powered up, a 560 Ω resistor  
must be placed on the analog inputs.  
Table 3.  
Parameter  
Rating  
VDD to AGND, DGND  
VSS to AGND, DGND  
VDD to AVCC  
AVCC to AGND, DGND  
DVCC to AVCC  
DVCC to DGND, AGND  
AGND to DGND  
VDRIVE to DGND  
Analog Input Voltage to AGND  
Digital Input Voltage to DGND  
Digital Output Voltage to DGND  
REFIN/REFOUT to AGND  
Input Current to Any Pin Except Supplies1  
Operating Temperature Range  
Storage Temperature Range  
Junction Temperature  
Pb/Sn Temperature, Soldering  
Reflow (10 sec to 30 sec)  
0 V to +16.5 V  
0 V to −16.5 V  
AVCC + 0.7 V to 16.5 V  
−0.3 V to +7 V  
−0.3 V to AVCC + 0.3 V  
−0.3 V to +7 V  
−0.3 V to +0.3 V  
−0.3 V to DVCC + 0.3 V  
VSS + 1V to VDD − 1 V  
−0.3 V to VDRIVE + 0.3 V  
−0.3 V to VDRIVE + 0.3 V  
−0.3 V to AVCC + 0.3 V  
10 mA  
−40°C to +85°C  
−65°C to +150°C  
150°C  
A number of sequencing combinations can lead to temporary  
high current states; however, when all supplies are powered up,  
the device returns to normal operating currents. The analog  
input (AIN) coming before AVCC causes temporary high current  
on the analog inputs. Digital inputs before DVCC, and DVCC  
before other supplies, also cause temporary high current states.  
THERMAL RESISTANCE  
θJA is specified for the worst-case conditions, that is, a device  
soldered in a circuit board for surface-mount packages. These  
specifications apply to a 4-layer board.  
Table 4. Thermal Resistance  
Package Type  
θJA  
θJC  
Unit  
240(0)°C  
64-Lead LQFP  
45  
11  
°C/W  
Pb-Free Temperature, Soldering Reflow 260(0)°C  
1 Transient currents of up to 100 mA do not cause SCR latch-up.  
ESD CAUTION  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rev. 0 | Page 6 of 28  
 
 
 
 
 
 
Data Sheet  
AD7656A  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DB14/REFBUF  
V6  
AV  
AV  
V5  
EN/DIS  
DB13  
PIN 1  
2
3
CC  
CC  
DB12  
DB11  
4
5
DB10/DOUT C  
DB9/DOUT B  
DB8/DOUT A  
DGND  
AGND  
AGND  
V4  
6
AD7656A  
7
TOP VIEW  
8
(Not to Scale)  
AV  
AV  
V3  
CC  
CC  
9
V
DRIVE  
10  
11  
12  
13  
14  
15  
16  
DB7/HBEN/DCEN  
DB6/SCLK  
AGND  
AGND  
V2  
DB5/DCIN A  
DB4/DCIN B  
DB3/DCIN C  
DB2/SEL C  
AV  
AV  
V1  
CC  
CC  
DB1/SEL B  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions1  
Pin No.  
Mnemonic  
Description  
1
Data Bit 14/Reference Buffer Enable and Disable. When SER/PAR/SEL = 0, this pin acts as a three-  
state digital input/output pin.  
DB14/REFBUFEN  
/DIS  
2, 3, 64  
DB13, DB12, DB15  
Data Bit 13, Data Bit 12, and Data Bit 15. When SER/PAR/SEL = 0, these pins act as three-state parallel  
digital input/output pins. When CS and RD are low, these pins are used to output the conversion  
result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR/SEL =  
1, tie these pins to DGND.  
4
5
DB11  
Data Bit 11/Digital Ground. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1, tie this pin to DGND.  
DB10/DOUT C  
Data Bit 10/Serial Data Output C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs  
serial conversion data. this pin configures the serial interface to have three DOUT x output lines.  
Data Bit 9/Serial Data Output B. When SER/PAR/SEL = 0, Pin 6 acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1 and SEL B = 1, Pin 6 takes on its DOUT B function and outputs  
serial conversion data. this pin configures the serial interface to have two DOUT x output lines.  
Data Bit 8/Serial Data Output A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs  
serial conversion data.  
6
7
DB9/DOUT B  
DB8/DOUT A  
8, 25  
9
DGND  
VDRIVE  
Digital Ground. These pins are the ground reference point for all digital circuitry on the AD7656A.  
Connect both DGND pins to the DGND plane of a system. Ideally, the DGND and AGND voltages are at  
the same potential and must not be more than 0.3 V apart, even on a transient basis.  
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the  
interface. Nominally, it is at the same supply as the supply of the host interface. Decouple this pin to  
DGND, and place 10 µF and 100 nF decoupling capacitors on the VDRIVE pin.  
Rev. 0 | Page 7 of 28  
 
AD7656A  
Data Sheet  
Pin No.  
Mnemonic  
Description  
10  
DB7/HBEN/DCEN  
Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode (SER/PAR/SEL  
= 0 and W/B = 0), Pin 10 takes on its Data Bit 7 function. When operating in parallel byte mode  
(SER/PAR/SEL = 0 and W/B = 1), Pin 10 takes on its HBEN function. When in this mode and the HBEN  
pin is logic high, the data is output MSB byte first on DB15 to DB8. When the HBEN pin is logic low,  
the data is output LSB byte first on DB15 to DB8. When operating in serial mode (SER/PAR/SEL = 1),  
Pin 10 takes on its DCEN function. When the DCEN pin is logic high, the AD7656A operates in daisy-  
chain mode with DB5 to DB3 taking on their DCIN A to DCIN C function. When operating in serial  
mode but not in daisy-chain mode, tie DCEN to DGND.  
11  
12  
13  
14  
15  
DB6/SCLK  
Data Bit 6/Serial Clock. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output pin.  
When SER/PAR/SEL = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial  
transfer.  
Data Bit 5/Daisy-Chain Input A. When SER/PAR/SEL is low, this pin acts as a three-state parallel  
digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When  
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.  
Data Bit 4/Daisy-Chain Input B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When  
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.  
Data Bit 3/Daisy-Chain Input C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital  
output pin. When SER/PAR/SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When  
operating in serial mode but not in daisy-chain mode, tie this pin to DGND.  
DB5/DCIN A  
DB4/DCIN B  
DB3/DCIN C  
DB2/SEL C  
Data Bit 2/Select DOUT C. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output  
pin. When SER/PAR/SEL = 1, this pin takes on its SEL C function; it is used to configure the serial  
interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables  
DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data  
output pin. Leave unused serial DOUT pins unconnected.  
16  
17  
DB1/SEL B  
DB0/SEL A  
Data Bit 1/Select DOUT B. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output  
pin. When SER/PAR/SEL = 1, this pin takes on its SEL B function; it is used to configure the serial  
interface. If this pin is 1, the serial interface operates with two or three DOUT x output pins and  
enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial  
data output pin and only one DOUT output pin, DOUT A, is used. Leave unused serial DOUT pins  
unconnected.  
Data Bit 0/Select DOUT A. When SER/PAR/SEL = 0, this pin acts as a three-state parallel digital output  
pin. When SER/PAR/SEL = 1, Pin 17 takes on its SEL A function; it is used to configure the serial  
interface. If this pin is 1, the serial interface operates with one, two, or three DOUT x output pins and  
enables DOUT A as a serial output. When operating in serial mode, this pin must always be 1.  
18  
19  
BUSY  
CS  
Busy Output. This pin transitions high when a conversion is started and remains high until the  
conversion is complete and the conversion data is latched into the output data registers. Do not  
initiate a new conversion on the AD7656A when the BUSY signal is high.  
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low  
in parallel mode, the output bus is enabled and the conversion result is output on the parallel data  
bus lines. When both CS and WR are logic low in parallel mode, DB15 to DB8 are used to write data  
to the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and  
clock out the MSB of the serial output data.  
20  
RD  
Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial  
mode, hold the RD line low.  
21, 22, 23  
CONVST C,  
CONVST B,  
CONVST A  
Conversion Start Input C, Conversion Start Input B, and Conversion Start Input A. These logic inputs  
are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions  
on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C is  
used to initiate simultaneous conversions on V5 and V6. When CONVST x switches from low to high,  
the track-and-hold switch on the selected ADC pair switches from track to hold, and the conversion  
is initiated. These inputs can also be used to place the ADC pairs into partial power-down mode.  
24  
26  
STBY  
DVCC  
Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is  
high for normal operation and low for standby operation.  
Digital Power, 4.75 V to 5.25 V. Ideally, the DVCC and AVCC voltages are at the same potential and must  
not be more than 0.3 V apart, even on a transient basis. Decouple this supply to DGND, and place  
10 µF and 100 nF decoupling capacitors on the DVCC pin.  
Rev. 0 | Page 8 of 28  
Data Sheet  
AD7656A  
Pin No.  
Mnemonic  
Description  
27  
RANGE  
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range  
of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the  
next conversion is 2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the  
next conversion is 4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge  
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is  
determined by the RNGA, RNGB, and RNGC bits in the control register.  
28  
29  
RESET  
Reset Input. When set to logic high, this pin resets the AD7656A, and the current conversion, if  
any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656A is configured  
depending on the logic levels on the hardware select pins. In all modes, after power-up, the device  
must receive a RESET pulse. The reset high pulse is typically 100 ns wide. After the RESET pulse, the  
AD7656A needs to see a valid CONVST pulse to initiate a conversion; this typically consists of a high-  
to-low CONVST edge followed by a low-to-high CONVST edge. During the RESET pulse, the CONVST x  
signal must be high.  
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656A using  
the parallel data lines DB15 to DB0. When this pin is logic high, byte mode is enabled. In this mode,  
data is transferred using data lines DB15 to DB8 and DB7 takes on its HBEN function. To obtain the  
16-bit conversion result, 2-byte reads are required. In serial mode, tie this pin to DGND.  
W/B  
30  
31  
VSS  
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. Place  
10 µF and 100 nF decoupling capacitors on the VSS pin.  
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. Place  
10 µF and 100 nF decoupling capacitors on the VDD pin.  
VDD  
32, 37, 38, 43,  
44, 49, 52, 53,  
55, 57, 59  
AGND  
Analog Ground. Ground reference point for all analog circuitry on the AD7656A. Refer all analog input  
signals and any external reference signal to the AGND voltage. Connect all AGND pins to the AGND  
plane of a system. Ideally, the AGND and DGND voltages are at the same potential and must not be  
more than 0.3 V apart, even on a transient basis.  
33, 36, 39,  
42, 45, 48  
V1 to V6  
AVCC  
Analog Input 1 to Analog Input 6. These are six single-ended analog inputs. In hardware mode,  
the analog input range on these channels is determined by the RANGE pin. In software mode, it  
is determined by Bit RNGC to Bit RNGA of the control register (see Table 9).  
Analog Supply Voltage, 4.75 V to 5.25 V. The AVCC pin is the supply voltage for the ADC cores. Ideally,  
the AVCC and DVCC voltages are at the same potential and must not be more than 0.3 V apart, even  
on a transient basis. Decouple these supply pins to AGND, and place 10 µF and 100 nF decoupling  
capacitors on the AVCC pins.  
34, 35, 40,  
41, 46, 47,  
50, 60  
51  
REFIN/REFOUT  
Reference Input/Reference Output. The on-chip reference is available on Pin 51 for external use to  
the AD7656A. Alternatively, the internal reference can be disabled and an external reference can be  
applied to this input. See the Reference Section. When the internal reference is enabled, decouple  
Pin 51 using at least a 10 µF decoupling capacitor.  
54, 56, 58  
61  
REFCAPA, REFCAPB,  
REFCAPC  
Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are  
connected to these pins, which decouples the reference buffer for each ADC pair. Decouple each  
REFCAPx pin to AGND using 10 µF and 100 nF capacitors.  
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is  
high, the serial interface mode is selected. In serial mode, DB10 to DB8 take on their DOUT C to  
DOUT A function, DB0 to DB2 take on their DOUT select function, and DB7 takes on its DCEN  
function. In serial mode, tie DB15 and DB13 to DB11 to DGND  
SER/PAR/SEL  
62  
63  
H/S SEL  
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656A operates in hardware  
select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST x pins.  
When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the  
control register. In serial mode, CONVST A is used to initiate conversions on the selected ADC pairs.  
Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low,  
DB15 to DB8 are used to write data to the internal control register. When the H/S SEL pin is low, this  
pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal  
reference is disabled, and an external reference must be applied to the REFIN/REFOUT pin. When  
H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin must be  
decoupled. See the Reference Section.  
WR/REFEN/DIS  
1 Multifunction pin names may be referenced by their relevant function only.  
Rev. 0 | Page 9 of 28  
 
AD7656A  
Data Sheet  
TYPICAL PERFORMANCE CHARACTERISTICS  
0
2.0  
1.5  
V
/V = ±15V  
DD SS  
AV /DV /V  
INTERNAL REFERENCE  
±10V RANGE  
= +5V  
CC  
CC DRIVE  
–20  
–40  
T
= 25°C  
A
1.0  
f
f
= 250kSPS  
= 50kHz  
S
IN  
–60  
0.5  
SNR = +87.33dB  
SINAD = +87.251dB  
THD = –104.32dB  
SFDR = –104.13dB  
–80  
0
–100  
–120  
–140  
–160  
–0.5  
–1.0  
–1.5  
–2.0  
AV /DV /V  
= +5V  
CC  
CC DRIVE  
V
/V = ±12V  
DD SS  
f
= 250kSPS  
RANGE  
SAMPLE  
2 × V  
REF  
DNL WCP = 0.81LSB  
DNL WCN = –0.57LSB  
0
25  
50  
75  
100  
125  
0
10k  
20k  
30k  
CODE  
40k  
50k  
60k 65535  
FREQUENCY (kHz)  
Figure 4. FFT for 10 V Range  
Figure 7. Typical DNL  
0
–20  
90  
85  
80  
75  
70  
65  
AV /DV /V  
= +5.25V  
V
/V = ±12V  
CC  
CC DRIVE  
DD SS  
V
/V = ±16.5V  
AV /DV /V  
INTERNAL REFERENCE  
±5V RANGE  
= +5V  
DD SS  
CC  
CC DRIVE  
±10V RANGE  
AV /DV  
/
CC  
CC  
= +5V  
T
f
= 25°C  
= 250kSPS  
= 50kHz  
A
–40  
V
DRIVE  
V /V = ±12V  
AV /DV  
CC  
/
S
CC  
= +4.75 V  
DD SS  
±5V RANGE  
f
V
V
IN  
DRIVE  
/V = ±10V  
–60  
SNR = +86.252dB  
SINAD = +86.196dB  
THD = –105.11dB  
SFDR = –98.189dB  
DD SS  
±10V RANGE  
–80  
AV /DV  
CC  
/
CC  
= +5V  
–100  
–120  
–140  
–160  
V
V
DRIVE  
/V = ±5.25V  
DD SS  
±5V RANGE  
f
= 250kSPS  
INTERNAL REFERENCE  
= 25°C  
SAMPLE  
T
A
60  
10  
100  
ANALOG INPUT FREQUENCY (kHz)  
1000  
0
25  
50  
75  
100  
125  
FREQUENCY (kHz)  
Figure 8. SINAD vs. Analog Input Frequency  
Figure 5. FFT for 5 V Range  
–60  
–70  
2.0  
1.5  
f
= 250kSPS  
AV /DV /V  
= +5V  
SAMPLE  
CC  
CC DRIVE  
INTERNAL REFERENCE  
T
V
f
2 × V  
/V = ±12V  
DD SS  
= 25°C  
= 250kSPS  
RANGE  
A
SAMPLE  
AV /DV /V  
= +5V  
CC  
CC DRIVE  
REF  
V
/V = ±5.25V  
DD SS  
INL WCP = 0.64LSB  
INL WCN = –0.76LSB  
1.0  
±5V RANGE  
AV /DV  
/
CC  
CC  
–80  
V
V
= +4.75V  
DRIVE  
0.5  
/V = ±10V  
DD SS  
±10V RANGE  
AV /DV  
/
CC  
CC  
–90  
0
V
V
= +5V  
DRIVE  
/V = ±12V  
DD SS  
±5V RANGE  
–0.5  
–1.0  
–1.5  
–2.0  
–100  
–110  
–120  
AV /DV  
/
CC  
= +5.25V  
CC  
V
V
DRIVE  
/V = ±16.5V  
±10V RANGE  
DD SS  
10  
100  
1000  
0
10k  
20k  
30k  
CODE  
40k  
50k  
60k 65535  
ANALOG INPUT FREQUENCY (kHz)  
Figure 9. THD vs. Analog Input Frequency  
Figure 6. Typical INL  
Rev. 0 | Page 10 of 28  
 
Data Sheet  
AD7656A  
–60  
3.20  
3.15  
3.10  
3.05  
3.00  
2.95  
2.90  
2.85  
2.80  
2.75  
2.70  
V
/V = ±16.5V  
AV /DV /V  
= +5V  
DD SS  
CC  
CC DRIVE  
AV /DV /V  
= +5.25V  
V
/V = ±12V  
CC  
CC DRIVE  
DD SS  
T
= 25°C  
A
–70  
–80  
INTERNAL REFERENCE  
±4 × V RANGE  
REF  
R
= 1000Ω  
SOURCE  
–90  
R
= 100Ω  
SOURCE  
R
= 220Ω  
SOURCE  
–100  
–110  
–120  
R
= 10Ω  
SOURCE  
R
= 50Ω  
SOURCE  
10  
100  
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
ANALOG INPUT FREQUENCY (kHz)  
TEMPERATURE (°C)  
Figure 10. THD vs. Analog Input Frequency for Various Source Impedances,  
4 × VREF Range  
Figure 13. Conversion Time vs. Temperature  
–40  
3500  
3000  
2500  
2000  
1500  
1000  
500  
V
/V = ±12V  
DD SS  
3212  
AV /DV /V  
= +5V  
CC  
CC DRIVE  
V
/V = ±15V  
DD SS  
–50  
–60  
T
= 25°C  
A
AV /DV /V  
INTERNAL REFERENCE  
= +5V  
CC  
CC DRIVE  
2806  
INTERNAL REFERENCE  
±2 × V RANGE  
REF  
8192 SAMPLES  
–70  
–80  
R
= 1000Ω  
SOURCE  
1532  
–90  
R
= 220Ω  
SOURCE  
R
= 100Ω  
SOURCE  
–100  
–110  
–120  
392  
–3  
R
= 50Ω  
168  
25  
R
= 10Ω  
SOURCE  
SOURCE  
57  
–4  
0
0
3
0
–5  
10  
100  
–2  
–1  
0
1
2
ANALOG INPUT FREQUENCY (kHz)  
CODE  
Figure 11. THD vs. Analog Input Frequency for Various Source Impedances,  
2 × VREF Range  
Figure 14. Histogram of Codes  
2.510  
100  
90  
80  
70  
60  
50  
40  
f
= 250kSPS  
RANGE  
AV /DV /V  
= +5V  
SAMPLE  
CC  
CC DRIVE  
±2 × V  
INTERNAL REFERENCE  
T
f
V
/V = ±12V  
REF  
DD SS  
2.508  
2.506  
2.504  
2.502  
2.500  
2.498  
2.496  
2.494  
2.492  
= 25°C  
= 10kHz  
A
IN  
100nF ON V AND V  
DD  
SS  
V
SS  
V
DD  
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
30  
80  
130 180 230 280 330 380 430 480 530  
SUPPLY RIPPLE FREQUENCY (kHz)  
TEMPERATURE (°C)  
Figure 12. Reference Voltage vs. Temperature  
Figure 15. PSRR vs. Supply Ripple Frequency  
Rev. 0 | Page 11 of 28  
 
AD7656A  
Data Sheet  
87.0  
86.5  
86.0  
120  
110  
100  
90  
±5V RANGE  
AV /DV /V  
= +5V  
CC DRIVE  
CC  
85.5  
85.0  
84.5  
84.0  
83.5  
83.0  
±10V RANGE  
AV /DV /V  
V
/V = ±12V  
DD SS  
= +5.25V  
CC DRIVE  
CC  
V
/V = ±16.5V  
DD SS  
80  
AV /DV /V  
= 5V  
CC  
CC DRIVE  
V
/V = ±12V  
DD SS  
T
= 25°C  
A
70  
INTERNAL REFERENCE  
f
f
= 250kSPS  
= 50kHz  
SAMPLE  
±2 × V RANGE  
REF  
IN  
30kHz ON SELECTED CHANNEL  
20 40 60 80  
FREQUENCY OF INPUT NOISE (kHz)  
INTERNAL REFERENCE  
60  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
0
100  
120  
140  
TEMPERATURE (°C)  
Figure 16. SNR vs. Temperature  
Figure 18. Channel-to-Channel Isolation  
–100  
–101  
–102  
–103  
–104  
–105  
–106  
–107  
30  
25  
20  
15  
10  
5
f
f
= 250kSPS  
= 50kHz  
SAMPLE  
IN  
INTERNAL REFERENCE  
±10V RANGE  
±5V RANGE  
±10V RANGE  
AV /DV /V  
= +5.25V  
CC DRIVE  
CC  
V
/V = ±16.5V  
DD SS  
±5V RANGE  
AV /DV /V  
= +5V  
CC DRIVE  
CC  
V
/V = ±12V  
DD SS  
AV /DV /V  
= +5V  
CC  
CC DRIVE  
f
= 250kSPS  
SAMPLE  
FOR ±5V RANGE V /V = ±12V  
DD SS  
FOR ±10V RANGE V /V = ±16.5V  
DD SS  
0
–40  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
140  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 17. THD vs. Temperature  
Figure 19. Dynamic Current vs. Temperature  
Rev. 0 | Page 12 of 28  
Data Sheet  
AD7656A  
TERMINOLOGY  
Signal-to-Noise-and-Distortion (SINAD) Ratio  
Integral Nonlinearity (INL)  
The SINAD ratio is the measured ratio of signal-to-noise-and-  
distortion at the output of the ADC. The signal is the rms  
amplitude of the fundamental. Noise is the sum of all  
nonfundamental signals up to half the sampling frequency  
(fSAMPLE/2, excluding dc).  
INL is the maximum deviation from a straight line passing  
through the endpoints of the ADC transfer function. The  
endpoints of the transfer function are zero scale, a ½ LSB below  
the first code transition and full scale at ½ LSB above the last  
code transition.  
The ratio depends on the number of quantization levels in the  
digitization process: the more levels, the smaller the quantization  
noise. The theoretical SINAD ratio for an ideal N-bit converter  
with a sine wave input is given by  
Differential Nonlinearity (DNL)  
DNL is the difference between the measured and the ideal  
1 LSB change between any two adjacent codes in the ADC.  
Bipolar Zero-Scale Error  
SINAD = (6.02 N + 1.76) dB  
The bipolar zero-scale error is the deviation of the midscale  
transition (all 1s to all 0s) from the ideal VIN voltage, that is,  
AGND − 1 LSB.  
Therefore, SINAD is 98 dB for a 16-bit converter.  
Total Harmonic Distortion (THD)  
Bipolar Zero-Scale Error Matching  
The bipolar zero-scale error matching is the difference in  
bipolar zero-code error between any two input channels.  
THD is the ratio of the rms sum of the harmonics to the  
fundamental. For the AD7656A, it is defined as  
2
2
2
2
2
V2 +V3 +V4 +V5 +V6  
THD(dB) = 20log  
Positive Full-Scale Error  
The positive full-scale error is the deviation of the last code  
V1  
transition (011 … 110) to (011 … 111) from the ideal (4 × VREF  
1 LSB or 2 × VREF − 1 LSB) after adjusting for the bipolar zero  
scale error.  
–
where:  
V1 is the rms amplitude of the fundamental.  
V2, V3, V4, V5, and V6 are the rms amplitudes of the second  
through sixth harmonics.  
Positive Full-Scale Error Matching  
The positive full-scale error matching is the difference in  
positive full-scale error between any two input channels.  
Peak Harmonic or Spurious Noise  
The peak harmonic or spurious noise is the ratio of the rms value  
of the next largest component in the ADC output spectrum (up  
to fSAMPLE/2, excluding dc) to the rms value of the fundamental.  
Normally, the value of this specification is determined by the  
largest harmonic in the spectrum, but for ADCs where the  
harmonics are buried in the noise floor, it is determined by a  
noise peak.  
Negative Full-Scale Error  
The negative full-scale error is the deviation of the first code  
transition (10 … 000) to (10 … 001) from the ideal (−4 × VREF  
1 LSB or −2 × VREF + 1 LSB) after adjusting for the bipolar zero-  
code error.  
+
Negative Full-Scale Error Matching  
The negative full-scale error matching is the difference in  
negative full-scale error between any two input channels.  
Intermodulation Distortion (IMD)  
With inputs consisting of sine waves at two frequencies, fa and  
fb, any active device with nonlinearities create distortion  
products at sum and difference frequencies of mfa nfb, where  
m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for  
which neither m nor n are equal to 0. For example, the second-  
order terms include (fa + fb) and (fa − fb), and the third-order  
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).  
Track-and-Hold Acquisition Time  
The track-and-hold amplifier returns to track mode at the end  
of the conversion. The track-and-hold acquisition time is the  
time required for the output of the track-and-hold amplifier to  
reach its final value, within 1 LSB, after the end of the conversion.  
See the Track-and-Hold Amplifiers section for more details.  
The AD7656A is tested using the CCIF standard in which two  
input frequencies near the maximum input bandwidth are used.  
In this case, the second-order terms are usually distanced in  
frequency from the original sine waves, and the third-order  
terms are usually at a frequency close to the input frequencies.  
As a result, the second- and third-order terms are specified  
separately. The calculation of the intermodulation distortion is  
per the THD specification, where it is the ratio of the rms sum  
of the individual distortion products to the rms amplitude of  
the sum of the fundamentals expressed in decibels.  
Signal-to-Noise Ratio (SNR)  
SNR is the ratio of the rms value of the measured output signal  
to the rms sum of all other spectral components below the  
Nyquist frequency. The value for SNR is expressed in decibels.  
Rev. 0 | Page 13 of 28  
 
AD7656A  
Data Sheet  
Channel-to-Channel Isolation  
Figure 15 shows the power supply rejection ratio vs. supply  
Channel-to-channel isolation is a measure of the level of crosstalk  
between any two channels. It is measured by applying a full-scale,  
100 kHz sine wave signal to all unselected input channels and  
determining the degree to which the signal attenuates in the  
selected channel with a 30 kHz signal.  
ripple frequency for the AD7656A. The power supply rejection  
ratio is defined as the ratio of the power in the ADC output at the  
full-scale frequency, f, to the power of a 200 mV p-p sine wave  
applied to the VDD and VSS supplies of the fSAMPLE of the ADC.  
PSRR (dB) = 10 log (Pf/PfS)  
Power Supply Rejection Ratio (PSRR)  
where:  
Variations in power supply affect the full-scale transition but  
not the linearity of the converter. Power supply rejection is the  
maximum change in the full-scale transition point due to a change  
in power supply voltage from the nominal value. See the Typical  
Performance Characteristics section.  
Pf is equal to the power at frequency f in the ADC output.  
PfS is equal to the power at frequency fS coupled onto the VDD  
and VSS supplies.  
Percent Full-Scale Ratio (% FSR)  
%FSR is calculated using the full theoretical span of the ADC.  
Rev. 0 | Page 14 of 28  
Data Sheet  
AD7656A  
THEORY OF OPERATION  
Analog Input  
CONVERTER DETAILS  
The AD7656A can handle true bipolar input voltages. The logic  
level on the RANGE pin or the value written to the RNGx bits  
in the control register determines the analog input range on the  
AD7656A for the next conversion. When the RANGE pin or  
RNGx bit is 1, the analog input range for the next conversion is  
2 × VREF. When the RANGE pin or RNGx bit is 0, the analog  
The AD7656A is a high speed, low power converter that allows  
the simultaneous sampling of six on-chip analog-to-digital  
converts (ADCs). The analog inputs on the AD7656A can  
accept true bipolar input signals. The RANGE pin/RNGx bits  
are used to select either 4 × VREF or 2 × VREF as the input  
range for the next conversion.  
input range for the next conversion is 4 × VREF  
.
The AD7656A contains six successive approximation (SAR)  
ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference,  
reference buffers, and high speed parallel and serial interfaces.  
The AD7656A allows the simultaneous sampling of all six ADCs  
when the three CONVST x pins (CONVST A, CONVST B, and  
CONVST C) are tied together. Alternatively, the six ADCs can be  
grouped into three pairs. Each pair has an associated CONVST  
signal used to initiate simultaneous sampling on each ADC pair,  
on four ADCs, or on all six ADCs. CONVST A is used to initiate  
simultaneous sampling on V1 and V2, CONVST B is used to  
initiate simultaneous sampling on V3 and V4, and CONVST C  
is used to initiate simultaneous sampling on V5 and V6.  
V
DD  
V
_INTERNAL  
DD  
SS  
D1  
C2  
R1  
V1  
C1  
D2  
V
_INTERNAL  
V
SS  
Figure 20. Equivalent Analog Input Structure  
Figure 20 shows an equivalent circuit of the analog input of  
structure of the AD7656A. The two diodes, D1 and D2, provide  
ESD protection for the analog inputs. Care must be taken to  
ensure that the analog input signal never exceeds the VDD and  
A conversion is initiated on the AD7656A by pulsing the  
CONVST x input. On the rising edge of CONVST x, the track-  
and-hold amplifier of the selected ADC pair is placed into hold  
mode and the conversions are started. After the rising edge of  
CONVST x, the BUSY signal goes high to indicate that the  
conversion is taking place. The conversion clock for the  
AD7656A is internally generated, and the conversion time for  
the device is 3 µs. The BUSY signal returns low to indicate the  
end of conversion. On the falling edge of BUSY, the track-and-  
hold amplifier returns to track mode. Data can be read from the  
output register via the parallel or serial interface.  
V
SS supply rail limits by more than VSS + 1 V and VDD − 1 V.  
Signals exceeding this value cause these diode to become forward-  
biased and to start conducting into the substrate. The maximum  
current these diodes can conduct without causing irreversible  
damage to the device is 10 mA. Capacitor C1 in Figure 20 is  
typically about 4 pF and can be attributed primarily to pin  
capacitance. Resistor R1 is a lumped component made up of the  
on resistance of a switch (that is, track-and-hold switch). This  
resistor is typically about 25 Ω. Capacitor C2 is the ADC  
sampling capacitor and has a capacitance of 10 pF typically.  
Track-and-Hold Amplifiers  
The AD7656A requires VDD and VSS dual supplies for the high  
voltage analog input structures. These supplies must be greater  
than the analog input range (see Table 6 for the requirements on  
these supplies for each analog input range). The AD7656A  
requires a low voltage AVCC supply of 4.75 V to 5.25 V to power  
the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital  
power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface  
power.  
The track-and-hold amplifiers on the AD7656A allow the ADCs  
to accurately convert an input sine wave of full-scale amplitude  
to 16-bit resolution. The input bandwidth of the track-and-hold  
amplifiers is greater than the Nyquist rate of the ADC, even  
when the AD7656A is operating at its maximum throughput  
rate. The device can handle input frequencies of up to 12 MHz.  
The track-and-hold amplifiers sample their respective inputs  
simultaneously on the rising edge of CONVST x. The aperture time  
(that is, the delay time between the external CONVST x signal  
actually entering hold) for the track-and-hold is 10 ns. This is well  
matched across all six track-and-hold amplifiers on one device and  
from device to device. This allows more than six ADCs to be  
sampled simultaneously. The end of the conversion is signaled by  
the falling edge of BUSY, and it is at this point that the track-and-  
hold amplifiers return to track mode and the acquisition time  
begins.  
To meet the specified performance when using the minimum  
supply voltage for the selected analog input range, it may be  
necessary to reduce the throughput rate from the maximum  
throughput rate.  
Table 6. Minimum VDD/VSS Supply Voltage Requirements  
Analog Input  
Range (V)  
Reference  
Voltage (V)  
Full-Scale  
Input (V)  
Minimum  
VDD/VSS (V)  
4 × VREF  
4 × VREF  
2 × VREF  
2 × VREF  
2.5  
3.0  
2.5  
3.0  
10  
12  
5
11  
13  
6
6
7
Rev. 0 | Page 15 of 28  
 
 
 
 
 
AD7656A  
Data Sheet  
operating in external reference mode with the internal reference  
buffers enabled. The internal reference can be enabled in either  
hardware or software mode. To enable the internal reference in  
ADC TRANSFER FUNCTION  
The output coding of the AD7656A is twos complement. The  
designed code transitions occur midway between successive  
integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is  
FSR/65,536 for the AD7656A. The ideal transfer characteristic  
is shown in Figure 21.  
H
hardware mode, set the /S SEL pin to 0 and the REFEN/DIS pin to 1.  
H
To enable the internal reference in software mode, set the /S SEL  
pin to 1 and write to the control register to set DB9 of the  
control register to 1. For the internal reference mode, decouple  
the REFIN/REFOUT pin using 10 µF and 100 nF capacitors.  
011...111  
011...110  
The AD7656A contains three on-chip reference buffers. Each of  
the three ADC pairs has an associated reference buffer. These  
reference buffers require external decoupling capacitors on the  
REFCAPA, REFCAPB, and REFCAPC pins.Place 10 µF and  
100 nF decoupling capacitors on these REFCAPx pins. The  
internal reference buffers can be disabled in software mode by  
writing to Bit DB8 in the internal control register. If the serial  
interface is selected, the internal reference buffers can be disabled  
in hardware mode by setting the DB14/REFBUFEN/DIS pin high. If  
the internal reference and its buffers are disabled, apply an  
external buffered reference to the REFCAPx pins.  
000...001  
000...000  
111...111  
100...010  
100...001  
100...000  
AGND – 1LSB  
–FSR/2 + 1/2LSB  
+FSR/2 – 3/2LSB  
ANALOG INPUT  
Figure 21. Transfer Characteristic  
The LSB size is dependent on the analog input range selected  
(see Table 7).  
TYPICAL CONNECTION DIAGRAM  
Figure 22 shows the typical connection diagram for the AD7656A.  
There are eight AVCC supply pins on the device. The AVCC supply  
is the supply that is used for the AD7656A conversion process;  
therefore, it must be well decoupled. Individually decouple each  
AVCC supply pin with a 10 µF tantalum capacitor and a 100 nF  
ceramic capacitor. The AD7656A can operate with the internal  
reference or an externally applied reference. In this configuration,  
the device is configured to operate with the external reference.  
The REFIN/REFOUT pin is decoupled with a 10 µF and 100 nF  
capacitor pair. The three internal reference buffers are enabled.  
Each of the REFCAPx pins is decoupled with the 10 µF and  
100 nF capacitor pair.  
Table 7. LSB Size for Each Analog Input Range  
Input Range (V)  
LSB Size (mV)  
Full Scale Range  
10  
5
0.305  
0.152  
20 V/65,536  
10 V/65,536  
REFERENCE SECTION  
Either the REFIN/REFOUT pin allows access to the 2.5 V reference  
of the AD7656A, or it allows an external reference to be connected,  
providing the reference source for the conversions of the device.  
The AD7656A can accommodate a 2.5 V to 3 V external reference  
range. When using an external reference, the internal reference  
must be disabled. After a reset, the AD7656A defaults to  
DV  
CC  
DIGITAL SUPPLY  
VOLTAGE +3V OR +5V  
ANALOG SUPPLY  
1
VOLTAGE 5V  
+
+
+
10µF  
100nF  
100nF  
10µF  
100nF  
DGND  
10µF  
AGND AV  
DV  
DGND  
V
DRIVE  
CC  
CC  
2
+11.0V TO +16.5V  
V
DD  
SUPPLY  
PARALLEL  
INTERFACE  
+
DB0 TO DB15  
10µF  
100nF  
MICROPROCESSOR/  
MICROCONTROLLER/  
DSP  
AGND  
CONVST A, CONVST B, CONVST C  
REFCAPA, REFCAPB, REFCAPC  
CS  
RD  
+
10µF  
100nF  
100nF  
AGND  
BUSY  
AD7656A  
2.5V  
REF  
RESET  
REFIN/REFOUT  
AGND  
+
10µF  
SER/PAR/SEL  
H/S SEL  
W/B  
SIX ANALOG  
INPUTS  
RANGE  
2
–11.0V TO –16.5V  
SUPPLY  
V
SS  
V
STBY  
DRIVE  
10µF  
+
100nF  
AGND  
1
2
DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN.  
SEE THE POWER SUPPLY SEQUENCING SECTION.  
CC  
CC  
Figure 22. Typical Connection Diagram  
Rev. 0 | Page 16 of 28  
 
 
 
 
 
 
Data Sheet  
AD7656A  
Six of the AVCC supply pins are used as the supply to the six ADC  
cores on the AD7656A and, as a result, are used for the conversion  
process. Each analog input pin is surrounded by an AVCC supply  
pin and an AGND pin. These AVCC and AGND pins are the supply  
and ground for the individual ADC cores. For example, Pin 33 is  
V1, Pin 34 is the AVCC supply for ADC Core 1, and Pin 32 is  
AGND for ADC Core 1. An alternative reduced decoupling  
solution is to group these six AVCC supply pins into three pairs,  
Pin 34 and Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47.  
INTERFACE SECTION  
The AD7656A provides two interface options: a parallel interface  
and a high speed serial interface. The required interface mode is  
PAR  
selected via the SER/  
SEL pin. The parallel interface can  
W
W
operate in word ( /B = 0) or byte ( /B = 1) mode. The  
interface modes are discussed in the following sections.  
Parallel Interface (SER/  
SEL = 0)  
PAR/  
The AD7656A consists of six 16-bit ADCs. A simultaneous sample  
of all six ADCs can be performed by connecting all three CONVST x  
pins together (CONVST A, CONVST B, and CONVST C). The  
AD7656A needs to see a CONVST x pulse to initiate a conversion;  
this typically consists of a falling CONVST x edge followed by a  
rising CONVST x edge. The rising edge of CONVST x initiates  
simultaneous conversions on the selected ADCs. The AD7656A  
contains an on-chip oscillator that is used to perform the  
conversions. The conversion time, tCONVERT, is 3 µs. The BUSY signal  
goes low to indicate the end of conversion. The falling edge of  
the BUSY signal is used to place the track-and-hold amplifier  
into track mode. The AD7656A also allows the six ADCs to be  
converted simultaneously in pairs by pulsing the three  
CONVST x pins independently. CONVST A is used to initiate  
simultaneous conversions on V1 and V2, CONVST B is used to  
initiate simultaneous conversions on V3 and V4, and CONVST C  
is used to initiate simultaneous conversions on V5 and V6. The  
conversion results from the simultaneously sampled ADCs are  
stored in the output data registers.  
For the AD7656A, a 100 µF decoupling capacitor can be placed  
on each of the pin pairs. Decouple all of the other supply and  
reference pins with a 10 µF decoupling capacitor.  
If the same supply is being used for the AVCC supply and DVCC  
supply, place a ferrite or small RC filter between the supply pins.  
The AGND pins are connected to the analog ground plane of the  
system. The DGND pins are connected to the digital ground plane  
in the system. Connect the AGND and DGND planes together  
at one place in the system. Make this connection as close as  
possible to the AD7656A in the system.  
The VDRIVE supply is connected to the same supply as the processor.  
The voltage on VDRIVE controls the voltage value of the output  
logic signals.  
Decouple the VDD and VSS signals with a minimum 10 µF  
decoupling capacitor. These supplies are used for the high voltage  
analog input structures on the AD7656A analog inputs.  
DRIVING THE ANALOG INPUTS  
Data can be read from the AD7656A via the parallel data bus  
Together, the driver amplifier and the analog input circuit  
used for the AD7656A must settle for a full-scale step input to  
a 16-bit level (0.0015%), which is within the specified 550 ns  
acquisition time of the AD7656A. The noise generated by the  
driver amplifier must be kept as low as possible to preserve the  
SNR and transition noise performance of the AD7656A. In  
addition, the driver needs to have a THD performance suitable  
for the AD7656A.  
CS  
RD  
W
with standard  
and  
signals ( /B = 0). To read the data  
PAR CS RD  
over the parallel bus, tie SER/  
input signals are internally gated to enable the conversion result  
onto the data bus. The data lines, the DB0 to DB15 pins, leave  
SEL low. The  
and  
CS  
RD  
their high impedance state when both  
and  
are logic low.  
The AD8021 meets all these requirements. The AD8021 needs an  
external compensation capacitor of 10 pF. If a dual version of the  
AD8021 is required, the AD8022 can be used. The AD8610 and the  
AD797 can also be used to drive the AD7656A.  
Rev. 0 | Page 17 of 28  
 
 
AD7656A  
Data Sheet  
t10  
CONVST A,  
CONVST B,  
CONVST C  
tCONVERT  
tACQ  
BUSY  
t4  
CS  
RD  
t3  
t2  
t5  
t9  
t7  
t6  
t8  
tQUIET  
DATA  
V1  
V2  
V3  
V4  
V5  
V6  
W
Figure 23. Parallel Interface Timing Diagram ( /B = 0)  
CS  
RD  
t4  
t3  
t9  
t5  
t8  
t7  
t6  
DB15 TO DB8  
LOW BYTE  
HIGH BYTE  
W
Figure 24. Parallel Interface—Read Cycle for Byte Mode of Operation ( /B = 1, HBEN = 0)  
CS  
RD  
signal can  
If there is only an 8-bit bus available, the AD7656A interface can  
The  
signal can be permanently tied low, and the  
W
be configured to operate in byte mode ( /B = 1). In this  
be used to access the conversion results. A read operation can take  
place after the BUSY signal goes low. The number of required  
read operations depends on the number of ADCs that are  
simultaneously sampled (see Figure 23). If CONVST A and  
CONVST B are simultaneously brought low, four read operations  
are required to obtain the conversion results from V1, V2, V3, and  
V4. If CONVST A and CONVST C are simultaneously brought  
low, four read operations are required to obtain the conversion  
results from V1, V2, V5, and V6. The conversion results are  
output in ascending order.  
configuration, the DB7/HBEN/DCEN pin takes on its HBEN  
function. Each channel conversion result from the AD7656A  
can be accessed in two read operations, with eight bits of data  
provided on DB15 to DB8 for each of the read operations (see  
Figure 24). The HBEN pin determines whether the read  
operation first accesses the high byte or the low byte of the  
16-bit conversion result. To always access the low byte first on  
DB15 to DB8, tie the HBEN pin low. To always access the high  
byte first on DB15 to DB8, tie the HBEN pin high. In byte mode  
when all three CONVST x pins are pulsed together to initiate  
simultaneous conversions on all six ADCs, 12 read operations  
are necessary to read back the six 16-bit conversion results.  
Leave DB6 to DB0 unconnected in byte mode.  
When using the three CONVST x signals to independently initiate  
conversions on the three ADC pairs, ensure that a conversion is  
not initiated on a channel pair when the BUSY signal is high. It is  
also recommended not to initiate a conversion during a read  
sequence because doing so can affect the performance of the  
conversion. For the specified performance, it is recommended to  
perform the read after the conversion. For unused input  
channel pairs, tie the associated CONVST x pin to VDRIVE  
.
Rev. 0 | Page 18 of 28  
 
 
Data Sheet  
AD7656A  
SOFTWARE SELECTION OF ADCS  
The AD7656A control register allows individual ranges to be  
programmed on each ADC pair. DB12 to DB10 bits in the  
control register are used to program the range on each ADC pair.  
H
The /S SEL pin determines the source of the combination of  
H
ADCs that are to be simultaneously sampled. When the /S SEL  
pin is logic low, the combination of channels to be simultaneously  
sampled is determined by the CONVST A, CONVST B, and  
After a reset occurs on the AD7656A, the control register  
contains all zeros.  
H
CONVST C pins. When the /S SEL pin is logic high, the  
combination of channels selected for simultaneous sampling is  
determined by the contents of the DB15 to DB13 bits in the  
control register. In this mode, a write to the control register is  
necessary.  
The CONVST A signal is used to initiate a simultaneous  
conversion on the combination of channels selected via the  
control register. The CONVST B and CONVST C signals can be  
H
tied low when operating in software mode ( /S SEL = 1). The  
The control register is an 8-bit write-only register. Data is  
number of read pulses required depends on the number of  
ADCs selected in the control register and on whether the  
devices are operating in word or byte mode. The conversion  
results are output in ascending order.  
CS  
WR  
written to this register using the  
and  
pins and the DB15  
to DB8 data pins (see Figure 25). The control register is detailed  
in Table 8. To select an ADC pair to be simultaneously sampled,  
set the corresponding data line high during the write operation.  
CS  
During the write operation, Data Bus Bit DB15 to Data Bus  
Bit DB8 are bidirectional and become inputs to the control  
RD  
CS  
WR  
register when  
is logic high and  
and  
are logic low.  
WR  
The logic state on DB15 through DB8 is latched into the control  
t13  
t12  
t11  
WR  
register when  
goes logic high.  
t15  
t14  
DB15 TO DB8  
DATA  
W
Figure 25. Parallel Interface—Write Cycle for Word Mode ( /B= 0)  
Table 8. Control Register Bits (Default All 0s)  
DB1±  
DB14  
DB13  
DB12  
DB11  
DB10  
RNGA  
DB9  
DB8  
VC  
VB  
VA  
RNGC  
RNGB  
REFEN  
REFBUF  
Table 9. Control Register Bit Function Descriptions (Default All 0s)  
Bit  
Mnemonic Description  
DB15 VC  
This bit selects the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are  
simultaneously converted on the next CONVST A rising edge.  
DB14 VB  
This bit selects the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are  
simultaneously converted on the next CONVST B rising edge.  
DB13 VA  
This bit selects the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are  
simultaneously converted on the next CONVST C rising edge.  
DB12 RNGC  
DB11 RNGB  
DB10 RNGA  
This bit selects the analog input range for the V5 and V6 analog inputs. When this bit is set to 1, the 2 × VREF range is  
selected for the next conversion. When this bit is set to 0, the 4 × VREF range is selected for the next conversion.  
This bit selects the analog input range for the V3 and V4 analog inputs. When this bit is set to 1, the 2 × VREF range is  
selected for the next conversion. When this bit is set to 0, the 4 × VREF range is selected for the next conversion.  
This bit selects the analog input range for the V1 and V2 analog inputs. When this bit is set to 1, the 2 × VREF range is  
selected for the next conversion. When this bit is set to 0, the 4 × VREF range is selected for the next conversion.  
DB9  
DB8  
REFEN  
This bit selects the internal reference or an external reference. When this bit is set to 0, the external reference mode is  
selected. When this bit is set to 1, the internal reference is selected.  
REFBUF  
This bit selects between using the internal reference buffers and choosing to bypass these reference buffers. When this  
bit is set to 0, the internal reference buffers are enabled and decoupling is required on the REFCAPx pins. When this bit is  
set to 1, the internal reference buffers are disabled and a buffered reference is applied to the REFCAPx pins.  
Rev. 0 | Page 19 of 28  
 
 
 
 
AD7656A  
Data Sheet  
Changing the Analog Input Range ( /S SEL = 0)  
H
Figure 26 shows six simultaneous conversions and the read  
sequence using three DOUT x lines. Also in Figure 26, 32 SCLK  
transfers are used to access data from the AD7656A; however,  
The AD7656A RANGE pin allows the user to select either 2 ×  
VREF or 4 × VREF as the analog input range for the six analog  
CS  
two 16 SCLK individually framed transfers with the  
signal  
H
inputs. When the /S SEL pin is low, the logic state of the  
RANGE pin is sampled on the falling edge of the BUSY signal  
to determine the range for the next simultaneous conversion.  
When the RANGE pin is logic high at the falling edge of the  
can also be used to access the data on the three DOUT x lines.  
When the serial interface is selected and the conversion data  
clocks out on all three DOUTx lines, tie DB0/SEL A, DB1/SEL B,  
and DB2/SEL C to VDRIVE. These pins are used to enable the  
DOUT A to DOUT C lines, respectively.  
BUSY signal, the range for the next conversion is 2 × VREF  
When the RANGE pin is logic low at the falling edge of the  
.
If it is required to clock conversion data out on two data out lines,  
use DOUT A and DOUT B. To enable DOUT A and DOUT B,  
tie DB0/SEL A and DB1/SEL B to VDRIVE and tie DB2/SEL C low.  
When six simultaneous conversions are performed and only two  
DOUT x lines are used, a 48 SCLK transfer can be used to  
access the data from the AD7656A. The read sequence is shown  
in Figure 27 for a simultaneous conversion on all six ADCs  
using two DOUT x lines. If a simultaneous conversion occurred  
on all six ADCs, only two DOUT x lines are used to read the  
results from the AD7656A. DOUT A clocks out the result from  
V1, V2, and V5, and DOUT B clocks out the results from V3,  
V4, and V6.  
BUSY signal, the range for the next conversion is 4 × VREF  
After a RESET pulse, the range is updated on the first falling  
BUSY edge after the RESET pulse.  
.
Changing the Analog Input Range ( /S SEL = 1)  
H
H
When the /S SEL pin is high, the range can be changed by  
writing to the control register. Bits[DB12:DB10] in the control  
register are used to select the analog input ranges for the next  
conversion. Each analog input pair has an associated range bit,  
allowing independent ranges to be programmed on each ADC  
pair. When the RNGx bit is set to 1, the range for the next  
conversion is 2 × VREF. When the RNGx bit is set to 0, the  
range for the next conversion is 4 × VREF  
.
Data can also be clocked out using just one DOUT x line, in which  
case, use DOUT A to access the conversion data. To configure the  
AD7656A to operate in this mode, tie DB0/SEL A to VDRIVE and  
tie DB1/SEL B and DB2/SEL C low. The disadvantage of using  
only one DOUT x line is that the throughput rate is reduced.  
Data can be accessed from the AD7656A using one 96-SCLK  
transfer, three 32-SCLK individually framed transfers, or six 16-  
Serial Interface (SER/ /SEL = 1)  
PAR  
By pulsing one, two, or all three CONVST x signals, the AD7656A  
use their on-chip trimmed oscillator to simultaneously convert  
the selected channel pairs on the rising edge of CONVST x.  
After the rising edge of CONVST x, the BUSY signal goes high  
to indicate that the conversion has started. It returns low when  
the conversion is complete 3 µs later. The output register is  
loaded with the new conversion results, and data can be read  
from the AD7656A. To read the data back from the device over  
RD  
SCLK individually framed transfers. In serial mode, tie the  
signal low. Leave the unused DOUT x line(s) unconnected in serial  
mode.  
PAR  
CS  
the serial interface, tie SER/  
high. The  
and SCLK signals  
are used to transfer data from the AD7656A. The device has three  
DOUT x pins: DOUT A, DOUT B, and DOUT C. Data can be  
read back from the device using one, two, or all three DOUT x  
lines.  
CONVST A,  
CONVST B,  
CONVST C  
tCONVERT  
tACQ  
BUSY  
CS  
16  
32  
SCLK  
tQUIET  
DOUT A  
V1  
V3  
V5  
V2  
V4  
V6  
DOUT B  
DOUT C  
Figure 26. Serial Interface with Three DOUT x Lines  
Rev. 0 | Page 20 of 28  
 
Data Sheet  
AD7656A  
CS  
48  
SCLK  
DOUT A  
DOUT B  
V5  
V6  
V1  
V3  
V2  
V4  
Figure 27. Serial Interface with Two DOUT x Lines  
t1  
CONVST A,  
CONVST B,  
CONVST C  
t10  
tACQ  
tCONVERT  
t2  
BUSY  
ACQUISITION  
CONVERSION  
ACQUISITION  
CS  
tQUIET  
t19  
t18  
SCLK  
t16  
t17  
t20  
t21  
DB15  
DB14  
DB13  
DB1  
DB0  
DOUT A,  
DOUT B,  
DOUT C  
Figure 28. Serial Read Operation  
CONVERT  
DIGITAL HOST  
CONVST x  
CONVST x  
DOUT A  
DOUT B  
DCIN A  
DCIN B  
DOUT A  
DOUT B  
DATA IN1  
DATA IN2  
AD7656A  
AD7656A  
SCLK  
CS  
SCLK  
CS  
CS  
SCLK  
DCEN = 0  
DEVICE 2  
DCEN = 1  
DEVICE 1  
Figure 29. Daisy-Chain Configuration  
provide 16 clock pulses to the AD7656A. Figure 28 shows how a  
16-SCLK read is used to access the conversion results.  
SERIAL READ OPERATION  
Figure 28 shows the timing diagram for reading data from the  
AD7656A serial interface. The SCLK input signal provides the  
clock source for the serial interface. The  
DAISY-CHAIN MODE (DCEN = 1, SER/  
PAR  
/SEL = 1)  
CS  
signal goes low to  
CS  
When reading conversion data back from the AD7656A using  
their three, two, and one DOUT x pins, it is possible to configure  
the device to operate in daisy-chain mode using the DCEN pin.  
This daisy-chain feature allows multiple AD7656A devices to be  
cascaded together and is useful for reducing the component  
count and wiring connections. An example connection of two  
devices is shown in Figure 29. This configuration shows the use  
of two DOUT x lines. Simultaneous sampling of the 12 analog  
inputs is possible by using a common CONVST x signal. The  
DB5, DB4, and DB3 pins are used as the DCIN A to DCIN C data  
input pins for the daisy-chain mode.  
access data from the AD7656A. The falling edge of  
takes  
the bus out of a three-state condition and clocks out the MSB of  
the 16-bit conversion result. The ADCs output 16 bits for each  
conversion result; the data stream of the AD7656A consists of  
16 bits of conversion data provided MSB first.  
The first bit of the conversion result is valid on the first SCLK  
CS  
falling edge after the  
falling edge. The subsequent 15 data  
bits are clocked out on the rising edge of the SCLK signal. Data  
is valid on the SCLK falling edge. To access each conversion result,  
Rev. 0 | Page 21 of 28  
 
 
 
 
 
AD7656A  
Data Sheet  
The rising edge of CONVST x is used to initiate a conversion on  
the AD7656A. After the BUSY signal has gone low to indicate  
that the conversion is complete, the user can begin to read the data  
from the two devices. Figure 30 shows the serial timing diagram  
when operating two AD7656A devices in daisy-chain mode.  
During the first 48 SCLKs, Device 1 transfers data into the digital  
host. DOUT A on Device 1 transfers conversion data from V1,  
V2, and V5. DOUT B on Device 1 transfers conversion data from  
V3, V4, and V6. During the last 48-SCLKs, Device 2 clocks out  
zeros and Device 1 shifts the data clocked in from Device 2 during  
the first 48 SCLKs into the digital host. This example can also  
be implemented using six 16-SCLK individually framed transfers if  
DCEN remains high during the transfers.  
CS  
The  
falling edge is used to frame the serial transfer from the  
AD7656A to take the bus out of three-state and to clock out the  
MSB of the first conversion result. In the example shown in  
Figure 30, all 12 ADC channels are simultaneously sampled. Two  
DOUT x lines are used to read the conversion results in this  
Figure 31 shows the timing if two AD7656A devices are configured  
in daisy-chain mode and are operating with three DOUT x  
lines. Assuming a simultaneous sampling of all 12 inputs  
CS  
example. frames a 96-SCLK transfer. During the first 48 SCLKs,  
CS  
occurs, the  
frames a 64-SCLK transfer during the read  
the conversion data is transferred from Device 2 to Device 1.  
DOUT A on Device 2 transfers conversion data from V1, V2,  
and V5 into DCIN A in Device 1. DOUT B on Device 2 transfers  
conversion results from V3, V4, and V6 to DCIN B in Device 1.  
operation. During the first 32 SCLKs of this transfer, the  
conversion results from Device 1 are clocked into the digital  
host, and the conversion results from Device 2 are clocked into  
Device 1. During the last 32 SCLKs of the transfer, the  
conversion results from Device 2 are clocked out of Device 1  
and into the digital host. Device 2 clocks out zeros.  
CONVST A,  
CONVST B,  
CONVST C  
BUSY  
CS  
1
2
3
15  
16  
17  
31  
32  
33  
47  
48  
49  
63  
64  
65  
94  
95  
96  
SCLK  
DEVICE 1, DOUT A  
DEVICE 1, DOUT B  
DEVICE 2, DOUT A  
DEVICE 2, DOUT B  
MSB V1  
MSB V3  
MSB V1  
MSB V3  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V2 MSB V5  
LSB V4 MSB V6  
LSB V2 MSB V5  
LSB V4 MSB V6  
LSB V5 MSB V1  
LSB V6 MSB V3  
LSB V5  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V5  
LSB V6  
LSB V6  
Figure 30. Daisy-Chain Serial Interface Timing with Two DOUT x Lines  
CONVST A,  
CONVST B,  
CONVST C  
BUSY  
CS  
1
2
3
15  
16  
17  
31  
32  
33  
47  
48  
49  
63  
64  
SCLK  
DEVICE 1, DOUT A  
DEVICE 1, DOUT B  
DEVICE 1, DOUT C  
DEVICE 2, DOUT A  
DEVICE 2, DOUT B  
DEVICE 2, DOUT C  
MSB V1  
MSB V3  
MSB V5  
MSB V1  
MSB V3  
MSB V5  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V5 MSB V6  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V5 MSB V6  
LSB V2 MSB V1  
LSB V4 MSB V3  
LSB V6 MSB V5  
LSB V2  
LSB V1 MSB V2  
LSB V3 MSB V4  
LSB V5 MSB V6  
LSB V2  
LSB V4  
LSB V6  
LSB V4  
LSB V6  
Figure 31. Daisy-Chain Serial Interface Timing with Three DOUT x Lines  
Rev. 0 | Page 22 of 28  
 
 
Data Sheet  
AD7656A  
Standby/Partial Power-Down Modes of Operation  
(SER/PAR/SEL = 0 or SER/PAR/SEL = 1)  
STBY  
low and can be powered up again for normal  
logic input  
STBY  
operation by bringing  
logic high. The output data buffers  
are still operational when the AD7656A is in standby mode,  
meaning the user can continue to access the conversion results  
of the device. This standby feature can be used to reduce the  
average power consumed by the AD7656A when operating at  
lower throughput rates. The AD7656A can be placed into standby  
at the end of each conversion when BUSY goes low and taken out  
of standby again prior to the next conversion. The wake-up  
time is when the AD7656A comes out of standby mode. The  
wake-up time limits the maximum throughput rate at which the  
AD7656A can operate when powering down between  
conversions. See the Specifications section.  
Each ADC pair can be individually placed into partial power-  
down mode by bringing the CONVST x signal low before the  
falling edge of BUSY. Bring the CONVST x signal high to power  
up the ADC pair and place the track-and-hold amplifier into  
track mode. After the power-up time from the partial power-  
down has elapsed, the CONVST x signal typically receives a  
rising edge to initiate a valid conversion. In partial power-down  
mode, the reference buffers remain powered up. While an ADC  
pair is in partial power-down mode, conversions can still occur  
on the other ADCs.  
The AD7656A has a power-down mode whereby the device can  
be placed into a low power mode consuming 100 mW maximum.  
The AD7656A is placed into standby mode by bringing the  
Rev. 0 | Page 23 of 28  
AD7656A  
Data Sheet  
APPLICATION HINTS  
Good decoupling is also important to lower the supply impedance  
presented to the AD7656A and to reduce the magnitude of the  
supply spikes. Place decoupling ceramic capacitors, typically  
LAYOUT  
Design the printed circuit board (PCB) that houses the AD7656A  
so that the analog and digital sections are separated and confined  
to different areas of the board.  
100 nF, on all of the power supply pins, VDD, VSS, AVCC, DVCC  
and VDRIVE. Place these decoupling capacitors close to, but  
ideally right up against, these pins and their corresponding  
,
Use at least one ground plane. The ground plane can be common  
or split between the digital and analog sections. In the case of  
the split plane, join the digital and analog ground planes in only  
one place, preferably underneath the AD7656A, or at least as  
close as possible to the device.  
ground pins. Additionally, place low ESR 10 µF capacitors on  
each of the supply pins. Avoid sharing these capacitors between  
pins. Use big vias to connect the capacitors to the power and  
ground planes. Use wide, short traces between the via and the  
capacitor pad, or place the via adjacent to the capacitor pad to  
minimize parasitic inductances. Recommended decoupling  
capacitors are 100 nF, low ESR, ceramic capacitors and 10 µF, low  
ESR, tantalum capacitors for the AVCC decoupling. Place a large  
tantalum decoupling capacitor where the AVCC supply enters  
the board.  
If the AD7656A is in a system where multiple devices require  
analog-to-digital ground connections, still make the connection  
at only one point, a star ground point, and established it as close  
as possible to the AD7656A. Make good connections to the  
ground plane. Avoid sharing one connection for multiple  
ground pins. Use individual vias or multiple vias to the ground  
plane for each ground pin.  
An alternative reduced decoupling arrangement is outlined in  
the Typical Connection Diagram section. This decoupling  
arrangement groups the AVCC supply pins into pairs and allows  
the decoupling capacitors to be shared between the supply pairs.  
Group the six AVCC core supply pins into three pairs, Pin 34 and  
Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the  
supply pins in each pair together; their location on the AD7656A  
pin configuration easily facilitates this. For the AD7656A, decouple  
each pair with a 100 µF capacitor. For this minimum decoupling  
configuration, decouple all other supply and reference pins with  
a 10 µF decoupling capacitor.  
Avoid running digital lines under the device because doing so  
couples noise onto the die. Allow the analog ground plane to  
run under the AD7656A to avoid noise coupling. Shield fast  
switching signals, like CONVST x or clocks, with digital ground  
to avoid radiating noise to other sections of the board, and  
ensure that they never run near the analog signal paths. Avoid  
crossover of digital and analog signals. Run traces in close  
proximity on the board at right angles to each other to reduce  
the effect of feedthrough through the board.  
For the power supply lines to the AVCC, DVCC, VDRIVE, VDD, and  
V
SS pins on the AD7656A use as large a trace as possible to  
provide low impedance paths and to reduce the effect of glitches  
on the power supply lines. Establish good connections between  
the AD7656A supply pins and the power tracks on the board;  
involve the use of a single via or multiple vias for each supply  
pin.  
Rev. 0 | Page 24 of 28  
 
 
Data Sheet  
AD7656A  
OUTLINE DIMENSIONS  
12.20  
12.00 SQ  
11.80  
0.75  
0.60  
0.45  
1.60  
MAX  
64  
49  
1
48  
PIN 1  
10.20  
10.00 SQ  
9.80  
TOP VIEW  
(PINS DOWN)  
1.45  
1.40  
1.35  
0.20  
0.09  
7°  
3.5°  
0°  
0.08  
COPLANARITY  
16  
33  
0.15  
0.05  
SEATING  
17  
32  
PLANE  
VIEW A  
0.27  
0.22  
0.17  
0.50  
BSC  
LEAD PITCH  
VIEW A  
ROTATED 90° CCW  
COMPLIANT TO JEDEC STANDARDS MS-026-BCD  
Figure 32. 64-Lead Low Profile Quad Flat Package [LQFP]  
(ST-64-2)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
AD7656ABSTZ  
AD7656ABSTZ-RL  
Temperature Range  
−40°C to +85°C  
−40°C to +85°C  
Package Description  
Package Option  
64-Lead Low Profile Quad Flat Package [LQFP]  
64-Lead Low Profile Quad Flat Package [LQFP]  
ST-64-2  
ST-64-2  
1 Z = RoHS Compliant Part.  
Rev. 0 | Page 25 of 28  
 
 
 
AD7656A  
NOTES  
Data Sheet  
Rev. 0 | Page 26 of 28  
Data Sheet  
NOTES  
AD7656A  
Rev. 0 | Page 27 of 28  
AD7656A  
NOTES  
Data Sheet  
©2013 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D11127-0-12/13(0)  
Rev. 0 | Page 28 of 28  

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