AD7671ASTZ [ADI]
16-Bit, 1 MSPS CMOS ADC; 16位， 1 MSPS ADC CMOS
| 型号： | AD7671ASTZ |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1 MSPS CMOS ADC |
| 文件： | 总24页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
16-Bit, 1 MSPS CMOS ADC
AD7671
___
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Throughput
1 MSPS (Warp Mode)
AVDD AGND REF REFGND
DVDD DGND
800 kSPS (Normal Mode)
4R
4R
2R
R
IND(4R)
INC(4R)
INB(2R)
INA(R)
AD7671
INL: ꢀ2.5 LSB Max (ꢀ0.0038% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 250 kHz
THD: –100 dB Typ @ 250 kHz
Analog Input Voltage Ranges
Bipolar: ꢀ10 V, ꢀ5 V, ꢀ2.5 V
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
OVDD
OGND
SERIAL
PORT
SWITCHED
CAP DAC
SER/PAR
BUSY
D[15:0]
CS
INGND
PARALLEL
INTERFACE
16
CLOCK
PD
RESET
RD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OB/2C
BYTESWAP
WARP IMPULSE
CNVST
112 mW Typical
15 ꢁW @ 100 SPS
PulSAR Selection
Power-Down Mode: 7 ꢁW Max
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP)
Pin-to-Pin Compatible Upgrade of the AD7665/AD7664
Type/kSPS
100–250
500–570
800–1000
Pseudo
Differential
AD7660
AD7650
AD7664
True Bipolar
True Differential
18-Bit
AD7663
AD7675
AD7678
AD7665
AD7676
AD7679
AD7654
AD7671
AD7677
AD7674
AD7655
APPLICATIONS
Data Acquisition
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
Simultaneous/
Multichannel
GENERAL DESCRIPTION
It is fabricated using Analog Devices’ high performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP and a tiny
48-lead LFCSP, with operation specified from –40∞C to +85∞C.
The AD7671 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. It contains a high speed 16-bit sampling ADC, a resistor
input scaler that allows various input ranges, an internal
conversion clock, error correction circuits, and both serial
and parallel system interface ports.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7671 is a very high speed (1 MSPS in Warp Mode
and 800 kSPS in Normal Mode), charge redistribution, 16-bit
SAR ADC.
The AD7671 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
2. Single-Supply Operation
The AD7671 operates from a single 5 V supply, dissipates
only 112 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.
It features a very high sampling rate mode (Warp), a fast mode
(Normal) for asynchronous conversion rate applications, and, for
low power applications, a reduced power mode (Impulse) where
the power is scaled with the throughput.
3. Superior INL
The AD7671 has a maximum integral nonlinearity of 2.5 LSB
with no missing 16-bit code.
4. Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
Analog Devices, Inc. All rights reserved.
2012
©
AD7671–SPECIFICATIONS (–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
Common-Mode Input Voltage
Analog Input CMRR
Input Impedance
V
IND – VINGND
±4 REF, 0 V to 4 REF, ±2 REF (See Table I)
VINGND
fIN = 100 kHz
–0.1
+0.5
V
dB
74
See Table I
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time between Conversions
Complete Cycle
Throughput Rate
In Warp Mode
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
1
ms
1
1000
1
1.25
800
1.5
666
kSPS
ms
ms
0
0
kSPS
ms
Complete Cycle
Throughput Rate
kSPS
DC ACCURACY
Integral Linearity Error
No Missing Codes
–2.5
16
+2.5
+45
LSB1
Bits
LSB
LSB
Transition Noise
0.7
Bipolar Zero Error2, TMIN to TMAX
±5 V Range, Normal or
Impulse Modes
–45
Other Range or Mode
–0.1
+0.1
% of FSR
% of FSR
% of FSR
% of FSR
LSB
Bipolar Full-Scale Error2, TMIN to TMAX
Unipolar Zero Error2, TMIN to TMAX
Unipolar Full-Scale Error2, TMIN to TMAX
Power Supply Sensitivity
–0.38
–0.18
–0.76
+0.38
+0.18
+0.76
AVDD = 5 V ±5%
±9.5
AC ACCURACY
Signal-to-Noise
f
IN = 20 kHz
89
90
90
dB3
dB
fIN = 250 kHz
Spurious-Free Dynamic Range
Total Harmonic Distortion
fIN = 250 kHz
fIN = 20 kHz
fIN = 250 kHz
fIN = 20 kHz
100
–100
–100
90
dB
dB
dB
dB
–96
Signal-to-(Noise+Distortion)
88.5
fIN = 250 kHz, –60 dB Input
30
dB
–3 dB Input Bandwidth
9.6
MHz
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
2
5
ns
ps rms
ns
Transient Response
Full-Scale Step
250
REFERENCE
External Reference Voltage Range
External Reference Current Drain
2.3
2.5
200
AVDD – 1.85
V
mA
1 MSPS Throughput
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
–1
+0.8
DVDD + 0.3
+1
+1
V
V
mA
mA
IIH
–1
DIGITAL OUTPUTS
Data Format
Parallel or Serial 16-Bit
Pipeline Delay
Conversion Results Available Immediately
after Completed Conversion
0.4
OVDD – 0.6
VOL
VOH
ISINK = 1.6 mA
ISOURCE = –570 mA
V
V
REV. C
–2–
AD7671
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
5.25
5.254
V
V
V
DVDD
OVDD
Operating Current5
AVDD
1 MSPS Throughput
15
7.2
37
mA
mA
mA
mW
mW
mW
mW
DVDD6
OVDD6
Power Dissipation6, 7
666 kSPS Throughput8
100 SPS Throughput8
1 MSPS Throughput5
84
15
112
95
125
7
In Power-Down Mode9
TEMPERATURE RANGE10
Specified Performance
TMIN to TMAX
–40
+85
∞C
NOTES
1LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 mV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5In Warp Mode.
6Tested in Parallel Reading Mode.
7Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.
8In Impulse Mode.
9With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
10Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Input
Range
IND(4R)
INC(4R)
INB(2R)
INA(R)
Impedance1
±4 REF2
VIN
VIN
VIN
VIN
VIN
VIN
INGND
VIN
VIN
VIN
VIN
INGND
INGND
VIN
INGND
VIN
REF
REF
REF
INGND
INGND
VIN
1.63 kW
948 W
711 W
948 W
711 W
Note 3
±2 REF
±REF
0 V to 4 REF
0 V to 2 REF
0 V to REF
VIN
VIN
NOTES
1Typical analog input impedance.
2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3For this range the input is high impedance.
TIMING SPECIFICATIONS (–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time between Conversions
t1
t2
5
ns
ms
1/1.25/1.5
Note 1
30
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read after
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t3
t4
ns
0.75/1/1.25 ms
t5
t6
t7
t8
t9
2
ns
ns
10
0.75/1/1.25 ms
250
10
ns
ns
RESET Pulsewidth
REV. C
–3–
AD7671
TIMING SPECIFICATIONS (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t10
0.75/1/1.25 ms
t11
t12
t13
20
5
ns
40
15
ns
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
t14
t15
t16
t17
10
10
10
ns
ns
ns
ns
CNVST LOW to SYNC Delay (Read during Convert)
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
25/275/525
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
4
ns
ns
ns
ns
ns
ns
25
15
9.5
4.5
2
40
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
3
10
10
10
ns
ns
ns
ms
ms
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay
See Table II
0.75/1/1.25
t30
25
ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
16
External SCLK HIGH
External SCLK LOW
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum (Warp)
BUSY HIGH Width Maximum (Normal)
BUSY HIGH Width Maximum (Impulse)
t18
t19
t19
t20
t21
t22
t23
t24
t28
t28
t28
4
20
50
70
25
24
22
4
60
2
2.25
2.5
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
25
40
15
9
4.5
2
100
140
50
49
22
30
140
3
3.25
3.5
200
280
100
99
22
89
300
5.25
5.5
5.75
3
1.5
1.75
2
Specifications subject to change without notice.
REV. C
–4–
AD7671
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
Analog Inputs
ST-48 and CP-48-1
IND2, INC2, INB2 . . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND, AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . .2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range
48
47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
AGND
AVDD
36 AGND
PIN 1
IDENTIFIER
35
34
33
32
31
30
29
CNVST
PD
NC
BYTESWAP
RESET
CS
OB/2C
WARP
AD7671
TOP VIEW
RD
IMPULSE
SER/PAR
D0
DGND
BUSY
D15
(Not to Scale)
8
9
28
27
26
25
10
11
D1
D14
D2/DIVSCLK[0]
D13
D3/DIVSCLK[1] 12
D12
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C
13 14
15 16 17 18
21 22 23 24
19 20
NC = NO CONNECT
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2 See Analog Inputs section.
NOTES:
3 Specification is for device in free air: 48-Lead LQFP: qJA = 91∞C/W, qJC = 30∞C/W.
4 Specification is for device in free air: 48-Lead LFCSP: qJA = 26∞C/W.
1. PADDLE CONNECTED TO AGND FOR THE LFCSP (CP-48-1). THIS
CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
*
60pF
2V
I
0.8V
500ꢁA
OH
tDELAY
tDELAY
*
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
L
2V
0.8V
2V
0.8V
C
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
Figure 2. Voltage Reference Levels for Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7671 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–5–
AD7671
PIN FUNCTION DESCRIPTION
Pin
No.
Mnemonic
Type Description
1
2
AGND
AVDD
P
P
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
No Connect.
3, 44–48 NC
4
BYTESWAP
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
OB/2C
DI
DI
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.
6
WARP
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum
throughput is achievable and a minimum conversion rate must be applied in order to guarantee
full specified accuracy. When LOW, full accuracy is maintained independent of the minimum
conversion rate.
7
IMPULSE
SER/PAR
D[0:1]
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced Power Mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
8
DI
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial
Interface Mode is selected and some bits of the data bus are used as a Serial Port.
9, 10
11, 12
DO
DI/O
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are
in high impedance.
D[2:3] or
DIVSCLK[0:1]
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
13
D[4]
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for
choosing the internal or an external data clock, called Master and Slave Modes, respectively. With
EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
HIGH, output data is synchronized to an external clock signal connected to the SCLK input and
the external clock is gated by CS.
14
15
D[5]
DI/O
DI/O
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
D[6]
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is
active in both Master and Slave Mode.
16
D[7]
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input
or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output
on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can
be output on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19
20
DVDD
DGND
P
P
Digital Power. Nominally at 5 V.
Digital Power Ground.
REV. C
–6–
AD7671
PIN FUNCTION DESCRIPTION (continued)
Pin
No.
Mnemonic
Type Description
21
D[8]
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7671 provides
the conversion result, MSB first, from its internal shift register. The data format is determined
by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
22
23
D[9]
DI/O
DO
or SCLK
When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT
is updated depends upon the logic state of the INVSCLK pin.
D[10]
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence
is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT
output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW
and remains LOW while SDOUT output is valid.
24
D[11]
DO
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an
incomplete read error flag. In Slave Mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25–28
D[12:15]
BUSY
DO
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in
high impedance.
29
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could
be used as a data-ready clock signal.
30
31
32
DGND
RD
P
Must Be Tied to Digital Ground.
DI
DI
Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
CS
Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
CS is also used to gate the external serial clock.
33
34
35
RESET
PD
DI
DI
DI
Reset Input. When set to a logic HIGH, reset the AD7671. Current conversion, if any, is aborted.
If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
CNVST
Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion. In Impulse Mode (IMPULSE HIGH and WARP LOW), if CNVST is
held LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the
hold state and a conversion is immediately started.
36
37
38
39
AGND
REF
P
Must Be Tied to Analog Ground.
Reference Input Voltage.
AI
AI
P
REFGND
INGND
Reference Input Analog Ground.
Analog Input Ground.
40, 41,
42, 43
INA, INB,
INC, IND
AI
Analog Inputs. Refer to Table I for input range configuration.
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
Paddle connected to AGND for the LFCSP (CP-48-1). This connection is not required to meet the electrical performances.
REV. C
–7–
AD7671
DEFINITION OF SPECIFICATIONS
Effective Number of Bits (ENOB)
Integral Nonlinearity Error (INL)
A measurement of the resolution with a sine wave input. It is
related to S/(N+D) by the following formula:
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
ENOB = (S/[N + D]dB – 1.76)/6.02)
and is expressed in bits.
Total Harmonic Distortion (THD)
The rms sum of the first five harmonic components to the rms
value of a full-scale input signal, expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Full-Scale Error
The last transition (from 011 . . . 10 to 011 . . . 11 in twos
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the ±2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc. The value for
S/(N+D) is expressed in decibels.
Bipolar Zero Error
Aperture Delay
The difference between the ideal midscale input voltage (0 V) and
the actual voltage producing the midscale output code.
A measure of the acquisition performance measured from the
falling edge of the CNVST input to when the input signal is
held for a conversion.
Unipolar Zero Error
In Unipolar Mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.
Transient Response
The time required for the AD7671 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
REV. C
–8–
Typical Performance Characteristics–AD7671
60
2.5
2.0
50
40
30
20
10
0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
0
16384
32768
CODE
49152
65536
–3.0 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3
NEGATIVE INL – LSB
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Typical Negative INL Distribution (314 Units)
8000
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
7029 7039
7000
6000
5000
4000
3000
–0.25
–0.50
–0.75
–1.00
2000
1297
986
1000
0
0
17
25
0
0
0
0
16384
32768
CODE
49152
65536
7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8005
CODE IN HEXA
TPC 2. Differential Nonlinearity vs. Code
TPC 5. Histogram of 16,384 Conversions of a DC Input at
the Code Transition
10000
60
9503
9000
8000
7000
6000
5000
4000
50
40
30
20
10
0
3296
3344
3000
2000
1000
0
0
0
2
132
106
1
0
0
7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEXA
0
0.3
0.6 0.9
1.2
1.5
1.8
2.1 2.4
2.7 3.0
POSITIVE INL – LSB
TPC 3. Typical Positive INL Distribution (314 Units)
TPC 6. Histogram of 16,384 Conversions of a DC Input at
the Code Center
REV. C
–9–
AD7671
0
–98
96
93
90
87
84
FS = 1MSPS
fIN = 45.5322kHz
SNR = 89.45dB
THD = –100.05dB
SFDR = 100.49dB
SINAD = 89.1dB
–20
–40
–60
–100
–102
–104
THD
–80
–100
–120
–140
–160
SNR
–180
0
100
200
300
400
500
–55
–35
–15
5
25
45
65
85
105 125
FREQUENCY – kHz
TEMPERATURE – ꢂC
TPC 7. FFT Plot
TPC 10. SNR, THD vs. Temperature
100
95
16.0
110
105
100
95
–60
–65
SFDR
15.5
15.0
–70
–75
SNR
SINAD
90
85
80
75
–80
90
–85
14.5
14.0
13.5
85
–90
ENOB
80
SECOND HARMONIC
THD
–95
75
–100
–105
–110
–115
70
65
THIRD HARMONIC
70
1
13.0
1000
60
1000
10
100
FREQUENCY – kHz
1
10
100
FREQUENCY – kHz
TPC 8. SNR, S/(N + D), and ENOB vs. Frequency
TPC 11. THD, Harmonics, and SFDR vs. Frequency
–60
–70
–80
–90
92
90
88
86
–100
SECOND HARMONIC
–110
THD
–120
–130
THIRD HARMONIC
–140
–150
–60
–50
–40
–30
–20
–10
0
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL – dB
INPUT LEVEL – dB
TPC 12. THD, Harmonics vs. Input Level
TPC 9. SNR vs. Input Level
REV. C
–10–
AD7671
50
40
30
20
10
0
1000
900
800
700
600
500
400
300
200
100
0
DVDD
OVDD
AVDD
0
50
100
– pF
150
200
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE – ꢂC
C
L
TPC 13. Typical Delay vs. Load Capacitance CL
TPC 15. Power-Down Operating Currents vs. Temperature
100000
10
8
AVDD, WARP/NORMAL
10000
6
DVDD, WARP/NORMAL
1000
4
–FS
OFFSET
100
2
AVDD, IMPULSE
10
0
+FS
–2
–4
0
DVDD, IMPULSE
0.1
–6
–8
OVDD, ALL MODES
0.01
–10
0.001
–55
–35
–15
5
25
45
65
85
105 125
1
10
100
1000
10000
100000 1000000
TEMPERATURE – ꢂC
SAMPLING RATE – SPS
TPC 14. Operating Currents vs. Sample Rate
TPC 16. +FS, Offset, and –FS vs. Temperature
CIRCUIT INFORMATION
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The AD7671 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7671 features different
modes to optimize performances according to the applications.
The AD7671 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package or a 48-lead LFCSP package that com-
bines space savings and flexible configurations as either serial
or parallel interface. The AD7671 is a pin-to-pin compatible
upgrade of the AD7665 and AD7664.
In Warp Mode, the AD7671 is capable of converting 1,000,000
samples per second (1 MSPS).
The AD7671 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
REV. C
–11–
AD7671
4R
4R
2R
R
IND
REF
REFGND
INC
INB
INA
SWITCHES
CONTROL
MSB
SW
A
LSB
SW
32,768C 16,384C
4C
C
C
2C
BUSY
CONTROL
LOGIC
COMP
OUTPUT
CODE
INGND
65,536C
B
CNVST
Figure 3. ADC Simplified Schematic
CONVERTER OPERATION
Modes of Operation
The AD7671 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is
first scaled down and level shifted by the internal input resistive
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,
and 0 V to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V).
The output voltage range of the resistive scaler is always 0 V to
2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capacitor
of the same value as the capacitive DAC array.
The AD7671 features three modes of operation, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp Mode allows the fastest conversion rate up to 1 MSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7671 ideal
for applications where both high accuracy and fast sample rate
are required.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND via
SWA. All independent switches are connected to the output of the
resistive scaler. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal. Similarly, the dummy
capacitor acquires the analog signal on INGND input.
The Normal Mode is the fastest mode (800 kSPS) without any limi-
tation about the time between conversions. This mode makes the
AD7671 ideal for asynchronous applications such as data acquisi-
tion systems, where both high accuracy and fast sample rate are
required.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput in
this mode is 666 kSPS. When operating at 100 SPS, for example,
it typically consumes only 15 mW. This feature makes the AD7671
ideal for battery-powered applications.
When the acquisition phase is complete and the CNVST input goes
or is LOW, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor array
and the dummy capacitor are then disconnected from the inputs and
connected to the REFGND input. Therefore, the differential
voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
Transfer Functions
Using the OB/2C digital input, the AD7671 offers two output
codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7671 is shown in Figure 4 and Table III.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . . VREF/65,536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the completion
of this process, the control logic generates the ADC output code
and brings BUSY output LOW.
111...111
111...110
111...101
000...010
000...001
000...000
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
ANALOG INPUT
–FS + 0.5 LSB
Figure 4. ADC Ideal Transfer Function
REV. C
–12–
AD7671
Table III. Output Codes and Ideal Input Voltages
Analog Input
Digital Output
Code (Hexa)
Straight Twos
Binary Complement
Description
Full-Scale Range1
Least Significant Bit 305.2 mV
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
±10 V
±5 V
±2.5 V
0 V to 10 V 0 V to 5 V
152.6 mV 76.3 mV
0 V to 2.5 V
38.15 mV
152.6 mV
76.3 mV
9.999695 V 4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF2
305.2 mV
0 V
7FFF2
0001
0000
152.6 mV
0 V
–152.6 mV
76.3 mV
0 V
–76.3 mV
5.000153 V 2.570076 V 1.257038 V 8001
5 V 2.5 V 1.25 V 8000
4.999847 V 2.499924 V 1.249962 V 7FFF
–305.2 mV
FFFF
8001
–9.999695 V –4.999847 V –2.499924 V 152.6 mV
76.3 mV
0 V
38.15 mV
0 V
0001
–10 V
–5 V
–2.5 V
0 V
00003
80003
NOTES
1Values with REF = 2.5 V. With REF = 3 V, all values will scale linearly.
2This is also the code for an overrange analog input.
3This is also the code for an underrange analog input.
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7671. Different circuitry shown on this diagram is optional and is discussed below.
DVDD
20ꢃ
ANALOG
SUPPLY
(5V)
DIGITAL SUPPLY
(3.3V OR 5V)
NOTE 7
+
+
+
100nF
10ꢁF
100nF
100nF
10ꢁF
10ꢁF
ADR421
AVDD AGND
DGND
DVDD
OVDD
OGND
SERIAL
PORT
REF
2.5V REF
NOTE 1
SCLK
SDOUT
BUSY
1Mꢃ
+
C
50kꢃ
REF
NOTE 2
100nF
REFGND
NOTE 3
50ꢃ
ꢁC/ꢁP/DSP
D
CNVST
U2
+
INA
AD7671
NOTE 8
DVDD
10ꢁF
+
100nF
AD8031
NOTE 4
OB/2C
SER/PAR
50ꢃ
WARP
CLOCK
15ꢃ
2.7nF
NOTE 6
IMPULSE
CS
U1
+
NOTE 5
IND
ANALOG
INPUT
(ꢀ10V)
AD8021
RD
C
C
BYTESWAP
RESET
PD
INGND
INB
INC
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
IS 47ꢁF. SEE VOLTAGE REFERENCE INPUT SECTION.
REF
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. FOR BIPOLAR RANGE ONLY. SEE SCALER REFERENCE INPUT SECTION.
5. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
6. WITH 0V TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION.
7. OPTION. SEE POWER SUPPLY SECTION.
8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
Figure 5. Typical Connection Diagram (±10 V Range Shown)
REV. C
–13–
AD7671
Analog Inputs
75
70
The AD7671 is specified to operate with six full-scale analog input
ranges. Connections required for each of the four analog inputs,
IND, INC, INB, and INA, and the resulting full-scale ranges
are shown in Table I. The typical input impedance for each
analog input range is also shown.
65
60
Figure 6 shows a simplified analog input section of the AD7671.
55
50
The four resistors connected to the four analog inputs form a
resistive scaler that scales down and shifts the analog input range
to a common input range of 0 V to 2.5 V at the input of the
switched capacitive ADC.
45
40
AVDD
35
1
10
100
1000
10000
FREQUENCY – kHz
4R
IND
Figure 7. Analog Input CMRR vs. Frequency
4R
INC
Except when using the 0 V to 2.5 V analog input voltage range,
the AD7671 has to be driven by a very low impedance source to
avoid gain errors. That can be done by using a driver amplifier
whose choice is eased by the primarily resistive analog input
circuitry of the AD7671.
R1
C
2R
R
INB
INA
S
R = 375 Ω
When using the 0 V to 2.5 V analog input voltage range, the input
impedance of the AD7671 is very high so the AD7671 can be
driven directly by a low impedance source without gain error.
That allows, as shown in Figure 5, putting an external one-pole
RC filter between the output of the amplifier output and the
ADC analog inputs to even further improve the noise filtering
done by the AD7671 analog input circuit. However, the source
impedance has to be kept low because it affects the ac perfor-
mances, especially the total harmonic distortion (THD). The
maximum source impedance depends on the amount of total THD
that can be tolerated. The THD degradation is a function of the
source impedance and the maximum input frequency as shown
in Figure 8.
AGND
Figure 6. Simplified Analog Input
By connecting the four inputs INA, INB, INC, and IND to the
input signal itself, the ground, or a 2.5 V reference, other analog
input ranges can be obtained.
The diodes shown in Figure 6 provide ESD protection for the
four analog inputs. The inputs INB, INC, and IND have a high
voltage protection (–11 V to +30 V) to allow a wide input voltage
range. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs, including
INA (0 V to 5 V). This will cause these diodes to become forward-
biased and start conducting current. These diodes can handle
a forward-biased current of 120 mA maximum. For instance,
when using the 0 V to 2.5 V input range, these conditions could
eventually occur on the input INA when the input buffer’s (U1)
supplies are different from AVDD. In such cases, an input buffer
with a short-circuit current limitation can be used to protect the part.
–70
–80
R = 100ꢃ
R = 50ꢃ
This analog input structure allows the sampling of the differen-
tial signal between the output of the resistive scaler and INGND.
Unlike other converters, the INGND input is sampled at the
same time as the inputs. By using this differential input, small
signals common to both inputs are rejected as shown in Figure 7,
which represents the typical CMRR over frequency. For instance,
by using INGND to sense a remote signal ground, the difference of
ground potentials between the sensor and the local ADC ground
is eliminated. During the acquisition phase for ac signals, the
AD7671 behaves like a one-pole RC filter consisting of the
equivalent resistance of the resistive scaler R/2 in series with R1
and CS. The resistor R1 is typically 100 W and is a lumped
component made up of some serial resistors and the on resis-
tance of the switches.
–90
R = 11ꢃ
–100
–110
0
100
1000
FREQUENCY – kHz
Figure 8. THD vs. Analog Input Frequency and Input
Resistance (0 V to 2.5 V Only)
The capacitor CS is typically 60 pF and is mainly the ADC
sampling capacitor. This one-pole filter with a typical –3 dB
cutoff frequency of 9.6 MHz reduces undesirable aliasing effects
and limits the noise coming from the inputs.
REV. C
–14–
AD7671
Driver Amplifier Choice
Voltage Reference Input
Although the AD7671 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
The AD7671 uses an external 2.5 V voltage reference.
The voltage reference input REF of the AD7671 has a dynamic
input impedance; it should therefore be driven by a low impedance
source with an efficient decoupling between REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a 1 mF ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and REFGND
inputs with minimum parasitic inductance. 47 mF is an appropriate
value for the tantalum capacitor when used with one of the
recommended reference voltages:
∑
The driver amplifier and the AD7671 analog input circuit
must be able, together, to settle for a full-scale step the capaci-
tor array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% to 0.01% is more commonly speci-
fied. It could significantly differ from the settling time at
16-bit level and it should therefore be verified prior to the
driver selection. The tiny op amp AD8021, which combines
ultralow noise and a high gain bandwidth, meets this settling
time requirement even when used with a high gain up to 13.
∑
The low noise, low temperature drift ADR421 and AD780
voltage references
∑
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transi-
tion noise performance of the AD7671. The noise coming
from the driver is first scaled down by the resistive scaler
according to the analog input voltage range used and is then
filtered by the AD7671 analog input circuit one-pole, low-
pass filter made by (R/2 + R1) and CS. The SNR degradation
due to the amplifier is
∑
∑
The low power ADR291 voltage reference
The low cost AD1582 voltage reference
For applications using multiple AD7671s, it is more effective to
buffer the reference voltage with a low noise, very stable op amp
like the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference that directly affects the full-scale
accuracy if this parameter matters. For instance, a ±15 ppm/∞C
temperature coefficient of the reference changes the full scale
by ±1 LSB/∞C.
Ê
ˆ
Á
Á
Á
Á
˜
˜
˜
˜
28
SNRLOSS = 20 LOG
ˆ2
¯
Note that VREF , as mentioned in the Specifications table, could
be increased to AVDD – 1.85 V. The benefit here is the increased
SNR obtained as a result of this increase. Since the input range
is defined in terms of VREF, this would essentially increase the
±REF range from ±2.5 V to ±3 V and so on with an AVDD
above 4.85 V. The theoretical improvement as a result of this
increase in reference is 1.58 dB (20 log [3/2.5]). Due to the
theoretical quantization noise, however, the observed improve-
ment is approximately 1 dB. The AD780 can be selected with a
3 V reference voltage.
Ê
p
2
2.5 N eN
FSR
784 + f–3dB
Á
Ë
Á
Ë
˜ ˜
¯
where:
f–3 dB is the –3 dB input bandwidth in MHz of the AD7671
(9.6 MHz) or the cutoff frequency of the input filter if
any used (0 V to 2.5 V range).
N
is the noise factor of the amplifier (1 if in buffer
configuration).
Scaler Reference Input (Bipolar Input Ranges)
eN
is the equivalent input noise voltage of the op amp
When using the AD7671 with bipolar input ranges, the connec-
tion diagram in Figure 5 shows a reference buffer amplifier. This
buffer amplifier is required to isolate the REF pin from the signal
dependent current in the INx pin. A high speed op amp, such as the
AD8031, can be used with a single 5 V power supply without
degrading the performance of the AD7671. The buffer must have
good settling characteristics and provide low total noise within
the input bandwidth of the AD7671.
in nV/ΊHz.
FSR is the full-scale span (i.e., 5 V for ±2.5 V range).
For instance, when using the 0 V to 5 V range, a driver like
the AD8021, with an equivalent input noise of 2 nV/ΊHz and
configured as a buffer, thus with a noise gain of 1, the SNR
degrades by only 0.08 dB.
∑
The driver needs to have a THD performance suitable to that
of the AD7671. TPC 11 gives the THD versus frequency
that the driver should preferably exceed.
Power Supply
The AD7671 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and DVDD
+ 0.3 V. To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 5. The AD7671 is independent
of power supply sequencing, once OVDD does not exceed DVDD
by more than 0.3 V, and thus free from supply voltage induced
latch-up. Additionally, it is very insensitive to power supply varia-
tions over a wide frequency range as shown in Figure 9.
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs an external com-
pensation capacitor of 10 pF. This capacitor should have good
linearity as an NPO ceramic or mica type.
The AD8022 could also be used where a dual version is needed
and a gain of 1 is used.
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.
REV. C
–15–
AD7671
75
70
65
60
55
50
45
40
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7671 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of CS
and RD signals.
t2
t1
CNVST
35
1
10
100
1000
10000
BUSY
FREQUENCY – kHz
t4
t3
t6
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
In Impulse Mode, the AD7671 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows a
significant power savings when the conversion rate is reduced,
as shown in Figure 10. This feature makes the AD7671 ideal for
very low power battery applications.
t5
MODE
ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
Figure 11. Basic Conversion Timing
In Impulse Mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7671 controls
the acquisition phase and then automatically initiates a new conver-
sion. By keeping CNVST LOW, the AD7671 keeps the conversion
process running by itself. It should be noted that the analog input
has to be settled when BUSY goes LOW. Also, at power-up,
CNVST should be brought LOW once to initiate the conversion
process. In this mode, the AD7671 could sometimes run slightly
faster than the guaranteed limits in the Impulse Mode of
666 kSPS. This feature does not exist in Warp or Normal Modes.
This does not take into account the power, if any, dissipated by
the input resistive scaler, which depends on the input voltage
range used and the analog input voltage even in Power-Down
Mode. There is no power dissipated when the 0 V to 2.5 V is used
or when both the analog input voltage is 0 V and a unipolar range,
0 V to 5 V or 0 V to 10 V, is used.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum over-
shoot and undershoot or ringing. It is a good thing to shield the
CNVST trace with ground and also to add a low value serial
resistor (i.e., 50 W) termination close to the output of the
component that drives this line.
100000
WARP/NORMAL
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. To achieve this, some use a dedicated
oscillator for CNVST generation, or at least to clock it with a
high frequency low jitter clock as shown in Figure 5.
10000
1000
100
t9
RESET
10
IMPULSE
1
BUSY
0.1
1
10
100
1000
10000
100000 1000000
SAMPLING RATE – SPS
DATA BUS
Figure 10. Power Dissipation vs. Sample Rate
t8
CNVST
Figure 12. RESET Timing
REV. C
–16–
AD7671
DIGITAL INTERFACE
CS = 0
The AD7671 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7671 digital interface also accommodates both 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7671 to the
host system interface digital supply. Finally, by using the OB/2C
input pin, straight binary and twos complement coding can be used.
t1
CNVST,
RD
BUSY
t4
t3
The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7671 in
multicircuit applications and is held LOW in a single AD7671
design. RD is generally used to enable the conversion result on
the data bus.
PREVIOUS
DATA BUS
CONVERSION
t12
t13
Figure 15. Slave Parallel Data Timing for Reading (Read
during Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16 data bits
can be read in two bytes on either D[15:8] or D[7:0].
CS = RD = 0
t1
CNVST
t10
BUSY
t4
t3
t11
DATA BUS
PREVIOUS CONVERSION DATA
NEW DATA
CS
RD
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
BYTE
PARALLEL INTERFACE
The AD7671 is configured to use the parallel interface when the
SER/PAR is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or during
the following conversion as shown, respectively, in Figures 14 and
15. When the data is read during the conversion, however, it is
recommended that it be read-only during the first half of the con-
version phase. That avoids any potential feedthrough between
voltage transients on the digital interface and the most critical
analog conversion circuitry.
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
PINS D[15:8]
PINS D[7:0]
t12
t12
t13
HI-Z
LOW BYTE
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7671 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7671 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
CS
RD
SLAVE SERIAL INTERFACE
External Clock
BUSY
The AD7671 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS and the data
are output when both CS and RD are LOW. Thus, depending on
CS, the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either normally
HIGH or normally LOW when inactive. Figures 19 and 21
show the detailed timing diagrams of these methods.
CURRENT
DATA BUS
CONVERSION
t12
t13
Figure 14. Slave Parallel Data Timing for Reading (Read
after Convert)
REV. C
–17–
AD7671
MASTER SERIAL INTERFACE
Internal Clock
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
The AD7671 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. It also gener-
ates a SYNC signal to indicate to the host when the serial data is
valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on RDC/SDIN input, the data can be read
after each conversion or during conversion. Figures 17 and 18
show the detailed timing diagrams of these two modes.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns LOW after the 16 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
While the AD7671 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
dation of the conversion result could occur. This is particularly
important during the second half of the conversion phase because
Usually, because the AD7671 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
Serial Mode when it can be used.
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CS, RD
t3
CNVST
BUSY
t28
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
2
t26
1
3
14
15
16
SCLK
t15
t27
SDOUT
D2
D1
D0
D15
D14
t23
X
t16
t22
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
CNVST
BUSY
t1
t3
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
14
15
16
t18
t27
SDOUT
X
D15
D14
t23
D2
D1
D0
t16
t22
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
–18–
REV. C
AD7671
EXT/INT = 1
INVSCLK = 0
RD = 0
CS, RD
BUSY
t35
t36 t37
SCLK
1
2
3
14
15
16
17
18
t31
t32
X
D15
t34
D14
D13
X13
D1
X1
X15
Y15
X14
Y14
SDOUT
D0
X0
t16
SDIN
X15
X14
t33
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
the AD7671 provides error correction circuitry that can correct
for an improper bit decision made during the first half of the
conversion phase. For this reason, it is recommended that when
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly,
that does not transition during the latter half of BUSY HIGH.
BUSY
OUT
BUSY
BUSY
AD7671
#2
(UPSTREAM)
AD7671
#1
(DOWNSTREAM)
DATA
OUT
External Discontinuous Clock Data Read after Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning LOW,
the result of this conversion can be read while both CS and RD
are LOW. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both the rising and falling edge of the clock.
RDC/SDIN
SDOUT
RDC/SDIN SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
SCLK IN
CS IN
CNVST IN
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Figure 20. Two AD7671s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Another advantage is to be able to read the data at any speed up to
40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Figure 21 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both the rising and
the falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed HIGH and can be used to interrupt the host interface
to prevent incomplete data reading. There is no daisy-chain feature
in this mode, and RDC/SDIN input should always be tied either
HIGH or LOW.
Finally, in this mode only, the AD7671 provides a “daisy-chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in Fig-
ure 20. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Therefore, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
REV. C
–19–
AD7671
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
14
15
16
t31
t32
X
D15
D14
D13
D1
D0
SDOUT
t16
Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
DVDD
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 25 MHz when Impulse Mode is
used, 32 MHz when Normal or 40 MHz when Warp Mode is
used, is recommended to ensure that all the bits are read during
the first half of the conversion phase. It is also possible to begin
to read the data after conversion and continue to read the last bits
even after a new conversion has been initiated. That allows the use
of a slower clock speed like 18 MHz in Impulse Mode, 21 MHz
in Normal Mode, and 26 MHz in Warp Mode.
AD7671*
MC68HC11*
SER/PAR
EXT/INT
CS
RD
IRQ
BUSY
SDOUT
SCLK
MISO/SDI
SCK
INVSCLK
CNVST
I/O PORT
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
Figure 22. Interfacing the AD7671 to SPI Interface
The AD7671 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The AD7671
is designed to interface either with a parallel 8-bit or 16-bit wide
interface or with a general-purpose Serial Port or I/O Ports on a
microcontroller. A variety of external buffers can be used with
the AD7671 to prevent digital noise from coupling into the ADC.
The following sections illustrate the use of the AD7671 with an
SPI equipped microcontroller, the ADSP-21065L and ADSP-218x
signal processors.
ADSP-21065L in Master Serial Interface
As shown in Figure 23, the AD7671 can be interfaced to the
ADSP-21065L using the serial interface in Master Mode without
any glue logic required. This mode combines the advantages
of reducing the wire connections and the ability to read the
data during or after conversion at maximum speed transfer
(DIVSCLK[0:1] both low).
The AD7671 is configured for the Internal Clock Mode (EXT/INT
LOW) and acts therefore as the master device. The convert
command can be generated by either an external low jitter oscil-
lator or, as shown, by a FLAG output of the ADSP-21065L or by
a frame output TFS of one Serial Port of the ADSP-21065L, which
can be used like a timer. The Serial Port on the ADSP-21065L
is configured for external clock (IRFS = 0), rising edge active
(CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial
Port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)—see ADSP-2106x SHARC User’s
Manual. Because the Serial Port within the ADSP-21065L will
be seeing a discontinuous clock, an initial word reading has to
be done after the ADSP-21065L has been reset to ensure that
the Serial Port is properly synchronized to this clock during each
following data read operation.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7671 and an
SPI-equipped microcontroller, such as the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7671 acts as
a slave device and data must be read after conversion. This mode
also allows the daisy-chain feature. The convert command could be
initiated in response to an internal timer interrupt. The reading of
output data, one byte at a time if necessary, could be initiated in
response to the end-of-conversion signal (BUSY going low) using
an interrupt line of the microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for Master Mode
(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit
(CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing to
the SPI Control Register (SPCR). The IRQ is configured for edge-
sensitive-only operation (IRQE = 1 in the OPTION register).
REV. C
–20–
AD7671
The power supply lines to the AD7671 should use as large a trace
as possible to provide low impedance paths and reduce the effect of
glitches on the power supply lines. Good decoupling is also impor-
tant to lower the supplies impedance presented to the AD7671
and to reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed on all of
the power supply pins power supplies pins AVDD, DVDD, and
OVDD close to, and ideally right up against, these pins and
their corresponding ground pins. Additionally, low ESR 10 mF
capacitors should be located in the vicinity of the ADC to further
reduce low frequency ripple.
DVDD
AD7671*
ADSP-21065L*
SHARC®
SER/PAR
RDC/SDIN
RD
EXT/INT
CS
SYNC
SDOUT
SCLK
RFS
DR
INVSYNC
INVSCLK
RCLK
CNVST
FLAG ORTFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the ADSP-21065L Using
the Serial Master Mode
The DVDD supply of the AD7671 can be either a separate sup-
ply or come from the analog supply, AVDD, or from the digital
interface supply, OVDD. When the system digital supply is noisy,
or fast switching digital signals are present, it is recommended,
if no separate supply is available, to connect the DVDD digital
supply to the analog supply AVDD through an RC filter as shown
in Figure 5 and to connect the system supply to the interface
digital supply OVDD and the remaining digital circuitry. When
DVDD is powered from the system supply, it is useful to insert
a bead to further reduce high frequency spikes.
APPLICATION HINTS
Layout
The AD7671 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The printed circuit board that houses the AD7671 should be
designed so the analog and digital sections are separated and con-
fined to certain areas of the board. This facilitates the use of ground
planes that can be easily separated. Digital and analog ground
planes should be joined in only one place, preferably underneath
the AD7671, or, at least, as close as possible to the AD7671. If
the AD7671 is in a system where multiple devices require analog-
to-digital ground connections, the connection should still be made at
one point only, a star ground point, which should be established
as close as possible to the AD7671.
The AD7671 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the
analog input signal. REFGND senses the reference voltage and
should be a low impedance return to the reference because it carries
pulsed currents. AGND is the ground to which most internal ADC
analog signals are referenced. This ground must be connected
with the least resistance to the analog ground plane. DGND must
be tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system ground.
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7671 to avoid noise
coupling. Fast switching signals like CNVST or clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board.
The layout of the decoupling of the reference voltage is important.
The decoupling capacitor should be close to the ADC and con-
nected with short and large traces to minimize parasitic inductances.
Evaluating the AD7671 Performance
A recommended layout for the AD7671 is outlined in the evalua-
tion board for the AD7671. The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the Eval-
Control Board.
REV. C
–21–
AD7671
Data Sheet
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 1. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 2. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-48
ST-48
CP-48-1
CP-48-1
AD7671ASTZ
AD7671ASTZRL
AD7671ACPZ
AD7671ACPZRL
EVAL-AD7671EDZ
EVAL-CED1Z
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Converter Evaluation and Development Board
1 Z = RoHS Compliant Part.
Rev. C | Page 22 of 24
Data Sheet
AD7671
REVISION HISTORY
4/12—Rev. B to Rev. C
5/02—Rev. 0 to Rev. A.
Added Exposed Pad Notation to Pin Configuration................... 5
Added Exposed Pad Notation to Pin Function Description
Table ................................................................................................... 7
Change to Figure 6 ......................................................................... 14
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 22
Edits to Features................................................................................ 1
Edits to General Description ...........................................................1
Chart Added to Product Highlights ...............................................1
Edits to Specifications ................................................................. 2–3
Edits to Table I ..................................................................................3
Edits to Absolute Maximum Ratings .............................................5
Edits to Ordering Guide ..................................................................5
Edits to TPC 4....................................................................................9
New TPC 9 ..................................................................................... 10
Addition of TPC 16........................................................................ 11
Edits to Table III ............................................................................ 13
Edits to Driver Amplifier Choice Section .................................. 15
New Voltage Reference Input Section ......................................... 15
New ST-48 Package Outline ........................................................ 22
4/03—Rev. A to Rev. B.
Changes to PulSAR Selection Table............................................... 1
Changes to Ordering Guide ........................................................... 5
Changes to Figure 5........................................................................ 13
Updated Outline Dimensions....................................................... 22
Rev. C | Page 23 of 24
Data Sheet
NOTES
AD7671
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02567-0- /12(C)
Rev. C | Page 24 of 24
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