AD7687BRMRL7 [ADI]
IC 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10, MO-187BA, MSOP-10, Analog to Digital Converter;
| 型号： | AD7687BRMRL7 |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10, MO-187BA, MSOP-10, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™
Differential ADC in MSOP/QFN
AD7687
APPLICATION DIAGRAM
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS
0.5V TO 5V
2.5 TO 5V
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
S/(N + D): 95.5 dB @ 20 kHz
THD: −118 dB @ 20 kHz
True differential analog input range
±±REF
VREF
0
VIO
1.8V TO VDD
REF VDD
SDI
SCK
SDO
CNV
IN+
AD7687
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
IN–
VREF
0
GND
0 ± to ±REF with ±REF up to ±DD on both inputs
No pipeline delay
Figure 2.
Single-supply 2.3 ± to 5.5 ± operation with
1.8 ±/2.5 ±/3 ±/5 ± logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
Table 1. MSOP, QFN1 (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type
100 kSPS
AD7684
AD7683
250 kSPS
AD7687
AD7685
AD7694
500 kSPS
AD7688
AD7686
True Differential
Pseudo
Differential/Unipolar
Unipolar
1.35 mW @ 2.5 ±/100 kSPS, 4 mW @ 5 ±/100 kSPS, and
1.4 µW @ 2.5 ±/100 SPS
AD7680
Standby current: 1 nA
GENERAL DESCRIPTION
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm QFN1 (LFCSP) (SOT-23 size)
Pin-for-pin compatible with AD7685, AD7686, and AD7688
The AD7687 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V to 5.5 V. It
contains a low power, high speed, 16-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. The part also contains a low noise, wide
bandwidth, short aperture delay track-and-hold circuit. On the
CNV rising edge, it samples the voltage difference between IN+
and IN− pins. The voltages on these pins usually swing in
opposite phase between 0 V to REF. The reference voltage, REF,
is applied externally and can be set up to the supply voltage.
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
1.5
POSITIVE INL = +0.32LSB
NEGATIVE INL = –0.41LSB
1.0
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
0.5
0
–0.5
The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN1
(LFCSP) with operation specified from −40°C to +85°C.
–1.0
–1.5
0
16384
32768
CODE
49152
65535
1 QFN package in development. Contact sales for samples and availability.
Figure 1. Integral Nonlinearity vs. Code
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
AD7687
TABLE OF CONTENTS
Specifications..................................................................................... 3
Power Supply............................................................................... 16
Supplying the ADC from the Reference.................................. 17
Digital Interface.......................................................................... 17
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Circuit Information.................................................................... 13
Converter Operation.................................................................. 13
Typical Connection Diagram ................................................... 14
Analog Input ............................................................................... 15
Driver Amplifier Choice............................................................ 16
Single-to-Differential Driver..................................................... 16
Voltage Reference Input............................................................. 16
CS
CS
CS
CS
MODE 3-Wire, No BUSY Indicator .................................. 18
Mode 3-Wire with BUSY Indicator ................................... 19
Mode 4-Wire, No BUSY Indicator..................................... 20
Mode 4-Wire with BUSY Indicator ................................... 21
Chain Mode, No BUSY Indicator ............................................ 22
Chain Mode with BUSY Indicator........................................... 23
Application Hints ........................................................................... 24
Layout .......................................................................................... 24
Evaluating the AD7687’s Performance.................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
RE±ISION HISTORY
4/05—Revision 0: Initial Version
Rev 0 | Page 2 of 28
AD7687
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
IN+ − IN−
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
0
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
VREF/2
65
1
See the Analog Input section
ACCURACY
No Missing Codes
16
−1
−1.5
Bits
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
0.4
0.4
0.35
2
0.3
0.1
0.7
0.3
+1
+1.5
LSB1
LSB
LSB
LSB
ppm/°C
mV
mV
ppm/°C
LSB
REF = VDD = 5 V
6
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
1.6
3.5
Offset Temperature Drift
Power Supply Sensitivity
0.05
VDD = 5 V ± 5%
THROUGHPUT
Conversion Rate
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
250
200
1.8
kSPS
kSPS
µs
Transient Response
AC ACCURACY
Dynamic Range
Signal-to-Noise
VREF = 5 V
95.8
94
92
96.5
95.5
92.5
−118
−118
95.5
36.5
92.5
115
dB3
dB
dB
dB
dB
dB
dB
dB
dB
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
fIN = 20 kHz
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
fIN = 20 kHz, VREF = 2.5 V
94
92
Intermodulation Distortion4
1 LSB means least significant bit. With the 5 V input range, one LSB is 152.6 µV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale.
Rev 0 | Page 3 of 28
AD7687
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
µA
250 kSPS, REF = 5 V
VDD = 5 V
50
2
2.5
MHz
ns
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
µA
µA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 16-bits twos complement
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = +500 µA
ISOURCE = −500 µA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current1, 2
Power Dissipation
Specified performance
Specified performance
2.3
2.3
1.8
5.5
V
V
V
nA
µW
mW
mW
mW
mW
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5 V, 25°C
1
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
1.4
1.35
2.7
4
5.5
12.5
TEMPERATURE RANGE3
Specified Performance
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
Rev 0 | Page 4 of 28
AD7687
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Symbol
tCONV
tACQ
Min
0.5
1.8
4
Typ
Max
Unit
µs
µs
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
2.2
tCYC
µs
CNV Pulse Width (CS Mode)
tCNVH
tSCK
10
15
ns
SCK Period (CS Mode)
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
17
18
19
20
7
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
7
5
14
15
16
17
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
tEN
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
VIO Above 4.5 V
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
3
4
15
26
ns
ns
VIO Above 2.3 V
Rev 0 | Page 5 of 28
AD7687
−40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 5.
Parameter
Symbol
tCONV
tACQ
Min
0.7
1.8
5
Typ
Max
Unit
µs
µs
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
3.2
tCYC
µs
CNV Pulse Width ( CS Mode )
tCNVH
tSCK
10
25
ns
SCK Period ( CS Mode )
ns
SCK Period ( Chain Mode )
tSCK
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
29
35
40
12
12
5
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
24
30
35
ns
ns
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 2.7 V
tEN
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
30
0
5
8
5
4
36
Rev 0 | Page 6 of 28
AD7687
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Analog Inputs
IN+1, IN−1
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature Range
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W (MSOP-10)
44°C/W (MSOP-10)
JEDEC J-STD-20
1 See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µA
I
OL
1.4V
TO SDO
C
L
50pF
500µA
I
OH
Figure 3. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
Figure 4. Voltage Levels for Timing
Rev 0 | Page 7 of 28
AD7687
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
REF 1
VDD 2
IN+ 3
10 VIO
9
8
7
6
SDI
AD7687
TOP VIEW
(Not to Scale)
9
8
7
6
SDI
SCK
SDO
CNV
AD7687
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
IN–
IN– 4
GND
GND 5
Figure 5. 10-Lead MSOP Pin Configuration
Figure 6. 10-Lead QFN1 (LFCSP) Pin Configuration
1 QFN package in development. Contact sales for samples and availability.
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
AI
AI
P
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
CS CS
selects the interface mode, chain or . In mode, it enables the SDO pin when low. In chain mode, the
data should be read when CNV is high.
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.
Rev 0 | Page 8 of 28
AD7687
TERMINOLOGY
Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
It refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 26).
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
ENOB = (S/[N + D]dB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
Differential Nonlinearity Error (DNL)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Dynamic Range
Zero Error
It is the ratio of the rms value of the full scale to the total rms
noise measured with the inputs shorted together. The value for
dynamic range is expressed in dB.
It is the difference between the ideal midscale voltage, that is, 0
V, from the actual voltage producing the midscale output code,
that is, 0 LSB.
Signal-to-Noise Ratio (SNR)
Gain Error
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999924 V
for the 5 V range). The last transition (from 011…10 to
011…11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the 5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
Aperture Delay
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
It is the time required for the ADC to accurately acquire its
input after a full-scale step function was applied.
Rev 0 | Page 9 of 28
AD7687
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.5
1.0
POSITIVE INL = +0.32LSB
NEGATIVE INL = –0.41LSB
POSITIVE DNL = +0.27LSB
NEGATIVE DNL = –0.24LSB
1.0
0.5
0
0.5
0
–0.5
–0.5
–1.0
–1.5
–1.0
–1.5
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
300000
250000
200000
VDD = REF = 5V
VDD = REF = 2.5V
258680
200403
250000
200000
150000
100000
50000
0
150000
100000
50000
0
30721
47
29918
49
0
0
1049
43
1391
45
0
0
0
0
60
46
18
0
0
41
42
44
46
47
44
45
48
4A
4B
4C
CODE IN HEX
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
Figure 11. Histogram of a DC Input at the Code Center
0
–20
0
–20
8192 POINT FFT
VDD = REF = 5V
32768 POINT FFT
VDD = REF = 2.5V
F
F
= 250KSPS
= 2.1kHz
F
F
= 250KSPS
= 2kHz
S
S
IN
IN
–40
–40
SNR = 95.5dB
SNR = 92.8dB
THD = –118.3dB
2nd HARM = –130dB
3rd HARM = –122.7dB
THD = –115.9dB
2nd HARM = –124dB
3rd HARM = –119dB
–60
–60
–80
–80
–100
–100
–120
–140
–160
–180
–120
–140
–160
–180
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 9. FFT Plot
Figure 12. FFT Plot
Rev 0 | Page 10 of 28
AD7687
100
95
17.0
16.0
–100
–105
–110
–115
–120
–125
–130
SNR
S/[N + D]
ENOB
15.0
14.0
13.0
90
THD
SFDR
85
70
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
REFERENCE VOLTAGE (V)
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
200
125
REFERENCE VOLTAGE (V)
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
Figure 16. THD, SFDR vs. Reference Voltage
100
95
90
85
80
75
70
–60
–70
VREF = 5V, –10dB
VREF = 2.5V, –10dB
–80
VREF = 5V, –1dB
VREF = 2.5V, –1dB
VREF = 2.5V, –1dB
–90
VREF = 5V, –1dB
–100
–110
–120
VREF = 2.5V, –10dB
VREF = 5V, –10dB
0
50
100
150
200
0
50
100
FREQUENCY (kHz)
150
FREQUENCY (kHz)
Figure 14. S/(N + D) vs. Frequency
Figure 17. THD vs. Frequency
100
95
90
85
80
–90
–100
–110
–120
–130
VREF = 5V
VREF = 2.5V
VREF = 5V
VREF = 2.5V
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. SNR vs. Temperature
Figure 18. THD vs. Temperature
Rev 0 | Page 11 of 28
AD7687
100
99
1000
750
500
250
0
fS = 100kSPS
VDD = 5V
98
97
VDD = 2.5V
VREF = 5V
96
95
94
93
92
91
VREF = 2.5V
VIO
90
–10
–55
–35
–15
5
25
45
65
85
105
125
–8
–6
–4
–2
0
TEMPERATURE (°C)
INPUT LEVEL (dB)
Figure 19. SNR vs. Input Level
Figure 22. Operating Currents vs. Temperature
1000
6
4
fS = 100kSPS
VDD
750
500
250
0
GAIN ERROR
2
0
–2
–4
–6
OFFSET ERROR
VIO
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
–55
–35
–15
5
25
45
65
85
105
125
SUPPLY (V)
TEMPERATURE (°C)
Figure 20. Operating Currents vs. Supply
Figure 23. Offset and Gain Error vs. Temperature
1000
750
500
250
0
25
20
15
10
5
VDD = 2.5V, 85°C
VDD = 2.5V, 25°C
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD = 3.3V, 85°C
VDD = 3.3V, 25°C
VDD + VIO
0
–55
–35
–15
5
25
45
65
85
105
125
0
20
40
60
80
100
120
TEMPERATURE (°C)
SDO CAPACITIVE LOAD (pF)
Figure 21. Power-Down Currents vs. Temperature
Figure 24. tDSDO Delay vs. Capacitance Load and Supply
Rev 0 | Page 12 of 28
AD7687
IN+
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C
MSB
CNV
IN–
Figure 25. ADC Simplified Schematic
CIRCUIT INFORMATION
CON±ERTER OPERATION
The AD7687 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7687 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
The AD7687 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it typically consumes
1.35 µW, which is ideal for battery-powered applications.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536).
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced
The AD7687 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7687 is specified from 2.3 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN1 (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin-compatible with the AD7685, AD7686, and
AD7688.
1. QFN package in development. Contact sales for samples and availability.
condition. After the completion of this process, the part returns
to the acquisition phase and the control logic generates the
ADC output code and a BUSY signal indicator.
Because the AD7687 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev 0 | Page 13 of 28
AD7687
Transfer Functions
TYPICAL CONNECTION DIAGRAM
The ideal transfer characteristic for the AD7687 is shown in
Figure 26 and Table 8.
Figure 27 shows an example of the recommended connection
diagram for the AD7687 when multiple supplies are available.
011...111
011...110
011...101
100...010
100...001
100...000
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR + 0.5 LSB
ANALOG INPUT
Figure 26. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Analog Input
Description
±REF = 5 ±
Digital Output Code Hexa
FSR – 1 LSB
+4.999847 V
7FFF1
0001
0000
FFFF
8001
80002
Midscale + 1 LSB +152.6 µV
Midscale 0 V
Midscale – 1 LSB −152.6 µV
–FSR + 1 LSB
–FSR
−4.999847 V
−5 V
1. This is also the code for an overranged analog input (VIN+ − VIN− above VREF
VGND).
−
2. This is also the code for an underranged analog input (VIN+ − VIN− below − VREF
+ VGND).
1
≥7V
REF
5V
2
10µF
100nF
≥7V
1.8V TO VDD
100nF
33Ω
REF
VDD
VIO
SDI
0 TO VREF
IN+
IN–
3
2.7nF
4
SCK
≤–2V
≥7V
5
3- OR 4-WIRE INTERFACE
AD7687
SDO
CNV
GND
33Ω
VREF TO 0
3
2.7nF
4
≤–2V
1
2
3
4
5
SEE REFERENCE SECTION FOR REFERENCE SELECTION.
C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
SEE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 27. Typical Application Diagram with Multiple Supplies
Rev 0 | Page 14 of 28
AD7687
ANALOG INPUT
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 3 kΩ and is a lumped component made up of
some serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
Figure 28 shows an equivalent circuit of the input structure of
the AD7687.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forward-
bias and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit current limitation can be used to
protect the part.
When the source impedance of the driving circuit is low, the
AD7687 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 30.
VDD
D1
D2
C
IN
R
IN
IN+
OR IN–
C
PIN
GND
–60
–70
–80
–90
Figure 28. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 29, which represents the typical CMRR over
frequency.
90
R
R
= 250Ω
= 100Ω
S
S
VDD = 5V
–100
80
VDD = 2.5V
–110
–120
R
R
= 50Ω
= 33Ω
S
S
70
60
0
25
50
75
100
FREQUENCY (kHz)
Figure 30. THD vs. Analog Input Frequency and Source Resistance
50
40
1
10
100
FREQUENCY (kHz)
1000
Figure 29. Analog Input CMRR vs. Frequency
Rev 0 | Page 15 of 28
AD7687
SINGLE-TO-DIFFERENTIAL DRI±ER
DRI±ER AMPLIFIER CHOICE
For applications using a single-ended analog signal, either
bipolar or unipolar, a single-ended-to-differential driver
allows for a differential input into the part (see Figure 31 for
the schematic). When provided a single-ended input signal,
this configuration produces a differential VREF with midscale
at VREF/2.
Although the AD7687 is easy to drive, the driver amplifier
needs to meet the following requirements:
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7687. Note that
the AD7687 has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system perform-
ance. The noise coming from the driver is filtered by the
AD7687 analog input circuit 1-pole, low-pass filter made
by RIN and CIN or by the external filter, if one is used.
Because the typical noise of the AD7687 is 53 µV rms,
the SNR degradation due to the amplifier is
590Ω
ANALOG INPUT
(±10V, ±5V, ..)
U1
VREF
VREF
10µF
100nF
590Ω
590Ω
REF
IN+
AD7687
IN–
U2
10kΩ
10kΩ
⎛
⎜
⎞
⎟
VREF
53
100nF
SNRLOSS = 20log⎜
⎟
π
2
2
2
⎜
⎜
⎟
⎟
53 + f−3dB
(
2NeN
)
⎝
⎠
Figure 31. Single-Ended-to-Differential Driver Circuit
where:
–3dB is the input bandwidth in MHz of the AD7687
(2 MHz) or the cutoff frequency of the input filter, if
one is used.
±OLTAGE REFERENCE INPUT
The AD7687 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
f
N is the noise gain of the amplifier (for example, +1 in
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7687. Figure 17
shows the THD vs. frequency that the driver should
exceed.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
For multichannel multiplexed applications, the driver
amplifier and the AD7687 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
Table 9. Recommended Driver Amplifiers.
POWER SUPPLY
Amplifier
Typical Application
The AD7687 is specified over a wide operating range of 2.3 V to
5.5 V. Unlike other low voltage converters, it has a low enough
noise to design a 16-bit resolution system with low supply and
respectable performance. It uses two power supply pins: a core
supply VDD and a digital input/output interface supply VIO.
VIO allows direct interface with any logic between 1.8 V and
VDD. To reduce the supplies needed, the VIO and VDD can be
tied together. The AD7687 is independent of power supply
sequencing between VIO and VDD. Additionally, it is very
AD8021
AD8022
OP184
AD8605, AD8615
AD8519
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power and low frequency
High frequency and low power
AD8031
Rev 0 | Page 16 of 28
AD7687
insensitive to power supply variations over a wide frequency
range, as shown in Figure 32, which represents PSRR over
frequency.
5V
5V
10Ω
5V 10kΩ
1µF
100
10µF
1µF
AD8031
95
1
VDD = 5V
90
REF
VDD
VIO
85
80
75
AD7687
1
OPTIONAL REFERENCE BUFFER AND FILTER.
VDD = 2.5V
70
Figure 34. Example of Application Circuit
65
60
DIGITAL INTERFACE
Though the AD7687 has a reduced number of pins, it offers
flexibility in its serial interface modes.
55
50
1
10
100
1000
10000
CS
The AD7687, when in
mode, is compatible with SPI, QSPI,
FREQUENCY (kHz)
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A 3-
wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
Figure 32. PSRR vs. Frequency
The AD7687 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 33. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
The AD7687, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
1000
VDD = 5V
VDD = 2.5V
The mode in which the part operates depends on the SDI level
10
CS
when the CNV rising edge occurs. The
mode is selected if
VIO
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
0.1
In either mode, the AD7687 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
0.001
10
100
1000
10000
100000
1000000
SAMPLING RATE (SPS)
Figure 33. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
The BUSY indicator feature is enabled as:
For simplified applications, the AD7687, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by either:
CS
• In the
mode, if CNV or SDI is low when the ADC
conversion ends (Figure 38 and Figure 42).
• In the chain mode, if SCK is high during the CNV rising edge
(Figure 46).
•
•
The system power supply directly
A reference voltage with enough current output capability,
such as the ADR43x
•
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 34
Rev 0 | Page 17 of 28
AD7687
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35 and the corresponding timing is given in
Figure 36.
CONVERT
With SDI tied to VIO, a rising edge on CNV initiates a
DIGITAL HOST
CNV
CS
conversion, selects the
mode, and forces SDO to high
VIO
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7687
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
DATA IN
SDI
SDO
AD7687
SCK
CLK
CS
Figure 35. Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
15
16
D0
tHSDO
tSCKH
tDSDO
tEN
tDIS
D15
D14
D13
D1
SDO
CS
Figure 36. Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev 0 | Page 18 of 28
AD7687
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 37 and the
corresponding timing is given in Figure 38.
If multiple AD7687s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7687 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47k
Ω
DATA IN
IRQ
SDI
SDO
AD7687
SCK
CLK
CS
Figure 37. Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
ACQUISITION
tCONV
ACQUISITION
CONVERSION
tSCK
tSCKL
SCK
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
SDO
D15
D14
D1
D0
CS
Figure 38. Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev 0 | Page 19 of 28
AD7687
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7687 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7687s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7687s is shown in
Figure 39 and the corresponding timing is given in Figure 40.
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7687 can be read.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7687
AD7687
SCK
SCK
DATA IN
CLK
CS
Figure 39. Mode 4-Wire, No BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tDSDO
tDIS
tEN
SDO
D15
D14
D13
D1
D0
D15
D14
D1
D0
CS
Figure 40. Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev 0 | Page 20 of 28
AD7687
the digital host. The AD7687 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 41 and the
corresponding timing is given in Figure 42.
CS1
CONVERT
With SDI high, a rising edge on CNV initiates a conversion,
VIO
DIGITAL HOST
CNV
CS
selects the
mode, and forces SDO to high impedance. In this
47kΩ
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
DATA IN
IRQ
SDI
SDO
AD7687
SCK
CLK
CS
Figure 41. Mode 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
tEN
D15
D14
D1
D0
CS
Figure 42. Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev 0 | Page 21 of 28
AD7687
onto SDO and the AD7687 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently more AD7687s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
For instance, with a 3 ns digital host set-up time and 3 V
interface, up to eight AD7687s running at a conversion rate of
220 kSPS can be daisy-chained on a 3-wire port.
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy chain multiple AD7687s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7687s is shown in
Figure 43 and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
CONVERT
CNV
CNV
DIGITAL HOST
SDI
SDO
SDI
SDO
AD7687
AD7687
DATA IN
A
B
SCK
SCK
CLK
Figure 43. Chain Mode, No BUSY Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
t
CONV
ACQUISITION
CONVERSION
tSSCKCNV
ACQUISITION
tSCK
tSCKL
SCK
1
A
2
3
14
15
16
17
18
30
31
32
tHSCKCNV
tSSDISCK
tSCKH
tHSDISC
tEN
D 15
D 14
A
D 13
A
D 1
A
D 0
A
SDO = SDI
A
B
tHSDO
tDSDO
D 15
D 14
B
D 13
B
D 1
B
D 0
B
D 15
A
D 14
A
D 1
A
D 0
A
SDO
B
B
Figure 44. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev 0 | Page 22 of 28
AD7687
Figure 45) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7687 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7687s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to eight AD7687s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7687s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7687s is shown
in Figure 45 and the corresponding timing is given in Figure 46.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC ( ADC C in
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
SDI
SDO
SDI
SDO
SDI
SDO
AD7687
AD7687
AD7687
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 45. Chain Mode with BUSY Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
4
15
16
17
18
19
31
32
33
34
35
47
48
49
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISC
tEN
SDO = SDI
A
D 15 D 14 D 13
D 1 D 0
A A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D 15 D 14 D 13
D 1 D 0 D 15 D 14
D 1 D 0
A A
C
C
B
B
B
B
B
A
A
tDSDOSDI
SDO
D 15 D 14 D 13
D 1 D 0 D 15 D 14
D 1 D 0 D 15 D 14
D 1 D 0
C
C
C
C
C
B
B
B
B
A
A
A
A
Figure 46. Chain Mode with BUSY Indicator Serial Interface Timing
Rev 0 | Page 23 of 28
AD7687
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7687 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7687, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7687 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7687s.
Figure 47. Example of Layout of the AD7687 (Top Layer)
The AD7687 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7687
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7687 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 47 and Figure 48.
E±ALUATING THE AD7687’S PERFORMANCE
Figure 48. Example of Layout of the AD7687 (Bottom Layer)
Other recommended layouts for the AD7687 are outlined
in the documentation of the evaluation board for the AD7687
(EVAL-AD7687). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Rev 0 | Page 24 of 28
AD7687
OUTLINE DIMENSIONS
3.00 BSC
6
10
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 49.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
ELECTRICAL PERFORMANCES
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN1 (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
1 QFN package in development. Contact sales for samples and availability.
Rev 0 | Page 25 of 28
AD7687
ORDERING GUIDE
Integral
Nonlinearity
Transport Media,
Quantity
Package
Description
Package
Option
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
Branding
C03
C03
AD7687BRM
1.5 LSB max
1.5 LSB max
Tube, 50
Reel, 1,000
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
Controller Board
RM-10
RM-10
AD7687BRMRL7
EVAL-AD7687CB1
EVAL-CONTROL BRD22
EVAL-CONTROL BRD32
1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
2 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev 0 | Page 26 of 28
AD7687
NOTES
Rev 0 | Page 27 of 28
AD7687
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02972–0–4/05(0)
Rev 0 | Page 28 of 28
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