AD7703SQ/883B [ADI]
IC 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20, CERDIP-20, Analog to Digital Converter;
| 型号： | AD7703SQ/883B |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP20, CERDIP-20, Analog to Digital Converter CD 转换器 |
| 文件： | 总16页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
20-Bit A/D Converter
AD7703
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Monolithic 16-Bit ADC
0.0015% Linearity Error
AV
DV
SS
SC1
4
SC2
17
SS
7
6
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or ؎2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
AD7703
DV
DD
15
14
CALIBRATION
MICROCONTROLLER
CALIBRATION
SRAM
CAL
13
AV
DD
Ultralow Power
20-BIT CHARGE BALANCE A/D
CONVERTER
A
9
IN
12 BP/UP
11 SLEEP
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
6-POLE GAUSSIAN
ANALOG
V
10
REF
AGND
DGND
LOW-PASS
DIGITAL FILTER
MODULATOR
8
5
SDATA
SCLK
20
19
CLOCK
SERIAL INTERFACE
GENERATOR
LOGIC
3
2
1
16
18
MODE
CLKIN CLKOUT
CS
DRDY
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7703 is a 20-bit ADC that uses a S-D conversion tech-
nique. The analog input is continuously sampled by an analog
modulator whose mean output duty cycle is proportional to the
input signal. The modulator output is processed by an on-chip
digital filter with a six-pole Gaussian response, which updates the
output data register with 16-bit binary words at word rates up to
4 kHz. The sampling rate, filter corner frequency, and output
word rate are set by a master clock input that may be supplied
externally, or by a crystal controlled on-chip clock oscillator.
1. The AD7703 offers 20-bit resolution coupled with outstanding
0.0003% accuracy.
2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.
The inherent linearity of the ADC is excellent and endpoint accu-
racy is ensured by self-calibration of zero and full scale, which
may be initiated at any time. The self-calibration scheme can
also be extended to null system offset and gain errors in the input
channel.
4. Flexible synchronous/asynchronous interface allows the
AD7703 to interface directly to the serial ports of industry-
standard microcontrollers and DSP processors.
5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction ensures low power dissipation, and a power-
down mode reduces the idle power consumption to only 10 µW.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(TA = 25؇C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN = 4.096 MHz;
AD7703–SPECIFICATIONS
BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 k⍀1 with 1 nF to AGND at AIN; unless otherwise noted.)
Parameter
A/S Version2
B Version2
C Version2
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
20
20
20
Bits
Integral Nonlinearity, TMIN to TMAX
25°C
TMIN to TMAX
0.0015
0.003
0.003
0.5
4
16
1ꢁ/ 37
4
0.0007
0.0015
0.0015
0.5
4
16
1ꢁ
4
16
26
67
4
16
13
34
ꢀ
32
0.0003
0.000ꢀ
0.0012
0.5
4
16
1ꢁ
4
16
26
67
4
16
13
34
ꢀ
32
% FSR typ
% FSR max
% FSR max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB typ
LSB max
LSB typ
LSB rms typ
Differential Nonlinearity, TMIN to TMAX
Guaranteed No Missing Codes
Positive Full-Scale Error3
Full-Scale Drift4
Unipolar Offset Error3
16
26
Unipolar Offset Drift4
Bipolar Zero Error3
Temp Range: 0°C to +70°C
Specified Temp Range
67 +4ꢀ/–400
4
16
13
34 +24/–200
ꢀ
32
10/ 20
1.6
Bipolar Zero Drift4
Temp Range: 0°C to +70°C
Specified Temp Range
Bipolar Negative Full-Scale Errors3
Bipolar Negative Full-Scale Drift4
Noise (Referred to Output)
10
1.6
10
1.6
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Output Update Rate, fOUT
Filter Corner Frequency, f–3 dB
Settling Time to 0.0007% FS
fCLKIN/256
fCLKIN/256
fCLKIN/256
Hz
Hz
Hz
sec
fCLKIN/1024
fCLKIN/40ꢁ,600
507ꢁ04/fCLKIN
fCLKIN/1024
fCLKIN/40ꢁ,600
507ꢁ04/fCLKIN
fCLKIN/1024
fCLKIN/40ꢁ,600
507ꢁ04/fCLKIN
For Full-Scale Input Step
SYSTEM CALIBRATION
Positive Full-Scale Calibration Range
Positive Full-Scale Overrange
Negative Full-Scale Overrange
Maximum Offset Calibration Ranges5, 6
Unipolar Input Range
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
V max
V max
V max
System calibration applies to
unipolar and bipolar ranges.
After calibration, if AIN > VREF
the device will output all 1s.
If AIN < 0 (unipolar) or –VREF
(bipolar), the device will
output all 0s.
,
–(VREF + 0.1)
–(VREF + 0.1)
–(VREF + 0.1)
V max
Bipolar Input Range
–0.4 VREF to +0.4 VREF –0.4 VREF to +0.4 VREF –0.4 VREF to +0.4 VREF V max
0.ꢀ VREF
2 VREF + 0.2
Input Span7
0.ꢀ VREF
2 VREF + 0.2
0.ꢀ VREF
2 VREF + 0.2
V min
V max
ANALOG INPUT
Unipolar Input Range
Bipolar Input Range
Input Capacitance
Input Bias Current1
0 to 2.5
2.5
20
0 to 2.5
2.5
20
0 to 2.5
2.5
20
V
V
pF typ
nA typ
1
1
1
LOGIC INPUTS
All Inputs Except CLKIN
VINL, Input Low Voltage
VINH, Input High Voltage
CLKIN
0.ꢀ
2.0
0.ꢀ
2.0
0.ꢀ
2.0
V max
V min
VINL, Input Low Voltage
VINH, Input High Voltage
IIN, Input Current
0.ꢀ
3.5
10
0.ꢀ
3.5
10
0.ꢀ
3.5
10
V max
V min
µA max
LOGIC OUTPUTS
VOL, Output Low Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
0.4
DVDD – 1
10
ꢁ
0.4
DVDD – 1
10
ꢁ
0.4
DVDD – 1
10
ꢁ
V max
V min
µA max
pF typ
ISINK = 1.6 mA
ISOURCE = 100 µA
POWER REQUIREMENTS
Power Supply Voltages
Analog Positive Supply (AVDD
Digital Positive Supply (DVDD
Analog Negative Supply (AVSS
Digital Negative Supply (DVSS
)
)
)
4.5/5.5
4.5/5.5
4.5/5.5
V min/V max For Specified Performance
V min/V max
V min/V max
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
)
V min/V max
Calibration Memory Retention
Power Supply Voltage
2.0
2.0
2.0
V min
–2–
REV. E
AD7703
Parameter
A/S Version2
B Version2
C Version2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
DC Power Supply Currents8
Analog Positive Supply (AIDD
Digital Positive Supply (DIDD
Analog Negative Supply (AISS
Digital Negative Supply (DISS
Power Supply Rejection9
Positive Supplies
)
)
)
2.7
2
2.7
0.1
2.7
2
2.7
0.1
2.7
2
2.7
0.1
mA max
mA max
mA max
mA max
Typically 2 mA
Typically 1 mA
Typically 2 mA
Typically 0.03 mA
)
70
75
70
75
70
75
dB typ
dB typ
Negative Supplies
Power Dissipation
Normal Operation
37
37
37
mW max
SLEEP = Logic 1,
Typically 25 mW
SLEEP = Logic 0,
Typically 10 µW
Standby Operations10
A, B, C
S
20
40
20
40
20
40
µW max
µW max
NOTES
1The AIN pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the AIN pin to AGND is necessary.
Source resistance should be 750 ꢀ or less.
2Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
4Total drift over the specified temperature range after calibration at power-up at 25°C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
5In Unipolar mode, the offset can have a negative value (–VREF) such that the Unipolar mode can mimic Bipolar mode operation.
6The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale
points. When using less than the maximum input span, the span range may be placed anywhere within the range of (VREF + 0.1).
8All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10 CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . AVSS – 0.3 V to AVDD + 0.3 V
ORDERING GUIDE
Linearity
Temperature
Range
Error
(% FSR)
Package
Options*
Input Current to Any Pin Except Supplies2 . . . . . . . .
Operating Temperature Range
10 mA
Model
AD7703AN
AD7703BN
AD7703CN
AD7703AR
AD7703BR
AD7703CR
AD7703AQ
AD7703BQ
AD7703CQ
AD7703SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0.003
N-20
N-20
N-20
R-20
R-20
R-20
Q-20
Q-20
Q-20
Q-20
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (DIP Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Power Dissipation (SOIC Package) to 75°C . . . . . . . 250 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C
0.0015
0.0012
0.003
0.0015
0.0012
0.003
0.0015
0.0012
0.003
*N = Plastic DIP; R = SOIC; Q = CERDIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
AD7703
TIMING CHARACTERISTICS1, 2
(AVDD = DVDD = +5 V ؎ 10%; AVSS = DVSS = –5 V ؎ 10%; AGND = DGND = O V;
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)
Limit at TMIN, TMAX Limit at TMIN, TMAX
Parameter
(A, B Versions)
(S, T Versions)
Unit
Conditions/Comments
3, 4
fCLKIN
200
200
kHz min
Master Clock Frequency: Internal Gate Oscillator
5
5
MHz max Typically 4.096 MHz
200
5
50
50
0
200
5
50
50
0
kHz min
MHz max
ns max
ns max
ns min
Master Clock Frequency: Externally Supplied
tr5
tf5
t1
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time
t26
50
1000
50
1000
ns min
ns min
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
t3
SSC MODE
t4
t5
t6
7
3/fCLKIN
100
250
300
790
3/fCLKIN
100
250
300
790
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
7
t88
t9
t10
l/fCLKIN + 200
4/fCLKIN + 200
l/fCLKIN + 200
4/fCLKIN + 200
8, 9
SEC MODE
fSCLK
t11
5
35
160
160
150
250
200
5
35
160
160
150
250
200
MHz max Serial Clock Input Frequency
ns min
ns min
ns max
ns max
ns max
ns max
SCLK Input High Pulsewidth
SCLK Low Pulsewidth
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay
t12
7, 10
t13
11
t14
8
t15
8
t16
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 to 6.
3CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4The AD7703 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5Specified using 10% and 90% points on waveform of interest.
6In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
CAL
I
OL
t2
SC1, SC2VALID
t1
1.6mA
SC1, SC2
TO
OUTPUT
PIN
+
2.1V
C
L
Figure 2. Calibration Control Timing
100pF
I
OH
200A
CLKIN
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
t3
SLEEP
Figure 3. Sleep Mode Timing
–4–
REV. E
AD7703
CS
CS
t15
t10
HI-Z
HI-Z
DATA
VALID
DATA
VALID
SDATA
SDATA
Figure 4. SSC Mode Data Hold Time
Figure 5b. SEC Mode Data Hold Time
CLKIN
DRDY
CS
CS
t7
t8
HI-Z
HI-Z
HI-Z
t12
SCLK
t11
t9
t4
SCLK
t8
t13
t5
t16
t14
HI-Z
HI-Z
HI-Z
SDATA
DB19
DB19
DB18
DB18
DB1
DB0
SDATA
DB1
DB0
Figure 5a. SEC Mode Timing Diagram
Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS
Linearity Error
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +VREF (for example, noise
peaks or excess voltages due to system gain errors in system
calibration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero-scale (not to be
confused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full-scale, a point
1.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages below
–VREF without overloading the analog modulator or overflowing
the digital filter. Note that the analog input will accept negative
voltage peaks even in the Unipolar mode.
Differential Linearity Error
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSB. A differential linearity specification of 1 LSB or less
guarantees monotonicity.
Offset Calibration Range
In the system calibration modes (SC2 low), the AD7703 calibrates
its offset with respect to the AIN pin. The offset calibration range
specification defines the range of voltages, expressed as a
percentage of VREF, that the AD7703 can accept and still accurately
calibrate offset.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (VREF 3/2 LSB).
It applies to both positive and negative analog input ranges and
is expressed in microvolts.
Full-Scale Calibration Range
This is the range of voltages that the AD7703 can accept in the
system calibration mode and still correctly calibrate full scale.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the
Unipolar mode.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7703 can accept
and still accurately calibrate gain. The input span is expressed
as a percentage of VREF.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating
in the Bipolar mode. It is expressed in microvolts.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
(–VREF + 0.5 LSB) when operating in the Bipolar mode.
REV. E
–5–
AD7703
Table I. Bit Weight Table (2.5 V Reference Voltage)
PIN CONFIGURATION
DIP, CERDIP, SOIC
Unipolar Mode
ppm
FS
Bipolar Mode
ppm
MODE
CLKOUT
CLKIN
SC1
20
19
1
2
SDATA
SCLK
V
LSB % FS
LSB % FS
FS
3
18 DRDY
0.5ꢁ6 0.25
1.1ꢁ2 0.5
2.3ꢀ4 1.00
4.76ꢀ 2.00
ꢁ.537 4.00
0.000023ꢀ 0.24 0.13
0.0000477 0.4ꢀ 0.26
0.0000ꢁ54 0.ꢁ5 0.5
0.0001ꢁ07 1.ꢁ1 1.00
0.0003ꢀ14 3.ꢀ1 2.00
0.000011ꢁ 0.12
0.000023ꢀ 0.24
0.0000477 0.4ꢀ
0.0000ꢁ54 0.ꢁ5
0.0001ꢁ07 1.ꢁ1
17 SC2
4
AD7703
TOP VIEW
5
16
15
14
13
12
11
CS
DGND
(Not to Scale)
DV
DV
SS
6
DD
AV
AV
SS
7
DD
CAL
AGND
8
A
9
BP/UP
IN
V
10
REF
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1
MODE
Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)
mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB
coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.
SCLK is configured as an output, with a clock frequency for fCLKIN/4 and 25% duty cycle.
2
CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
3
CLKIN
Clock Input for External Clock.
4, 17
SC1, SC2
System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration
performed.
5
DGND
DVSS
AVSS
Digital Ground. Ground reference for all digital signals.
Digital Negative Supply, –5 V Nominal.
Analog Negative Supply, –5 V Nominal.
Analog Ground. Ground reference for all analog signals.
Analog Input.
6
7
ꢀ
AGND
AIN
ꢁ
10
VREF
Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar
mode and the value of both positive and negative full scale in the Bipolar mode.
11
12
13
SLEEP
BP/UP
CAL
Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW
power consumption.
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7703 is configured for a bipolar input range, VREF
.
Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs
a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize
the operation of several AD7703s.
14
15
16
AVDD
DVDD
CS
Analog Positive Supply, 5 V Nominal.
Digital Positive Supply, 5 V Nominal.
Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined
by the state of the MODE pin.
1ꢀ
DRDY
Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans-
mission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded
into the output register, to indicate that valid data is not available, irrespective of whether data transmission
is complete or not.
1ꢁ
20
SCLK
Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of
serial data transmission that has been selected by the MODE pin. When configured as an output in the
Synchronous Self-Clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
SDATA
Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word.
–6–
REV. E
AD7703
GENERAL DESCRIPTION
4. A 1-bit A/D converter (comparator)
5. A 1-bit DAC
The AD7703 is a 20-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical, or biological processes. It contains a charge-balancing
(⌺-⌬) ADC, calibration microcontroller with on-chip static
RAM, clock oscillator, and serial communications port.
6. A digital low-pass filter
S/H AMP
COMPARATOR
ANALOG
LOW-PASS
FILTER
DIGITAL
FILTER
The analog input signal to the AD7703 is continuously sampled
at a rate determined by the frequency of the master clock, CLKIN.
A charge-balancing A/D converter (⌺-⌬ modulator) converts
the sampled signal into a digital pulse train whose duty cycle
contains the digital information. A six-pole Gaussian digital
low-pass filter processes the output of the ⌺-⌬ modulator and
updates the 20-bit output register at a 4 kHz rate. The output
data can be read from the serial port randomly or periodically at
any rate up to 4 kHz.
DIGITAL DATA
DAC
Figure 8. General ⌺-⌬ ADC
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
sampling frequency (oversampling).
+5V
ANALOG
SUPPLY
AV
DV
DD
DD
0.1F
10F
0.1F
Oversampling is fundamental to the operation of ⌺-⌬ ADCs.
SLEEP
MODE
DRDY
CS
Using the quantization noise formula for an ADC
DATA READY
SNR = (6.02 ¥ number of bits + 1.76) dB
2.5V
VOLTAGE
REFERENCE
V
REF
READ
(TRANSMIT)
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
AD7703
SERIAL CLOCK
SERIAL DATA
SCLK
The AD7703 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 kHz to 8 kHz. Since the specified
analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the
noise energy in this bandwidth would be only 1/800 of the total
quantization noise, even if the noise energy were spread evenly
throughout the spectrum. It is reduced still further by analog
filtering in the modulator loop, which shapes the quantization
noise spectrum to move most of the noise energy to frequencies
above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range
is conditioned to the 20-bit level in this fashion.
RANGE
SELECT
BP/UP
SDATA
CAL
CALIBRATE
CLKIN
A
ANALOG
INPUT
CLKOUT
IN
SC1
SC2
AGND
ANALOG
GROUND
DGND
0.1F
0.1F
AV
SS
DV
SS
–5V
ANALOG
SUPPLY
10F
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
that minimizes the difference signal. The digital data that repre-
sents the analog input voltage is in the duty cycle of the pulse train
appearing at the output of the comparator. It can be retrieved as
a parallel binary data-word using a digital filter.
Figure 7. Typical System Connection Diagram
The AD7703 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
⌺-⌬ ADCs are generally described by the order of the analog
low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is
shown in Figure 8. This contains only a first-order, low-pass
filter or integrator. It also illustrates the derivation of the alter-
native name for these devices: charge-balancing ADCs.
Other system components may also be included in the calibra-
tion loop to remove offset and gain errors in the input channel.
For battery operation, the AD7703 also offers a standby mode
that reduces idle power consumption to typically 10 µW.
The AD7703 uses a second-order, ⌺-⌬ modulator and a sophis-
ticated digital filter that provides a rolling average of the sampled
output. After power-up or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
THEORY OF OPERATION
The general block diagram of a ⌺-⌬ ADC is shown in Figure 8.
It contains the following elements:
1. A sample-hold amplifier
2. A differential amplifier or subtracter
3. An analog low-pass filter
REV. E
–7–
AD7703
DIGITAL FILTERING
The AD7703’s digital filter behaves like an analog filter, with a
few minor differences.
The output settling of the AD7703 in response to a step input
change is shown in Figure 10. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
0.0007% is 125 ms with a 4.0ꢁ6 MHz master clock frequency.
First, since digital filtering occurs after the analog-to-digital
conversion, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
100
80
60
40
20
0
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator and
digital filter, even though the average value of the signal is within
limits. To alleviate this problem, the AD7703 has overrange
headroom built into the ⌺-⌬ modulator and digital filter that
allows overrange excursions of 100 mV. If noise signals are larger
than this, consideration should be given to analog input filtering,
or to reducing the gain in the input channel so that a full-scale
input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).
This will provide an overrange capability greater than 100% at
the expense of reducing the dynamic range by one bit (50%).
0
40
80
120
160
TIME – ms
Figure 10. AD7703 Step Response
FILTER CHARACTERISTICS
The cutoff frequency of the digital filter is fCLK/40ꢁ600. At the
maximum clock frequency of 4.0ꢁ6 MHz, the cutoff frequency
of the filter is 10 Hz and the data update rate is 4 kHz.
USING THE AD7703
SYSTEM DESIGN CONSIDERATIONS
The AD7703 operates differently from successive approximation
ADCs or integrating ADCs. Since it samples the signal continu-
ously, like a tracking ADC, there is no need for a start convert
command. The 20-bit output register is updated at a 4 kHz rate,
and the output can be read at any time, either synchronously or
asynchronously.
Figure ꢁ shows the filter frequency response. This is a six-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than ꢁ0 dB.
20
0
CLOCKING
fCLK = 4MHz
The AD7703 requires a master clock input, which may be an exter-
nal TTL/CMOS compatible clock signal applied to the CLKIN
pin (CLKOUT not used). Alternatively, a crystal of the correct
frequency can be connected between CLKIN and CLKOUT,
when the clock circuit will function as a crystal controlled oscillator.
–20
–40
–60
fCLK = 2MHz
–80
Figure 11 shows a simple model of the on-chip gate oscillator
and Table II gives some typical capacitor values to be used with
various resonators.
–100
–120
fCLK = 1MHz
–140
R1
5M⍀
–160
1
100
10
FREQUENCY – Hz
2
Figure 9. Frequency Response of AD7703 Filter
C2*
10pF
X1
g
= 1500MHO
m
Since the AD7703 contains this low-pass filtering, there is a
settling time associated with step function inputs, and data will
be invalid after a step change until the settling time has elapsed.
The AD7703 is, therefore, unsuitable for high speed multiplex-
ing, where channels are switched and converted sequentially at
high rates, as switching between channels can cause a step change
in the input. However, slow multiplexing of the AD7703 is
possible, provided that the settling time is allowed to elapse
before data for the new channel is accessed.
3
C1*
10pF
AD7703
*SEETABLE II
Figure 11. On-Chip Gate Oscillator
–8–
REV. E
AD7703
low capacitance/voltage coefficient. The device also achieves low
input drift through the use of chopper-stabilized techniques in
its input stage. To ensure excellent performance over time and
temperature, the AD7703 uses digital calibration techniques
that minimize offset and gain error to typically 4 LSB.
Table II. Resonator Loading Capacitors
Resonators
C1 (pF)
C2 (pF)
Ceramic
200 kHz
455 kHz
1.0 MHz
2.0 MHz
330
100
50
470
100
50
AUTOCALIBRATION
The AD7703 offers both self-calibration and system-calibration
facilities. For calibration to occur, the on-chip microcontroller
must record the modulator output for two different input condi-
tions. These are the zero-scale and full-scale points. In Unipolar
self-calibration mode, the zero-scale point is VAGND and the
full-scale point is VREF. With these readings, the microcontroller
can calculate the gain slope for the input to output transfer
function of the converter. In Unipolar mode, the slope factor is
determined by dividing the span between zero and full scale by
220. In Bipolar mode, it is determined by dividing the span by
20
20
Crystal
2.000 MHz
3.57ꢁ MHz
4.0ꢁ6 MHz
30
20
None
30
20
None
The input sampling frequency, output data rate, filter character-
istics, and calibration time are all directly related to the master
clock frequency, fCLKIN, by the ratios given in the Specification
table under Dynamic Performance. Therefore, the first step in
system design with the AD7703 is to select a master clock fre-
quency suitable for the bandwidth and output data rate required
by the application.
2
1ꢁ since the inputs applied represent only half the total codes.
In both Unipolar and Bipolar modes, the slope factor is saved
and used to calculate the binary output code when an analog
input is applied to the device. Table IV gives the output code
size after calibration.
ANALOG INPUT RANGES
System calibration allows the AD7703 to compensate for system
gain and offset errors. A typical circuit where this might be used
is shown in Figure 12.
The AD7703 performs conversion relative to an externally
supplied reference voltage that allows easy interfacing to ratio-
metric systems. In addition, either unipolar or bipolar input
voltage ranges may be selected using the BP/UP input. With
BP/UP tied low, the input range is unipolar and the span is
(VREF to VAGND), where VAGND is the voltage at the device AGND
pin. With BP/UP tied high, the input range is bipolar and the
span is 2VREF. In the Bipolar mode, both positive and negative
full scale are directly determined by VREF. This offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
System calibration performs the same slope factor calculations
as self-calibration but uses voltage values presented by the system
to the AIN pin for the zero- and full-scale points. There are two
system calibration modes.
The first mode offers system level calibration for system offset
and system gain. This is a two step operation. The zero-scale
point must be presented to the converter first. It must be applied
to the converter before the calibration step is initiated and remain
stable until the step is complete. The DRDY output from the
device will signal when the step is complete by going low. After
the zero-scale point is calibrated, the full-scale point is applied
and the second calibration step is initiated. Again, the voltage
must remain stable throughout the calibration step.
The digital output coding for the unipolar range is unipolar binary;
for the bipolar range it is offset binary. Bit weights for the Unipolar
and Bipolar modes are shown in Table I.
ACCURACY
The two step calibration mode offers another feature. After the
sequence has been completed, additional offset calibrations can be
performed by themselves to adjust the zero reference point to a
new system zero reference value. This second system calibration
mode uses an input voltage for the zero-scale calibration point
but uses the VREF value for the full-scale point.
S-D ADCs, like VFCs and other integrating ADCs, do not
contain any source of nonmonotonicity and inherently offer
no-missing-codes performance.
The AD7703 achieves excellent linearity by the use of high
quality, on-chip silicon dioxide capacitors, which have a very
SCLK
SYSTEM
REF HI
SDATA
ANALOG
MUX
SIGNAL
CONDITIONING
A
CAL
SC1
SC2
IN
A
MICRO-
COMPUTER
IN
SYSTEM
REF LO
A0
A1
AD7703
Figure 12. Typical Connections for System Calibration
REV. E
–9–
AD7703
Initiating Calibration
When self-calibration is completed, DRDY falls and the output
port is updated with a data-word that represents the analog input
signal. When a system calibration step is completed, DRDY will
fall and the output port will be updated with the appropriate data
value (all 0s for the zero-scale point and all 1s for the full-scale
point). In the system calibration mode, the digital filter must
settle before the output code will represent the value of the
analog input signal. Tables IV and V indicate the output code
size and output coding of the AD7703 in its various modes. In
these tables, SOFF is the measured system offset in volts and
SGAIN is the measured system gain at the full-scale point in volts.
Table III illustrates the calibration modes available in the AD7703.
Not shown in the table is the function of the BP/UP pin, which
determines whether the converter has been calibrated to mea-
sure bipolar or unipolar signals. A calibration step is initiated by
bringing the CAL pin high for at least four CLKIN cycles and
then bringing it low again. The states of SC1 and SC2 along
with the BP/UP pin will determine the type of calibration to be
performed. All three signals should be stable before the CAL
pin is taken positive. The SC1 and SC2 inputs are latched when
CAL goes high. The BP/UP input is not latched and, therefore,
must remain in a fixed state throughout the calibration and
measurement cycles. Any time the state of the BP/UP is changed,
a new calibration cycle must be performed to enable the AD7703
to function properly in the new mode.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits
on the amount of offset and span that can be accommodated.
The range of input span in both the Unipolar and Bipolar
modes has a minimum value of 0.ꢀ VREF and a maximum
value of 2(VREF + 0.1 V).
When a calibration step is initiated, the DRDY signal will go high
and remain high until the step is finished. Table III shows the
number of clock cycles each calibration requires. Once a calibra-
tion step is initiated, it must finish before a new calibration step
can be executed. In the two step system calibration mode, the
offset calibration step must be initiated before initiating the gain
calibration step.
The amount of offset that can be accommodated depends on
whether the Unipolar or Bipolar mode is being used. In Unipolar
mode, the system calibration modes can handle a maximum
offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V).
Therefore the AD7703 in the Unipolar mode can be calibrated
to mimic bipolar operation.
Table III. Calibration Truth Table*
Zero-Scale Full-Scale
Calibration
Type
Calibration
Time
CAL
SC1
SC2
Calibration Calibration
Sequence
0
1
0
1
0
1
1
0
Self-Calibration
System Offset
System Gain
VAGND
AIN
VREF
One Step
First Step
Second Step
One Step
3,145,655 Clock Cycles
1,052,5ꢁꢁ Clock Cycles
1,06ꢀ,ꢀ13 Clock Cycles
2,117,3ꢀꢁ Clock Cycles
AIN
VREF
System Offset
AIN
*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other
modes, DRDY falls as the device begins to settle.
Table IV. Output Code Size After Calibration
1 LSB
Calibration Mode
Zero Scale
Gain Factor
Unipolar
Bipolar
(VREF –VAGND
)
2(VREF –VAGND )
Self-Calibration
VAGND
VREF
104ꢀ576
104ꢀ576
(SGAIN –SOFF
)
2(SGAIN –SOFF )
System Calibration
SOFF
SGAIN
104ꢀ576
104ꢀ576
–10–
REV. E
AD7703
Table V. Output Coding
I
nput Voltage, Unipolar Mode
Input Voltage, Bipolar Mode
System Calibration
Self-Calibration
Output Codes
Self-Calibration
System Calibration
>(SGAIN –1.5 LSB)
>(VREF – 1.5 LSB)
FFFFF
>(VREF –1.5 LSB)
>(SGAIN – 1.5 LSB)
FFFFF
FFFFE
SGAIN – 1.5 LSB
VREF – 1.5 LSB
VREF – 1.5 LSB
SGAIN – 1.5 LSB
ꢀ0000
(SGAIN – SOFF)/2 – 0.5 LSB
(VREF – VAGND)/2 – 0.5 LSB
VAGND – 0.5 LSB
SOFF – 0.5 LSB
7FFFF
00001
00000
SOFF + 0.5 LSB
VAGND + 0.5 LSB
–VREF + 0.5 LSB
–SGAIN + 2 SOFF + 0.5 LSB
<(–SGAIN +2 SOFF + 0.5 LSB)
<(SOFF + 0.5 LSB)
<(VAGND + 0.5 LSB)
00000
<(–VREF + 0.5 LSB)
accordingly. The value of the voltage on the sample capacitor is
updated at a rate determined by the master clock; therefore, the
amount of offset drift that occurs will be proportional to the
elapsed time between samples. Thus, to minimize offset drift at
higher temperatures, higher CLKIN rates are recommended.
In the Bipolar mode, the system offset calibration range is
restricted to 0.4 VREF. It should be noted that the span restric-
tions limit the amount of offset that can be calibrated. The span
range of the converter in Bipolar mode is equidistant around the
voltage used for the zero-scale point. When the zero-scale point
is calibrated, it must not cause either of the two endpoints of the
bipolar transfer function to exceed the positive or the negative
input overrange points (+VREF + 0.1) V or (–VREF + 0.1) V. If
the span range is set to a minimum (0.ꢀ VREF), the offset voltage
can move +0.4 VREF without causing the endpoints of the trans-
fer function to exceed the overrange points. Alternatively, if the
span range is set to 2VREF, the input offset cannot move more
than +0.1 V or –0.1 V before an endpoint of the transfer func-
tion exceeds the input overrange limit.
Gain drift within the converter depends mainly upon the tem-
perature tracking of the internal capacitors. It is not affected by
leakage currents so it is significantly less than offset drift. The
typical gain drift of the AD7703 is less than 40 LSB over the
specified temperature range.
Measurement errors due to offset drift or gain drift can be
eliminated at any time by recalibrating the converter. Using the
system calibration mode can also minimize offset and gain errors
in the signal conditioning circuitry. Integral and differential
linearity are not significantly affected by temperature changes.
POWER-UP AND CALIBRATION
A calibration cycle must be carried out after power-up to initial-
ize the device to a consistent starting condition and correct
calibration. The CAL pin must be held high for at least four
clock cycles, after which calibration is initiated on the falling
edge of CAL and takes a maximum of 3,145,655 clock cycles
(approximately 76ꢀ ms with a 4.0ꢁ6 MHz clock). See Table III.
160
CLKIN = 4.096MHz
80
0
–80
The type of calibration cycle initiated by CAL is determined by
the SC1 and SC2 inputs, in accordance with Table III.
Drift Considerations
–160
–240
–320
The AD7703 uses chopper stabilization techniques to minimize
input offset drift. Charge injection in the analog switches and
leakage currents at the sampling node are the primary sources of
offset voltage drift in the converter. Figure 13 indicates the typical
offset due to temperature changes after calibration at 25°C. Drift
is relatively flat up to 75°C. Above this temperature, leakage
current becomes the main source of offset drift. Since leakage
current doubles approximately every 10°C, the offset drifts
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE – ؇C
Figure 13. Typical Bipolar Offset vs. Temperature
after Calibration at 25°C
REV. E
–11–
AD7703
INPUT SIGNAL CONDITIONING
An RC filter may be added in front of the AD7703 to reduce
high frequency noise. With an external capacitor added from
Reference voltages from 1 V to 3 V may be used with the AD7703,
with little degradation in performance. Input ranges that cannot
be accommodated by this range of reference voltages may be
achieved by input signal conditioning. This may take the form of
gain to accommodate a smaller signal range, or passive attenua-
tion to reduce a larger input voltage range.
A
IN to AGND, the following equation will specify the maximum
allowable source resistance:
62
RS(MAX )
=
È
CIN
(CIN + CEXT
VE
˘
˙
˙
˙
100 mV ¥
Í
Í
Í
Î
)
fCLKIN ¥ (CIN + CEXT ) ¥ ln
Source Resistance
If passive attenuators are used in front of the AD7703, care must
be taken to ensure that the source impedance is sufficiently low.
The dc input resistance for the AD7703 is over 1 GW. In paral-
lel with this, there is a small dynamic load that varies with the
clock frequency (see Figure 14).
Í
˙
˚
The practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source:
R1
A
IN
AD7703
V = 4 kTRf Volts
n
V
IN
in = 4 kTf / R Amperes
where k is Boltzmann’s constant (1.3ꢀ ¥ 10–23 J/K), and T is
temperature in degrees Kelvin (°C + 273).
R2
C
1G⍀
EXT
C
IN
10pF
V
100mV
OS
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their open-
loop output resistance is normally only tens of ohms and, in any
case, most modern general-purpose op amps have sufficiently fast
closed-loop settling time for this not to be a problem. Offset volt-
age in op amps can be eliminated in a system calibration routine.
AGND
Figure 14. Equivalent Input Circuit and Input Attenuator
Each time the analog input is sampled, a 10 pF capacitor draws a
charge packet of maximum 1 pC (10 pF ¥ 100 mV) from the
analog source with a frequency fCLKIN/256. For a 4.0ꢁ6 MHz
CLKIN, this yields an average current draw of 16 nA. After
each sample, the AD7703 allows 62 clock periods for the input
voltage to settle. The equation that defines settling time is
Antialias Considerations
The digital filter of the AD7703 does not provide any rejection
at integer multiples of the sampling frequency (nfCLKIN/256,
where n = 1, 2, 3 . . . ).
With a 4.0ꢁ6 MHz master clock, there are narrow ( 10 Hz)
bands at 16 kHz, 32 kHz, 4ꢀ kHz, and so on, where noise passes
unattenuated to the output.
VO =VIN [1– e–t/RC
]
where VO, is the final settled value, VIN, is the value of the input
signal, R is the value of the input source resistance, and C is the
10 pF sample capacitor. The value of t is equal to 62/fCLKIN
The following equation can be developed, which gives the maxi-
mum allowable source resistance, RS(MAX), for an error of VE:
However, due to the AD7703’s high oversampling ratio of ꢀ00
(16 kHz to 20 Hz), these bands occupy only a small fraction of
the spectrum, and most broadband noise is filtered.
.
The reduction in broadband noise is given by
62
RS(MAX )
=
eout = ein 2fC / fS = 0.035 ein
fCLKIN ¥ (10 pF) ¥ ln (100 mV /VE )
where ein and eout are rms noise terms referred to the input, fC is
the filter –3 dB corner frequency (fCLKIN/40ꢁ600), and fS is the
sampling frequency (fCLKIN/256).
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. These
can be calibrated in system calibration schemes.
Since the ratio of fS to fCLKIN is fixed, the digital filter reduces
broadband white noise by ꢁ6.5% independent of the master
clock frequency.
If a limit of 600 nV (0.25 LSB at 20 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
125 kW from the above equation, assuming that there is no
external stray capacitance.
–12–
REV. E
AD7703
VOLTAGE REFERENCE CONNECTIONS
provide rejection of broadband noise on the power supplies,
except at integer multiples of the sampling frequency. There-
fore, the two analog supplies should be individually decoupled
to AGND using 100 nF ceramic capacitors to provide power
supply noise rejection at these frequencies. The two digital
supplies should similarly be decoupled to DGND.
The voltage applied to the VREF pin defines the analog input
range. The specified reference voltage is 2.5 V, but the AD7703
will operate with reference voltages from 1 V to 3 V with little
degradation in performance.
The reference input presents exactly the same dynamic load as
the analog input, but in the case of the reference input, source
resistance and long settling time introduce gain errors rather
than offset errors. Fortunately, most precision references have
sufficiently low output impedance and wide enough bandwidth
to settle to the required accuracy within 62 clock cycles.
The positive digital supply (DVDD) must never exceed the positive
analog supply (AVDD) by more than 0.3 V. Power supply sequenc-
ing is, therefore, important. If separate analog and digital supplies
are used, care must be taken to ensure that the analog supply is
powered up first.
The digital filter of the AD7703 removes noise from the reference
input, just as it does with noise at the analog input, and the same
limitations apply regarding lack of noise rejection at integer
multiples of the sampling frequency. Note that the reference
should be chosen to minimize noise below 10 Hz. The AD7703
typically exhibits 1.6 LSB rms noise in its measurements. This
specification assumes a clean reference. Many monolithic band gap
references are available, which can supply the 2.5 V needed for
the AD7703. However, some of these are not specified for noise,
especially in the 0.1 Hz to 10 Hz bandwidth. If the reference noise
in this bandwidth is excessive, it can degrade the performance of
the AD7703. Recommended references are the AD5ꢀ0 and the
LT101ꢁ. Both of these 2.5 V references typically have less than
10 µV p-p noise in the 0.1 Hz to 10 Hz band.
It is also important that power is applied to the AD7703 before
signals at VREF, AIN, or the logic input pins in order to avoid
any possibility of latch-up. If separate supplies are used for
the AD7703 and the system digital circuitry, the AD7703 should
be powered up first.
A typical scheme for powering the AD7703 from a single set of
5 V rails is shown in Figure 7. In this circuit, AVDD and DVDD
are brought along separate tracks from the same 5 V supply.
Thus, there is no possibility of the digital supply coming up
before the analog supply.
SLEEP MODE
The low power standby mode is initiated by taking the SLEEP
input low, which shuts down all analog and digital circuits and
reduces power consumption to 10 µW. When coming out of
SLEEP mode, it is sometimes possible (when using a crystal to
generate CLKIN, for example) to lose the calibration coeffi-
cients. Therefore, it is advisable as a safeguard to always do a
calibration cycle after coming out of SLEEP mode.
POWER SUPPLIES AND GROUNDING
AGND is the ground reference voltage for the AD7703, and is
completely independent of DGND. Any noise riding on the AGND
input with respect to the system analog ground will cause con-
version errors. AGND should, therefore, be used as the system
ground and also as the ground for the analog input and the
reference voltage.
DIGITAL INTERFACE
The AD7703’s serial communications port allows easy inter-
facing to industry-standard microprocessors. Two different
modes of operation are available, optimized for different types
of interface.
The analog and digital power supplies to the AD7703 are inde-
pendent and separately pinned out to minimize coupling between
analog and digital sections of the device. The digital filter will
REV. E
–13–
AD7703
Synchronous Self-Clocking Mode (SSC)
and the data-word currently in the output register will be trans-
mitted, MSB first. After the LSB has been transmitted, DRDY
will go high until the new data-word becomes available. If CS,
having been brought low, is taken high again at any time during
data transmission, SDATA and SCLK will go three-state after
the current bit finishes. If CS is subsequently brought low,
transmission will resume with the next bit during the subse-
quent digital computation period. If transmission has not been
initiated and completed by the time the next data-word is avail-
able, DRDY will go high for four clock cycles then low again as
the new word is loaded into the output register.
The SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. This mode allows interfacing to 74XX2ꢁꢁ
Universal Shift registers without any additional decoding. The
SSC mode can also be used with microprocessors such as the
6ꢀHC11 and 6ꢀHC05, which allow an external device to clock
their serial port.
Figure 15 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. The AD7703
divides each sampling interval into 16 distinct periods. Eight
periods of 64 clock pulses are for analog settling and eight peri-
ods of 64 clock pulses are for digital computation. The status of
CS is polled at the beginning of each digital computation period. If
it is low at any of these times, then SCLK will become active
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 16. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.
1024 CLKIN CYCLES
64 CLKIN
CYCLES
64 CLKIN
CYCLES
INTERNAL
STATUS
ANALOGTIME 0
DIGITALTIME 0
DIGITALTIME 7
72 CLKIN CYCLES
DRDY (O)
CS POLLED
CS (I)
HI-Z
HI-Z
SCLK (O)
MSB
LSB
HI-Z
HI-Z
SDATA (O)
Figure 15. Timing Diagram for SSC Transmission Mode
CLKIN (I)
72
CLKIN
CYCLES
DRDY (O)
CS (I)
HI-Z
HI-Z
HI-Z
HI-Z
SDATA (O)
DB19 (MSB)
DB18
DB17
DB2
DB1
DB0 (LSB)
SCLK (O)
Figure 16. SSC Mode Showing Data Timing Relative to SCLK
–14–
REV. E
AD7703
Synchronous External Clock Mode (SEC)
DIGITAL NOISE AND OUTPUT LOADING
The SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry-standard
microprocessors such as the 6ꢀHC11 and 6ꢀHC05. The SEC
mode also allows customized interfaces, using I/O port pins, to
microprocessors that do not have a direct fit with the AD7703’s
other mode.
As mentioned earlier, the AD7703 divides its internal timing
into two distinct phases, analog sampling and settling and digi-
tal computation. In the SSC mode, data is transmitted only
during the digital computation periods, to minimize the effects
of digital noise on analog performance. In the SEC mode, data
transmission is externally controlled, so this automatic safeguard
does not exist. To compensate, synchronize the AD7703 to the
digital system clock via CLKIN when used in the SEC mode.
As shown in Figure 17, a falling edge on CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK. After
the LSB has been transmitted, DRDY and SDATA go three-state.
If CS is low and the AD7703 is still transmitting data when a
new data-word becomes available, the old data-word continues
to be transmitted and the new data is lost.
Whatever mode of operation is used, resistive and capacitive
loads on digital outputs should be minimized in order to reduce
crosstalk between analog and digital portions of the circuit. For
this reason, connection to low power CMOS logic such as one
of the 4000 series or 74C families is recommended.
If CS is taken high at any time during data transmission, SDATA
will go three-state immediately. If CS returns low, the AD7703
will continue transmission with the same data bit. If transmis-
sion has not been initiated and completed by the time the next
data-word becomes available, and if CS is high, DRDY returns
high for four clock cycles, then falls as the new word is loaded
into the output register.
DRDY (O)
CS (I)
SCLK (O)
HI-Z
HI-Z
SDATA (O)
DB19 (MSB)
DB18
DB17
DB2
DB1
DB0 (LSB)
Figure 17. Timing Diagram for SEC Mode
REV. E
–15–
AD7703
OUTLINE DIMENSIONS
20-Lead Ceramic Dual In-Line Package [CERDIP]
20-Lead Plastic Dual In-Line Package [PDIP]
(Q-20)
(N-20)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
0.005
(0.13)
MIN
0.985 (25.02)
MAX
0.310 (7.87)
0.220 (5.59)
0.965 (24.51)
0.295 (7.49)
0.945 (24.00)
0.285 (7.24)
20
11
10
PIN 1
0.275 (6.99)
20
1
11
1
10
0.060 (1.52)
0.015 (0.38)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
1.060 (26.92) MAX
MAX
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.180 (4.57)
MAX
0.150 (3.81)
MIN
0.015 (0.38) MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
0
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.100
(2.54)
BSC
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AE
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-20)
Dimensions shown in millimeters and (inches)
13.00 (0.5118)
12.60 (0.4961)
20
1
11
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
10
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
؋
45؇ 0.30 (0.0118)
0.10 (0.0039)
8؇
0؇
1.27
(0.0500)
BSC
0.51 (0.0201) SEATING
0.33 (0.0130)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.32 (0.0126)
0.23 (0.0091)
PLANE
COMPLIANT TO JEDEC STANDARDS MS-013AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
4/03—Data Sheet changed from REV. D to REV. E.
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
–16–
REV. E
相关型号：
AD7705BR
2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16, 0.300 INCH, MS-013AA, SOIC-16
ROCHESTER
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