AD7709BRUZ-REEL7_技术文档

16-Bit ꢀ-ꢁ ADC with

Switchable Current Sources

a

AD7709

FEATURES

APPLICATIONS

16-Bit ꢀ-ꢁ ADC

Sensor Measurement

Temperature Measurement

Pressure Measurements

Weigh Scales

Programmable Gain Front End

Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz

Update Rate

VREF Select™ Allows Absolute and Ratiometric

Measurement Capability

Portable Instrumentation

4–20 mA Loops

ISOURCE Select™

16-Bit No Missing Codes

GENERAL DESCRIPTION

The AD7709 is a complete analog front end for low frequency

measurement applications. It contains a 16-bit ⌺-⌬ ADC, selectable

reference inputs, three switchable matched excitation current

sources, low-side power switches, and a digital I/O port. The

16-bit channel with PGA accepts fully differential, unipolar,

and bipolar input signal ranges from 1.024 ϫ REFIN/128 to

1.024 ϫ REFIN. It can be configured as two fully differential

input channels or four pseudo-differential input channels. Signals

can be converted directly from a transducer without the need for

signal conditioning.

13-Bit p-p Resolution @ 20 Hz, 20 mV Range

16-Bit p-p Resolution @ 20 Hz, 2.56 V Range

INTERFACE

3-Wire Serial

SPI^®, QSPI™, MICROWIRE™, and DSP Compatible

Schmitt Trigger on SCLK

POWER

Specified for Single 3 V and 5 V Operation

Normal: 1.25 mA Typ @ 3 V

The device operates from a 32.768 kHz crystal with an on-chip

PLL generating the required internal operating frequency. The

output data rate from the part is software programmable. The

p-p resolution from the part varies with the programmed gain

and output data rate.

Power-Down: 7 ꢂA (32.768 kHz Crystal Running)

ON-CHIP FUNCTIONS

Rail-to-Rail Input Buffer and PGA

Selectable Reference Inputs

3 Switchable, Ratioed Current Sources for

V_BEMeasurements

4-Bit Digital I/O Port

Low-Side Power Switches

The part operates from a single 3 V or 5 V supply. When

operating from 3 V supplies, the power dissipation for the part

is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

REFIN1(+) REFIN2(+)

REFIN1(–) REFIN2(–)

XTAL1 XTAL2

V

DD

IEXC1

8I

IEXC2

8I

IEXC3

I

OSCILLATOR

AND

IOUT1

IOUT2

PLL

DOUT

DIN

SERIAL

INTERFACE

AND

CONTROL

LOGIC

I = 25ꢂA

SCLK

CS

AIN1

AIN2

AIN3/P3

AIN4/P4

AINCOM

RDY

PGA

16-BIT ꢀ-ꢁ ADC

BUF

MUX

RESET

V

DD

I/O PORT

AD7709

GND

PWRGND

V

P1/SW1 P2/SW2

DD

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD7709* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

TOOLS AND SIMULATIONS

• Sigma-Delta ADC Tutorial

EVALUATION KITS

REFERENCE MATERIALS

• AD7709 Evaluation Board

Technical Articles

• Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter

• MS-2210: Designing Power Supplies for High Speed ADC

DOCUMENTATION

Application Notes

• Part 1: Circuit Suggestions Using Features and

Functionality of New Sigma-Delta ADCs

• AN-202: An IC Amplifier User’s Guide to Decoupling,

Grounding, and Making Things Go Right for a Change

• Part 2: Circuit Suggestions Using Features and

Functionality of New Sigma-Delta ADCs

• AN-283: Sigma-Delta ADCs and DACs

• AN-311: How to Reliably Protect CMOS Circuits Against

DESIGN RESOURCES

• AD7709 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Power Supply Overvoltaging

• AN-388: Using Sigma-Delta Converters-Part 1

• AN-389: Using Sigma-Delta Converters-Part 2

• AN-397: Electrically Induced Damage to Standard Linear

Integrated Circuits:

• AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-

Delta ADC

DISCUSSIONS

View all AD7709 EngineerZone Discussions.

• AN-608: Input Buffers on Sigma-Delta ADCs

• AN-609: Chopping on Sigma-Delta ADCs

• AN-610: The PGA on Sigma-Delta ADCs

SAMPLE AND BUY

Visit the product page to see pricing options.

• AN-611: 50 Hz/60Hz Rejection on Sigma-Delta ADCs

• AN-615: Peak-to-Peak Resolution Versus Effective

Resolution

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

Data Sheet

• AD7709: 16-Bit Sigma Delta ADC with Switchable Current

Sources Data Sheet

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

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AD7709

TABLE OF CONTENTS

MICROCOMPUTER/MICROPROCESSOR

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9

TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10

ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 11

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

S-D ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . 13

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 14

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . 18

CONFIGURING THE AD7709 . . . . . . . . . . . . . . . . . . . . . 19

DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AD7709-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 21

AD7709-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 21

AD7709-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 21

CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 22

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 23

Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 23

Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 26

3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 27

Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

–2–

REV. A

AD7709

(V_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 =

32.768 kHz Crystal; all specifications T_MINto T_MAX, unless otherwise noted.)

SPECIFICATIONS¹

Parameter

AD7709A, AD7709B

Unit

Test Conditions

ADC CHANNEL SPECIFICATION

Output Update Rate

5.4

105

Hz min

Hz max

0.732 ms Increments

ADC CHANNEL

No Missing Codes²

Resolution

16

13

16

Bits min

Bits p-p

20 Hz Update Rate

± 20 mV Range, 20 Hz Update Rate

± 2.56 V Range, 20 Hz Update Rate

Output Noise and Update Rates

Integral Nonlinearity²

Offset Error

See Tables II to V

± 30

± 3

± 10

± 0.75

± 0.2

± 0.5

85

2 ¥ 1.024 REFIN

FSR =

Typically 2 ppm

ppm of FSR max

mV typ

nV/∞C typ

LSB typ

% of FS typ

ppm/∞C typ

dB typ

GAIN

Offset Error Drift vs. Temperature

Full-Scale Error³

B Grade, V_DD= 4 V

A Grade

Gain Drift vs. Temperature

Power Supply Rejection (PSR)

Input Range = ± 2.56 V

100 dB typ on ± 20 mV Range

ANALOG INPUTS

Differential Input Voltage Ranges

±1.024 ¥ REFIN

V nom

REFIN = REFIN(+) – REFIN(–)

GAIN = 1 to 128

GAIN

ADC Range Matching

± 2

mV typ

V min

V max

Input Voltage = 19 mV on All Ranges

Absolute AIN1–AIN4 Voltage Limits²GND + 100 mV

V_DD– 100 mV

AIN1–AIN4 Analog Input Current

DC Input Current²

± 1

nA max

pA /∞C typ

V min

DC Input Current Drift

± 5

Absolute AINCOM Voltage Limits²

GND – 30 mV

V_DD+ 30 mV

V max

AINCOM Analog Input Current

DC Input Current

DC Input Current Drift

Normal-Mode Rejection^{2, 4}

@ 50 Hz

@ 60 Hz

Common-Mode Rejection

@ DC

Pseudo-Differential Mode of Operation

Input Current Varies with Input Range

± 125

± 2

nA/V typ

pA/V/∞C typ

100

dB min

50 Hz ± 1 Hz, 16.65 Hz Update Rate, SF = 82

60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68

100

dB typ

Input Range = ± 2.56 V, AIN = 1 V

110 dB typ on ± 20 mV Range

50 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V

60 Hz ± 1 Hz, Range = ± 2.56 V, AIN = 1 V

@ 50 Hz²

@ 60 Hz²

100

dB min

REFERENCE INPUTS

(REFIN1 and REFIN2)

REFIN Voltage

2.5

1

V nom

V min

REFIN = REFIN(+) – REFIN(–)

REFIN Voltage Range²

V_DD

V max

V min

V max

mA/V typ

nA/V/∞C typ

Absolute REFIN Voltage Limits²

GND – 30 mV

V_DD+ 30 mV

0.5

Average Reference Input Current

Average Reference Input Current Drift

Normal-Mode Rejection^{2, 4}

@ 50 Hz

± 0.01

100

dB min

50 Hz ± 1 Hz, SF = 82

60 Hz ± 1 Hz, SF = 68

@ 60 Hz

Common-Mode Rejection

@ DC

@ 50 Hz

110

dB typ

Input Range = ± 2.56 V, AIN = 1 V

50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V

60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V

@ 60 Hz

See Notes on page 5.

–3–

REV. A

AD7709

(continued)

SPECIFICATIONS

Parameter

AD7709A, AD7709B

Unit

Test Conditions

EXCITATION CURRENT SOURCES

(IEXC1, IEXC2, and IEXC3)

Output Current

IEXC1, IEXC2

IEXC3

Initial Tolerance at 25∞C

Drift

Initial Current Matching at 25∞C

(between IEXC1 and IEXC2)

Drift Matching

200

25

± 10

200

± 2.5

mA nom

% typ

ppm/∞C typ

% max

B Grade, No Load

A Grade, No Load

% typ

(between IEXC1 and IEXC2)

Initial Current Matching at 25∞C

(between 8 ϫ IEXC3 and

IEXC1/IEXC2)

20

± 5

ppm/∞C typ

% max

B Grade, No Load

A Grade, No Load

± 5

% typ

Drift Matching

(between 8 ϫ IEXC3 and

IEXC1/IEXC2)

Line Regulation

20

ppm/∞C typ

V_DD= 5 V ± 5%

A, B Grades

B Grade

A Grade

IEXC1, IEXC2

1.25

2.6

1

300

V_DD– 0.6

GND –30 mV

mA/V typ

mA/V max

mA/V typ

nA/V typ

V max

IEXC3

Load Regulation

Output Compliance

V min

LOW-SIDE POWER SWITCHES

(SW1 and SW2)

R_ON

3

5

4.5

7

20

W typ

V_DD= 5 V, A and B Grade

B Grade

V_DD= 3 V, A and B Grade

B Grade

W max

W typ

W max

mA max

Allowable Current²

Continuous Current per Switch

LOGIC INPUTS

All Inputs Except SCLK and XTAL1²

V_INL, Input Low Voltage

0.8

0.4

2.0

V max

V min

V_DD= 5 V

V_DD= 3 V

V_DD= 3 V or 5 V

V_INH, Input High Voltage

SCLK Only (Schmitt-Triggered Input)²

V_T(+)

V_T(–)

V_T(+)– V_T(–)

V_T(+)

V_T(–)

1.4/2

V min/V max

V_DD= 5 V

V_DD= 3 V

0.8/1.4

0.3/0.85

0.95/2

0.4/1.1

0.3/0.85

V_T(+)– V_T(–)

XTAL1 Only²

V_INL, Input Low Voltage

V_INH, Input High Voltage

V_INL, Input Low Voltage

V_INH, Input High Voltage

Input Currents (except XTAL)

0.8

3.5

0.4

2.5

± 2

V max

V min

V max

V min

mA max

V_DD= 5 V

V_DD= 3 V

V_IN= V_DD

–70

V_IN= GND, Typically –40 mA @ 5 V and

–20 mA at 3 V; Weak Pull-Ups on the

Logic Inputs

Input Capacitance

10

pF typ

All Digital Inputs

–4–

REV. A

AD7709

Parameter

AD7709A, AD7709

B

Unit

Test Conditions

LOGIC OUTPUTS (Excluding XTAL2)

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V_DD– 0.6

0.4

4

0.4

± 10

Binary

Offset Binary

V min

V max

V min

V max

mA max

pF typ

V_DD= 3 V, I_SOURCE= 100 mA

V_DD= 3 V, I_SINK= 100 mA

V_DD= 5 V, I_SOURCE= 200 mA

V_DD= 5 V, I_SINK= 1.6 mA

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

Floating-State Leakage Current

Floating-State Output Capacitance

Data Output Coding

Unipolar Mode

Bipolar Mode

I/O PORT

V_INL, Input Low Voltage²

0.8

0.4

2.0

± 2

V max

V min

mA max

V_DD= 5 V

V_DD= 3 V

V_INH, Input High Voltage²

Input Currents

V_DD= 3 V or 5 V

V_IN= V_DD

V_IN= GND, Typically –40 mA @ V_DD= 5 V

and –20 mA at V_DD= 3 V; Weak Pull-Ups on

the Logic Inputs

–70

Input Capacitance

10

V_DD– 0.6

0.4

4

0.4

± 10

pF typ

V min

V max

V min

V max

mA max

pF typ

All Digital Inputs

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

Floating-State Output Leakage Current

Floating-State Output Capacitance

V_DD= 3 V, I_SOURCE= 100 mA

V_DD= 3 V, I_SINK= 100 mA

V_DD= 5 V, I_SOURCE= 200 mA

V_DD= 5 V, I_SINK= 1.6 mA

START-UP TIME

From Power-On

From Standby Mode

From Power-Down Mode

300

1

300

ms typ

OSCPD = 0

OSCPD = 1

POWER REQUIREMENTS

Power Supply Voltage

V_DD– GND

2.7/3.6

4.75/5.25

V min/max

V_DD= 3 V nom

V_DD= 5 V nom

Power Supply Currents

I_DDCurrent

1.5

1.75

7

mA max

mA typ

V_DD= 3 V, 1.25 mA typ

V_DD= 5 V, 1.45 mA typ

I_DD(Low Power Mode)

B Grade, V_DD= 3 V, Standby Mode

A Grade, V_DD= 3 V, Standby Mode

B Grade, V_DD= 3 V, Power-Down Mode

A Grade, V_DD= 3 V, Power-Down Mode

B Grade, V_DD= 5 V, Standby Mode

A Grade, V_DD= 5 V, Standby Mode

B Grade, V_DD= 5 V, Power-Down Mode

A Grade, V_DD= 5 V, Power-Down Mode

V_DD= 3 V, Standby Mode

7

1.5

26

mA max

mA typ

mA max

mA typ

26

6.5

107⁵

134⁵

mA max

mA typ

I_DDfor One Conversion Second

mA typ

V_DD= 5 V, Standby Mode

NOTES

¹Temperature Range –40∞C to +85∞C.

²Guaranteed by design and/or characterization data on production release.

³Full-scale error applies to both positive and negative full scale.

⁴Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.79 Hz update rate. Normal mode rejection in this case is 60 dB min.

⁵When the part is placed in power-down mode for a single conversion/second, at an update rate of 19.79 Hz, the current consumption is higher compared to when the

part is placed in standby mode as the crystal oscillator takes approximately 100 ms to begin clocking. The device will, therefore, use full current for the conversion

time and the 100 ms period required for the oscillator to begin clocking. However, if the conversion rate is lower, the current consumption will be reduced so that it

is worthwhile to use the power-down rather than the standby mode.

Specifications subject to change without notice.

REV. A

–5–

AD7709

(V_DD= 2.7 V to 3.6 V or V_DD= 4.75 V to 5.25 V; GND = 0 V; X_TAL= 32.768 kHz; Input Logic 0 = 0 V,

Logic 1 = V_DDunless otherwise noted.)

TIMING CHARACTERISTICS^{1, 2}

Limit at T_MIN, T_MAX

(A, B Version)

Parameter

Unit

Conditions/Comments

t₁

t₂

30.5176

50

ms typ

ns min

Crystal Oscillator Period

RESET Pulsewidth

Read Operation

t₃

0

ns min

ns max

ns min

ns max

ns min

ns max

RDY to CS Setup Time

t₄₄

CS Falling Edge to SCLK Active Edge Setup Time³

SCLK Active Edge to Data Valid Delay³

V_DD= 4.75 V to 5.25 V

t₅

60

80

0

60

80

100

0

V_DD= 2.7 V to 3.6 V

CS Falling Edge to Data Valid Delay

V_DD= 4.75 V to 5.25 V

V_DD= 2.7 V to 3.6 V

SCLK High Pulsewidth

4, 5

t_5A

t₆

t₇

SCLK Low Pulsewidth

t₈₆

CS Rising Edge to SCLK Inactive Edge Hold Time³

Bus Relinquish Time after SCLK Inactive Edge³

t₉

10

80

100

t₁₀

SCLK Active Edge to RDY High^{3, 7}

Write Operation

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

0

ns min

CS Falling Edge to SCLK Active Edge Setup Time³

Data Valid to SCLK Edge Setup Time

Data Valid to SCLK Edge Hold Time

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge to SCLK Edge Hold Time

30

25

100

0

NOTES

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

²See Figures 2 and 3.

³SCLK active edge is falling edge of SCLK.

⁴These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁵This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.

⁶These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-

lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish

times of the part and as such are independent of external bus loading capacitances.

⁷RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur

close to the next output update.

–6–

REV. A

AD7709

I

(1.6mA WITH V = 5V

DD

SINK

100ꢂA WITH V = 3V)

DD

TO OUTPUT

1.6V

50pF

I

(200ꢂA WITH V = 5V

DD

SOURCE

100ꢂA WITH V = 3V)

DD

Figure 1. Load Circuit for Timing Characterization

CS

t₁₁

t₁₆

t₁₄

SCLK

t₁₅

t₁₂

t₁₃

DIN

MSB

LSB

Figure 2. Write Cycle Timing Diagram

RDY

t₃

t₁₀

CS

t₈

t₄

t₆

SCLK

t₇

t₅

t₉

t_5A

MSB

LSB

DOUT

Figure 3. Read Cycle Timing Diagram

REV. A

–7–

AD7709

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25∞C, unless otherwise noted.)

PIN CONFIGURATION

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1

2

3

4

5

6

7

8

9

24

23

22

21

20

IOUT1

IOUT2

XTAL1

XTAL2

PWRGND to AGND . . . . . . . . . . . . . . –20 mV to +20 mV

Analog Input Voltage to GND . . . . . –0.3 V to V_DD+ 0.3 V

Reference Input Voltage to GND . . . –0.3 V to V_DD+ 0.3 V

Total AIN/REFIN Current (Indefinite) . . . . . . . . . . 30 mA

Digital Input Voltage to GND . . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Output Voltage to GND . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

V

REFIN1(+)

REFIN1(–)

AIN1

DD

GND

DIN

AD7709

AIN2

19

18

17

16

15

14

13

DOUT

RDY

TOP VIEW

(Not to Scale)

AIN3/P3

AIN4/P4

AINCOM

CS

SCLK

REFIN2(+) 10

REFIN2(–) 11

RESET

q

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . 97.9∞C/W

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . 14∞C/W

P1/SW1

q

12

PWRGND

P2/SW2

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Model

AD7709ARU

AD7709BRU

–40∞C to +85∞C TSSOP

RU-24

EVAL-AD7709EB

Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–8–

REV. A

AD7709

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1

2

3

IOUT1

Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina-

tion of the current sources, can be switched to this output.

Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina-

tion of the current sources, can be switched to this output.

IOUT2

REFIN1(+) Positive Reference Input. REFIN1(+) can lie anywhere between V_DDand GND + 1 V. The nominal refer-

ence voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V_DD

.

4

5

REFIN1(–) Negative Reference Input. This reference input can lie anywhere between GND and V_DD– 1 V.

AIN1

Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with

AINCOM or as the positive input of a fully differential input pair when used with AIN2.

6

7

AIN2

Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with

AINCOM or as the negative input of a fully differential input pair when used with AIN1.

Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when

used with AINCOM or as the positive input of a fully differential input pair when used with AIN4. This pin

can also be programmed as a general-purpose digital input bit.

AIN3/P3

8

AIN4/P4

Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when

used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3. This pin

can also be programmed as a general-purpose digital input bit.

9

AINCOM

All analog inputs are referenced to this input when configured in pseudo-differential input mode.

10

REFIN2(+) Positive Reference Input. REFIN2(+) can lie anywhere between V_DDand GND + 1 V. The nominal reference

voltage (REFIN2(+) – REFIN2(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V_DD

.

11

12

REFIN2(–) Negative Reference Input. This reference input can lie anywhere between GND and V_DD– 1 V.

P2/SW2

Dual-Purpose Pin. It can act as a general-purpose output (P2) bit or as a low-side power switch (SW2) to

PWRGND.

13

14

PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to GND.

P1/SW1

Dual-Purpose Pin. It can act as a general-purpose output (P1) bit or as a low-side power switch (SW1) to

PWRGND.

15

16

RESET

Digital Input Used to Reset the ADC to Its Power-On-Reset Status. This pin has a weak pull-up internally to V_DD.

Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input making

the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted

in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being

transmitted to or from the AD7709 in smaller batches of data. A weak pull-up to V_DDis provided on the

SCLK input.

SCLK

17

18

CS

Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the

AD7709 in systems with more than one device on the serial bus or as a frame synchronization signal in com-

municating with the device. CS can be hardwired low allowing the AD7709 to operate in 3-wire mode with

SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to V_DDis provided on the CS input.

RDY is a Logic Low Status Output from the AD7709. RDY is low if the ADC has valid data in its data

register. This output returns high on completion of a read operation from the data register. If data is not

read, RDY will return high prior to the next update indicating to the user that a read operation should

not be initiated.

RDY

19

20

DOUT

DIN

Serial Data Output Accessing the Output Shift Register of the AD7709. The output shift register can contain

data from any of the on-chip data or control registers.

Serial Data Input Accessing the Input Shift Register on the AD7709. Data in this shift register is transferred to

the control registers within the ADC, the selection bits of the communications register selecting which

control register. A weak pull-up to V_DDis provided on the DIN input.

21

22

23

24

GND

V_DD

XTAL2

XTAL1

Ground Reference Point for the AD7709

Supply Voltage, 3 V or 5 V Nominal

Output from the 32.768 kHz Crystal Oscillator Inverter

Input to the 32.768 kHz Crystal Oscillator Inverter

REV. A

–9–

AD7709–Typical Performance Characteristics

32772

700

600

500

400

300

V

= 5V

DD

INPUT RANGE = ꢄ20mV

32771

32770

32769

32768

32767

32766

32765

32764

UPDATE RATE = 19.79Hz

200

100

0

V

T

= 2.5V

= 25 C

REF

A

0

100 200 300 400 500 600 700 800 900 1000

READING NUMBER

32766

32767

32768

32769

32770

32771

CODE

TPC 3. Noise Histogram

TPC 1. Typical Noise Plot on ±20 mV Input Range

3.0

V

= 5V

DD

= 25ꢃC

T

A

ꢄ2.56V RANGE

2.5

V

DD

2.0

V

= 5V

DD

V

= 2.5V

REF

1.5

1.0

0.5

0

OSCILLATOR

INPUT RANGE = ꢄ2.56V

UPDATE RATE = 19.79Hz

T

= 25ꢃC

A

ꢄ20mV RANGE

TIME BASE = 100ms/DIV

TRACE 1 =TRACE 2 = 2V/DIV

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

V

–V

REF

TPC 2. RMS Noise vs. Reference Input

TPC 4. Typical Oscillator Power-Up

–10–

REV. A

AD7709

ADC CIRCUIT INFORMATION

Overview

The AD7709 incorporates a ⌺-⌬ ADC channel with on-chip digital

filtering intended for the measurement of wide dynamic range, low

frequency signals such as those in weigh-scale, strain-gauge,

pressure transducer, or temperature measurement applications.

word from the filter is summed and averaged with the previous

filter output to produce a new valid output result to be written to

the ADC data register.

The input chopping is incorporated into the input multiplexer

while the output chopping is accomplished by an XOR gate at

the output of the modulator. The chopped modulator bit stream

is applied to a Sinc³filter. The programming of the Sinc³deci-

mation factor is restricted to an 8-bit register SF, the actual

decimation factor is the register value × 8. The decimated out-

put rate from the Sinc³filter (and the ADC conversion rate) will

therefore be:

⌺-⌬ ADC

This channel can be programmed to have one of eight input

voltage ranges from 20 mV to 2.56 V. This channel can be

configured as either two fully differential inputs (AIN1/AIN2

and AIN3/AIN4) or four pseudo-differential input channels

(AIN1/AINCOM, AIN2/AINCOM, AIN3/AINCOM, and

AIN4/AINCOM). Buffering the input channel means that the

part can accommodate significant source impedances on the

analog input and that R, C filtering (for noise rejection or RFI

reduction) can be placed on the analog inputs if required.

1

3



1



f_ADC

=

×

× f_MOD









8 × SF

where:

_ADCis the ADC update rate.

f

The ADC employs a ⌺-⌬ conversion technique to realize up to

16 bits of no-missing-codes performance. The ⌺-⌬ modulator

converts the sampled input signal into a digital pulse train whose

duty cycle contains the digital information. A Sinc³programmable

low-pass filter is then employed to decimate the modulator output

data stream to give a valid data conversion result at programmable

output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).

A chopping scheme is also employed to minimize ADC channel

offset errors. A block diagram of the ADC input channel is shown

in Figure 4.

SF is the decimal equivalent of the word loaded to the

filter register.

f

_MODis the modulator sampling rate of 32.768 kHz.

Programming the filter register determines the update rate for the

ADC. The chop rate of the channel is half the output data rate.

The frequency response of the filter H(f ) is as follows:



sin (SF × 8 × π × f/ f_MOD) ³

1

×







SF × 8

sin (π × f/ f_MOD)



The sampling frequency of the modulator loop is many times

higher than the bandwidth of the input signal. The integrator in

the modulator shapes the quantization noise (which results from

the analog-to-digital conversion) so that the noise is pushed

toward one-half of the modulator frequency. The output of the

⌺-⌬ modulator feeds directly into the digital filter. The digital

filter then band-limits the response to a frequency significantly

lower than one-half of the modulator frequency. In this manner,

the 1-bit output of the comparator is translated into a band-

limited, low noise output from the AD7709 ADC. The AD7709

filter is a low-pass, Sinc³, or (SIN(x)/x)³filter whose primary

function is to remove the quantization noise introduced at the

modulator. The cutoff frequency and decimated output data

rate of the filter are programmable via the SF word loaded to the

filter register.



sin (2 × π × f/ f_OUT) 

1

2

×







sin (π × f/ f_OUT

)



where:

_MOD= 32,768 Hz.

SF = value programmed into Filter Register.

_OUT= f_MOD/(SF ϫ 8 ϫ 3)

f

The following shows plots of the filter frequency response for the

SF words shown in Table I. The overall frequency response is the

product of a Sinc³and a sinc response. There are Sinc³notches

at integer multiples of 3 ϫ f_ADC, and there are sinc notches at odd

integer multiples of f_ADC/2. The 3 dB frequency for all values of SF

obeys the following equation:

A chopping scheme is employed where the complete signal chain

is chopped, resulting in excellent dc offset and offset drift speci-

fications, and is extremely beneficial in applications where drift,

noise rejection, and optimum EMI rejection are important fac-

tors. With chopping, the ADC repeatedly reverses its inputs.

The decimated digital output words from the Sinc³filters there-

fore have a positive offset and negative offset term included. As a

result, a final summing stage is included so that each output

f 3 dB = 0.24 × f

The signal chain is chopped as shown in Figure 4. The chop

frequency is:

(

)

ADC

 f_ADC



f_CHOP

=







2



f_CHOP

f_IN

f_MOD

f_CHOP

f_ADC

⌺-⌬

3

DIGITAL

OUTPUT

ANALOG

INPUT

1

2

1

PGA

3

؋

(8

؋

SF )

MUX

XOR

⌺

BUF

⌺

(

)

8

؋

SF

MOD

3

SINC FILTER

A

+V

–V

OS

IN

Figure 4. ADC Channel Block Diagram

–11–

REV. A

AD7709

As shown in the block diagram, the Sinc³filter outputs alternately

contain +V_OSand –V_OS, where V_OSis the respective channel offset.

This offset is removed by performing a running average of 2, which

means that the settling time to any change in programming of

the ADC will be twice the normal conversion time, while an

asynchronous step change on the analog input will not be fully

reflected until the third subsequent output.

Table I. ADC Conversion and Settling Times for Various

SF Words

Data Update Rate

f_ADC(Hz)

Settling Time

t_SETTLE(ms)

SF Word

13

105.3

19.79

5.35

19.04

101.07

373.54

69 (Default)

255

Ê

ˆ

2

t_SETTLE

=

= 2 ¥ t_ADC

Á

Ë

˜

¯

Normal mode rejection is the major function of the digital filter

on the AD7709. The normal mode 50 ± 1 Hz rejection with an

SF word of 82 is typically –100 dB. The 60 ± 1 Hz rejection with

SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz

rejection of better than 60 dB is achieved with an SF of 69.

Choosing an SF word of 69 places notches at both 50 Hz and

60 Hz. Figures 5 to 8 show the filter rejection for a selection

of SF words.

f

ADC

The allowable range for SF is 13 to 255, with a default of 69

(45H). The corresponding conversion rates, conversion times,

and settling times are shown in Table I. Note that the conver-

sion time increases by 0.732 ms for each increment in SF.

0

–20

0

–20

–40

–60

–40

–80

–60

–100

–120

–140

–160

–180

–200

–80

–100

–120

–140

–160

700

450 500 550 600 650

0

50 100 150 200 250 300 350 400

0

10

20

30

40

50

60

70

80

90 100

FREQUENCY – Hz

SF = 13

FREQUENCY – Hz

OUTPUT DATA RATE = 105Hz

INPUT BANDWIDTH = 25.2Hz

FIRST NOTCH = 52.5Hz

50Hz REJECTION = –23.6dB, 50Hz ꢄ 1Hz REJECTION = –20.5dB

60Hz REJECTION = –14.6dB, 60Hz ꢄ 1Hz REJECTION = –13.6dB

SF = 69

OUTPUT DATA RATE = 19.8Hz

INPUT BANDWIDTH = 4.74Hz

FIRST NOTCH = 9.9Hz

50Hz REJECTION = –66dB, 50Hz ꢄ 1Hz REJECTION = –60dB

60Hz REJECTION = –117dB, 60Hz ꢄ 1Hz REJECTION = –94dB

Figure 5. Filter Profile with SF = 13

Figure 7. Filter Profile with Default SF = 69 Giving Filter

Notches at Both 50 Hz and 60 Hz

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY – Hz

SF = 82

FREQUENCY – Hz

SF = 255

OUTPUT DATA RATE = 5.35Hz

INPUT BANDWIDTH = 1.28Hz

50Hz REJECTION = –93dB, 50Hz ꢄ 1Hz REJECTION = –93dB

60Hz REJECTION = –74dB, 60Hz ꢄ 1Hz REJECTION = –68dB

OUTPUT DATA RATE = 16.65Hz

INPUT BANDWIDTH = 4Hz

50Hz REJECTION = –171dB, 50Hz ꢄ 1Hz REJECTION = –100dB

60Hz REJECTION = –58dB, 60Hz ꢄ 1Hz REJECTION = –53dB

Figure 6. Filter Profile with SF = 82

Figure 8. Filter Profile with SF = 255

–12–

REV. A

AD7709

level and is independent of frequency. The quantization noise starts

at an even lower level but rises rapidly with increasing frequency

to become the dominant noise source. The numbers in the tables

are given for the bipolar input ranges. For the unipolar ranges,

the rms noise numbers will be the same as the bipolar range, but

the peak-to-peak resolution is now based on half the signal range,

which effectively means losing 1 bit of resolution.

NOISE PERFORMANCE

Tables II and III show the output rms noise and output peak-to-

peak resolution in bits (rounded to the nearest 0.5 LSB) for a

selection of output update rates. The numbers are typical and

generated at a differential input voltage of 0 V. The output update

rate is selected via the SF7–SF0 bits in the Filter Register. It is

important to note that the peak-to-peak resolution figures

represent the resolution for which there will be no code flicker

within a six-sigma limit. The output noise comes from two sources.

The first is the electrical noise in the semiconductor devices

(device noise) used in the implementation of the modulator.

Second, when the analog input is converted into the digital

domain, quantization noise is added. The device noise is at a low

ON-CHIP REGISTERS

The AD7709 is controlled and configured via a number of on-chip

registers, as shown in Figure 9 and described in more detail in the

following pages. In the following descriptions, set implies a Logic 1

state and cleared implies a Logic 0 state, unless otherwise stated.

Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise in ꢂV)

Input Range

ꢄ160 mV

SF

Word

Data Update

Rate (Hz)

ꢄ20 mV

ꢄ40 mV

ꢄ80 mV

ꢄ320 mV

ꢄ640 mV

ꢄ1.28 V

ꢄ2.56 V

13

69

255

105.3

19.79

5.35

1.50

0.60

0.35

1.50

0.65

0.35

1.60

0.65

0.37

1.75

0.65

0.37

3.50

0.65

0.37

4.50

0.95

0.51

6.70

1.40

0.82

11.75

2.30

1.25

Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709 (Peak-to-Peak Resolution in Bits)

Input Range

ꢄ160 mV

SF

Word

Data Update

Rate (Hz)

ꢄ20 mV ꢄ40 mV

ꢄ80 mV

ꢄ320 mV

ꢄ640 mV

ꢄ1.28 V

ꢄ2.56 V

13

69

255

105.3

19.79

5.35

12

13

14

13

14

15

14

15

16

15

16

15

16

15.5

16

DIN

WEN R/W STBY OSCPD

0 0 A1 A0

DOUT

ADC STATUS REGISTER

(8 BITS)

REGISTER

SELECT

DECODER

DIN

DOUT

CONFIGURATION REGISTER

(24 BITS)

FILTER REGISTER

(8 BITS)

ADC DATA REGISTER

(16 BITS)

DOUT

Figure 9. On-Chip Registers

REV. A

–13–

AD7709

Communications Register (A1, A0 = 0, 0)

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the

Communications Register. The data written to the Communications Register determines whether the next operation is a read or

write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write

operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications

Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for

a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32

serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table IV outlines the bit designations for

the Communications Register. CR0 to CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7

denotes the first bit of the data stream.

CR7

CR6

CR5

CR4

CR3

0(0)

CR2

0(0)

CR1

CR0

A(0)

WEN(0)

R/W(0)

STBY(0)

OSCPD(0)

A1(0)

Table IV. Communications Register Bit Designations

Bit

Location

Bit

Name

Description

Write Enable Bit.

CR7

WEN

A 0 must be written to this bit so the write operation to the Communications Register actually takes place.

If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this

bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be

loaded to the Communications Register.

CR6

CR5

R/W

A 0 in this bit location indicates that the next operation will be a write to a specified register.

A 1 in this position indicates that the next operation will be a read from the designated register.

STBY

Standby Bit Location.

A 1 in this location places the AD7709 in low power mode.

A 0 in this location powers up the AD7709.

CR4

OSCPD

Oscillator Power-Down Bit.

If this bit is set, placing the AD7709 in standby mode will stop the crystal oscillator also, reducing the

power consumed by the part to a minimum. The oscillator will require 300 ms to begin oscillating when

the ADC is taken out of power-down mode.

If this bit is cleared, the oscillator is not stopped when the ADC is placed in power-down mode. When

the ADC is taken out of power-down mode, the oscillator does not require the 300 ms start-up time.

CR3–CR2

0

These bits must be programmed with a Logic 0 for correct operation.

CR1–CR0 A1–A0

Register Address Bits. These address bits are used to select which of the AD7709 registers are accessed

during this serial interface communication.

Table V. Register Selection Table

A1 A0 Register

0

1

0

1

0

1

Communications Register during a Write Operation

Status Register during a Read Operation

Configuration Register

Filter Register

ADC Data Register

–14–

REV. A

AD7709

Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H)

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-

tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the

Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the

data stream. The number in brackets indicates the power-on-reset default status of that bit.

SR7

SR6

0(0)

SR5

0(0)

SR4

0(0)

SR3

SR2

0(0)

SR1

SR0

RDY(0)

ERR(0)

STBY(0)

LOCK(0)

Table VI. Status Register Bit Designations

Bit

Location

Bit

Name

Description

SR7

RDY

Ready Bit for ADC.

Set when data is written to the ADC data register.

The RDY bit is cleared automatically after the ADC data register has been read or a period of time before

the data register is updated with a new conversion result.

SR6

SR5

SR4

SR3

0

This bit is automatically cleared.

0

ERR

ADC Error Bit. This bit is set at the same time as the RDY bit.

Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.

Error sources include Overrange, Underrange.

Cleared by a write to the mode bits to initiate a conversion.

SR2

SR1

0

This bit is automatically cleared.

STBY

Standby Bit Indication.

When this bit is set, the AD7709 is in power-down mode.

This bit is cleared when the ADC is powered up.

SR0

LOCK

PLL Lock Status Bit.

Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact

sampling frequencies, etc., the LOCK bit should be interrogated and the result discarded if the LOCK

bit is 0.

REV. A

–15–

AD7709

Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H)

The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is usedto

select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations

for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register.

CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. A

write to the Configuration Register has immediate effect and does not reset the ADC. Therefore, if a current source is switched

while the ADC is converting, the user will have to wait for the full settling time of the sinc³filter before obtaining a fully settled output.

This equates to three outputs.

CONFIG23

PSW2(0)

CONFIG22

PSW1(0)

CONFIG21

I3EN1(0)

CONFIG20

I3EN0(0)

CONFIG19

I2EN1(0)

CONFIG18

I2EN0(0)

CONFIG17

I1EN1(0)

CONFIG16

I1EN0(0)

CONFIG15

P4DIG(0)

CONFIG14

P3DIG(0)

CONFIG13

P2EN(0)

CONFIG12

P1EN(0)

CONFIG11

P4DAT(0)

CONFIG10

P3DAT(0)

CONFIG9

P2DAT(0)

CONFIG8

P1DAT(0)

CONFIG7

CONFIG6

CH2(0)

CONFIG5

CH1(0)

CONFIG4

CH0(0)

CONFIG3

UNI(0)

CONFIG2

RN2(1)

CONFIG1

RN1(1)

CONFIG0

RN0(1)

REFSEL(0)

Table VII. Configuration Register Bit Designations

Bit

Location

Bit

Name

Description

CONFIG23

PSW2

Power Switch 2 Control Bit.

Set by user to enable power switch SW2/P2 to PWRGND.

Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches

are open.

CONFIG22

PSW1

Power Switch 1 Control Bit.

Set by user to enable power switch SW1/P1 to PWRGND.

Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches

are open.

CONFIG21

CONFIG20

I3EN1

I3EN0

IEXC3 Current Source Enable Bit

I3EN1

I3EN0

Function

0

1

0

1

0

1

IEXC3 Current Source OFF

IEXC3 Current Source Routed to the IOUT1 Pin

IEXC3 Current Source Routed to the IOUT2 Pin

Reserved

CONFIG19

CONFIG18

I2EN1

I2EN0

IEXC2 Current Source Enable Bit

I2EN1

I2EN0

Function

0

1

0

1

0

1

IEXC2 Current Source OFF

IEXC2 Current Source Routed to the IOUT1 Pin

IEXC2 Current Source Routed to the IOUT2 Pin

Reserved

CONFIG17

I1EN1

IEXC1 Current Source Enable Bit

–16–

REV. A

AD7709

Table VII. Configuration Register Bit Designations (continued)

Bit

Location

Bit

Name

Description

CONFIG16 I1EN0

IEXC1 Current Source Enable Bit

I1EN1

I1EN0

Function

0

1

0

1

0

1

IEXC1 Current Source OFF

IEXC1 Current Source Routed to the IOUT1 Pin

IEXC1 Current Source Routed to the IOUT2 Pin

Reserved

CONFIG15 P4DIG

CONFIG14 P3DIG

CONFIG13 P2EN

CONFIG12 P1EN

CONFIG11 P4DAT

CONFIG10 P3DAT

Digital Input Enable.

Set by user to enable pin AIN4/P4 as a digital input. A weak pull-up resistor is activated in this state.

Cleared by user to configure pin AIN4/P4 as an analog input.

Digital Input Enable.

Set by user to enable pin AIN3/P3 as a digital input. A weak pull-up resistor is activated in this state.

Cleared by user to configure pin AIN3/P3 as an analog input.

SW2/P2 Digital Output Enable Bit.

Set by user to enable P2 as a regular digital output pin.

Cleared by user to three-state the P2 output. PSW2 takes precedence over P2EN.

SW1/P1 Digital Output Enable Bit.

Set by user to enable P1 as a regular digital output pin.

Cleared by user to three-state the P1 output. PSW1 takes precedence over P1EN.

Digital Input Port Data Bit.

P4DAT is read only and will return a zero if P4DIG equals zero.

If P4 is enabled as a digital input, the readback value indicates the status of pin P4.

Digital Input Port Data Bit.

P3DAT is read only and will return a zero if P3DIG equals zero.

If P3 is enabled as a digital input, the readback value indicates the status of pin P3.

CONFIG9

CONFIG8

CONFIG7

P2DAT

P1DAT

REFSEL

Digital Output Port Data Bit. P2 is a digital output only. When the port is active as an output (P2EN = 1),

the value written to this data bit appears at the output port. Reading P2DAT will return the last value

written to the P2DAT bit.

Digital Output Port Data Bit. P1 is a digital output only. When the port is active as an output (P1EN = 1),

the value written to this data bit appears at the output port. Reading P1DAT will return the last value

written to the P1DAT bit.

ADC Reference Input Select.

Cleared by the user to select REFIN1(+) and REFIN1(–) as the ADC reference.

Set by the user to select REFIN2(+) and REFIN2(–) as the ADC reference.

CONFIG6

CONFIG5

CONFIG4

CH2

CH1

CH0

ADC Input Channel Selection Bit. It is used in conjunction with CH1 and CH0 as shown below.

ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH0 as shown below.

ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH1 as shown below.

CH2 CH1 CH0 Positive Input

Negative Input Buffer

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN1

AIN2

AIN3

AIN4

AIN1

AIN3

AINCOM

AIN2

AINCOM

AIN2

AIN4

AINCOM

AIN2

Positive Analog Input

Positive and Negative Analog Inputs

None

Positive and Negative Analog Inputs

The Buffer column indicates if the analog inputs are buffered or unbuffered. This determines the common-mode input range

on each input. If the input is unbuffered (AINCOM), the common-mode input includes ground.

REV. A

–17–

AD7709

Table VII. Configuration Register Bit Designations (continued)

Bit

Location

Bit

Name

Description

CONFIG3

UNI

Unipolar/Bipolar Operation Selection Bit.

Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding

i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a

code of FFFFh.

Cleared by the user to enable pseudo-bipolar operation. The device uses offset binary coding, i.e., a nega-

tive full-scale differential input will result in a code of 0000h, a 0 differential input will generate a code of

8000h, while a positive full-scale differential input will result in a code of FFFFh.

CONFIG2

CONFIG1

CONFIG0

RN2

RN1

RN0

This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below.

This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below.

This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below.

RN2

RN1

RN0

Selected ADC Input Range (V_REF= 2.5 V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

± 20 mV

± 40 mV

± 80 mV

± 160 mV

± 320 mV

± 640 mV

± 1.28 V

± 2.56 V

Table VIII. Filter Register Bit Designations

FR7

SF7(0)

FR6

SF6(1)

FR5

FR4

FR3

FR2

FR1

FR0

SF5(0)

SF4(0)

SF3(0)

SF2(1)

SF1(0)

SF0(1)

Table IX. Update Rate vs. SF WORD

SF (Dec)

SF (Hex)

f_ADC(Hz)

t_ADC(ms)

13

69

255

0D

45

FF

105.3

19.79

5.35

9.52

50.34

186.77

Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h)

The Filter Register is an 8-bit register from which data can be

read or to which data can be written. This register determines

the amount of averaging performed by the sinc filter. Table VIII

outlines the bit designations for the Filter Register. FR7 through

FR0 indicate the bit location, FR denoting the bits are in the

Filter Register. FR7 denotes the first bit of the data stream. The

number in brackets indicates the power-on/reset default status

of that bit. The number in this register is used to set the decima-

tion factor and thus the output update rate for the ADC. The

Filter Register cannot be written to by the user while the ADC

is active. The update rate is calculated as follows:

The allowable range for SF is 13dec to 255dec. Examples of SF

values and corresponding conversion rate (f_ADC) and time (t_ADC

are shown in Table IX. It should also be noted that the ADC

input channel is chopped to minimize offset errors. This means

that the time for a single conversion or the time to the first con-

)

version result is 2 ϫ t_ADC

.

ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset =

0000h)

The conversion result is stored in the ADC Data Register (DATA).

This register is 16-bits wide. This is a read-only register. On

completion of a read from this register, the RDY bit in the

Status Register is cleared.

1

3

1

f_ADC

=

¥

¥ f_MOD

8 ¥ SF

where:

f

_ADCis the ADC output update rate.

_MODis the Modulator Clock Frequency = 32.768 kHz.

SF is the decimal value written to the SF Register.

–18–

REV. A

AD7709

CONFIGURING THE AD7709

2. Initialize the AD7709 by configuring the following registers:

The four user-accessible registers on the AD7709 are accessed via

the serial interface. Communication with any of these registers

is initiated by first writing to the Communications Register. The

AD7709 begins converting on power-up without the need to

write to the registers. The default conditions are used, i.e., the

AD7709 operates at a 19.79 Hz update rate that offers 50 Hz

and 60 Hz rejection.

a)Filter Register to configure the update rate for the channel.

The AD7709 must be placed in standby mode before the

Filter Register can be written to.

b)Configuration Register to select the input channel to be

converted, its input range, and reference. This register is also

used to configure internal current sources, power switches,

and I/O port.

Figure 10 outlines a flow diagram of the sequence used to

configure all registers after a power-up or reset on the AD7709.

The flowchart shows two methods of determining when it is valid

to read the data register. The first method is hardware polling of

the RDY pin and the second method involves software interrogation

of the RDY bit in the status register. The flowchart details all the

necessary programming steps required to initialize the ADC and

read data from the ADC channel following a power-on or reset.

The steps can be broken down as follows:

Both of these operations consist of a write to the Communi-

cations Register to specify the next operation as a write to a

specified register. Data is then written to this register. When

each sequence is complete, the ADC defaults to waiting for

another write to the Communications Register to specify the

next operation.

3. When configuration is complete, the user needs to determine

when it is valid to read the data from the data register. This is

accomplished either by polling the RDY pin (hardware polling)

or by interrogating the RDY bit in the STATUS register

(software polling). Both are shown in Figure 10.

1. Configure and initialize the microcontroller or microproces-

sor serial port.

SOFTWARE

POLLING

HARDWARE

POLLING

START

POLL RDY PIN

POWER-ON-RESET FOR AD7709

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

STATUS REGISTER (WRITE 40H TO REGISTER)

CONFIGURE AND INITIALIZE ꢂC/ꢂP SERIAL PORT

NO

READ STATUS REGISTER

RDY

LOW?

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A WRITE TO THE

FILTER REGISTER (WRITE 22H TO REGISTER)

YES

NO

RDY = 1

WRITE TO FILTER REGISTER CONFIRMING

THE REQUIRED UPDATE RATE

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

DATA REGISTER (WRITE 43H TO REGISTER)

YES

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A WRITE TO THE

CONFIGURATION REGISTER

READ 16-BIT DATA RESULT

WRITE TO COMMUNICATIONS REGISTER SETTING

UP NEXT OPERATION TO BE A READ FROM THE

DATA REGISTER (WRITE 43H TO REGISTER)

(WRITE 01H TO REGISTER)

WRITE TO CONFIGURATION REGISTER TO SELECT

THE INPUT CHANNEL, INPUT RANGE, AND

REFERENCE. CURRENT SOURCES AND I/O PORT

CAN ALSO BE CONFIGURED

YES

ANOTHER

READ

READ 16-BIT DATA RESULT

YES

ANOTHER

READ

READ DATA FROM OUTPUT REGISTER

YES

CHANNEL

CHANGE

NO

HARDWARE

POLLING

SOFTWARE

POLLING

YES

CHANNEL

CHANGE

NO

END

Figure 10. Flowchart for Initializing and Reading Data from the AD7709

REV. A

–19–

AD7709

DIGITAL INTERFACE

The serial interface can be reset by exercising the RESET input

on the part. It can also be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the AD7709 DIN line for

at least 32 serial clock cycles, the serial interface is reset. This

ensures that in 3-wire systems, if the interface gets lost either via

a software error or by some glitch in the system, it can be reset

back to a known state. This state returns the interface to where

the AD7709 is expecting a write operation to its Communications

Register. This operation resets the contents of all registers to their

power-on reset values.

As previously outlined, AD7709 programmable functions are

controlled using a set of on-chip registers. Data is written to

these registers via the part’s serial interface and read access to

the on-chip registers is also provided by this interface. All com-

munications to the part must start with a write operation to the

Communications Register. After power-on or reset, the device

expects a write to its Communications Register. The data writ-

ten to this register determines whether the next operation to the

part is a read or a write operation and also determines to which

register this read or write operation occurs. Therefore, write

access to any of the other registers on the part starts with a write

operation to the Communications Register followed by a write

to the selected register. A read operation from any other register

on the part (including the output data register) starts with a

write operation to the Communications Register followed by a

read operation from the selected register.

Some microprocessor or microcontroller serial interfaces have a

single serial data line. In this case, it is possible to connect the

AD7709 DOUT and DIN lines together and connect them to the

single data line of the processor. A 10 kW pull-up resistor should

be used on this single data line. In this case, if the interface gets

lost, because the read and write operations share the same line,

the procedure to reset it back to a known state is somewhat

different than previously described. It requires a read operation

of 24 serial clocks followed by a write operation where a Logic 1

is written for at least 32 serial clock cycles to ensure that the

serial interface is back into a known state.

The AD7709 serial interface consists of five signals: CS, SCLK,

DIN, DOUT, and RDY. The DIN line is used for transferring

data into the on-chip registers, while the DOUT line is used for

accessing data from the on-chip registers. SCLK is the serial

clock input for the device, and all data transfers (either on DIN

or DOUT) take place with respect to this SCLK signal. The

RDY line is used as a status signal to indicate when data is ready

to be read from the AD7709 data register. RDY goes low when a

new data-word is available in the output register. It is reset high

when a read operation from the data register is complete. It also

goes high prior to the updating of the output register to indicate

when not to read from the device to ensure that a data read is not

attempted while the register is being updated. CS is used to select

the device. It can be used to decode the AD7709 in systems where

a number of parts are connected to the serial bus.

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7709 flexible serial interface allows for easy interface to

most microcomputers and microprocessors. The flowchart of

Figure 10 outlines the sequence that should be followed when

interfacing a microcontroller or microprocessor to the AD7709.

Figures 11, 12, and 13 show some typical interface circuits. The

serial interface on the AD7709 is capable of operating from just

three wires and is compatible with SPI interface protocols. The

3-wire operation makes the part ideal for isolated systems where

minimizing the number of interface lines minimizes the number

of opto-isolators required in the system. The serial clock input is

a Schmitt-triggered input to accommodate slow edges from

opto-couplers. The rise and fall times of other digital inputs to

the AD7709 should be no longer than 1 ms.

Figures 2 and 3 show timing diagrams for interfacing to the

AD7709 with CS used to decode the part. Figure 3 is for a read

operation from the AD7709 output shift register while Figure 2

shows a write operation to the input shift register. It is possible

to read the same data twice from the output register even though

the RDY line returns high after the first read operation. Care must

be taken, however, to ensure that the read operations have been

completed before the next output update is about to take place.

Some of the registers on the AD7709 are 8-bit registers, which

facilitates easy interfacing to the 8-bit serial ports of microcon-

trollers. The Data Register on the AD7709 is 16 bits and the

Configuration Register is 24 bits, but data transfers to these

registers can consist of multiple 8-bit transfers to the serial port

of the microcontroller. DSP processors and microprocessors

generally transfer 16 bits of data in a serial data operation. Some

of these processors, such as the ADSP-2105, have the facility to

program the amount of cycles in a serial transfer. This allows the

user to tailor the number of bits in any transfer to match the

register length of the required register in the AD7709.

The AD7709 serial interface can operate in 3-wire mode by

tying the CS input low. In this case, the SCLK, DIN, and

DOUT lines are used to communicate with the AD7709, and

the status of the RDY bit can be obtained by interrogating the

Status Register. This scheme is suitable for interfacing to

microcontrollers. If CS is required as a decoding signal, it can

be generated from a port bit. For microcontroller interfaces, it is

recommended that the SCLK idles high between data transfers.

Even though some of the registers on the AD7709 are only 8 bits

in length, communicating with two of these registers in successive

write operations can be handled as a single 16-bit data transfer if

required. For example, if the Filter Register is to be updated, the

processor must first write to the Communications Register (say-

ing that the next operation is a write to the Filter Register), and

then write 8 bits to the Filter Register. If required, this can all be

done in a single 16-bit transfer because once the eight serial

clocks of the write operation to the Communications Register

have been completed, the part immediately sets itself up for a

write operation to the Filter Register.

The AD7709 can also be operated with CS used as a frame

synchronization signal. This scheme is suitable for DSP interfaces.

In this case, the first bit (MSB) is effectively clocked out by CS

since CS would normally occur after the falling edge of SCLK

in DSPs. The SCLK can continue to run between data transfers

provided the timing numbers are obeyed.

–20–

REV. A

AD7709

AD7709-to-68HC11 Interface

V

DD

8XC51

AD7709

Figure 11 shows an interface between the AD7709 and the

68HC11 microcontroller. The diagram shows the minimum

(3-wire) interface with CS on the AD7709 hardwired low. In this

scheme, the RDY bit of the Status Register is monitored to

determine when the Data Register is updated. An alternative

scheme, which increases the number of interface lines to four, is to

monitor the RDY output line from the AD7709. The monitoring

of the RDY line can be done in two ways. First, RDY can be

connected to one of the 68HC11 port bits (such as PC0), which

is configured as an input. This port bit is then polled to determine

the status of RDY. The second scheme is to use an interrupt

driven system, in which case the RDY output is connected to

the IRQ input of the 68HC11. For interfaces that require

control of the CS input on the AD7709, one of the port bits of the

68HC11 (such as PC1), which is configured as an output, can

be used to drive the CS input.

V

DD

RESET

10kꢅ

P3.0

DOUT

DIN

SCLK

P3.1

CS

Figure 12. AD7709-to-8XC51 Interface

The 68HC11 is configured in the master mode with its CPOL

bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the

68HC11 is configured like this, its SCLK line idles high between

data transfers. The AD7709 is not capable of full-duplex opera-

tion. If the AD7709 is configured for a write operation, no data

appears on the DOUT lines even when the SCLK input is active.

Similarly, if the AD7709 is configured for a read operation, data

presented to the part on the DIN line is ignored even when

SCLK is active.

The second scheme is to use an interrupt-driven system, in which

case the RDY output is connected to the INT1 input of the

8XC51. For interfaces that require control of the CS input on

the AD7709, one of the port bits of the 8XC51 (such as P1.1),

which is configured as an output, can be used to drive the CS

input. The 8XC51 is configured in its Mode 0 serial interface

mode. Its serial interface contains a single data line. As a result,

the DOUT and DIN pins of the AD7709 should be connected

together with a 10 kW pull-up resistor. The serial clock on the

8XC51 idles high between data transfers. The 8XC51 outputs

the LSB first in a write operation, while the AD7709 expects the

MSB first so the data to be transmitted has to be rearranged

before being written to the output serial register. Similarly, the

AD7709 outputs the MSB first during a read operation while

the 8XC51 expects the LSB first. Therefore, the data read into

the serial buffer needs to be rearranged before the correct data

word from the AD7709 is available in the accumulator.

V

DD

V

68HC11

AD7709

DD

SS

RESET

SCLK

DOUT

SCK

MISO

ADSP-2103/

ADSP-2105

V

DD

AD7709

DIN

MOSI

RESET

CS

RFS

CS

TFS

Figure 11. AD7709-to-68HC11 Interface

AD7709-to-8051 Interface

DR

DT

DOUT

DIN

An interface circuit between the AD7709 and the 8XC51 microcon-

troller is shown in Figure 12. The diagram shows the minimum

number of interface connections with CS on the AD7709 hard-

wired low. In the case of the 8XC51 interface, the minimum

number of interconnects is just two. In this scheme, the RDY

bit of the Status Register is monitored to determine when the

Data Register is updated. The alternative scheme, which increases

the number of interface lines to three, is to monitor the RDY output

line from the AD7709. The monitoring of the RDY line can be

done in two ways. First, RDY can be connected to one of the

8XC51 port bits (such as P1.0) which is configured as an input.

This port bit is then polled to determine the status of RDY.

SCLK

Figure 13. AD7709-to-ADSP-2103/ADSP-2105 Interface

AD7709-to-ADSP-2103/ADSP-2105 Interface

Figure 13 shows an interface between the AD7709 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface shown,

the RDY bit of the Status Register is again monitored to

determine when the Data Register is updated. The alternative

scheme is to use an interrupt-driven system, in which case the

REV. A

–21–

AD7709

ANALOG 5V

SUPPLY

RDY output is connected to the IRQ2 input of the ADSP-2103/

ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105

is set up for alternate framing mode. The RFS and TFS pins of

the ADSP-2103/ADSP-2105 are configured as active low

outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK,

is also configured as an output. The CS for the AD7709 is

active when either the RFS or TFS outputs from the ADSP-2103/

ADSP-2105 are active. The serial clock rate on the ADSP-2103/

ADSP-2105 should be limited to 3 MHz to ensure correct opera-

tion with the AD7709.

0.1ꢂF

10ꢂF

5V

V

DD

RESET

CS

IOUT1

IOUT2

CHIP

SELECT

AD7709

RECEIVE

(READ)

AIN1

DOUT

SERIAL DATA

(WRITE)

AIN2

DIN

CIRCUIT DESCRIPTION

SERIAL

CLOCK

AIN3/P3

AIN4/P4

SCLK

The AD7709 is a ⌺-⌬ A/D converter with on-chip digital filtering,

intended for the measurement of wide dynamic range, low

frequency signals such as those in weigh scale, pressure, tempera-

ture, industrial control, or process control applications. It employs

a ⌺-⌬ conversion technique to realize up to 16 bits of no-missing-

codes performance. The ⌺-⌬ modulator converts the sampled

input signal into a digital pulse train whose duty cycle contains

the digital information. A Sinc³programmable low-pass filter is

then employed to decimate the modulator output data stream to

give a valid data conversion result at programmable output rates

from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping

scheme is also employed to minimize ADC offset and offset and

gain drift errors. The channel is buffered and can be programmed

for one of eight input ranges from ± 20 mV to ± 2.56 V. The input

channels can be configured for either fully differential inputs or

pseudo-differential input channels via the CH2, CH1, and CH0

bits in the Configuration Register. Buffering the input channel

allows the part to handle significant source impedances on the

analog input, allowing R/C filtering (for noise rejection or RFI

reduction) to be placed on the analog inputs if required. These

input channels are intended for converting signals directly from

sensors without the need for external signal conditioning. Other

functions contained on-chip that augment the operation of the

ADC include software configurable current sources, switchable

reference inputs, and low-side power switches.

P1/SW1

P2/SW2

AINCOM

REFIN1(–)

REFIN1(+)

REFIN2(+)

ANALOG 5V

SUPPLY

10ꢂF

XTAL1

XTAL2

32.768kHz

CRYSTAL

0.1ꢂF

REFIN2(–)

V

OUT

IN

GND

PWRGND

AD780/

REF195

GND

Figure 14. Basic Connection Diagram

The output of the ADC multiplexer feeds into a high impedance

input stage of the buffer amplifier. As a result, the ADC inputs can

handle significant source impedances and are tailored for direct

connection to external resistive-type sensors like strain gauges or

Resistance Temperature Detectors (RTDs).

The basic connection diagram for the AD7709 is shown in

Figure 14. An AD780/REF195, precision 2.5 V reference, provides

the reference source for the part. A quartz crystal or ceramic

resonator provides the 32.768 kHz master clock source for the

part. In some cases, it will be necessary to connect capacitors on

the crystal or resonator to ensure that it does not oscillate at over-

tones of its fundamental operating frequency. The values of

capacitors will vary depending on manufacturer specifications.

The absolute input voltage range on the ADC inputs when buff-

ered (AIN1 to AIN4) is restricted to a range between GND +

100 mV and V_DD– 100 mV. Care must be taken in setting up

the common-mode voltage and input voltage range so that these

limits are not exceeded; otherwise, there will be a degradation in

linearity and noise performance.

The absolute input voltage range on the ADC inputs when

unbuffered (AINCOM) includes the range between GND – 30 mV to

V_DD+ 30 mV as a result of being unbuffered. The negative abso-

lute input voltage limit does allow the possibility of monitoring

small true bipolar signals with respect to GND.

Analog Input Channels

The main ADC has five associated analog input pins (labeled

AIN1 to AIN4 and AINCOM) that can be configured as two

fully differential input channels (AIN1–AIN2 and AIN3–AIN4)

or four pseudo-differential input channels (AIN1–AINCOM,

AIN2–AINCOM, AIN3–AINCOM, and AIN4–AINCOM).

Channel selection bits CH2, CHI, and CH0 in the Configuration

Register detail the different configurations. When the analog input

channel is switched, the settling time of the part must elapse

before a new valid word is available from the ADC.

–22–

REV. A

AD7709

Programmable Gain Amplifier

The output from the buffer on the ADC is applied to the input

of the on-chip programmable gain amplifier (PGA). The PGA

can be programmed through eight different unipolar and bipolar

ranges. The PGA gain range is programmed via the range bits

in the Configuration Register. With an external 2.5 V reference

applied, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV,

0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to

640 mV, 0 V to 1.28 V, and 0 to 2.56 V, while bipolar ranges

are 20 mV, 40 mV, 80 mV, 160 mV, 320 mV, 640

mV, 1.28 V, and 2.56 V. These are the ranges that should

appear at the input to the on-chip PGA.

MUX

AIN1

AIN2

AIN(+)

FULLY DIFFERENTIAL

AIN2

ADC CHANNEL

AIN(–)

AIN3

AIN4

FULLY DIFFERENTIAL

AIN4

Figure 16. Fully Differential Mode of Operation

Typical matching across ranges is shown in Figure 15. Here, the

ADC is configured in fully differential, bipolar mode with an

external 2.5 V reference, while an analog input voltage of just

greater than 19 mV is forced on its analog inputs. The ADC

continuously converts the dc voltage at an update rate of 5.35 Hz,

i.e., SF = FFh. A total of 800 conversion results are gathered.

The first 100 results gathered with the ADC operating in the

20 mV. The ADC range is then switched to 40 mV and 100

more results are gathered, and so on, until the last 100 samples

are gathered with the ADC configured in the 2.5 V range. From

Figure 15, the variation in the sample mean through each range,

i.e., the range matching, is seen to be on the order of 2 µV.

PSEUDO-DIFFERENTIAL

MUX

INPUT

AIN1

AIN2

AIN1

AIN1/AINCOM

AIN(+)

AIN2

AIN2/AINCOM

ADC CHANNEL

AIN3

AIN(–)

AIN3/AINCOM

AIN4

AIN4/AINCOM

AINCOM

PSEUDO-DIFFERENTIAL

INPUT

Figure 17. Pseudo-Differential Mode of Operation

19.372

19.371

19.370

19.369

For example, if AIN(–) is 2.5 V and the ADC is configured for

an analog input range of 0 mV to 20 mV, the input voltage range

on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and

the AD7709 is configured for an analog input range of 1.28 V,

the analog input range on the AIN(+) input is 1.22 V to 3.78 V

(i.e., 2.5 V 1.28 V). Bipolar or unipolar options are chosen by

programming the UNI bit in the Configuration Register. This

programs the ADC for either unipolar or bipolar operation.

Programming for either unipolar or bipolar operation does not

change any of the input signal conditioning; it simply changes

the data output coding.

19.368

19.367

19.366

19.365

19.364

Data Output Coding

When the ADC is configured for unipolar operation, the output

coding is natural (straight) binary with a zero differential input

voltage resulting in a code of 000 . . . 000, a midscale voltage

resulting in a code of 100 . . . 000, and a full-scale input voltage

resulting in a code of 111 . . . 111. The output code for any analog

input voltage on the ADC can be represented as follows:

0

100

200

300

400

500

600

700

800

SAMPLE COUNT

ADC RANGE

Figure 15. ADC Range Matching

Bipolar/Unipolar Configuration

AIN × GAIN × 2^N

The analog inputs on the AD7709 can accept either unipolar or

bipolar input voltage ranges. Bipolar input ranges do not imply that

the part can handle negative voltages with respect to system

GND. Unipolar and bipolar signals on the AIN(+) input on

the ADC are referenced to the voltage on the respective AIN(–)

input. AIN(+) and AIN(–) refer to the signals seen by the

modulator that come from the output of the multiplexer, as shown

in Figures 16 and 17.

(

)

Code =

1.024 ×V

(

)

REF

where:

AIN is the analog input voltage.

GAIN is the PGA gain, i.e., 1 on the 2.56 V range and 128 on

the 20 mV range.

N = 16.

REV. A

–23–

AD7709

When the ADC is configured for bipolar operation, the coding

is offset binary with a negative full-scale voltage resulting in a

code of 000 . . . 000, a zero differential voltage resulting in a

code of 100 . . . 000, and a positive full-scale voltage resulting in

a code of 111 . . . 111. The output code from the ADC for any

analog input voltage can be represented as follows:

because the application is ratiometric. If the AD7709 is used

in a nonratiometric application, a low noise reference should be

used. Recommended reference voltage sources for the AD7709

include the AD780, REF43, and REF192. It should also be noted

that the reference inputs provide a high impedance, dynamic load.

Because the input impedance of each reference input is dynamic,

resistor/capacitor combinations on these inputs can cause dc gain

errors, depending on the output impedance of the source that is

driving the reference inputs. Reference voltage sources like those

recommended above (e.g., AD780) will typically have low output

impedances and are therefore tolerant to having decoupling capaci-

tors on the REFIN(+) without introducing gain errors in the system.

Deriving the reference input voltage across an external resistor, as

shown in Figure 18, will mean that the reference input sees a

significant external source impedance. External decoupling on the

REFIN pins would not be recommended in this type of circuit

configuration.

Code = 2^{N -1}

where:

¥

AIN ¥ GAIN / 1.024 ¥ V

+ 1

(

)

(

[

REF

]

AIN is the analog input voltage.

GAIN in the PGA gain, i.e., 1 on the ± 2.56 V range and 128

on the ± 20 mV range.

N = 16.

Excitation Currents

The AD7709 also contains three software configurable constant

current sources. IEXC1 and IEXC2 provide 200 mA of current

while IEXC3 provides 25 mA of current. All source current

from V_DDis directed to either the IOUT1 or IOUT2 pins of the

device. These current sources are controlled via bits in the

Configuration Register. The configuration bits enable the current

sources, and they can be configured to source current individually

to both pins or a combination of currents, i.e., 400 mA, 225 mA, or

425 mA to either of the selected output pins. These current sources

can be used to excite external resistive bridge or RTD sensors.

Reset Input

The RESET input on the AD7709 resets all the logic, the digital

filter, and the analog modulator while all on-chip registers are reset

to their default state. RDY is driven high and the AD7709 ignores

all communications to any of its registers while the RESET

input is low. When the RESET input returns high, the AD7709

operates with its default setup conditions and it is necessary to

set up all registers after a RESET command.

Power-Down Mode

Crystal Oscillator

Loading 0 to the STBY bit in the ADC Communications Register

places the AD7709 in device power-down mode. The AD7709

retains the contents of all its on-chip registers (including the data

register) while in power-down mode.

The AD7709 is intended for use with a 32.768 kHz watch crys-

tal. A PLL internally locks onto a multiple of this frequency to

provide a stable 4.194304 MHz clock for the ADC. The modu-

lator sample rate is the same as the crystal oscillator frequency.

The device power-down mode does not affect the digital interface,

but it does affect the status of the RDY pin. Putting the AD7709

into power-down mode will reset the RDY line high. Placing the

part in power-down mode reduces the total current to 26 mA

typical when the part is operated at 5 V with the oscillator running

during power-down mode. With the oscillator shut down, the total

I_DDis 1.5 mA typical at 3 V and 6.5 mA typical at 5 V.

The start-up time associated with 32.768 kHz crystals is typically

300 ms. The OSCPD bit in the Communications Register can

be used to prevent the oscillator from powering down when the

AD7709 is placed in power-down mode. This avoids having to

wait 300 ms after exiting power-down to start a conversion at the

expense of raising the power-down current.

Reference Input

Grounding and Layout

The AD7709 has a fully differential reference input capability

for the channel. On the channel, the reference inputs can be

REFIN1(+) and REFIN1(–) or REFIN2(+) and REFIN2(–).

They provide a differential reference input capability. The

common-mode range for these differential inputs is from GND

to V_DD. The reference input is unbuffered and therefore

excessive R-C source impedances will introduce gain errors.

The nominal reference voltage, V_REF, ((REFIN1(+)

– REFIN1(–) or (REFIN2(+) – REFIN2(–)), for specified

operation is 2.5 V, but the AD7709 is functional with reference

voltages from 1 V to V_DD. In applications where the excitation

(voltage or current) for the transducer on the analog input also

drives the reference voltage for the part, the effect of the low

frequency noise in the excitation source will be removed

Since the analog inputs and reference inputs on the ADC are

differential, most of the voltages in the analog modulator are

common-mode voltages. The excellent common-mode rejection

of the part will remove common-mode noise on these inputs.

The digital filter will provide rejection of broadband noise on

the power supply, except at integer multiples of the modulator

sampling frequency. The digital filter also removes noise from

the analog and reference inputs, provided these noise sources do

not saturate the analog modulator. As a result, the AD7709 is

more immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD7709 is so high, and the noise levels from the AD7709 so

low, care must be taken with regard to grounding and layout.

–24–

REV. A

AD7709

The printed circuit board that houses the AD7709 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. A minimum etch

technique is generally best for ground planes as it gives the best

shielding.

system designer to achieve a much higher level of resolution because

noise performance of the AD7709 is significantly better than that

of integrating ADCs.

The on-chip PGA allows the AD7709 to handle an analog input

voltage range as low as 10 mV full scale with V_REF= 1.25 V. The

differential inputs of the part allow this analog input range to

have an absolute value anywhere between GND + 100 mV and

V_DD– 100 mV. It allows the user to connect the transducer

directly to the input of the AD7709. The programmable gain

front end on the AD7709 allows the part to handle unipolar

analog input ranges from 0 mV to 20 mV and 0 V to 2.5 V

and bipolar inputs of ± 20 mV to ± 2.5 V. Because the part oper-

ates from a single supply, these bipolar ranges are with respect

to a biased-up differential input.

It is recommended that the AD7709 GND pin be tied to the

AGND plane of the system. In any layout, it is important that the

user keep in mind the flow of currents in the system ensuring

that the return paths for all currents are as close as possible to

the paths the currents took to reach their destinations. Avoid

forcing digital currents to flow through the AGND sections of

the layout.

The PWRGND pin is tied internally to GND on the AD7709.

The PWRGND pad internally has a resistance of less than 50 mW

to the PWRGND pin, while the resistance back to the GND pad

is less than 3 W. This means that 19.5 mA of the maximum speci-

fied current (20 mA) will flow to PWRGND with the remaining

0.5 mA flowing to GND. PWRGND and GND should be tied

together at the AD7709, and it is important to minimize the

resistance on the ground return lines.

Pressure Measurement

One typical application of the AD7709 is pressure measurement.

Figure 18 shows the AD7709 used with a pressure transducer,

the BP01 from Sensym. The pressure transducer is arranged in

a bridge network and gives a differential output voltage between

its OUT(+) and OUT(–) terminals. With rated full-scale pres-

sure (in this case 300 mmHg) on the transducer, the differential

output voltage is 3 mV/V of the input voltage (i.e., the voltage

between its IN(+) and IN(–) terminals).

Avoid running digital lines under the device since these will

couple noise onto the die. The analog ground plane should be

allowed to run under the AD7709 to prevent noise coupling.

The power supply lines to the AD7709 should use as wide a trace as

possible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board, and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other, which will reduce the effects of

feedthrough through the board. A microstrip technique is by far the

best, but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

Assuming a 5 V excitation voltage, the full-scale output range

from the transducer is 15 mV. The excitation voltage for the

bridge can be used to directly provide the reference for the ADC

as the reference input range includes the supply. Alternatively, a

suitable resistor divider can be implemented that allows the full

dynamic range of the input to be utilized in this application.

This implementation is fully ratiometric, so variations in the

excitation voltage do not introduce errors in the system. Choosing

resistor values of 10 kW and 6 kW as per Figure 18 gives a 1.875 V

reference voltage for the AD7709 when the excitation voltage is 5 V.

EXCITATION VOLTAGE = 5V

Good decoupling is important when using high resolution ADCs.

The supply should be decoupled with 10 mF tantalum in parallel

with 0.1 mF capacitors to GND. To achieve the best from these

decoupling components, they have to be placed as close as possible;

chips should be decoupled with 0.1 mF ceramic capacitors to DGND.

IN+

10kꢅ

V

DD

OUT+

OUT–

AIN1

AIN2

IN–

REFIN1(+)

REFIN2(–)

6kꢅ

APPLICATIONS

The AD7709 provides a low cost, high resolution, analog-to-digital

function. Because the analog-to-digital function is provided by a

⌺-⌬ architecture, it makes the part more immune to noisy

environments, making it ideal for use in sensor measurement and

industrial and process control applications. Given the architecture

used in the AD7709, where the signal chain is chopped and the

device is factory-calibrated at final test, field calibration is not

needed due to the extremely low offset and gain drifts exhibited

by this converter. It also provides a programmable gain amplifier

and a digital filter. Thus, it provides far more system-level func-

tionality than off-the-shelf integrating ADCs without the

disadvantage of having to supply a high quality integrating

capacitor. In addition, using the AD7709 in a system allows the

AD7709

P1

GND

PWRGND

Figure 18. Pressure Measurement Using the AD7709

Using the part with a programmed gain of 128 results in the

full-scale input span of the AD7709 being 15 mV, which corre-

sponds with the output span from the transducer.

REV. A

–25–

AD7709

A second key advantage to using the AD7709 in transducer-based

applications is that the on-chip low-side power switch can be fully

utilized in low power applications. The low-side power switch is

connected in series with the cold side of the bridge. In normal

operation, the switch is closed and measurements can be taken

from the bridge. In applications where power is a concern, the

AD7709 can be put into low power mode, substantially reducing

the power burned in the application. In addition to this, the power

switch can be opened while in low power mode, thus avoiding

the unnecessary burning of power in the front end transducer.

When taken back out of power-down, and the power switch is

closed, the user should ensure that the front end circuitry is fully

settled before attempting a read from the AD7709.

Temperature Measurement

The AD7709 is also useful in temperature measurement appli-

cations. Figure 20 shows an RTD temperature measurement

application.

5V

V

AD7709

DD

REFIN(–)

XTAL1

REFIN(+)

IOUT1

R

RL1

REF

XTAL2

6.25kꢅ

200ꢂA

IOUT2

AIN1

The circuit in Figure 19 shows a method that utilizes three

pseudo-differential input channels on the AD7709 to temperature-

compensate a pressure transducer.

RL2

DRDY

SCLK

DIN

RTD

AIN2

CONTROLLER

5V

RL3

RL4

DOUT

CS

R

CM

V

DD

IOUT1

GND

PWRGND

I1

I2

Figure 20. 4-Wire RTD Temperature Measurement

Using the AD7709

REFIN(+)

In this application, the transducer is an RTD (Resistive Tem-

perature Device), a PT100. The arrangement is a 4-lead RTD

configuration. There are voltage drops across the lead resistances

RL1 and RL4, but these simply shift the common-mode voltage.

There is no voltage drop across lead resistances RL2 and RL3

since the input current to the AD7709 is very low, looking into a

high input impedance buffer. R_CMis included to shift the analog

input voltage to ensure that it lies within the common-mode

range (GND + 100 mV to V_DD– 100 mV) of the ADC. In the

application shown, the on-chip 200 mA current source provides

the excitation current for the PT100 and also generates the reference

voltage for the AD7709 via the 6.25 kW resistor. Variations in

the excitation current do not affect the circuit since both the

input voltage and the reference voltage vary ratiometrically with the

excitation current. However, the 6.25 kW resistor must have a low

temperature coefficient to avoid errors in the reference voltage

over temperature.

6.25kꢅ

REFIN(–)

AIN2

IN(+)

IN(–)

XTAL1

XTAL2

AD7709

OUT(+)

AIN1

OUT(–)

PRESSURE

BRIDGE

AINCOM

AIN3

GND

250ꢅ

Figure 19. Temperature-Compensating a Pressure

Transducer

In this application, pseudo-differential input channel AIN1/

AINCOM is used to measure the bridge output while pseuo-

differential channels AIN2/AINCOM and AIN3/AINCOM

measure the voltage across the bridge. The voltage measured

across the bridge will vary proportionally with temperature,

and the delta in this voltage can be used to temperature-

compensate the output of the pressure bridge.

–26–

REV. A

AD7709

Figure 21 shows a further enhancement to the circuit shown in

Figure 20. Generally, dc excitation has been accepted as the

normal method of exciting resistive based sensors like RTDs in

temperature measurement applications.

3-Wire RTD Configurations

To fully optimize a 3-wire RTD configuration, two identically

matched current sources are required. The AD7709, which

contains two well matched 200 mA current sources, is ideally

suited to these applications. One possible 3-wire configuration

using the AD7709 is shown in Figure 22.

V

DD

EMF1

IOUT1

IOUT2

5V

I1

200ꢂA

V

DD

RESISTIVE

TRANSDUCER

IOUT1

XTAL1

XTAL2

BUF

AND

PGA

200ꢂA

AIN1

AIN2

REFIN(+)

REFIN(–)

EMF2

MUX1

6.25kꢅ

AIN3

AIN4

A

RL1

P1

P2

AIN1

AIN2

REFIN(+)

DRDY

RTD

RL2

AD7709

SCLK

DIN

R

REF

IOUT2

REFIN(–)

CONTROLLER

RL3

DOUT

CS

200ꢂA

R

CM

Figure 21. Low Resistance Measurement

GND

With dc excitation, the excitation current through the sensor

must be large enough so that the smallest temperature/resis-

tance change to be measured results in a voltage change that

is larger than the system noise, offset, and drift of the system.

The purpose of switching the excitation source is to eliminate

dc-induced errors. DC errors (EMF1 and EMF2) due to para-

sitic thermocouples produced by differential metal connections

(solder and copper track) within the circuit are also eliminated

when using this switching arrangement. This excitation is a

form of synchronous detection where the sensor is excited with

an alternating excitation source and the ADC measures infor-

mation only in the same phase as the excitation source.

AD7709

Figure 22. 3-Wire RTD Configuration Using the AD7709

In this 3-wire configuration, the lead resistances will result in

errors if only one current source is used since the 200 mA will flow

through RL1, developing a voltage error between AIN1 and AIN2.

In the scheme outlined below, the second RTD current source

is used to compensate for the error introduced by the 200 mA

flowing through RL1. The second RTD current flows through

RL2. Assuming that RL1 and RL2 are equal (the leads would

normally be of the same material and of equal length) and that

IOUT1 and IOUT2 match, the error voltage across RL2 equals

the error voltage across RL1 and no error voltage is developed

between AIN1 and AIN2. Twice the voltage is developed across RL3

but, since this is a common-mode voltage, it will not introduce

errors. R_CMis included so the current flowing through the

combination of RL3 and R_CMdevelops enough voltage that the

The switched polarity current source is developed using the

on-chip current sources and external phase control switches (A

and A) driven by AD7709 logic outputs P1 and P2. During the

conversion process, the AD7709 takes two conversion results,

one on each phase. During Phase 1, the on-chip current source is

directed to IOUT1 and flows top to bottom through the sensor

and switch controlled by A. In Phase 2, the current source is

directed to IOUT2 and flows in the opposite direction through

the sensor and through switch controlled by A. In all cases, the

current flows in the same direction through the reference resistor

to develop the reference voltage for the ADC. All measurements

are ratiometrically derived. The results of both conversions are

combined within the microcontroller to produce one output

measurement representing the resistance or temperature of the

transducer. For example, if the RTD output during Phase 1 is

10 mV, a 1 mV circuit-induced dc error exists due to parasitic

thermocouples, the ADC measures 11 mV. During the second

phase, the excitation current is reversed and the ADC measures

–10 mV from the RTD and again sees 1 mV dc error, giving an

ADC output of –9 mV during this phase. These measurements

are processed in the controller (11 mV – (–9 mV)/2 = 10 mV),

thus removing the dc-induced errors within the system.

analog input voltage seen by the AD7709 is within the common

mode range of the ADC. The reference voltage for the AD7709

is also generated using one of these matched current sources.

-

This reference voltage is developed across the 6.25 kW resistor

as shown, and applied to the differential reference inputs of the

AD7709. This scheme ensures that the analog input voltage span

remains ratiometric to the reference voltage. Any errors in the

analog input voltage due to the temperature drift of the RTD

current source is compensated for by the variation in the reference

voltage. The typical drift matching between the two RTD current

sources is less than 20 ppm/∞C. The voltage on either I_OUTpin

can go to within 0.6 V of the V_DDsupply.

The AD7709 also includes a 25 mA current source that can be used

along with the two 200 mA current sources for V_BEmeasurement

where a 17:1 ratio is required from the current sources.

In the circuit shown in Figure 20, the resistance measurement is

made using ratiometric techniques. Resistor R_REF, which develops

the ADC reference, must be stable over temperature to prevent

reference-induced errors in the measurement output.

REV. A

–27–

AD7709

Smart Transmitters

amount of current available to power the transmitter is as low as

3.5 mA. Figure 23 shows a block diagram of a smart transmitter

that includes the AD7709.

Smart transmitters are another key design-in area for the AD7709.

The ⌺-⌬ converter, single-supply operation, 3-wire interface

capabilities, and small package size are all of benefit in smart

transmitters. Here, the entire smart transmitter must operate

from the 4–20 mA loop. Tolerances in the loop mean that the

Not shown in Figure 23 is the isolated power source required to

power the front end.

DN25D

3.3V

0.01␮F

10␮F

0.1␮F

10␮F

1.25V

V

REF OUT1

REF OUT2

BOOST

V

LV

DD

CC

AIN1

AIN2

0.01␮F

VARIABLES

COMP

DRIVE

REF IN

REFIN(+)

REFIN(–)

4.7␮F

AIN3

AIN4

0.1␮F

V

CC

1k⍀

CLOCK

LATCH

DATA

MICROCONTROLLER

GND

1000pF

AD7709

AD421

C2

CS

DOUT

SCLK

LOOP

POWER

LOOP

RTN

COM

C1

DIN

C3

GND

Figure 23. Smart Transmitter Employing the AD7709

–28–

REV. A

AD7709

OUTLINE DIMENSIONS

24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8ꢃ

0ꢃ

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AD

REV. A

–29–

AD7709

Revision History

Location

Page

3/03—Data Sheet changed from REV. 0 to REV. A.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change to Communications Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Changes to Table VIII. Filter Register Bit Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

–30–

REV. A

–31–

–32–


型号：	AD7709BRUZ-REEL7
厂家：	ADI
描述：	16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port 光电二极管转换器
文件：	总33页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7709BRUZ-REEL7 [ADI]

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