AD7709_技术文档

PRELIMINARY TECHNICAL DATA

16-Bit Sigma Delta ADC with Current Sources,

a

Preliminary Technical Data

SwitchableReferenceInputsandI/OPort

AD7709

FEATURES

G E NE R AL D E S C R IP T IO N

16-BIT SINGLE CHANNEL SIGMA DELTA-ADC

Factory Calibrated (field calibration not required)

Output settles in one conversion cycle (single conver

sion m ode)

Program m able Gain Front End

16-bit No Missing Codes

13-bit Pk-Pk Resolution @ 20Hz, 20m V Range

16-bit Pk-PK Resolution @ 20Hz, 2.56V Range

INTERFACE

T he AD7709 is a complete analog front-end for low

frequency measurement applications. T he AD7709

contains a 16-bit sigma delta ADC with PGA and can be

configured as 2 fully-differential input channels or 4

pseudo-differential input channels. Inputs signal ranges

from 20mV to 2.56V can be directly converted using the

AD7709. T hese signals can be converted directly from a

transducer without the need for signal conditioning. Other

on-chip features include three software configurable

current sources, switchable reference inputs, low side

power switches and a 4-bit digital I/O port.

Three-Wire Serial

SPI^TM, QSPI^TM, MICROWIRE^TMand DSP Com patible

Schm itt Trigger on SCLK

T he device operates from a 32kHz crystal with an on-

board PLL generating the required internal operating

frequency. T he output data rate from the part is software

programmable. T he pk-pk resolution from the part varies

with the programmed gain and output data rate.

POWER

Specified for Single 3V and 5V operation

Norm al : 2m A @ 3V

Pow erdow n : 20uA (32kHz Crystal Running)

On-Chip Functions

T he part operates from a single +3V or +5V supply.

When operating from +3V supplies, the power dissipation

for the part is XmW. T he AD7709 are housed in a 24-

pin SOIC and T SSOP packages.

Rail-to-Rail Input Buffer and PGA

Sw itchable Reference Inputs

3 Configurable Current Sources

Low Side Pow er Sw tches

Digital I/ O Port

APPLICATIONS

Industrial Process Control

Instrum entation

FUNC TIO NAL BLO C K D IAGRAM

REFIN2(+) REFIN1(+)

REFIN2(-) REFIN1(-)

XTAL1 XTAL2

VDD

Pressure Transducers

Portable Instrum entation

OSC

&

.

I2

I3

I1

PLL

IOUT 1

IOUT 2

DOUT

DIN

SERIAL

INTERFACE

&

CONTROL

LOGIC

AIN1

AIN2

16-BIT

Σ−∆ ADC

BUF

PGA

SCLK

CS

MUX

AIN3 / P3

AIN4 / P4

RDY

RESET

AINCOM

AD7709

VDD

I/O PORT

GND

PWRGND

SW1/P1 SW2/P2

®

SPIand QSPI are a Registered Trademark of Motorola Inc.

REV. PrA January 2001

® MICROWIRE is a Registered Trademark of National Semiconductor Corp.

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

World Wide Web Site: http:/ / w w w.analog.com

Analog Devices, Inc., 2001

Fax: 781/ 326-8703

PRELIMINARY TECHNICAL DATA

(V = +3V or +5.0V , REFIN(+) = +2.5V; REFIN(-) = 0V;

XTAL1/XTAL2 = 32 kHz Crystal;

All specifications T_MINto T_MAXunless otherwise noted.)

1

DD

AD7709-SPECIFICATIONS

P ARAME TE R

B Gr ade

Units

Test Conditions

Output Update Rate

5.4

105

H z min.

H z max.

0.021H z (0.732msec.) increments

N o M issing Codes

Resolution

16

13

16

bits min.

bits pk-pk

+20mV range, 20H z Update Rate

+2.56V range, 20H z Update Rate

Output Noise and Update Rates

Integral Nonlinearity

See T ables Below in ADC Description

15

ppm of FSR max.

Offset Error

T BD

10

T BD

1

Offset Error Drift Vs T emp

Offset Error Drift Vs T ime

Gain Error

Gain Error Drift Vs T emp

Gain Error Drift Vs T ime

Power Supply Rejection(PSR)

nV/°C typ.

nV/1000 H ours typ.

ppm/°C typ.

ppm/1000 H ours typ.

T BD

90

dB min.

Input Range = ±20mV

Input Range = ±2.56V

90

C ommon M ode Rejection(C M R)

On AIN

90

dB min.

At DC, Range = ±20mV

At DC, Range = ±2.56V

At DC, Range = ±20mV

At DC, Range = ±2.56V

On AIN

On REFIN

Analog Input Current

DC Bias Current

DC Bias Current Drift

DC Offset Current

DC Offset Current Drift

1

nA max.

nA typ.

T BD

REF EREN C E IN PU T S (REF IN 1& REF IN 2)

Normal Mode

50Hz/60Hz Rejection

60

T BD

+ 2.5V

+ 1

V_DD

dB min.

µA typ.

nom .

V min.

V max.

V min.

V max.

Reference DC Input Current

REFIN(+) to REFIN(-) Voltage

REFIN(+) to REFIN(-) Range

REFIN referes to both REFIN1 and REFIN2

REFIN Common Mode Range

G N D -30m V

V

_{D D}+30mV

REFIN Common Mode

50/60Hz Rejection

T BD

dB min.

ANALO G INP UTS

Normal Mode 50H z/60H z Rejection

Common Mode 50/60Hz Rejection

60

90

dB min.

50/60Hz ±1Hz , 20Hz Update Rate

50/60Hz ±1Hz, Range = ±20mV

50/60Hz ±1Hz, Range = ±2.5V

Differential Input Voltage Ranges

± REF IN /G AIN

V nom.

REFIN refers to both REFIN1 and

REF IN 2.

REF IN = REF IN (+ )-REF IN (-)

GAIN =1to 128.

Pseudo-Differential Input Voltage Ranges

0V to REFIN /GAIN V nom.

Full-scale Range Matching

Absolute Ain Voltage Limits

Buffered Inputs

5

uV typ.

G N D + 50m V

_DD-50mV

G N D -30m V

_{D D}+30mV

V min.

V max

Vm in

V

Unbuffered Inputs

V

Vm ax

REV. PrA J anuary 2001

–2–

PRELIMINARY TECHNICAL DATA

AD7709

P ARAMETER

B Grade

Units

Test Conditions

LO G IC IN PU T S

All Inputs Except SCLK and XT AL1

V_INL, Input Low Voltage

V_INH, Input High Voltage

0.8

0.4

2.0

V max.

V min.

V_DD= 5V

V_DD= 3V

V_DD= 3V or 5V

SCLK Only (Schmitt T riggered Input)

V_{T (+)}

V_{T (-)}

1.4/3

V min/V max V_DD= 5V

V min/V max V_DD= 3V

0.8/1.4

0.4/0.85

0.95/2.5

0.4/1.1

0.4/0.85

V_{T (+)-}V_{T (-)}

V_{T (+)}

V_{T (-)}

V_{T (+)-}V_{T (-)}

XT AL1 Only

V

_INL, Input Low Voltage

0.8

3.5

0.4

2.5

± 10

10

V max.

V min.

V max.

V min.

µA max.

pF typ.

V_DD= 5V

V_DD= 3V

V_IN= 0V or V_DD

All Digital Inputs

_INH, Input High Voltage

_INL, Input Low Voltage

_INH, Input High Voltage

Input Currents

Input Capacitance

LOG IC OU T PU T S (Excluding XT AL2)

V

_OH, Output High Voltage

_OL, Output Low Voltage

_OH, Output High Voltage

_OL, Output Low Voltage

V_DD- 0.6

0.4

4

0.4

± 10

Binary

Offset Binary

V min.

V max.

V min.

V max.

uA max.

pF typ.

V_DD= 3V, I_SOURCE= 100µA

V_DD= 3V, I_SINK= 100µA

V_DD= 5V, I_SOURCE= 200µA

V_DD= 5V, I_SINK= 1.6mA

Floating State Leakage Current

Floating State Output Capacitance

Data Output Coding

U nipolar M ode

Bipolar M ode

EXC IT AT IO N C U RREN T SO U RC ES

I1 and I2 Output Current

I3 Output Current

200

25

± 10

20

± 1

1

T BD

AV_DD-0.5

µA nom.

% typ.

ppm/°C typ.

%

ppm/°C typ.

nA/V max.

V max.

Initial T olerance at 25°C

D rift

Initial Current Matching at 25°C

D rift M atching

Matching between I1 and I2

V_DD= 5V±10%

Line Regulation (V_DD

Load Regulation

)

Output C ompliance

Low-Side Power Switches (SW1 and SW2)

Ron

5

7

20

Ω typ

mA max

V_DD= 5V

V_DD= 3V

Per Switch

Allowable Current

SYST EM C ALIBRAT IO N

Full-Scale C alibration Limit

Zero-Scale C alibration Limit

Input Span

1.05 X FS

-1.05 X FS

0.8 X FS

2.1 X FS

V max.

V min.

V max.

ST ART UP T IM E

From Power-On

500

1

msec typ.

msec. typ.

From Idle Mode

From Power-D own M ode

500

Osc. powered down

P O WER REQ U IREM EN T S

P ower Supply Voltages

V_DD- GND

2.7/3.6

4.5/5.5

V min/max

V_DD= 3V nom.

V_DD= 5V nom.

REV. PrA January 2001

–3–

PRELIMINARY TECHNICAL DATA

AD7709

P ARAMETER

B Grade

Units

Test Conditions

P ower Supply Cur r ents

V_DDCurrent (Normal Mode)

T BD

m A

V_DD=3V

V_DD=5V

V_DDCurrent (Idle Mode)

T BD

m A

V_DD=3V

V_DD=5V

V_DDCurrent (Power-Down Mode)

20

30

µA max.

V_DD=3V, 32.768kH z Osc. Running

V_DD=5V, 32.768kH z Osc. Running

NOTES

¹TemperatureRange-40°C to+85°C

2

3

4

REV. PrA J anuary 2001

–4–

PRELIMINARY TECHNICAL DATA

AD7709

AB SO LUT E M AXIM UM RAT ING S ¹

(T _A= +25°C unless otherwise noted)

O U T LINE D IM E NS IO NS

24-lead plastic SO IC (R-24)

V_{D D}to GN D .............................................-0.3V to +7V

Analog Input Voltage to GND...........-0.3V to V_DD+0.3V

Reference Input Voltage to GND.......-0.3V to V_DD+0.3V

AIN /REFIN C urrent (Indefinite)...........................30mA

Digital Input Voltage to GND...........-0.3V to V_DD+0.3V

Digital Output Voltage to GND........-0.3V to V_DD+0.3V

PWRG N D to GN D ...............................-0.3V to +0.3V

Operating T emperature Range..................-40°C to 85°C

Storage T emperature Range....................-65°C to 150°C

Junction T emperature........................................+ 150°C

PAC KAG E Power D issipation........................T BD mW

θ_JAT hermal Impedance..................................90°C /W

Lead T emperature, Soldering

0.6141 (15.60)

0.5985 (15.20)

24

13

1

12

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

x 45¡

0.0098 (0.25)

Vapor Phase (60sec)..................................+215°C

Infrared (15 sec).......................................+220°C

0.0500 (1.27)

0.0157 (0.40)

8¡

0¡

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0138 (0.35)

0.0091 (0.23)

¹Stressesabove those listed under "Absolute Maximum Ratings"maycause permanent

damage to the device. T hisisa stressratingonlyand functionaloperation ofthe device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods mayaffect device reliability.

24-lead plastic TSSO P (RU-24)

24-lead plastic

T SSO P (RU- 24)

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7709 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

O R D E R ING G U ID E

Model

Tem perature

Range

P ackage

Description

P ackage D rawing

Option

AD 7709BR

AD 7709BRU

-40°C to +85°C

SO IC

T SSO P

R-24

RU -24

REV. PrA January 2001

–5–

PRELIMINARY TECHNICAL DATA

AD7709

1,2

TIMINGCHARACTERISTICS (V = +3V±10%orV = +5V±10%;GND= 0V:X = 32.768kHz;InputLogic0= 0V,Logic1= V

DD

TAL

DD

unlessotherwisenoted)

Lim it at T_MIN, T_MAX

P ar am eter

(B Version)

Units

Conditions/Com m ents

t₁

t₂

32.768

50

kH z typ

ns min

Crystal Oscillator Frequency.

RESET Pulse Width

Read O per ation

t₃

t₄

0

ns min

RDY to CS Setup T ime

CS Falling Edge to SCLK Active Edge Setup

T ime³

4

t₅

0

ns min

ns max

ns min

ns max

ns min

SCLK Active Edge to Data Valid Delay³

V_DD= +4.5 V to +5.5 V

60

80

0

60

80

100

0

V_DD= +2.7 V to +3.6 V

4,5

t_5A

CS Falling Edge to Data Valid Delay³

V_DD= +4.5 V to +5.5 V

V_DD= +2.7 V to +3.6 V

SCLK H igh Pulse Width

SCLK Low Pulse Width

t₆

t₇

t₈

CS Rising Edge to SCLK Inactive Edge Hold

T ime³

6

t₉

10

80

100

ns min

ns max

Bus Relinquish T ime after SCLK Inactive Edge³

7

t₁₀

SCLK Active Edge to RDY High^3,

Wr ite O per ation

t₁₁

0

ns min

CS Falling Edge to SCLK Active Edge Setup

T ime³

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

30

25

100

0

ns min

Data Valid to SCLK Edge Setup T ime

Data Valid to SCLK Edge Hold T ime

SCLK H igh Pulse Width

SCLK Low Pulse Width

CS Rising Edge to SCLK Edge Hold T ime

NOTES

¹Sampletestedduringinitialreleasetoensurecompliance.Allinputsignalsarespecifiedwithtr= tf= 5ns(10%to90%ofV_DD)andtimedfromavoltagelevelof1.6V.

²SeeFigures1and2.

³SCLKactiveedgeisfallingedgeofSCLK.

⁴ThesenumbersaremeasuredwiththeloadcircuitofFigure3anddefinedasthetimerequiredfortheoutputtocrosstheV_OLorV_OHlimits.

⁵ThisspecificationonlycomesintoplayifCSgoeslowwhileSCLKislow.ItisrequiredprimarilyforinterfacingtoDSPmachines.

⁶Thesenumbersarederivedfromthemeasuredtimetakenbythedataoutputtochange0.5VwhenloadedwiththecircuitofFigure3.Themeasurednumberisthenextrapolatedbacktoremoveeffectsofchargingor

dischargingthe50pFcapacitor.Thismeansthatthetimesquotedinthetimingcharacteristicsarethetruebusrelinquishtimesofthepartandassuchareindependentofexternalbusloadingcapacitances.

⁷RDYreturnshighafterthefirstreadfromthedeviceafteranoutputupdate.Thesamedatacanbereadagain,ifrequired,whileRDYishigh,althoughcareshouldbetakenthatsubsequentreadsdonotoccurcloseto

thenextoutputupdate.

REV. PrA J anuary 2001

–6–

PRELIMINARY TECHNICAL DATA

AD7709

CS

t₁₆

t₁₁

t₁₄

SCLK

t₁₅

t₁₂

t₁₃

MSB

LSB

DIN

Figure1.WriteCycleTiming Diagram

RDY

t₁₀

t₃

CS

t₈

t₄

t₆

SCLK

t₇

t₆

t₅

t₉

t_5A

MSB

LSB

DOUT

Figure2.ReadCycleTimingDiagram

REV. PrA January 2001

–7–

PRELIMINARY TECHNICAL DATA

AD7709

PINCONFIGURATION

XTAL1

XTAL2

1

2

3

4

5

6

7

8

24

23

22

21

20

IOUT 1

IOUT 2

REFIN1(+)

REFIN1(-)

V

D D

AD7709

GND

DIN

AIN1

AIN 2

TOP VIEW

(Not to Scale)

19 DOUT

18

17

16

DRDY

CS

AIN3/P3

AIN4/P4

SCLK

9

AINCOM

10

REFIN2(+)

15

RESET

REFIN2(-)

P2/SW2

11

12

P1/SW1

PWRGND

14

13

P in Fu n c t io n De s c rip t io n

Pin No

Mnemonic

Function

1

IO U T 1

Output for internal excitation current sources. A single current source or any

combination of the internal current sources I1,I2 and I3 can be switched to this

output.

2

3

IO U T 2

Output for internal excitation current sources. A single current source or any

combination of the internal current sources I1,I2 and I3 can be switched to this

output.

Positive reference input. REFIN(+) can lie anywhere between V_DDand GND.

T he nominal reference voltage (REFIN(+)-REFIN(-)) is 2.5V but the part is

REF IN 1(+ )

functional with a reference range from 1V to V_DD

.

4

5

REF IN 1(-)

AIN 1

Negative reference input. T his reference input can lie anywhere between GND

and V_DD-1V.

Analog Input Channel 1. Programmable-gain analog input which can be used

as a pseudo-differential input when used with AINCOM or as the positive in-

put of a fully-differential input pair when used with AIN2. (see Communica-

tions Register section)

6

7

8

AIN 2

Analog Input Channel 2. Programmable-gain analog input which can be used

as a pseudo-differential input when used with AINCOM or as the negative

input of a fully-differential input pair when used with AIN1. (see Communica-

tions Register section)

AIN 3/P 3

AIN 4/P 4

Analog Input Channel 3 or Digital Port Bit. Programmable-gain analog input

which can be used as a pseudo-differential input when used with AINCOM or

as the positive input of a fully-differential input pair when used with AIN4.

T he second function of this bit is as a general purpose digital input bit.

Analog Input Channel 4 or digital port bit. Programmable-gain analog input

which can be used as a pseudo-differential input when used with AINCOM or

as the negative input of a fully-differential input pair when used with AIN3.

T he second function of this bit is as a general purpose digital input bit.

All analog inputs are referenced to this input when configured in pseudo-dif-

ferential input mode.

9

AI N C O M

10

REF IN 2(+ )

Positive reference input. REFIN2(+) can lie anywhere between V_DDand GND.

T he nominal reference voltage (REFIN2(+)-REFIN2(-)) is 2.5V but the part

is functional with a reference range from 1V to V_DD

.

REV. PrA J anuary 2001

–8–

PRELIMINARY TECHNICAL DATA

AD7709

11

12

13

14

15

16

REF IN 2(-)

P 2/SW2

P W R G N D

P 1/SW1

RESET

Negative reference input. T his reference input can lie anywhere between GND

and V_DD-1V.

P2 can act as a general purpose Input/Output bit referenced between V_DDand

GND or as a low-side power switch to PWRGND..

Ground point for the low-side power switches SW2 and SW1. PWRGND

must be tied to GND.

P1 can act as a general purpose Output bit referenced between V_DDand GND

or as a low-side power switch to PWRGND.

Digital input used to reset the ADC to its power-on-reset status. T his pin has

a weak pull-up internally to DV_DD

.

SC L K

Serial clock input for data transfers to and from the ADC. T he SCLK has a

schmitt triggered input making the interface suitable for opto-isolated applica-

tions. T he serial clock can be continuous with all data transmitted in a con-

tinuous train of pulses. Alternatively, it can be noncontinuous clock with the

information being transmitted to or from the AD7709 in smaller batches of

data.

17

18

CS

Chip Select Input. T his is an active low logic input used to select the

AD7709. CS can be used to select the AD7709 in systems with more than one

device on the serial bus or as a frame synchronisation signal in communicating

with the device. CS can be hardwired low allowing the AD7709 to be operated

in three-wire mode with SCLK, DIN and DOUT used to interface with the

device.

RDY is a logic low status output from the AD7709. RDY is low if the ADC

has valid data in its data register. T his output returns high on completion of a

read operation from the data register. If data is not read, RDY will return high

prior to the next update indicating to the user that a read operation should not

be initiated.

RDY

19

20

D O U T

D I N

Serial data output with serial data being read from the output shift register of

the ADC. T he output shift register can contain data from any of the on-chip

data, calibration or control registers.

Serial Data Input with serial data being written to the input shift register on

the AD7709. Data in this shift register is transferred to the control registers

within the ADC depending on the selection bits of the Communications regis-

ter.

21

22

23

24

G N D

V_DD

XT AL2

XT AL1

Ground Reference point for the AD7709.

Supply voltage, 3V or 5V nominal.

Output from the 32kH z crystal oscillator inverter.

Input to the 32kHz crystal oscillator inverter.

REV. PrA January 2001

–9–

PRELIMINARY TECHNICAL DATA

AD7709

AD C C IR C U IT INF O R M AT IO N

O verview

T he AD7709 incorporates an analog multiplexer with a Sigma-Delta ADC, on-chip programmable gain amplifier and

digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale,

strain-gauge, pressure transducer or temperature measurement applications. T he AD7709 offers 16-bit resolution. T he

AD7709 can be configured as 2 fully differential input channels or as 4 pseudo differential input channels referenced to

AINCOM. T he channel is buffered and can be programmed for one of 8 input ranges from +20mV to +2.56V. Buffering

the input channel means that the part can handle significant source impedances on the analog input and that R, C

filtering (for noise rejection or RFI reduction) can be placed on the analog inputs if required. T hese input channels are

intended to convert signals directly from sensors without the need for external signal conditioning. Other functions

contained on-chip that augment the operation of the ADC include software configurable current sources, switchable

reference inputs and low side power switches.

T he ADC employs a sigma-delta conversion technique to realize up to 16-bits of no missing codes performance. T he

sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital

information. A Sinc³programmable low pass filter is then employed to decimate the modulator output data stream to

give a valid data conversion result at programmable output rates from 5.35Hz (186.77mS) to 105.03Hz (9.52mS). A

Chopping scheme is also employed to minimize ADC channel offset errors. A block diagram of the ADC input channel

is shown in Figure 3 below.

f_chop

f_in

f_mod

f_chop

f_adc

Analog

Input

3

)

Digital

Output

1

---

2

1

∑

S-D

MOD0

∑

(

3 ×(8

× SF)

×

SF

8

3

Mux

Buffer

PGA

XOR

Sinc Filter

A _in+ V_os

A_in- V_os

Figure3.AD7709 ADC ChannelBlockDiagram

REV. PrA J anuary 2001

–10–

PRELIMINARY TECHNICAL DATA

AD7709

AD C NO ISE P E RF O RM ANC E

T ables I and II below show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest

0.5LSB) for some typical output update rates . T he numbers are typical and generated at a differential input voltage of

0V. T he output update rate is selected via the SF7-SF0 bits in the Filter Register. It is important to note that the peak-

to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit.T he

output noise comes from two sources. T he first is the electrical noise in the semiconductor devices (device noise) used in

the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization

noise is added. T he device noise is at a low level and is independant of frequency. T he quantization noise starts at an even

lower level but rises rapidly with increasing frequency to become the dominant noise source.T he numbers in the tables are

given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range

but the peak to peak resolution is now based on half the signal range which effectively means loosing 1 bit of resolution.

Table I. Typical O utput RMS Noise vs. Input Range and Update Rate for AD 7709

O utput RMS Noise in µV

SF

Wor d

D ata Update

Rate (H z)

Input Range

±20m V ±40m V ±80m V ±160m V ±320m V ±640m V ±1.24V

±2.56V

11.75

2.30

13

105.3

19.79

5.35

1.50

0.60

0.35

1.50

0.65

0.35

1.60

0.65

0.37

1.75

0.65

0.37

3.50

0.65

0.37

4.50

0.95

0.51

6.70

1.40

0.82

69

255

1.25

Table II. P eak-to-P eak Resolution vs. Input Range and Update Rate for AD 7709

P eak-to-P eak Resolution in Bits

SF

Wor d

D ata Update

Rate (H z)

Input Range

±20m V ±40m V ±80m V ±160m V ±320m V ±640m V ±1.24V

±2.56V

16

13

105.3

19.79

5.35

12

13

14

13

14

15

14

15

16

15

16

15

16

15.5

16

69

16

255

16

AD 7709 O N- C H IP RE G IST E RS

Both the AD7709 is controlled and configured via 4 on-chip registers as shown in figure 4 and described in more detail

in the following section. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state

unless otherwise stated.

Com m unications Register

DIN

OSC PD

STBY

0

A1

A0

W EN R/W

DOUT

Status Register

REGISTER

SELECT

DECODER

DIN

DOUT

Configuration Register(24-Bits)

DIN

DOUT

Filter Register

ADC Data Register

Figure4.AD7709On-ChipRegisters

REV. PrA January 2001

–11–

PRELIMINARY TECHNICAL DATA

AD7709

Com m unications Register - ( A1, A0= 0,0):

T he Communications Register is an 8-bit write-only register. All communications to the part must start with a write

operation to the Communications Register. T he data written to the Communications Register determines whether the

next operation is a read or write operation, the type of read operation and to which register this operation takes place.

For read or write operations, once the subsequent read or write operation to the selected register is complete, the inter-

face returns to where it expects a write operation to the Communications Register. T his is the default state of the inter-

face, and on power-up or after a RESET, the AD7709 is in this default state waiting for a write operation to the

Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock

cycles with DIN high, returns the AD7709 to this default state by resetting the part. T able III outlines the bit designa-

tions for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the

Communications Register. CR7 denotes the first bit of the data stream.

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN( 0)

R/W(0)

ST BY(0)

O SCP D (0)

0 (0)

0(0)

A1(0)

A(0)

Table III. Com m unications Register Bit D esignations

Bit

Location Mnem onic Description

C R7

WEN

Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications

Register actually takes place. If a 1 is written to this bit, the part will not clock on to subse-

quent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0

is written to the WEN bit, the next seven bits will be loaded to the Communications Register.

C R6

C R5

C R4

R /W

A zero in this bit location indicates that the next operation will be a write to a specified regis-

ter. A one in this position indicates that the next operation will be a read from the designated

register.

ST BY

O SC P D

Standby bit indication.

Set when its required to put the AD7709 in low power mode.

Clear to power up the AD7709.

Oscillator Power D own Bit.

If this bit is set, then placing the AD7709 in standby mode will stop the crystal oscillator reduc-

ing the power drawn by these parts to a minimum. T he oscillator will require 500ms to begin

oscillating when the ADC is taken out of standby mode.

If this bit is clear ed the oscillator is not shut off when the ADC is put into standby mode and

will not require the 500ms start-up time when the ADC is taken out of standby.

C R3

C R2

0

T his bit must be programmed with a logic 0 for correct operation.

C R1-C R0 A1-A0

Register Address Bits. T hese address bits are used to address the AD7709’s registers and are

outlined in table IV.

Table IV. AD7709 Register Selection Table

A1

A0

Register

0

1

0

1

0

1

Communications register during a write operation.

Status Register register during a read operation.

C onfiguration Register

Filter register

ADC Data Register

REV. PrA J anuary 2001

–12–

PRELIMINARY TECHNICAL DATA

AD7709

Status Register - (A1,A0=0,0; P ower -O n-Reset = 00H ex):

T he ADC Status Register is an 8-bit read-only register. T o access the ADC Status Register, the user must write to the

Communications Register selecting the next operation to be a read and load bits A1-A0 with 0,0. T able V outlines the

bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in

the Status Register. SR7 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset

default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RD Y(0)

0(0)

ERR (0)

0(0)

ST BY(0)

LO CK(0)

Table V. Status Register Bit D esignations

Bit

Location Mnem onic Description

SR7

RD Y

Ready bit for the ADC

Set when data is transferred to the ADC data register.

T he RDY bit is clear ed automatically a period of time before the data register is updated with a

new conversion result or after the ADC data register has been read.

SR6

SR5

SR4

SR3

0

Bit is automatically clear ed. Reserved for future use

T his bit is automatically clear ed. Reserved for future use

0

E RR

ADC Error Bit. T his qualifying bit is set at the same at the RDY bit.

When Set it indicates that the result written to the ADC data register has been clamped to all

zeros or all ones. Error sources include Overrange and loss of lock.

T his bit is Clear ed at the same time as the RDY bit.

SR2

SR1

0

T his bit is automatically clear ed. Reserved for future use

ST BY

Standby bit indication.

When Set it indicates that the AD7709 is in low power mode.

Clear ed when the ADC is powerd up.

SR0

L O C K

PLL lock status bit.

T his bit is SET if the PLL has locked onto the 32kHz crystal oscillator clock. T he ADC will

not start conversion till this bit has been set. If the LOCK bit subsequently goes low the ERR

bit will be set.

Configur ation Register (CO NFIG) :(A1,A0 = 0,1; P ower -O n-Reset = 000000H ex)

T he CONFIG Register is a 24-bit register from which data can either be read or to which data can be written. T his

register is used to select the input channel and configure the input range, excitation current sources and I/O port.T able

XIII outlines the bit designations for this register. CONFIG24 through CONFIG0 indicate the bit location, CONFIG

denoting the bits are in the Configuration Register. CONFIG24 denotes the first bit of the data stream. T he number in

brackets indicates the power-on/reset default status of that bit. A write to the CONFIG register has immediate effect and

does not reset the the ADCs. T hus , if a current source is switched while the ADC is converting the user will have to wait

for the fullsettling time of the sinc^3 filter before getting a fully settled output. T his equates to 4 outputs.

REV. PrA January 2001

–13–

PRELIMINARY TECHNICAL DATA

AD7709

C O N F IG 2 3

C O N F IG 2 2 C O N F IG 2 1 C O N F IG 2 0

P SW2(0) I3EN1 (0) I3EN1(0)

C O N F IG 1 9 C O N F IG 1 8 C O N F IG 1 7

I2EN1(0) I2EN0(0) I1EN1(0)

C O N F IG 1 6

P SW1(0)

I1EN0(0)

C O N F IG 1 5

C O N F IG 1 4 C O N F IG 1 3 C O N F IG 1 2

P 3D IG(0) P 2E N(0) P 1E N(0)

C O N F IG 1 1 C O N F IG 1 0 C O N F IG 9

C O N F IG 8

P 4D IG(0)

P 4D AT(0)

P 3D AT(0)

P 2D AT(0)

P 1D AT(0)

C O N F I G 7

C O N F I G 6 C O N F I G 5 C O N F I G 4

C H 1(0) C H 0(0)

C O N F I G 3 C O N F I G 2

UNI(0) RN2(0)

C O N F I G 1

C O N F I G 0

RE FSE L(0) C H 2(0)

RN1(0)

RN0(0)

Table VI. Configur ation Register Bit D esignations

Bit

Location

Bit

Mnem onic

Description

C O N F IG 23 P SW 1

Power Switch 1 Control bit.

Set by user to enable Power switch P1 to PWRGND.

Clear ed by user to enable use as a standard I/O pin.

When ADC is in standby mode the power switches are open.

C O N F IG 22 P SW 2

Power Switch 2 Control bit.

Set by user to enable Power switch P2 to PWRGND.

Clear ed by user to enable use as a standard I/O pin.

When ADC is in standby mode the power switches are open.

C O N F IG 2 1 I3EN 1

C O N F IG 2 0 I3EN 0

Current Source Enable Bits. Used in conjunction with bit I3EN0 to determine the function

of current source I3

Current Source Enable Bits. Used in conjunction with bit I3EN1 to determine the function

of current source I3

I3EN1

I3EN0

Function

0

1

0

1

0

1

Current Source OFF

Current Source Routed to IOUT 1 pin.

Current Source Routed to IOUT 2 pin.

Current Source Routed to GND

C O N F IG 1 9 I2EN 1

C O N F IG 1 8 I2EN 0

Current Source Enable Bits. Used in conjunction with bit I2EN0 to determine the function

of current source I2

Current Source Enable Bits. Used in conjunction with bit I2EN1 to determine the function

of current source I2

I2EN1

I2EN0

Function

0

1

0

1

0

1

Current Source OFF

Current Source Routed to IOUT 1 pin.

Current Source Routed to IOUT 2 pin.

Current Source Routed to GND

C O N F IG 1 7 I1EN 1

C O N F IG 1 6 I1EN 0

Current Source Enable Bits. Used in conjunction with bit I1EN0 to determine the function

of current source I3

Current Source Enable Bits. Used in conjunction with bit I1EN1 to determine the function

of current source I3

I1EN1

I1EN0

Function

0

1

0

1

0

1

Current Source OFF

Current Source Routed to IOUT 1 pin.

Current Source Routed to IOUT 2 pin.

Current Source Routed to GND

C O N F IG 1 5 P 4D IG

D igital Input Enable

Set by user to enable P4 as a digital input

Clear ed by user to configure as pin P4/AIN4 as analog input.

REV. PrA J anuary 2001

–14–

PRELIMINARY TECHNICAL DATA

AD7709

C O N F IG 1 4 P 3D IG

C O N F IG 1 3 P 2E N

C O N F IG 1 2 P 1E N

D igital Input Enable

Set by user to enable P3 as a digital input

Clear ed by user to configure as pin P3/AIN3 as analog input. T he default configuration is

analog input.

P2 digital output enable bit.

Set by user to enable P2 as a regular digital output pin.

Clear ed by user to tristate P2 output.

PSW2 takes presedance over P2EN.

P1 digital output enable bit.

Set by user to enable P1 as a regular digital output pin.

Clear ed by user to tristate P1 output.

PSW1 takes presedance over P1EN.

C O N F IG 1 1 P 4D AT

C O N F IG 1 0 P 3D AT

Digital input port data bit. P4DAT is read only and will return a 0 if P4DIG=0. If P4 is

enabled as a digital input then the read back value indicates the status of pin P4.

Digital input port data bit. P3DAT is read only and will return a 0 if P3DIG=0. If P3 is

enabled as a digital input then the read back value indicates the status of pin P3.

C O N F I G 9

C O N F I G 8

C O N F I G 7

P 2D AT

P 1D AT

R E F SE L

Digital output port data bit. P2 is digital output only. When the port is active as an output

(P2EN=1), then the value written to the this data bit appears at the output port. Reading

P2DAT will return what was last written to the P2DAT bit on the AD7709.

Digital output port data bit. P1 is digital output only. When the port is active as an output

(P1EN=1), then the value written to the this data bit appears at the output port. Reading

P1DAT will return what was last written to the P1DAT bit on the AD7709.

ADC reference input select.

Clear ed by user to select REFIN1(+) and REFIN1(-) as the ADC reference.

Set by user to select REFIN2(+) and REFIN2(-) as the ADC reference.

C O N F I G 6

C O N F I G 5

C O N F I G 4

C H 2

C H 1

C H 0

ADC Input Channel Selection bit. Used in conjunction with CH1 and CH0 as shown in

the analog input selection table.

ADC Input Channel Selection bit. Used in conjunction with CH2 and CH0 as shown in

the analog input selection table.

ADC Input Channel Selection bit. Used in conjunction with CH2 and CH2 as shown in

the analog input selection table.

CH 2

CH 1

CH 0

P ositive Input

AIN 1

AIN 2

AIN 3

AIN 4

AIN 1

AIN 3

AI N C O M

Negative Input

AI N C O M

AIN 2

Buffer

Positive Analog Input

0

1

0

1

0

1

0

1

0

1

0

1

0

Positive Analog Input

Positive and Negative Analog Inputs

AIN 4

AI N C O M

T he final column indicates if the analog inputs are buffered or unbuffered. T his determines the common mode

input range on each input. If the input is unbuffered (AINCOM) the common mode input includes GND.

C O N F I G 3

U N I

Unipolar/Bipolar Operation Selection Bit.

Set by user to enable unipolar operation with straight binary output coding i.e. zero differ-

ential input will result in 0000hex output and a fullscale differential input will result in

FFFF H ex output.

Clear ed by user to enable pseudo bipolar operation and offset binary coding, negative

fullscale differential input will result in an output code of 0000 Hex, zero differential in-

put will result in an output code of 8000Hex and a positive fullscale differential input will

result in an output code of FFFF Hex.

REV. PrA January 2001

–15–

PRELIMINARY TECHNICAL DATA

AD7709

C O N F I G 2

C O N F I G 1

C O N F I G 0

RN 2

RN 1

RN 0

Used in conjunction with RN1 and RN0 to select the analog input range.

Used in conjunction with RN2 and RN0 to select the analog input range.

Used in conjunction with RN2 and RN1 to select the analog input range.

RN2

RN1

RN0

Selected Main AD C Input Range (Vr ef=2.5V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

± 20m V

± 40m V

± 80m V

± 160m V

± 320m V

± 640m V

± 1.28V

± 2.56V

Filter Register :(A1,A0=1,0; P ower -O n-Reset = 00H ex)

T he Filter Register is an 8-bit register from which data can either be read or to which data can be written. T his register

determines the amount of averaging performed by the sinc filter. T able VII outlines the bit designations for the Filter

Register. FR7 through FR0 indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the

first bit of the data stream. T he number in brackets indicates the power-on/reset default status of that bit. T he number in

this register is used to set the decimation factor and thus the output update rate for the ADCs. T he filter register cannot

be written to by the user while the ADC is active. T he update rate is used for the ADC is calculated as follows :

f_adc

=

1

3

1

f_mod

X

8.SF

Wher e :

fadc =

fmod =

SF =

ADC Output Update Rate

Modulator Clock Frequency= 32.768KH z (Main and Aux ADC)

Decimal Value written to SF Register

F R7

SF7(0)

F R6

F R5

F R4

F R3

F R2

F R1

F R0

SF6(1)

SF5(0)

SF4(0)

SF3(0)

SF2(1)

SF1(0)

SF0(1)

Table VII. Filter Register Bit D esignations

T he allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (f_adc) and time

(t_adc) are shown in table XII below. It should also be noted that both ADC input channels are chopped to minimise offset

errors. T his means that the time for a single conversion or the time to the first conversion result is 2 X t_adc

.

SF (d ec)

S F ( h e x)

f_adc(H z)

105.3

t_adc(m s)

9.52

13

0D

45

69

19.79

50.34

255

FF

5.35

186.77

Table XII. Update Rate Vs SF Wor d.

AD C D ata Result Register (D ATA):(A1,A0=1,1; P ower -O n-Reset = 000000H ex)

T he conversion result for the selected ADC channel is stored in the ADC data register (DAT A). T his register is 16-bits

wide. T his is a read only register. On completion of a read from this register the RDY bit in the status register is cleared.

REV. PrA J anuary 2001

–16–

PRELIMINARY TECHNICAL DATA

AD7709

C O NF IG URING T H E AD 7709

On the AD7709 there are only four user accessable registers and these are configured via the serial interface. Communica-

tion with any of these registers is initiated by firstly writing to the Communications Register. T he AD7709 starts convert-

ing after a power up without the requiring any register to be written to. T he defaults conditions are used and the AD7709

operates at a 20Hz update rate offering 50 and 60Hz rejection.

Figure 5 outlines a flow diagram of the sequence used to configure the registers on the AD7709 following a power-up.

T he flowchart shows two methods of determining when its valid to read the data register. T he first method is hardware

polling of the RDY pin and the second method involves software interrogation of bits in the status and mode registers. The

flowchart details all the necessary programming steps required to initialize the ADC and read data from the selected ADC chan-

nel following a power-on or reset.The steps can be broken down as follows:

1. Configure and initialize the microcontroller or microprocessor serial port.

2. Initialize the AD7709 by configuring the following registers:

a)FILTER registers which determines the update rate. The AD7709 must be put into standby mode before writing to the

filter register.

b) CONFIGURATION register to select the input channel to be converted, its input range and reference. This register is

also used to configure the internal current sources, power switches and I/O port.

Both of these operations consist of a write to the communications register to specify the next operation as a write to a specified

register. Data is then written to this register. When each sequence is complete the ADC defaults to waiting for another write to

the communications register to specify the next operation.

3) When configuration is complete the user needs to determine when its valid to read the data from the data register. T his

is accomplished by either polling the RDY pin (hardware polling) or by interrogating the bits in the ST AT US register

(software polling). Both are shown in the following flowchart.

START

SOFTWARE POLLING

HARDWARE POLLING

POWER-ON/RESET FOR AD7709

POLL RDY PIN

CONFIGURE & INITIALIZE

C/ P SERIAL PORT

␮ ␮

WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT

OPERATION TO BE A READ FROM THE STATUS REGISTER

WRITE 40HEX TO COMMS REGISTER

WRITE TO COMMUNICATIONS REGISTER SELECTING

NEXT OPERATION TO BE A WRITE TO

THE FILTER REGISTER (WRITE 22HEX TO COMMS REG)

NO

RDY

LOW?

READ STATUS REGISTER

WRITE TO FILTER REGISTER TO CONFIGURE

THE REQUIRED UPDATE RATE.

NO

WRITE TO COMMUNICATIONS REGISTER SETTING UP

NEXT OPERATION TO BE A READ OF THE

RDY=1

DATA REGISTER (WRITE 43HEX TO COMMS REGISTER)

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

NEXT OPERATION TO BE A WRITE TO THE

CONFIGURATION REGISTER (WRITE 01Hex TO COMMS REG)

WRITE TO COMMUNICATIONS REGISTER SETTING UP

NEXT OPERATION TO BE A READ OF THE DATA

REGISTER. WRITE 43HEX TO COMMS REGISTER

READ16-BIT DATA RESULT

WRITE TO CONFIGURATION REGISTER TO SELECT INPUT

CHANNEL, INPUT RANGE AND REFERENCE. CURRENT

SOURCES AND I/O PORT CAN ALSO BE CONFIGURED

READ16-BIT DATA RESULT

YES

ANOTHER

READ?

NO

YES

ANOTHER

READ DATA FROM OUTPUT REGISTER

READ?

YES

CHANNEL

CHANGE

NO

HARDWARE

POLLING

NO

SOFTWARE

POLLING

YES

CHANNEL

CHANGE

NO

END

Figure5.FlowchartforConfiguringandreadingfromAD7709

REV. PrA January 2001

–17–


型号：	AD7709
厂家：	ADI
描述：	16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port 16位Σ-Δ型ADC，电流源，可切换基准电压输入和I / O端口
文件：	总17页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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