AD7715ACHIPS-3_技术文档

3 V/5 V, 450 ␮A

a

16-Bit, Sigma-Delta ADC

AD7715*

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Charge-Balancing ADC

16 Bits No Missing Codes

AV

DV

DD

REF IN(–) REF IN(+)

DD

0.0015% Nonlinearity

Programmable Gain Front End

Gains of 1, 2, 32 and 128

Differential Input Capability

Three-Wire Serial Interface

SPI™, QSPI™, MICROWIRE™ and DSP Compatible

Ability to Buffer the Analog Input

3 V (AD7715-3) or 5 V (AD7715-5) Operation

Low Supply Current: 450 ␮A max @ 3 V Supplies

Low-Pass Filter with Programmable Output Update

16-Lead SOIC/DIP/TSSOP

CHARGE BALANCING

A/D CONVERTER

SIGMA-DELTA

MODULATOR

DIGITAL

FILTER

AIN(+)

AIN(–)

BUFFER

PGA

A = 1–128

CLOCK

GENERATION

MCLK IN

MCLK OUT

SERIAL

INTERFACE

RESET

SCLK

CS

DIN

REGISTER BANK

DOUT

DRDY

AD7715

AGND

DGND

GENERAL DESCRIPTION

CMOS construction ensures very low power dissipation, and the

power-down mode reduces the standby power consumption to

50 µW typ. The part is available in a 16-lead, 0.3 inch-wide,

plastic dual-in-line package (DIP) as well as a 16-lead 0.3 inch-

wide small outline (SOIC) package and a 16-lead TSSOP package.

The AD7715 is a complete analog front end for low frequency

measurement applications. The part can accept low level input

signals directly from a transducer and outputs a serial digital

word. It employs a sigma-delta conversion technique to realize

up to 16 bits of no missing codes performance. The input signal

is applied to a proprietary programmable gain front end based

around an analog modulator. The modulator output is pro-

cessed by an on-chip digital filter. The first notch of this digital

filter can be programmed via the on-chip control register allow-

ing adjustment of the filter cutoff and output update rate.

PRODUCT HIGHLIGHTS

1. The AD7715 consumes less than 450 µA in total supply

current at 3 V supplies and 1 MHz master clock, making it

ideal for use in low-power systems. Standby current is less

than 10 µA.

The AD7715 features a differential analog input as well as a dif-

ferential reference input. It operates from a single supply (+3 V

or +5 V). It can handle unipolar input signal ranges of 0 mV to

+20 mV, 0 mV to +80 mV, 0 V to +1.25 V and 0 V to +2.5 V.

It can also handle bipolar input signal ranges of ±20 mV, ±80 mV,

±1.25 V and ±2.5 V. These bipolar ranges are referenced to

the negative input of the differential analog input. The AD7715

thus performs all signal conditioning and conversion for a single-

channel system.

2. The programmable gain input allows the AD7715 to accept

input signals directly from a strain gage or transducer remov-

ing a considerable amount of signal conditioning.

3. The AD7715 is ideal for microcontroller or DSP processor

applications with a three-wire serial interface reducing the

number of interconnect lines and reducing the number of

opto-couplers required in isolated systems. The part con-

tains on-chip registers which allow software control over

output update rate, input gain, signal polarity and calibration

modes.

The AD7715 is ideal for use in smart, microcontroller or DSP

based systems. It features a serial interface that can be config-

ured for three-wire operation. Gain settings, signal polarity and

update rate selection can be configured in software using the

input serial port. The part contains self-calibration and system

calibration options to eliminate gain and offset errors on the

part itself or in the system.

4. The part features excellent static performance specifications

with 16-bits no missing codes, ±0.0015% accuracy and low

rms noise (<550 nV). Endpoint errors and the effects of

temperature drift are eliminated by on-chip calibration op-

tions, which remove zero-scale and full-scale errors.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

*Protected by U.S. Patent No: 5,134,401.

See page 30 for data sheet index.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(AV_DD= +5 V, DV_DD= +3 V or +5 V, REF IN(+) = +2.5 V; REF IN(–) = AGND;

f_{CLK IN}= 2.4576 MHz unless otherwise noted. All specifications T_MINto T_MAXunless otherwise noted.)

AD7715-5–SPECIFICATIONS

Parameter

A Version¹

Unit

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

16

Bits min

Guaranteed by Design. Filter Notch ≤ 60 Hz

Depends on Filter Cutoffs and Selected Gain

Filter Notch ≤ 60 Hz

Output Noise

See Tables V to VIII

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift³

Bipolar Zero Error

±0.0015

See Note 2

0.5

See Note 2

0.5

See Note 2

0.5

See Note 2

0.5

% of FSR max

µV/°C typ

Bipolar Zero Drift³

Positive Full-Scale Error⁴

Full-Scale Drift^{3, 5}

Gain Error⁶

Gain Drift^{3, 7}

ppm of FSR/°C typ

% of FSR max

µV/°C typ

Bipolar Negative Full-Scale Error²

Bipolar Negative Full-Scale Drift³

±0.0015

1

0.6

Typically ±0.0004%

For Gains of 1 and 2

For Gains of 32 and 128

µV/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Input Common-Mode Rejection (CMR)

Normal-Mode 50 Hz Rejection⁸

Normal-Mode 60 Hz Rejection⁸

Common-Mode 50 Hz Rejection⁸

Common-Mode 60 Hz Rejection⁸

Common-Mode Voltage Range⁹

Absolute AIN/REF IN Voltage⁸

Specifications for AIN and REF IN Unless Noted

at DC. Typically 102 dB

90

98

150

dB min

V min to V max

V min

V max

V min

V max

nA max

pF max

For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f_NOTCH

AIN for BUF Bit of Setup Register = 0 and REF IN

150

AGND to AV_DD

AGND – 30 mV

AV_DD+ 30 mV

AGND + 50 mV

AV_DD– 1.5 V

1

Absolute/Common-Mode AIN Voltage⁹

BUF Bit of Setup Register = 1

AIN DC Input Current⁸

AIN Sampling Capacitance⁸

AIN Differential Voltage Range¹⁰

10

0 to +V_REF/GAIN¹¹nom

Unipolar Input Range (B/U Bit of Setup Register = 1)

Bipolar Input Range (B/U Bit of Setup Register = 0)

For Gains of 1 and 2

For Gains of 32 and 128

±1% for Specified Performance. Functional with

Lower V_REF

±V_REF/GAIN

GAIN × f_{CLK IN}/64

nom

AIN Input Sampling Rate, f_S

REF IN(+) – REF IN(–) Voltage

REF IN Input Sampling Rate, f_S

f

_{CLK IN}/8

+2.5

V nom

f_{CLK IN}/64

LOGIC INPUTS

Input Current

±10

µA max

All Inputs Except MCLK IN

V

_INL, Input Low Voltage

_INH, Input High Voltage

0.8

0.4

2.4

2.0

V max

V min

DV_DD= +5 V

DV_DD= +3.3 V

DV_DD= +5 V

MCLK IN Only

V

_INL, Input Low Voltage

_INH, Input High Voltage

0.8

0.4

3.5

2.5

V max

V min

DV_DD= +5 V

DV_DD= +3.3 V

DV_DD= +5 V

DV_DD= +3.3 V

V_INH, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT)

V_OL, Output Low Voltage

0.4

4.0

V max

V min

µA max

pF typ

I_SINK= 800 µA Except for MCLK OUT¹². DV_DD= +5 V

I_SINK= 100 µA Except for MCLK OUT¹². DV_DD= +3.3 V

I_SOURCE= 200 µA Except for MCLK OUT¹². DV_DD= +5 V

I_SOURCE= 100 µA Except for MCLK OUT¹². DV_DD= +3.3 V

V

_OL, Output Low Voltage

_OH, Output High Voltage

DV_DD– 0.6 V

±10

9

Binary

Offset Binary

Floating State Leakage Current

Floating State Output Capacitance¹³

Data Output Coding

Unipolar Mode

Bipolar Mode

–2–

REV. C

AD7715

(AV = +3 V, DV = +3 V, REF IN (+) = +1.25 V;

REF IN(–) = AGND; f_{CLK IN}= 2.4576 MHz unless otherwise noted. All specifications T_MINto T_MAXunless otherwise noted.)

AD7715-3–SPECIFICATIONS

DD

Parameter

A Version¹

Unit

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

16

Bits min

Guaranteed by Design. Filter Notch ≤ 60 Hz

Depends on Filter Cutoffs and Selected Gain

Filter Notch ≤ 60 Hz

Output Noise

See Tables IX to XII

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift³

Bipolar Zero Error

±0.0015

See Note 2

0.2

See Note 2

0.2

See Note 2

0.2

See Note 2

0.2

% of FSR max

µV/°C typ

Bipolar Zero Drift³

Positive Full-Scale Error⁴

Full-Scale Drift^{3, 5}

Gain Error⁶

Gain Drift^{3, 7}

ppm of FSR/°C typ

% of FSR max

µV/°C typ

Bipolar Negative Full-Scale Error²

Bipolar Negative Full-Scale Drift³

±0.003

1

0.6

Typically ±0.0004%

For Gains of 1 and 2

For Gains of 32 and 128

µV/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Input Common-Mode Rejection (CMR)

Normal-Mode 50 Hz Rejection⁸

Normal-Mode 60 Hz Rejection⁸

Common-Mode 50 Hz Rejection⁸

Common-Mode 60 Hz Rejection⁸

Common-Mode Voltage Range⁹

Absolute AIN/REF IN Voltage⁸

Specifications for AIN and REF IN Unless Noted

at DC. Typically 102 dB

90

98

150

dB min

V min to V max

V min

V max

V min

V max

For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × f_NOTCH

For Filter Notches of 20 Hz, 60 Hz, ± 0.02 × f_NOTCH

AIN for BUF Bit of Setup Register = 0 and REF IN

150

AGND to AV_DD

AGND – 30 mV

AV_DD+ 30 mV

AGND + 50 mV

AV_DD– 1.5 V

1

Absolute/Common-Mode AIN Voltage⁹

BUF Bit of Setup Register = 1

AIN DC Input Current⁸

nA max

pF max

nom

AIN Sampling Capacitance⁸

AIN Differential Voltage Range¹⁰

10

0 to +V_REF/GAIN¹¹

±V_REF/GAIN

GAIN × f_{CLK IN}/64

Unipolar Input Range (B/U Bit of Setup Register = 1)

Bipolar Input Range (B/U Bit of Setup Register = 0)

For Gains of 1 and 2

nom

AIN Input Sampling Rate, f_S

f

_{CLK IN}/8

For Gains of 32 and 128

REF IN(+) – REF IN(–) Voltage

REF IN Input Sampling Rate, f_S

+1.25

f_{CLK IN}/64

V nom

±1% for Specified Performance. Functional with Lower V_REF

LOGIC INPUTS

Input Current

±10

µA max

All Inputs Except MCLK IN

V

_INL, Input Low Voltage

_INH, Input High Voltage

0.8

2.0

V max

V min

MCLK IN Only

V

_INL, Input Low Voltage

0.4

2.5

V max

V min

V_INH, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT)

V_OL, Output Low Voltage

0.4

DV_DD– 0.6

±10

V max

V min

µA max

pF typ

I_SINK= 100 µA Except for MCLK OUT¹²

I_SOURCE= 100 µA Except for MCLK OUT¹²

V_OH, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance¹³

Data Output Coding

9

Binary

Offset Binary

Unipolar Mode

Bipolar Mode

–3–

REV. C

AD7715–SPECIFICATIONS

A

(AV_DD= +3 V to +5 V, DV_DD= +3 V to +5 V, REF IN(+) = +1.25 V (AD7715-3) or +2.5 V

(AD7715-5); REF IN(–) = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless otherwise noted. All specifications T_MINto T_MAXunless otherwise noted.)

Parameter

A Version

Unit

Conditions/Comments

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit¹⁴

(1.05 × V_REF)/GAIN

V max

GAIN Is the Selected PGA Gain (1, 2, 32 or 128)

Negative Full-Scale Calibration Limit¹⁴–(1.05 × V_REF)/GAIN V max

Offset Calibration Limit¹⁵

Input Span¹⁵

–(1.05 × V_REF)/GAIN V max

0.8 × V_REF/GAIN

(2.1 × V_REF)/GAIN

V min

V max

POWER REQUIREMENTS

Power Supply Voltages

AV_DDVoltage (AD7715-3)

AV_DDVoltage (AD7715-5)

DV_DDVoltage

+3 to +3.6

+4.75 to +5.25

+3 to +5.25

V

For Specified Performance

Power Supply Currents

AV_DDCurrent

AV_DD= 3.3 V or 5 V. Gain = 1 to 128 (f_{CLK IN}= 1 MHz) or

Gain = 1 or 2 (f_{CLK IN}= 2.4576 MHz)

0.27

0.6

mA max

Typically 0.2 mA. BUF Bit of Setup Register = 0

Typically 0.4 mA. BUF Bit of Setup Register = 1

AV_DD= 3.3 V or 5 V. Gain = 32 or 128 (f_{CLK IN}= 2.4576 MHz)¹⁶

Typically 0.3 mA. BUF Bit of Setup Register = 0

Typically 0.8 mA. BUF Bit of Setup Register = 1

Digital I/Ps = 0 V or DV_DD. External MCLK IN

Typically 0.15 mA. DV_DD= 3.3 V. f_{CLK IN}= 1 MHz

Typically 0.3 mA. DV_DD= 5 V. f_{CLK IN}= 1 MHz

Typically 0.4 mA. DV_DD= 3.3 V. f_{CLK IN}= 2.4576 MHz

Typically 0.6 mA. DV_DD= 5 V. f_{CLK IN}= 2.4576 MHz

0.5

1.1

mA max

DV_DDCurrent¹⁷

0.18

0.4

0.5

0.8

mA max

dB typ

Power Supply Rejection ¹⁸

See Note 19

Normal-Mode Power Dissipation¹⁷

AV_DD= DV_DD= +3.3 V. Digital I/Ps = 0 V or DV_DD. External MCLK IN

1.5

2.65

3.3

5.3

mW max BUF Bit = 0. All Gains 1 MHz Clock

mW max BUF Bit = 1. All Gains 1 MHz Clock

mW max BUF Bit = 0. Gain = 32 or 128 @ f_{CLK IN}= 2.4576 MHz

mW max BUF Bit = 1. Gain = 32 or 128 @ f_{CLK IN}= 2.4576 MHz

AV_DD= DV_DD= +5 V. Digital I/Ps = 0 V or DV_DD. External MCLK IN

mW max BUF Bit = 0. All Gains 1 MHz Clock

Normal-Mode Power Dissipation¹⁷

3.25

5

mW max BUF Bit = 1. All Gains 1 MHz Clock

6.5

9.5

20

mW max BUF Bit = 0. Gain = 32 or 128 @ f_{CLK IN}= 2.4576 MHz

mW max BUF Bit = 1. Gain = 32 or 128 @ f_{CLK IN}= 2.4576 MHz

Standby (Power-Down) Current²⁰

µA max

External MCLK IN = 0 V or DV_DD. Typically 10 µA. V_DD= +5 V

External MCLK IN = 0 V or DV_DD. Typically 5 µA. V_DD= +3.3 V

10

NOTES

¹Temperature Range as follows: A Version, –40°C to +85°C.

²A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the

temperature of interest.

³Recalibration at any temperature will remove these drift errors.

⁴Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

⁵Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

⁶Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error

for bipolar ranges.

⁷Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.

⁸These numbers are guaranteed by design and/or characterization.

⁹This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than A V_DD+ 30 mV or go more nega-

tive than AGND – 30 mV.

¹⁰The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-

tive than AV_DD+ 30 mV or go more negative than AGND – 30 mV.

11

V

= REF IN(+) – REF IN(–).

REF

¹²These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

¹³Sample tested at +25°C to ensure compliance.

¹⁴After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will

output all 0s.

¹⁵These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV_DD+ 30 mV or go more negative than AGND –

30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

¹⁶Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.

¹⁷When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV_DDcurrent and power dissipation will vary depending on

the crystal or resonator type (see Clocking and Oscillator Circuit section).

¹⁸Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB

with filter notches of 20 Hz or 60 Hz.

¹⁹PSRR depends on gain. Gain of 1: 85 dB typ; Gain of 2: 90 dB typ; Gains of 32 and 128: 95 dB typ.

²⁰If the external master clock continues to run in standby mode, the standby current increases to 50 µA typical. When using a crystal or ceramic resonator across the

MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or

resonator type (see Standby Mode section).

Specifications subject to change without notice.

–4–

REV. C

AD7715

(DV_DD= +3 V to +5.25 V; AV_DD= +3 V to +5.25 V; AGND = DGND = 0 V; f_CLKIN= 2.4576 MHz;

Input Logic 0 = 0 V, Logic 1 = DV_DD, unless otherwise noted)

TIMING CHARACTERISTICS^{1, 2}

Limit at T_MIN, T_MAX

Parameter

(A Version)

Unit

Conditions/Comments

3, 4

f_CLKIN

400

2.5

0.4 × t_{CLK IN}

500 × t_{CLK IN}

100

kHz min

MHz max

ns min

ns nom

ns min

Master Clock Frequency: Crystal Oscillator or Externally Supplied

for Specified Performance

Master Clock Input Low Time. t_{CLK IN}= 1/f_{CLK IN}

Master Clock Input High Time

DRDY High Time

RESET Pulsewidth

t_{CLK IN LO}

t_{CLK IN HI}

t₁

t₂

Read Operation

t₃

t₄

t₅

0

120

0

ns min

ns max

ns min

ns max

DRDY to CS Setup Time

CS Falling Edge to SCLK Rising Edge Setup Time

SCLK Falling Edge to Data Valid Delay

DV_DD= +5 V

DV_DD= +3.3 V

SCLK High Pulsewidth

5

80

100

0

10

60

t₆

t₇

t₈

SCLK Low Pulsewidth

CS Rising Edge to SCLK Rising Edge Hold Time

Bus Relinquish Time after SCLK Rising Edge

DV_DD= +5 V

6

t₉

100

DV_DD= +3.3 V

t₁₀

SCLK Falling Edge to DRDY High⁷

Write Operation

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

120

30

20

100

0

ns min

CS Falling Edge to SCLK Rising Edge Setup Time

Data Valid to SCLK Rising Edge Setup Time

Data Valid to SCLK Rising Edge Hold Time

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge to SCLK Rising Edge Hold Time

NOTES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of D V_DD) and timed from a voltage level of 1.6 V.

²See Figures 6 and 7.

³CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in Standby mode. If no clock is present in this case, the

device can draw higher current than specified and possibly become uncalibrated.

⁴The AD7715 is production tested with f_CLKINat 2.4576 MHz (1 MHz for some I_DDtests). It is guaranteed by characterization to operate at 400 kHz.

⁵These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁶These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is

then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and as such are independent of external bus loading capacitances.

⁷DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care

should be taken that subsequent reads do not occur close to the next output update.

Specifications subject to change without notice.

I

(800␮A AT DV = 5V

DD

SINK

100␮A AT DV = 3.3V)

DD

TO

OUTPUT

+1.6V

50pF

I

(200␮A AT DV = 5V

DD

SOURCE

100␮A AT DV = 3.3V)

DD

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

REV. C

–5–

AD7715

ABSOLUTE MAXIMUM RATINGS*

(T_A= +25°C unless otherwise noted)

PIN CONFIGURATION

DIP, SOIC and TSSOP

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND . . . . . –0.3 V to AV_DD+ 0.3 V

Reference Input Voltage to AGND . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Operating Temperature Range

SCLK

1

2

3

4

5

6

7

8

16 DGND

15 DV

MCLK IN

MCLK OUT

CS

DD

14

13

12

DIN

AD7715

TOP VIEW

(Not to Scale)

DOUT

DRDY

RESET

AV

DD

11 AGND

AIN(+)

AIN(–)

10

9

REF IN(–)

REF IN(+)

Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ORDERING GUIDE

AV_DD

Supply

Temperature

Range

Package

Options*

Model

AD7715AN-5

AD7715AR-5

AD7715ARU-5

AD7715AN-3

AD7715AR-3

AD7715ARU-3

AD7715AChips-5

AD7715AChips-3

EVAL-AD7715-5EB

EVAL-AD7715-3EB

5 V

3 V

5 V

3 V

5 V

3 V

–40°C to +85°C

Evaluation Board

N-16

R-16

RU-16

N-16

R-16

RU-16

Die

*N = Plastic DIP; R = SOIC RU = TSSOP.

REV. C

–6–

AD7715

PIN FUNCTION DESCRIPTION

Pin No. Mnemonic

Function

1

2

3

4

5

SCLK

Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from

the AD7715. This serial clock can be a continuous clock with all data transmitted in a continuous

train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmit-

ted to the AD7715 in smaller batches of data.

MCLK IN

MCLK OUT

CS

Master Clock signal for the device. This can be provided in the form of a crystal/resonator or exter-

nal clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alterna-

tively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left

unconnected. The part is specified with clock input frequencies of both 1 MHz and 2.4576 MHz.

When the master clock for the device is a crystal/resonator, the crystal/resonator is connected be-

tween MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT

provides an inverted clock signal. This clock can be used to provide a clock source for external

circuitry.

Chip Select. Active low Logic Input used to select the AD7715. With this input hardwired low, the

AD7715 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to inter-

face to the device. CS can be used to select the device in systems with more than one device on the

serial bus or as a frame synchronization signal in communicating with the AD7715.

RESET

Logic Input. Active low input which resets the control logic, interface logic, calibration coefficients,

digital filter and analog modulator of the part to power-on status.

6

7

8

9

AV_DD

Analog Positive Supply Voltage, +3.3 V nominal (AD7715-3) or +5 V nominal (AD7715-5).

Analog Input. Positive input of the programmable gain differential analog input to the AD7715.

Analog Input. Negative input of the programmable gain differential analog input to the AD7715.

AIN(+)

AIN(–)

REF IN(+)

Reference Input. Positive input of the differential reference input to the AD7715. The reference

input is differential with the provision that REF IN(+) must be greater than REF IN(–).

REF IN(+) can lie anywhere between AV_DDand AGND.

10

11

12

REF IN(–)

AGND

Reference Input. Negative input of the differential reference input to the AD7715. The REF IN(–)

can lie anywhere between AV_DDand AGND provided REF IN(+) is greater than REF IN(–).

Ground reference point for analog circuitry. For correct operation of the AD7715, no voltage on

any of the other pins should go more than 30 mV negative with respect to AGND.

DRDY

Logic Output. A logic low on this output indicates that a new output word is available from the

AD7715 data register. The DRDY pin will return high upon completion of a read operation of a full

output word. If no data read has taken place between output updates, the DRDY line will return

high for 500 × t_{CLK IN}cycles prior to the next output update. While DRDY is high, a read operation

should not be attempted or in progress to avoid reading from the data register as it is being updated.

The DRDY line will return low again when the update has taken place. DRDY is also used to indi-

cate when the AD7715 has completed its on-chip calibration sequence.

13

14

DOUT

DIN

Serial Data Output with serial data being read from the output shift register on the part. This output

shift register can contain information from the setup register, communications register or data regis-

ter depending on the register selection bits of the Communications Register.

Serial Data Input with serial data being written to the input shift register on the part. Data from this

input shift register is transferred to the setup register or communications register depending on the

register selection bits of the Communications Register.

15

16

DV_DD

Digital Supply Voltage, +3.3 V or +5 V nominal.

Ground reference point for digital circuitry.

DGND

REV. C

–7–

AD7715

Positive Full-Scale Overrange

TERMINOLOGY

Positive full-scale overrange is the amount of overhead available

to handle input voltages on AIN(+) input greater than AIN(–) +

V_REF/GAIN (for example, noise peaks or excess voltages due to

system gain errors in system calibration routines) without intro-

ducing errors due to overloading the analog modulator or over-

flowing the digital filter.

Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The end-

points of the transfer function are Zero-Scale (not to be confused

with Bipolar Zero), a point 0.5 LSB below the first code transition

(000 . . . 000 to 000 . . . 001) and Full-Scale, a point 0.5 LSB

above the last code transition (111 . . . 110 to 111 . . . 111). The

error is expressed as a percentage of full scale.

Negative Full-Scale Overrange

This is the amount of overhead available to handle voltages on

AIN(+) below AIN(–) –V_REF/GAIN without overloading the

analog modulator or overflowing the digital filter. Note that the

analog input will accept negative voltage peaks even in the uni-

polar mode provided that AIN(+) is greater than AIN(–) and

greater than AGND – 30 mV.

Positive Full-Scale Error

Positive Full-Scale Error is the deviation of the last code transi-

tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage

(AIN(–) + V_REF/GAIN –3/2 LSBs). It applies to both unipolar

and bipolar analog input ranges.

Offset Calibration Range

Unipolar Offset Error

In the system calibration modes, the AD7715 calibrates its

offset with respect to the analog input. The offset calibration

range specification defines the range of voltages that the

AD7715 can accept and still calibrate offset accurately.

Unipolar Offset Error is the deviation of the first code transition

from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-

ating in the unipolar mode.

Bipolar Zero Error

Full-Scale Calibration Range

This is the range of voltages that the AD7715 can accept in the

system calibration mode and still calibrate full scale correctly.

This is the deviation of the midscale transition (0111 . . . 111

to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–)

– 0.5 LSB) when operating in the bipolar mode.

Input Span

Gain Error

In system calibration schemes, two voltages applied in sequence

to the AD7715’s analog input define the analog input range.

The input span specification defines the minimum and maxi-

mum input voltages from zero to full scale that the AD7715 can

accept and still calibrate gain accurately.

This is a measure of the span error of the ADC. It includes full-

scale errors but not zero-scale errors. For unipolar input ranges

it is defined as (full scale error–unipolar offset error) while for

bipolar input ranges it is defined as (full-scale error–bipolar zero

error).

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal

AIN(+) voltage (AIN(–) – V_REF/GAIN + 0.5 LSB), when oper-

ating in the bipolar mode.

ON-CHIP REGISTERS

The part contains four on-chip registers which can be accessed by via the serial port on the part. The first of these is a Communica-

tions Register that decides whether the next operation is a read or write operation and also decides which register the read or write

operation accesses. All communications to the part must start with a write operation to the Communications Register. After power-

on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the

next operation to the part is a write or a read operation and also determines to which register this read or write operation occurs.

Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register fol-

lowed by a write to the selected register. A read operation from any register on the part (including the Communications Register itself

and the output data register) starts with a write operation to the Communications Register followed by a read operation from the

selected register. The Communication Register also controls the standby mode and the operating gain of the part. The DRDY status

is also available by reading from the Communications Register. The second register is a Setup Register that determines calibration

modes, filter selection and bipolar/unipolar operation. The third register is the Data Register from which the output data from the

part is accessed. The final register is a Test Register that is accessed when testing the device. It is advised that the user does not

attempt to access or change the contents of the test register as it may lead to unspecified operation of the device. The registers are

discussed in more detail in the following sections.

REV. C

–8–

AD7715

Communications Register (RS1, RS0 = 0, 0)

The Communications Register is an eight-bit register from which data can either be read or to which data can be written. All com-

munications to the part must start with a write operation to the Communications Register. The data written to the Communications

Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the

subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to

the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7715 is in this

default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a

write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715

returns to this default state. Table I outlines the bit designations for the Communications Register.

Table I. Communications Register

0/DRDY

ZERO

RS1

RS0

R/W

STBY

G1

G0

0/DRDY

For a write operation, a 0 must be written to this bit so that the write operation to the Communications Reg-

ister actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis-

ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits

will be loaded to the Communications Register. For a read operation, this bit provides the status of the

DRDY flag from the part. The status of this bit is the same as the DRDY output pin.

ZERO

For a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this will

result in unspecified operation of the device. For a read operation, a 0 will be read back from this bit location.

RS1– RS0

Register Selection Bits. These bits select to which one of four on-chip registers the next read or write opera-

tion takes place as shown in Table II along with the register size. When the read or write to the selected regis-

ter is complete, the part returns to where it is waiting for a write operation to the Communications Register.

It does not remain in a state where it will continue to access the selected register.

R/W

Read/Write Select. This bit selects whether the next operation is a read or write operation to the selected

register. A 0 indicates a write cycle as the next operation to the appropriate register, while a 1 indicates a read

operation from the appropriate register.

Table II. Register Selection

RS1

RS0

Register

Register Size

0

1

0

1

0

1

Communications Register

Setup Register

Test Register

8 Bits

16 Bits

Data Register

STBY

Standby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part

consumes only 10 µA of power supply current. The part retains its calibration and control word information

when in STANDBY. Writing a 0 to this bit places the part in its normal operating mode. The default value

for this bit after power-on or RESET is 0.

G2

0

G1

0

1

Gain Setting

1

2

1

0

1

32

128

REV. C

–9–

AD7715

Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status: 28 Hex

The Setup Register is an eight-bit register from which data can either be read or to which data can be written. This register controls

the setup which the device is to operate in such as the calibration mode, output rate, unipolar/bipolar operation etc. Table III out-

lines the bit designations for the Setup Register.

Table III. Setup Register

MD1

MD0

CLK

FS1

FS0

B/U

BUF

FSYNC

MD1

0

MD0

0

Operating Mode

Normal Mode; this is the normal mode of operation of the device whereby the device is performing normal

conversions. This is the default condition of these bits after Power-On or RESET.

0

1

0

1

Self-Calibration; this activates self-calibration on the part. This is a one step calibration sequence and when

complete the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit

goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid

word is available in the data register. The zero-scale calibration is performed at the selected gain on internally

shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally

generated V_REF/Selected Gain.

1

Zero-Scale System Calibration; this activates zero-scale system calibration on the part. Calibration is per-

formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.

This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes

high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid

word is available in the data register. At the end of the calibration, the part returns to Normal Mode with

MD1 and MD0 returning to 0, 0.

1

Full-Scale System Calibration; this activates full-scale system calibration on the part. Calibration is per-

formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.

This input voltage should remain stable for the duration of the calibration. Once again, the DRDY output or

bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a

new valid word is available in the data register. At the end of the calibration, the part returns to Normal

Mode with MD1 and MD0 returning to 0, 0.

CLK

Clock Bit. This bit should be set in accordance with the operating frequency of the AD7715. If the device has

a master clock frequency of 2.4576 MHz, then this bit should be set to a 1. If the device has a master clock

frequency of 1 MHz, then this bit should be set to a 0. This bit sets up the correct scaling currents for a given

master clock and also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is

not set correctly for the master clock frequency of the device, then the device may not operate to specifica-

tion. The default value for this bit after power-on or RESET is 1.

FS1, FS0

Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first

notch and –3 dB frequency as outlined in Table IV. The on-chip digital filter provides a Sinc³(or (Sinx/x)³)

filter response. In association with the gain selection, it also determines the output noise (and hence the

resolution) of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution.

Tables V through XII show the effect of the filter notch frequency and gain on the output noise and effective

resolution of the part. The output data rate (or effective conversion time) for the device is equal to the fre-

quency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz

then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 500 Hz, a new word is

available every 2 ms. The default value for these bits is 1, 0.

The settling-time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). For

example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is

80 ms max. If the first notch is at 500 Hz, the settling time of the filter to a full-scale input step is 8 ms max.

This settling-time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a

reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling-

time time will be 3 × 1/(output data rate) from when FSYNC returns low.

The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:

filter –3 dB frequency = 0.262 × filter first notch frequency.

REV. C

–10–

AD7715

Table IV. Output Update Rates

Output Update Rate –3 dB Filter Cutoff

CLK*

FS1

FS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

20 Hz

25 Hz

100 Hz

200 Hz

50 Hz

60 Hz

250 Hz

500 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

13.1 Hz

15.7 Hz

65.5 Hz

131 Hz

Default Status

*Assumes correct clock frequency at MCLK IN pin

B/U

Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or

RESET) status of this bit. A 1 in this bit selects unipolar operation.

BUF

Buffer Control. With this bit low, the on-chip buffer on the analog input is shorted out. With the buffer

shorted out, the current flowing in the AV_DDline is reduced to 250 µA (all gains at f_{CLK IN}= 1 MHz and gain

of 1 or 2 at f_{CLK IN}= 2.4576 MHz) or 500 µA (gains of 32 and 128 @ f_{CLK IN}= 2.4576 MHz) and the output

noise from the part is at its lowest. When this bit is high, the on-chip buffer is in series with the analog input

allowing the input to handle higher source impedances.

FSYNC

Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the

calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When

this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output

update rate), i.e., the settling-time of the filter. This FSYNC bit does not affect the digital interface and does

not reset the DRDY output if it is low.

Test Register (RS1, RS0 = 1, 0)

The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the

bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and

will not operate correctly. If the part enters one of its test modes, exercising RESET will exit the part from the mode. An alterna-

tive scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and

then load all 0s to the Test Register.

Data Register (RS1, RS0 = 1, 1)

The Data Register on the part is a read-only 16-bit register which contains the most up-to-date conversion result from the

AD7715. If the Communications Register data sets up the part for a write operation to this register, a write operation must actu-

ally take place to return the part to where it is expecting a write operation to the Communications Register (the default state of

the interface). However, the 16 bits of data written to the part will be ignored by the AD7715.

REV. C

–11–

AD7715

OUTPUT NOISE

AD7715-5

Table V shows the AD7715-5 output rms noise for the selectable notch and –3 dB frequencies for the part, as selected by FS1 and

FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a V_REFof +2.5 V. These numbers are typical

and are generated at a differential analog input voltage of 0 V with the part used in unbuffered mode (BUF bit of the Setup Register

= 0). Table VI meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is im-

portant to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but

on peak-to-peak noise. The numbers given are for the bipolar input ranges with a V_REFof +2.5 V and for the BUF bit of the Setup

Register = 0. These numbers are typical, are generated at an analog input voltage of 0 V and are rounded to the nearest LSB.

Meanwhile, Table VII and Table VIII show rms noise and peak-to-peak resolution respectively with the AD7715-5 operating under

the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).

Table V. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)

Filter First Notch & O/P Data Rate

–3 dB Frequency

Typical Output RMS Noise in ␮V

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2

GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

3.8

4.8

103

530

1.9

2.4

45

0.6

3.0

18

0.52

0.62

1.6

250

5.5

Table VI. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2 GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

16

13

10

16

13

10

16

13

10

14

13

12

10

Table VII. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Output RMS Noise in ␮V

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2 GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

4.3

5.1

103

550

2.2

3.1

50

0.9

1.0

3.9

18

0.9

1.0

2.1

6

280

Table VIII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2 GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

16

13

10

16

13

10

15

13

10

13

12

10

REV. C

–12–

AD7715

AD7715-3

Table IX shows the AD7715-3 output rms noise for the selectable notch and –3 dB frequencies for the part, as selected by FS1 and

FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a V_REFof +1.25 V. These numbers are typical

and are generated at an analog input voltage of 0 V with the part used in unbuffered mode (BUF bit of the Setup Register = 0).

Table X meanwhile shows the output peak-to-peak noise for the selectable notch and –3 dB frequencies for the part. It is important to

note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-

to-peak noise. The numbers given are for the bipolar input ranges with a V_REFof +1.25 V and for the BUF bit of the Setup Register =

0. These numbers are typical, are generated at an analog input voltage of 0 V and are rounded to the nearest LSB.

Meanwhile, Table XI and Table XII show rms noise and peak-to-peak resolution respectively with the AD7715-3 operating under

the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).

Table IX. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)

Filter First Notch & O/P Data Rate

–3 dB Frequency

Typical Output RMS Noise in ␮V

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2

GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

3.0

3.4

45

1.7

2.1

20

0.7

2.2

9.7

0.65

0.7

1.6

3.3

270

135

Table X. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2

GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

16

13

11

16

13

11

14

13

10

12

11

10

Table XI. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Output RMS Noise in ␮V

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2

GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

4.5

5.1

50

2.4

2.9

25

0.9

2.6

9.7

0.9

1.0

2

270

135

3.3

Table XII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)

Filter First Notch & O/P Data Rate –3 dB Frequency Typical Peak-to-Peak Resolution in Bits

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

MCLK IN =

2.4576 MHz

MCLK IN =

1 MHz

GAIN = 1

GAIN = 2

GAIN = 32

GAIN = 128

50 Hz

60 Hz

250 Hz

500 Hz

20 Hz

25 Hz

100 Hz

200 Hz

13.1 Hz

15.72 Hz

65.5 Hz

131 Hz

5.24 Hz

6.55 Hz

26.2 Hz

52.4 Hz

16

13

10

16

13

11

14

12

10

12

11

10

REV. C

–13–

AD7715

CALIBRATION SEQUENCES

The AD7715 contains a number of calibration options as outlined previously. Table XIII summarizes the calibration types, the op-

erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to

monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that

the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the cali-

bration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the

Setup Register. When these bits return to 0, 0 following a calibration command, it indicates that the calibration sequence is com-

plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier

indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0, 0 represents

the duration of the calibration carried out. The sequence to when DRDY goes low also includes a normal conversion and a pipeline

delay, t_P, to correctly scale the results of this first conversion. t_Pwill never exceed 2000 × t_{CLK IN}. The time for both methods is given

in the table.

Table XIII. Calibration Sequences

Calibration Type

MD1, MD0 Calibration Sequence

Duration to Mode Bits Duration to DRDY

Self Calibration

0, 1

Internal ZS Cal @ Selected Gain + 6 × 1/Output Rate 9 × 1/Output Rate + t_P

Internal FS Cal @ Selected Gain

ZS Cal on AIN @ Selected Gain

FS Cal on AIN @ Selected Gain

ZS System Calibration

FS System Calibration

1, 0

1, 1

3 × 1/Output Rate

4 × 1/Output Rate + t_P

CIRCUIT DESCRIPTION

information. The programmable gain function on the analog

input is also incorporated in this sigma-delta modulator with the

input sampling frequency being modified to give the higher

gains. A sinc³digital low-pass filter processes the output of the

sigma-delta modulator and updates the output register at a rate

determined by the first notch frequency of this filter. The out-

put data can be read from the serial port randomly or periodi-

cally at any rate up to the output register update rate. The first

notch of this digital filter (and hence its –3 dB frequency) can be

programmed via the Setup Register bits FS0 and FS1. With a

master clock frequency of 2.4576 MHz, the programmable

range for this first notch frequency is from 50 Hz to 500 Hz

giving a programmable range for the –3 dB frequency of

13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz,

the programmable range for this first notch frequency is from

20 Hz to 200 Hz giving a programmable range for the –3 dB

frequency of 5.24 Hz to 52.4 Hz.

The AD7715 is a sigma-delta A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low frequency signals such as those in industrial control or pro-

cess control applications. It contains a sigma-delta (or charge-

balancing) ADC, a calibration microcontroller with on-chip

static RAM, a clock oscillator, a digital filter and a bidirectional

serial communications port. The part consumes only 450 µA of

power supply current, making it ideal for battery-powered or

loop-powered instruments. The part comes in two versions, the

AD7715-5 which is specified for operation from a nominal

+5 V analog supply (AV_DD) and the AD7715-3 which is speci-

fied for operation from a nominal +3.3 V analog supply. Both

versions can be operated with a digital supply (DV_DD) voltage of

+3.3 V or +5 V.

The part contains a programmable-gain fully differential analog

input channel. The selectable gains on this input are 1, 2, 32

and 128 allowing the part to accept unipolar signals of between

0 mV to +20 mV and 0 V to +2.5 V or bipolar signals in the

range from ±20 mV to ±2.5 V when the reference input voltage

equals +2.5 V. With a reference voltage of +1.25 V, the input

ranges are from 0 mV to +10 mV to 0 V to +1.25 V in unipolar

mode and from ±10 mV to ±1.25 V in bipolar mode. Note that

the bipolar ranges are with respect to AIN(–) and not with re-

spect to AGND.

The basic connection diagram for the AD7715-5 is shown in

Figure 2. This shows both the AV_DDand DV_DDpins of the

AD7715 being driven from the analog +5 V supply. Some

applications will have AV_DDand DV_DDdriven from separate

supplies. An AD780, precision +2.5 V reference, provides the

reference source for the part. On the digital side, the part is

configured for three-wire operation with CS tied to DGND. A

quartz crystal or ceramic resonator provides the master clock

source for the part. In most cases, it will be necessary to connect

capacitors on the crystal or resonator to ensure that it does

not oscillate at overtones of its fundamental operating fre-

quency. The values of capacitors will vary depending on the

manufacturer’s specifications.

The input signal to the analog input is continuously sampled at

a rate determined by the frequency of the master clock,

MCLK IN, and the selected gain. A charge-balancing A/D

converter (sigma-delta modulator) converts the sampled signal

into a digital pulse train whose duty cycle contains the digital

REV. C

–14–

AD7715

ANALOG

+5V SUPPLY

C_SAMPmust be charged through R_SWand through any external

source impedances every input sample cycle. Therefore, in

unbuffered mode, source impedances mean a longer charge time

for C_SAMP, and this may result in gain errors on the part. Table

XIV shows the allowable external resistance/capacitance values,

for unbuffered mode, such that no gain error to the 16-bit level

is introduced on the part. Note that these capacitances are total

capacitances on the analog input, external capacitance plus

10 pF capacitance from the pins and lead frame of the device.

10␮F

0.1␮F

AV

DV

DD

AD7715

DRDY

DATA READY

AIN(+)

AIN(–)

DIFFERENTIAL

ANALOG INPUT

CS

DOUT

DIN

RECEIVE (READ)

SERIAL DATA

ANALOG

GROUND

AGND

DGND

ANALOG

+5V SUPPLY

SCLK

RESET

SERIAL CLOCK

DIGITAL

GROUND

Table XIV. External R, C Combination for No 16-Bit Gain

Error (Unbuffered Mode Only)

+5V

V

IN

V

REF IN(+)

OUT

0.1␮F

10␮F

AD780

GND

Gain

External Capacitance (pF)

50 100 500 1000

MCLK IN

REF IN(–)

MCLK OUT

CRYSTAL OR

CERAMIC

RESONATOR

10

5000

1

2

32

128

152 kΩ 53.9 kΩ 31.4 kΩ 8.4 kΩ 4.76 kΩ 1.36 kΩ

75.1 kΩ 26.6 kΩ 15.4 kΩ 4.14 kΩ 2.36 kΩ 670 Ω

Figure 2. AD7715-5 Basic Connection Diagram

ANALOG INPUT

16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω

150 Ω

Analog Input Ranges

The AD7715 contains a differential analog input pair AIN(+)

and AIN(–). This input pair provides a programmable-gain,

differential input channel which can handle either unipolar or

bipolar input signals. It should be noted that the bipolar input

signals are referenced to the respective AIN(–) input of the

input pair.

In buffered mode, the analog inputs look into the high imped-

ance inputs stage of the on-chip buffer amplifier. C_SAMPis

charged via this buffer amplifier such that source impedances do

not affect the charging of C_SAMP. This buffer amplifier has an

offset leakage current of 1 nA. In this buffered mode, large

source impedances result in a small dc offset voltage developed

across the source impedance but not in a gain error.

In unbuffered mode, the common-mode range of the input is

from AGND to AV_DDprovided that the absolute value of the

analog input voltage lies between AGND – 30 mV and

AV_DD+ 30 mV. This means that in unbuffered mode the part

can handle both unipolar and bipolar input ranges for all gains.

In buffered mode, the analog inputs can handle much larger

source impedances but the absolute input voltage range is re-

stricted to between AGND + 50 mV to AV_DD– 1.5 V which

also places restrictions on the common-mode range. This means

that in buffered mode there are some restrictions on the allow-

able gains for bipolar input ranges. Care must be taken in set-

ting up the common-mode voltage and input voltage range so

that the above limits are not exceeded, otherwise there will be a

degradation in linearity performance.

Input Sample Rate

The modulator sample frequency for the AD7715 remains at

f_{CLK IN}/128 (19.2 kHz @ f_{CLK IN}= 2.4576 MHz) regardless of

the selected gain. However, gains greater than 1 are achieved by

a combination of multiple input samples per modulator cycle

and a scaling of the ratio of reference capacitor to input capaci-

tor. As a result of the multiple sampling, the input sample rate

of the device varies with the selected gain (see Table XV). In

buffered mode, the input is buffered before the input sampling

Table XV. Input Sampling Frequency vs. Gain

Gain

Input Sampling Freq (f_S)

In unbuffered mode, the analog inputs look directly into the

input sampling capacitor, C_SAMP. The dc input leakage current

in this unbuffered mode is 1 nA maximum. As a result, the

analog inputs see a dynamic load that is switched at the input

sample rate (see Figure 3). This sample rate depends on master

clock frequency and selected gain. C_SAMPis charged to AIN(+)

and discharged to AIN(–) every input sample cycle. The effec-

tive on-resistance of the switch, R_SW, is typically 7 kΩ.

1

2

32

128

f

_{CLK IN}/64 (38.4 kHz @ f_{CLK IN}= 2.4576 MHz)

2 × f_{CLK IN}/64 (76.8 kHz @ f_{CLK IN}= 2.4576 MHz)

8 × f_{CLK IN}/64 (307.2 kHz @ f_{CLK IN}= 2.4576 MHz)

capacitor. In unbuffered mode, where the analog input looks

directly into the sampling capacitor, the effective input imped-

ance is 1/C_SAMP× f_Swhere C_SAMPis the input sampling capaci-

tance and f_Sis the input sample rate.

Bipolar/Unipolar Inputs

AIN(+)

The analog input on the AD7715 can accept either unipolar or

bipolar input voltage ranges. Bipolar input ranges do not imply

that the part can handle negative voltages on its analog input

since the analog input cannot go more negative than –30 mV to

ensure correct operation of the part. The input channel is fully

differential. As a result, the voltage to which the unipolar and

bipolar signals on the AIN(+) input are referenced is the voltage

on the respective AIN(–) input. For example, if AIN(–) is

+2.5 V and the AD7715 is configured for unipolar operation

R

(7k⍀ TYP)

HIGH

IMPEDANCE

1G⍀

SW

C

SAMP

AIN(–)

(10pF )

V

BIAS

SWITCHING FREQUENCY

DEPENDS ON f_CLKIN

AND SELECTED GAIN

Figure 3. Unbuffered Analog Input Structure

REV. C

–15–

AD7715

with a gain of 2 and a V_REFof +2.5 V, the input voltage range

on the AIN(+) input is +2.5 V to +3.75 V. If AIN(–) is +2.5 V

and the AD7715 is configured for bipolar mode with a gain of 2

and a V_REFof +2.5 V, the analog input range on the AIN(+)

input is +1.25 V to +3.75 V (i.e., 2.5 V ± 1.25 V). If AIN(–) is

at AGND, the part cannot be configured for bipolar ranges in

excess of ±30 mV.

DIGITAL FILTERING

The AD7715 contains an on-chip low-pass digital filter that

processes the output of the part’s sigma-delta modulator. There-

fore, the part not only provides the analog-to-digital conversion

function but it also provides a level of filtering. There are a

number of system differences when the filtering function is

provided in the digital domain rather than the analog domain

and the user should be aware of these.

Bipolar or unipolar options are chosen by programming the B/U

bit of the Setup Register. This programs the channel for either

unipolar or bipolar operation. Programming the channel for

either unipolar or bipolar operation does not change any of the

input signal conditioning; it simply changes the data output

coding and the points on the transfer function where calibra-

tions occur.

First, since digital filtering occurs after the A-to-D conversion

process, it can remove noise injected during the conversion

process. Analog filtering cannot do this. Also, the digital filter

can be made programmable far more readily than an analog

filter. Depending on the digital filter design, this gives the user

the capability of programming cutoff frequency and output

update rate.

REFERENCE INPUT

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator

and digital filter, even though the average value of the signal is

within limits. To alleviate this problem, the AD7715 has over-

range headroom built into the sigma-delta modulator and digital

filter which allows overrange excursions of 5% above the analog

input range. If noise signals are larger than this, consideration

should be given to analog input filtering, or to reducing the

input channel voltage so that its full scale is half that of the

analog input channel full scale. This will provide an overrange

capability greater than 100% at the expense of reducing the

dynamic range by 1 bit (50%).

The AD7715’s reference inputs, REF IN(+) and REF IN(–),

provide a differential reference input capability. The common-

mode range for these differential inputs is from AGND to

AV_DD. The nominal reference voltage, V_REF(REF IN(+) –

REF IN(–)), for specified operation is +2.5 V for the AD7715-5

and +1.25 V for the AD7715-3. The part is functional with

V_REFvoltages down to 1 V but with degraded performance as

the output noise will, in terms of LSB size, be larger. REF IN(+)

must always be greater than REF IN(–) for correct operation of

the AD7715.

Both reference inputs provide a high impedance, dynamic load

similar to the analog inputs in unbuffered mode. The maximum

dc input leakage current is ±1 nA over temperature and source

resistance may result in gain errors on the part. In this case, the

sampling switch resistance is 5 kΩ typ and the reference capaci-

tor (C_REF) varies with gain. The sample rate on the reference

inputs is f_{CLK IN}/64 and does not vary with gain. For gains of 1

and 2, C_REFis 8 pF; for a gain of 32, it is 4.25 pF, and for a gain

of 128, it is 3.3125 pF.

In addition, the digital filter does not provide any rejection at

integer multiples of the digital filter’s sample frequency. How-

ever, the input sampling on the part provides attenuation at

multiples of the digital filter’s sampling frequency so that the

unattenu-ated bands actually occur around multiples of the

sampling frequency f_S(as defined in Table XV). Thus the unat-

tenuated bands occur at n × f_S(where n = 1, 2, 3. . . ). At these

frequencies, there are frequency bands, ±f_{3 dB}wide (f_{3 dB}is the

cutoff frequency of the digital filter) at either side where noise

passes unattenuated to the output.

The output noise performance outlined in Tables V through XII

is for an analog input of 0 V which effectively removes the effect

of noise on the reference. To obtain the same noise performance

as shown in the noise tables over the full input range requires a

low noise reference source for the AD7715. If the reference

noise in the bandwidth of interest is excessive, it will degrade

the performance of the AD7715. In applications where the

excitation voltage for the bridge transducer on the analog input

also derives the reference voltage for the part, the effect of the

noise in the excitation voltage will be removed as the application

is ratiometric. Recommended reference voltage sources for the

AD7715-5 include the AD780, REF43 and REF192, while the

recommended reference sources for the AD7715-3 include the

AD589 and AD1580. It is generally recommended to decouple

the output of these references in order to further reduce the

noise level.

Filter Characteristics

The AD7715’s digital filter is a low-pass filter with a (sinx/x)³

response (also called sinc³). The transfer function for this filter

is described in the z-domain by:

3

−N

1

1–

z

H(z)=

×

1– z^–1

N

and in the frequency domain by:

3

f

f_s

in

S

×π×

N

1

|H( f )|=

×

N

f

f_s

Sin π×

where N is the ratio of the modulator rate to the output rate and

f_MODis the modulator rate.

REV. C

–16–

AD7715

Figure 4 shows the filter frequency response for a cutoff fre-

quency of 15.72 Hz which corresponds to a first filter notch

frequency of 60 Hz. The plot is shown from dc to 390 Hz. This

response is repeated at either side of the digital filter’s sample

frequency and at either side of multiples of the filter’s sample

frequency.

26.2 Hz. Post-filtering can be applied to this to reduce the

bandwidth and output noise, to the 7.86 Hz bandwidth level,

while maintaining an output rate of 100 Hz.

Post-filtering can also be used to reduce the output noise from

the device for bandwidths below 13.1 Hz. At a gain of 128 and

a bandwidth of 13.1 Hz, the output rms noise is 520 nV. This

is essentially device noise or white noise and since the input is

chopped, the noise has a primarily flat frequency response. By

reducing the bandwidth below 13.1 Hz, the noise in the result-

ant passband can be reduced. A reduction in bandwidth by a

factor of 2 results in a reduction of approximately 1.25 in the

output rms noise. This additional filtering will result in a longer

settling time.

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

–220

–240

ANALOG FILTERING

The digital filter does not provide any rejection at integer mul-

tiples of the modulator sample frequency, as outlined earlier.

However, due to the AD7715’s high oversampling ratio, these

bands occupy only a small fraction of the spectrum and most

broadband noise is filtered. This means that the analog filtering

requirements in front of the AD7715 are considerably reduced

versus a conventional converter with no on-chip filtering. In

addition, because the part’s common-mode rejection perfor-

mance of 95 dB extends out to several kHz, common-mode

noise in this frequency range will be substantially reduced.

0

60

180

FREQUENCY – Hz

120

300

360

240

Figure 4. Frequency Response of AD7715 Filter

The response of the filter is similar to that of an averaging filter

but with a sharper roll-off. The output rate for the digital filter

corresponds with the positioning of the first notch of the filter’s

frequency response. Thus, for the plot of Figure 4 where the

output rate is 60 Hz, the first notch of the filter is at 60 Hz. The

notches of this (sinx/x)³filter are repeated at multiples of the

first notch. The filter provides attenuation of better than 100 dB

at these notches.

Depending on the application, however, it may be necessary to

provide attenuation prior to the AD7715 in order to eliminate

unwanted frequencies from these bands which the digital filter

will pass. It may also be necessary in some applications to pro-

vide analog filtering in front of the AD7715 to ensure that dif-

ferential noise signals outside the band of interest do not

saturate the analog modulator.

The cutoff frequency of the digital filter is determined by the

value loaded to bits FS0 to FS1 in the Setup Register. Pro-

gramming a different cutoff frequency via FS0 and FS1 does not

alter the profile of the filter response; it changes the frequency of

the notches. The output update of the part and the frequency of

the first notch correspond.

If passive components are placed in front of the AD7715, in

unbuffered mode, care must be taken to ensure that the source

impedance is low enough so as not to introduce gain errors in

the system. This significantly limits the amount of passive anti-

aliasing filtering which can be provided in front of the AD7715

when it is used in unbuffered mode. However, when the part is

used in buffered mode, large source impedances will simply

result in a small dc offset error (a 10 kΩ source resistance will

cause an offset error of less than 10 µV). Therefore, if the sys-

tem requires any significant source impedances to provide pas-

sive analog filtering in front of the AD7715, it is recommended

that the part be operated in buffered mode.

Since the AD7715 contains this on-chip, low-pass filtering,

there is a settling time associated with step function inputs and

data on the output will be invalid after a step change until the

settling time has elapsed. The settling time depends upon the

output rate chosen for the filter. The settling time of the filter

to a full-scale step input can be up 4 times the output data

period. For a synchronized step input (using the FSYNC func-

tion), the settling time is 3 times the output data period.

CALIBRATION

Post-Filtering

The AD7715 provides a number of calibration options that can

be programmed via the MD1 and MD0 bits of the Setup Regis-

ter. The different calibration options are outlined in the Setup

Register and Calibration Sequences sections. A calibration cycle

may be initiated at any time by writing to these bits of the Setup

Register. Calibration on the AD7715 removes offset and gain

errors from the device. A calibration routine should be initiated

on the device whenever there is a change in the ambient operat-

ing temperature or supply voltage. It should also be initiated if

there is a change in the selected gain, filter notch or bipolar/

unipolar input range.

The on-chip modulator provides samples at a 19.2 kHz output

rate with f_{CLK IN}at 2.4576 MHz. The on-chip digital filter

decimates these samples to provide data at an output rate which

corresponds to the programmed output rate of the filter. Since

the output data rate is higher than the Nyquist criterion, the

output rate for a given bandwidth will satisfy most application

requirements. However, there may be some applications which

require a higher data rate for a given bandwidth and noise per-

formance. Applications that need this higher data rate will

require some post-filtering following the digital filter of the

AD7715.

The AD7715 offers self-calibration and system-calibration facili-

ties. For full calibration to occur on the selected channel, the

on-chip microcontroller must record the modulator output for

two different input conditions. These are “zero-scale” and

For example, if the required bandwidth is 7.86 Hz but the re-

quired update rate is 100 Hz, the data can be taken from the

AD7715 at the 100 Hz rate giving a –3 dB bandwidth of

REV. C

–17–

AD7715

“full-scale” points. These points are derived by performing a

conversion on the different input voltages provided to the input

of the modulator during calibration. As a result, the accuracy of

the calibration can only be as good as the noise level that it

provides in normal mode. The result of the “zero-scale” calibra-

tion conversion is stored in the Zero-Scale Calibration Register

while the result of the “full-scale” calibration conversion is

stored in the Full-Scale Calibration Register. With these read-

ings, the on-chip microcontroller can calculate the offset and the

gain slope for the input to output transfer function of the con-

verter. Internally, the part works with a resolution of 33 bits to

determine its conversion result of 16 bits.

step is complete. Once the system zero scale voltage has been set

up, a ZS System Calibration is then initiated by writing the ap-

propriate values (1, 0) to the MD1 and MD0 bits of the Setup

Register. The zero-scale system calibration is performed at the

selected gain. The duration of the calibration is 3 × 1/Output

Rate. At this time the MD1 and MD0 bits in the Setup Register

return to 0, 0. This gives the earliest indication that the calibration

sequence is complete. The DRDY line goes high when calibration

is initiated and does not return low until there is a valid new

word in the data register. The duration time from the calibra-

tion command being issued to DRDY going low is 4 × 1/Output

Rate as the part performs a normal conversion on the AIN volt-

age before DRDY goes low. If DRDY is low before (or goes low

during) the calibration command write to the Setup Register, it

may take up to one modulator cycle (MCLK IN/128) before

DRDY goes high to indicate that calibration is in progress.

Therefore, DRDY should be ignored for up to one modulator

cycle after the last bit is written to the Setup Register in the

calibration command.

Self-Calibration

A self-calibration is initiated on the AD7715 by writing the

appropriate values (0, 1) to the MD1 and MD0 bits of the

Setup Register. In the self-calibration mode with a unipolar

input range, the zero-scale point used in determining the cali-

bration coefficients is with the inputs of the differential pair

internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal

Bias Voltage). The PGA is set for the selected gain (as per G1

and G0 bits in the Communications Register) for this zero-scale

calibration conversion. The full-scale calibration conversion is

performed at the selected gain on an internally generated voltage

of V_REF/Selected Gain.

After the zero-scale point is calibrated, the full-scale point is

applied to AIN and the second step of the calibration process is

initiated by again writing the appropriate values (1, 1) to MD1

and MD0. Again the full-scale voltage must be set up before

the calibration is initiated and it must remain stable throughout

the calibration step. The full-scale system calibration is per-

formed at the selected gain. The duration of the calibration is

3 × 1/Output Rate. At this time the MD1 and MD0 bits in the

Setup Register return to 0, 0. This gives the earliest indication

that the calibration sequence is complete. The DRDY line goes

high when calibration is initiated and does not return low until

there is a valid new word in the data register. The duration time

from the calibration command being issued to DRDY going low

is 4 × 1/Output Rate as the part performs a normal conversion

on the AIN voltage before DRDY goes low. If DRDY is low

before (or goes low during) the calibration command, write to

the Setup Register, it may take up to one modulator cycle

(MCLK IN/128) before DRDY goes high to indicate that cali-

bration is in progress. Therefore, DRDY should be ignored for

up to one modulator cycle after the last bit is written to the

Setup Register in the calibration command.

The duration time for the calibration is 6 × 1/Output Rate. This

is made up of 3 × 1/Output Rate for the zero-scale calibration

and 3 × 1/Output Rate for the full-scale calibration. At this time

the MD1 and MD0 bits in the Setup Register return to 0, 0.

This gives the earliest indication that the calibration sequence is

complete. The DRDY line goes high when calibration is initi-

ated and does not return low until there is a valid new word in

the data register. The duration time from the calibration com-

mand being issued to DRDY going low is 9 × 1/Output Rate.

This is made up of 3 × 1/Output Rate for the zero-scale calibra-

tion, 3 × 1/Output Rate for the full-scale calibration, 3 × 1/

Output Rate for a conversion on the analog input and some

overhead to set up the coefficients correctly. If DRDY is low

before (or goes low during) the calibration command write to

the Setup Register, it may take up to one modulator cycle

(MCLK IN/128) before DRDY goes high to indicate that cali-

bration is in progress. Therefore, DRDY should be ignored for

up to one modulator cycle after the last bit is written to the

Setup Register in the calibration command.

In the unipolar mode, the system calibration is performed be-

tween the two endpoints of the transfer function; in the bipolar

mode, it is performed between midscale (zero differential volt-

age) and positive full scale.

For bipolar input ranges in the self-calibrating mode, the se-

quence is very similar to that just outlined. In this case, the two

points are exactly the same as above, but since the part is config-

ured for bipolar operation, the shorted inputs point is actually

midscale of the transfer function.

The fact that the system calibration is a two-step calibration

offers another feature. After the sequence of a full system cali-

bration has been completed, additional offset or gain calibra-

tions can be performed by themselves to adjust the system zero

reference point or the system gain. Calibrating one of the pa-

rameters, either system offset or system gain, will not affect the

other parameter.

System Calibration

System calibration allows the AD7715 to compensate for system

gain and offset errors as well as its own internal errors. System

calibration performs the same slope factor calculations as self-

calibration but uses voltage values presented by the system to

the AIN inputs for the zero- and full-scale points. Full System

calibration requires a two step process, a ZS System Calibration

followed by a FS System Calibration.

System calibration can also be used to remove any errors from

source impedances on the analog input when the part is used in

unbuffered mode. A simple R, C antialiasing filter on the front

end may introduce a gain error on the analog input voltage but

the system calibration can be used to remove this error.

For a full system calibration, the zero-scale point must be pre-

sented to the converter first. It must be applied to the converter

before the calibration step is initiated and remain stable until the

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on

the amount of offset and span which can be accommodated.

The overriding requirement in determining the amount of offset

REV. C

–18–

AD7715

and gain that can be accommodated by the part is the require-

ment that the positive full-scale calibration limit is ≤ 1.05 ×

V_REF/GAIN. This allows the input range to go 5% above the

nominal range. The in-built headroom in the AD7715’s analog

modulator ensures that the part will still operate correctly with a

positive full-scale voltage which is 5% beyond the nominal.

USING THE AD7715

Clocking and Oscillator Circuit

The AD7715 requires a master clock input, which may be an

external CMOS compatible clock signal applied to the MCLK IN

pin with the MCLK OUT pin left unconnected. Alternatively, a

crystal or ceramic resonator of the correct frequency can be

connected between MCLK IN and MCLK OUT in which case

the clock circuit will function as an oscillator, providing the

clock source for the part. The input sampling frequency, the

modulator sampling frequency, the –3 dB frequency, output

update rate and calibration time are all directly related to the

master clock frequency, f_{CLK IN}. Reducing the master clock

frequency by a factor of 2 will halve the above frequencies and

update rate and double the calibration time. The current drawn

The range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 × V_REF/GAIN and a maximum

value of 2.1 × V_REF/GAIN. However, the span (which is the

difference between the bottom of the AD7715’s input range and

the top of its input range) must take into account the limitation

on the positive full-scale voltage. The amount of offset that can

be accommodated depends on whether the unipolar or bipolar

mode is being used. Once again, the offset must take into ac-

count the limitation on the positive full-scale voltage. In unipo-

lar mode, there is considerable flexibility in handling negative

(with respect to AIN(–)) offsets. In both unipolar and bipolar

modes, the range of positive offsets which can be handled by the

part depends on the selected span. Therefore, in determining

the limits for system zero-scale and full-scale calibrations, the

user has to ensure that the offset range plus the span range does

exceed 1.05 × V_REF/GAIN. This is best illustrated by looking at

a few examples.

from the DV_DDpower supply is also directly related to f_{CLK IN}

Reducing f_{CLK IN}by a factor of 2 will halve the DV_DDcurrent

but will not affect the current drawn from the AV_DDpower

supply.

.

Using the part with a crystal or ceramic resonator between the

MCLK IN and MCLK OUT pins generally causes more cur-

rent to be drawn from DV_DDthan when the part is clocked from

a driven clock signal at the MCLK IN pin. This is because the

on-chip oscillator circuit is active in the case of the crystal or

ceramic resonator. Therefore, the lowest possible current on

the AD7715 is achieved with an externally applied clock at the

MCLK IN pin with MCLK OUT unconnected and unloaded.

If the part is used in unipolar mode with a required span of

0.8 × V_REF/GAIN, then the offset range which the system cali-

bration can handle is from –1.05 × V_REF/GAIN to +0.25 × V_REF

/

GAIN. If the part is used in unipolar mode with a required span of

V_REF/GAIN, then the offset range which the system calibration can

handle is from –1.05 × V_REF/GAIN to +0.05 × V_REF/GAIN. Simi-

larly, if the part is used in unipolar mode and required to re-

move an offset of 0.2 × V_REF/GAIN, then the span range which

the system calibration can handle is 0.85 × V_REF/GAIN.

The amount of additional current taken by the oscillator de-

pends on a number of factors—first, the larger the value of

capacitor placed on the MCLK IN and MCLK OUT pins, then

the larger the DV_DDcurrent consumption on the AD7715. Care

should be taken not to exceed the capacitor values recommended

by the crystal and ceramic resonator manufacturers to avoid

consuming unnecessary DV_DDcurrent. Typical values recom-

mended by crystal or ceramic resonator manufacturers are in the

range of 30 pF to 50 pF, and if the capacitor values on MCLK

IN and MCLK OUT are kept in this range, they will not result

in any excessive DV_DDcurrent. Another factor that influences

the DV_DDcurrent is the effective series resistance (ESR) of the

crystal which appears between the MCLK IN and MCLK OUT

pins of the AD7715. As a general rule, the lower the ESR value

then the lower the current taken by the oscillator circuit.

If the part is used in bipolar mode with a required span of

±0.4 × V_REF/GAIN, then the offset range which the system cali-

bration can handle is from –0.65 × V_REF/GAIN to +0.65 × V_REF

/

GAIN. If the part is used in bipolar mode with a required span

of ±V_REF/GAIN, then the offset range which the system calibra-

tion can handle is from –0.05 × V_REF/GAIN to +0.05 × V_REF

GAIN. Similarly, if the part is used in bipolar mode and required

to remove an offset of ±0.2 × V_REF/GAIN, then the span range

/

which the system calibration can handle is ±0.85 × V_REF/GAIN.

When operating with a clock frequency of 2.4576 MHz, there is

50 µA difference in the DV_DDcurrent between an externally

applied clock and a crystal resonator when operating with a

DV_DDof +3 V. With DV_DD= +5 V and f_{CLK IN}= 2.4576 MHz,

the typical DV_DDcurrent increases by 200 µA for a crystal/

resonator supplied clock versus an externally applied clock. The

ESR values for crystals and resonators at this frequency tend to

be low and as a result there tends to be little difference between

different crystal and resonator types.

Power-Up and Calibration

On power-up, the AD7715 performs an internal reset that sets

the contents of the internal registers to a known state. There

are default values loaded to all registers after a power-on or

reset. The default values contain nominal calibration coefficients

for the calibration registers. However, to ensure correct calibra-

tion for the device a calibration routine should be performed

after power-up.

The power dissipation and temperature drift of the AD7715 are

low, and no warm-up time is required before the initial calibra-

tion is performed. However, if an external reference is being

used, this reference must have stabilized before calibration is

initiated. Similarly, if the clock source for the part is generated

from a crystal or resonator across the MCLK pins, the start-up

time for the oscillator circuit should elapse before a calibration

is initiated on the part (see below).

When operating with a clock frequency of 1 MHz, the ESR value

for different crystal types varies significantly. As a result, the DV_DD

current drain varies across crystal types. When using a crystal

with an ESR of 700 Ω or when using a ceramic resonator, the

increase in the typical DV_DDcurrent over an externally-applied

clock is 50 µA with DV_DD= +3 V and 175 µA with DV_DD

=

+5 V. When using a crystal with an ESR of 3 kΩ, the increase in

the typical DV_DDcurrent over an externally applied clock is

100 µA with DV_DD= +3 V and 400 µA with DV_DD= +5 V.

REV. C

–19–

AD7715

The on-chip oscillator circuit also has a start-up time associated

with it before it is oscillating at its correct frequency and correct

voltage levels. The typical start-up time for the circuit is 10 ms

with a DV_DDof +5 V and 15 ms with a DV_DDof +3 V. At 3 V

supplies, depending on the loading capacitances on the MCLK

pins, a 1 MΩ feedback resistor may be required across the crys-

tal or resonator in order to keep the start up times around the

15 ms duration.

conditions after a RESET and it is generally necessary to set up

all registers and carry out a calibration after a RESET command.

The AD7715’s on-chip oscillator circuit continues to function

even when the RESET input is low. The master clock signal

continues to be available on the MCLK OUT pin. Therefore, in

applications where the system clock is provided by the AD7715’s

clock, the AD7715 produces an uninterrupted master clock

during RESET commands.

The AD7715’s master clock appears on the MCLK OUT pin of

the device. The maximum recommended load on this pin is one

CMOS load. When using a crystal or ceramic resonator to gen-

erate the AD7715’s clock, it may be desirable to then use this

clock as the clock source for the system. In this case, it is recom-

mended that the MCLK OUT signal is buffered with a CMOS

buffer before being applied to the rest of the circuit.

Standby Mode

The STBY bit in the Communications Register of the AD7715

allows the user to place the part in a power-down mode when it

is not required to provide conversion results. The AD7715

retains the contents of all its on-chip registers (including the

data register) while in standby mode. When released from

standby mode, the part starts to process data and a new word is

available in the data register in 3 × 1/Output Rate from when a 0

is written to the STBY bit.

System Synchronization

The FSYNC bit of the Setup Register allows the user to reset

the modulator and digital filter without affecting any of the

setup conditions on the part. This allows the user to start gath-

ering samples of the analog input from a known point in time,

i.e., when the FSYNC is changed from 1 to 0.

The STBY bit does not affect the digital interface, and it does

not affect the status of the DRDY line. If DRDY is high when

the STBY bit is brought low, it will remain high until there is a

valid new word in the data register. If DRDY is low when the

STBY bit is brought low, it will remain low until the data regis-

ter is updated at which time the DRDY line will return high for

500 × t_{CLK IN}before returning low again. If DRDY is low when

the part enters its standby mode (indicating a valid unread word

in the data register), the data register can be read while the part

is in standby. At the end of this read operation, the DRDY will

be reset high as normal.

With a 1 in the FSYNC bit of the Setup Register, the digital

filter and analog modulator are held in a known reset state and

the part is not processing any input samples. When a 0 is then

written to the FSYNC bit, the modulator and filter are taken

out of this reset state and on the next master clock edge the part

starts to gather samples again.

The FSYNC input can also be used as a software start convert

command allowing the AD7715 to be operated in a conven-

tional converter fashion. In this mode, writing to the FSYNC bit

starts conversion and the falling edge of DRDY indicates when

conversion is complete. The disadvantage of this scheme is that

the settling time of the filter has to be taken into account for

every data register update. This means that the rate at which the

data register is updated is three times slower in this mode.

Placing the part in standby mode reduces the total current to

5 µA typical when the part is operated from an external master

clock provided this master clock is stopped. If the external clock

continues to run in standby mode, the standby current increases

to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V

supplies. If a crystal or ceramic resonator is used as the clock

source, then the total current in standby mode is 400 µA typical

with 5 V supplies and 90 µA with 3.3 V supplies. This is because

the on-chip oscillator circuit continues to run when the part is in

its standby mode. This is important in applications where the

system clock is provided by the AD7715’s clock, so that the

AD7715 produces an uninterrupted master clock even when it is

in its standby mode.

Since the FSYNC bit resets the digital filter, the full settling

time of 3 × 1/Output Rate must elapse before there is a new

word loaded to the output register on the part. If the DRDY

signal is low when FSYNC goes to a 0, the DRDY signal will

not be reset high by the FSYNC command. This is because the

AD7715 recognizes that there is a word in the data register that

has not been read. The DRDY line will stay low until an update

of the data register takes place at which time it will go high for

500 × t_{CLK IN}before returning low again. A read from the data

register resets the DRDY signal high, and it will not return low

until the settling time of the filter has elapsed (from the FSYNC

command) and there is a valid new word in the data register. If

the DRDY line is high when the FSYNC command is issued,

the DRDY line will not return low until the settling time of the

filter has elapsed.

Accuracy

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7715 achieves excellent

linearity by the use of high quality, on-chip capacitors, which

have a very low capacitance/voltage coefficient. The device also

achieves low input drift through the use of chopper-stabilized

techniques in its input stage. To ensure excellent performance

over time and temperature, the AD7715 uses digital calibration

techniques which minimize offset and gain error.

Reset Input

The RESET input on the AD7715 resets all the logic, the digital

filter and the analog modulator while all on-chip registers are

reset to their default state. DRDY is driven high and the AD7715

ignores all communications to any of its registers while the

RESET input is low. When the RESET input returns high, the

AD7715 starts to process data, and DRDY will return low in

3 × 1/Output Rate indicating a valid new word in the data

register. However, the AD7715 operates with its default setup

Drift Considerations

The AD7715 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and

dc leakage currents at the sampling node are the primary

sources of offset voltage drift in the converter. The dc input

leakage current is essentially independent of the selected gain.

Gain drift within the converter depends primarily upon the

temperature tracking of the internal capacitors. It is not af-

fected by leakage currents.

REV. C

–20–

AD7715

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter. Using the sys-

tem calibration mode can also minimize offset and gain errors in

the signal conditioning circuitry. Integral and differential linear-

ity errors are not significantly affected by temperature changes.

also removes noise from the analog and reference inputs pro-

vided those noise sources do not saturate the analog modulator.

As a result, the AD7715 is more immune to noise interference

that a conventional high resolution converter. However, because

the resolution of the AD7715 is so high and the noise levels

from the AD7715 so low, care must be taken with regard to

grounding and layout.

POWER SUPPLIES

There is no specific power sequence required for the AD7715;

either the AV_DDor the DV_DDsupply can come up first. While

the latch-up performance of the AD7715 is good, it is important

that power is applied to the AD7715 before signals at REF IN,

AIN or the logic input pins in order to avoid excessive currents.

If this is not possible, then the current which flows in any of

these pins should be limited. If separate supplies are used for

the AD7715 and the system digital circuitry, then the AD7715

should be powered up first. If it is not possible to guarantee

this, then current limiting resistors should be placed in series

with the logic inputs to again limit the current.

The printed circuit board which houses the AD7715 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes which can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7715 is the only device requiring

an AGND to DGND connection, then the ground planes

should be connected at the AGND and DGND pins of the

AD7715. If the AD7715 is in a system where multiple devices

require AGND to DGND connections, the connection should

still be made at one point only, a star ground point which

should be established as close as possible to the AD7715.

During normal operation the AD7715 analog supply (AV_DD

)

should always be greater than or equal to its digital supply (DV_DD).

Supply Current

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7715 to avoid noise coupling. The power

supply lines to the AD7715 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

The current consumption on the AD7715 is specified for sup-

plies in the range +3 V to +3.6 V and in the range +4.75 V to

+5.25 V. The part operates over a +2.85 V to +5.25 V supply

range and the I_DDfor the part varies as the supply voltage varies

over this range. Figure 5 shows the variation of the typical

I_DDwith V_DDvoltage for both a 1 MHz external clock and a

2.4576 MHz external clock at +25°C. The AD7715 is operated

in unbuffered mode. The relationship shows that the I_DDis

minimized by operating the part with lower V_DDvoltages. I_DD

on the AD7715 is also minimized by using an external master

clock or by optimizing external components when using the on-

chip oscillator circuit.

1.0

0.9

0.8

Good decoupling is important when using high resolution

ADCs. All analog supplies should be decoupled with 10 µF

tantalum in parallel with 0.1 µF capacitors to AGND. To

achieve the best from these decoupling components, they must

be placed as close as possible to the device, ideally right up

against the device. All logic chips should be decoupled with

0.1 µF disc ceramic capacitors to DGND. In systems where a

common supply voltage is used to drive both the AV_DDand

DV_DDof the AD7715, it is recommended that the system’s

AV_DDsupply is used. This supply should have the recom-

mended analog supply decoupling capacitors between the AV_DD

pin of the AD7715 and AGND and the recommended digital

supply decoupling capacitor between the DV_DDpin of the

AD7715 and DGND.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

MCLK IN = 2.4576MHz

MCLK IN = 1MHz

3.15

4.05

SUPPLY VOLTAGE (AV & DV ) – Volts

5.25

2.85

3.45

3.75

4.35

4.65

4.95

DD

Figure 5. I_DDvs. Supply Voltage

Grounding and Layout

Evaluating the AD7715 Performance

The recommended layout for the AD7715 is outlined in the

evaluation board for the AD7715. The evaluation board pack-

age includes a fully assembled and tested evaluation board,

documentation, software for controlling the board over the

printer port of a PC and software for analyzing the AD7715’s

performance on the PC. For the AD7715-5, the evaluation

board order number is EVAL-AD7715-5EB and for the

AD7715-3, the order number is EVAL-AD7715-3EB.

Since the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. The excellent common-mode rejection of the part will

remove common-mode noise on these inputs. The analog and

digital supplies to the AD7715 are independent and separately

pinned out to minimize coupling between the analog and digital

sections of the device. The digital filter will provide rejection of

broadband noise on the power supplies, except at integer mul-

tiples of the modulator sampling frequency. The digital filter

Noise levels in the signals applied to the AD7715 may also

affect performance of the part. The AD7715 software evaluation

REV. C

–21–

AD7715

package allows the user to evaluate the true performance of the

part, independent of the analog input signal. The scheme

involves using a test mode on the part where the differential

inputs to the AD7715 are internally shorted together to provide

a zero differential voltage for the analog modulator. External to

the device, the AIN(–) input should be connected to a voltage

which is within the allowable common-mode range of the part.

This scheme should be used after a calibration has been per-

formed on the part.

is complete. It also goes high prior to the updating of the output

register to indicate when not to read from the device to ensure

that a data read is not attempted while the register is being

updated. CS is used to select the device. It can be used to de-

code the AD7715 in systems where a number of parts are con-

nected to the serial bus.

Figures 6 and 7 show timing diagrams for interfacing to the

AD7715 with CS used to decode the part. Figure 6 is for a read

operation from the AD7715’s output shift register, while Figure

7 shows a write operation to the input shift register. It is pos-

sible to read the same data twice from the output register even

though the DRDY line returns high after the first read opera-

tion. Care must be taken, however, to ensure that the read

operations have been completed before the next output update

is about to take place.

DIGITAL INTERFACE

The AD7715’s programmable functions are controlled using a

set of on-chip registers as outlined previously. Data is written to

these registers via the part’s serial interface and read access to

the on-chip registers is also provided by this interface. All com-

munications to the part must start with a write operation to the

Communications Register. After power-on or RESET, the de-

vice expects a write to its Communications Register. The data

written to this register determines whether the next operation to

the part is a read or a write operation and also determines to

which register this read or write operation occurs. Therefore,

write access to any of the other registers on the part starts with a

write operation to the Communications Register followed by a

write to the selected register. A read operation from any other

register on the part (including the output data register) starts

with a write operation to the Communications Register followed

by a read operation from the selected register.

The AD7715 serial interface can operate in three-wire mode by

tying the CS input low. In this case, the SCLK, DIN and

DOUT lines are used to communicate with the AD7715 and

the status of DRDY can be obtained by interrogating the MSB

of the Communications Register. This scheme is suitable for

interfacing to microcontrollers. If CS is required as a decoding

signal, it can be generated from a port bit. For microcontroller

interfaces, it is recommended that the SCLK idles high between

data transfers.

The AD7715 can also be operated with CS used as a frame

synchronization signal. This scheme is suitable for DSP inter-

faces. In this case, the first bit (MSB) is effectively clocked out

by CS since CS would normally occur after the falling edge of

SCLK in DSPs. The SCLK can continue to run between data

transfers provided the timing numbers are obeyed.

The AD7715’s serial interface consists of five signals, CS,

SCLK, DIN, DOUT and DRDY. The DIN line is used for

transferring data into the on-chip registers while the DOUT line

is used for accessing data from the on-chip registers. SCLK is

the serial clock input for the device and all data transfers (either

on DIN or DOUT) take place with respect to this SCLK signal.

The DRDY line is used as a status signal to indicate when data

is ready to be read from the AD7715’s data register. DRDY

goes low when a new data word is available in the output regis-

ter. It is reset high when a read operation from the data register

The serial interface can be reset by exercising the RESET input

on the part. It can also be reset by writing a series of 1s on the

DIN input. If a logic 1 is written to the AD7715 DIN line for at

least 32 serial clock cycles, the serial interface is reset. This

ensures that in three-wire systems that if the interface gets lost

DRDY

t₁₀

t₃

CS

t₄

t₈

t₆

SCLK

t₇

t₅

t₉

DOUT

MSB

LSB

Figure 6. Read Cycle Timing Diagram

CS

t₁₆

t₁₁

t₁₄

SCLK

t₁₅

t₁₂

t₁₃

LSB

DIN

MSB

Figure 7. Write Cycle Timing Diagram

REV. C

–22–

AD7715

either via a software error or by some glitch in the system, it can

be reset back into a known state. This state returns the interface

CONFIGURING THE AD7715

The AD7715 contains three on-chip registers which the user

accesses via the serial interface. Communication with any of

these registers is initiated by writing to the Communications

Register first. Figure 8 outlines a flow diagram of the sequence

which is used to configure all registers after a power-up or reset.

The flowchart also shows two different read options—the first

where the DRDY pin is polled to determine when an update of

the data register has taken place, the second where the DRDY

bit of the Communications Register is interrogated to see if a

data register update has taken place. Also included in the flow-

ing diagram is a series of words which should be written to the

registers for a particular set of operating conditions. These con-

ditions are gain of 1, no filter sync, bipolar mode, buffer off,

clock of 2.4576 MHz and an output rate of 60 Hz.

to where the AD7715 is expecting a write operation to its Com-

munications Register. This operation in itself does not reset the

contents of any registers, but since the interface was lost, the

information which was written to any of the registers is un-

known and it is advisable to set up all registers again.

Some microprocessor or microcontroller serial interfaces have a

single serial data line. In this case, it is possible to connect the

AD7715’s DATA OUT and DATA IN lines together and con-

nect then to the single data line of the processor. A 10 kΩ pull-

up resistor should be used on this single data line. In this case, if

the interface gets lost, because the read and write operations

share the same line the procedure to reset it back to a known

state is somewhat different than described previously. It requires

a read operation of 24 serial clocks followed by a write operation

where a logic 1 is written for at least 32 serial clock cycles to

ensure that the serial interface is back into a known state.

START

POWER-ON/RESET FOR AD7715

CONFIGURE & INITIALIZE ␮C/␮P SERIAL PORT

WRITE TO COMMUNICATIONS REGISTER SETTING UP

GAIN & SETTING UP NEXT OPERATION TO BE A WRITE

TO THE SETUP REGISTER (10 HEX)

WRITE TO SETUP REGISTER SETTING UP REQUIRED

VALUES & INITIATING A SELF CALIBRATION (68 HEX)

POLL DRDY PIN

WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME

GAIN & SETTING UP NEXT OPERATION TO BE A READ FROM

THE COMMUNICATIONS REGISTER (08 HEX)

NO

DRDY

LOW?

READ FROM COMMUNICATIONS REGISTER

YES

POLL DRDY BIT OF COMMUNICATIONS REGISTER

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME GAIN & SETTING UP NEXT OPERATION TO BE A

READ FROM THE DATA REGISTER (38 HEX)

NO

DRDY

READ FROM DATA REGISTER

LOW?

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME GAIN & SETTING UP NEXT OPERATION TO BE A

READ FROM THE DATA REGISTER (38 HEX)

READ FROM DATA REGISTER

Figure 8. Flowchart for Setting Up and Reading from the AD7715

REV. C

–23–

AD7715

DV

DD

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7715’s flexible serial interface allows for easy interface

to most microcomputers and microprocessors. The flowchart of

Figure 8 outlines the sequence which should be followed when

interfacing a microcontroller or microprocessor to the AD7715.

Figures 9, 10 and 11 show some typical interface circuits.

RESET

SS

SCK

SCLK

68HC11

AD7715

MISO

MOSI

DATA OUT

DATA IN

CS

The serial interface on the AD7715 has the capability of operat-

ing from just three wires and is compatible with SPI interface

protocols. The three-wire operation makes the part ideal for

isolated systems where minimizing the number of interface lines

minimizes the number of opto-isolators required in the system.

The rise and fall times of the digital inputs to the AD7715

(especially the SCLK input) should be no longer than 1 µs.

Figure 9. AD7715 to 68HC11 Interface

lines to four, is to monitor the DRDY output line from the

AD7715. The monitoring of the DRDY line can be done in two

ways. First, DRDY can be connected to one of the 68HC11’s

port bits (such as PC0) which is configured as an input. This

port bit is then polled to determine the status of DRDY. The

second scheme is to use an interrupt driven system, in which

case the DRDY output is connected to the IRQ input of the

68HC11. For interfaces that require control of the CS input on

the AD7715, one of the port bits of the 68HC11 (such as PC1),

which is configured as an output, can be used to drive the CS

input.

Most of the registers on the AD7715 are 8-bit registers. This

facilitates easy interfacing to the 8-bit serial ports of microcon-

trollers. Some of the registers on the part are up to 16 bits, but

data transfers to these 16-bit registers can consist of a full 16-bit

transfer or two 8-bit transfers to the serial port of the microcon-

troller. DSP processors and microprocessors generally transfer

16 bits of data in a serial data operation. Some of these proces-

sors, such as the ADSP-2105, have the facility to program the

amount of cycles in a serial transfer. This allows the user to

tailor the number of bits in any transfer to match the register

length of the required register in the AD7715.

The 68HC11 is configured in the master mode with its CPOL

bit set to a logic one and its CPHA bit set to a logic one. When

the 68HC11 is configured like this, its SCLK line idles high

between data transfers. The AD7715 is not capable of full du-

plex operation. If the AD7715 is configured for a write opera-

tion, no data appears on the DATA OUT lines even when the

SCLK input is active. Similarly, if the AD7715 is configured for

a read operation, data presented to the part on the DATA IN

line is ignored even when SCLK is active.

Even though some of the registers on the AD7715 are only eight

bits in length, communicating with two of these registers in

successive write operations can be handled as a single 16-bit

data transfer if required. For example, if the Setup Register is to

be updated, the processor must first write to the Communica-

tions Register (saying that the next operation is a write to the

Setup Register) and then write eight bits to the Setup Register.

This can all be done in a single 16-bit transfer if required be-

cause once the eight serial clocks of the write operation to the

Communications Register have been completed, the part imme-

diately sets itself up for a write operation to the Setup Register.

Coding for an interface between the 68HC11 and the AD7715

is given in Table XVI. In this example, the DRDY output line

of the AD7715 is connected to the PC0 port bit of the 68HC11

and is polled to determine its status.

AD7715 to 68HC11 Interface

Figure 9 shows an interface between the AD7715 and the

68HC11 microcontroller. The diagram shows the minimum

(three-wire) interface with CS on the AD7715 hardwired low.

In this scheme, the DRDY bit of the Communications Register

is monitored to determine when the Data Register is updated.

An alternative scheme, which increases the number of interface

REV. C

–24–

AD7715

AD7715 to 8XC51 Interface

AD7715 to ADSP-2103/ADSP-2105 Interface

An interface circuit between the AD7715 and the 8XC51

microcontroller is shown in Figure 10. The diagram shows the

minimum number of interface connections with CS on the

AD7715 hardwired low. In the case of the 8XC51 interface, the

minimum number of interconnects is just two. In this scheme,

the DRDY bit of the Communications Register is monitored to

determine when the Data Register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the DRDY output line from the AD7715. The

monitoring of the DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such

as P1.0) which is configured as an input. This port bit is then

polled to determine the status of DRDY. The second scheme is

to use an interrupt driven system in which case, the DRDY

output is connected to the INT1 input of the 8XC51. For inter-

faces that require control of the CS input on the AD7715, one

of the port bits of the 8XC51 (such as P1.1), which is config-

ured as an output, can be used to drive the CS input.

Figure 11 shows an interface between the AD7715 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface

shown, the DRDY bit of the Communications Register is again

monitored to determine when the Data Register is updated. The

alternative scheme is to use an interrupt driven system, in which

case the DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The serial interface of the ADSP-

2103/ADSP-2105 is set up for alternate framing mode. The

RFS and TFS pins of the ADSP-2103/ADSP-2105 are config-

ured as active low outputs, and the ADSP-2103/ADSP-2105

serial clock line, SCLK, is also configured as an output. The CS

for the AD7715 is active when either the RFS or TFS outputs

from the ADSP-2103/ADSP-2105 are active. The serial clock

rate on the ADSP-2103/ADSP-2105 should be limited to

3 MHz to ensure correct operation with the AD7715.

DV

DD

RESET

CS

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7715 should be

connected together with a 10 kΩ pull-up resistor. The serial

clock on the 8XC51 idles high between data transfers. The

8XC51 outputs the LSB first in a write operation while the

AD7715 rearranged before being written to the output serial

register. Similarly, the AD7715 outputs the MSB first during a

read operation while the 8XC51 expects the LSB first. There-

fore, the data which is read into the serial buffer needs to be

rearranged before the correct data word from the AD7715 is

available in the accumulator.

RFS

TFS

AD7715

ADSP-2103/2105

DATA OUT

DATA IN

DR

DT

SCLK

Figure 11. AD7715 to ADSP-2103/ADSP-2105 Interface

CODE FOR SETTING UP THE AD7715

DV

DD

Table XVI gives a set of read and write routines in C code for

interfacing the 68HC11 microcontroller to the AD7715. The

sample program sets up the various registers on the AD7715

and reads 1000 samples from the part into the 68HC11. The

setup conditions on the part are exactly the same as those out-

lined for the flowchart of Figure 8. In the example code given

here, the DRDY output is polled to determine if a new valid

word is available in the data register.

RESET

DV

DD

8XC51

AD7715

10k⍀

P3.0

P3.1

DATA OUT

DATA IN

SCLK

The sequence of the events in this program are as follows:

1. Write to the Communications Register, setting the gain to 1

with standby inactive.

CS

Figure 10. AD7715 to 8XC51 Interface

2. Write to the Setup Register, setting bipolar mode, buffer off,

no filter synchronization, confirming a clock frequency of

2.4576 MHz, setting the output rate for 60 Hz and initiating

a self-calibration.

3. Poll the DRDY Output.

4. Read the data from the Data Register.

5. Loop around doing Steps 3 and 4 until the specified number

of samples have been taken.

REV. C

–25–

AD7715

Table XVI. C Code for Interfacing AD7715 to 68HC11

/* This program has read and write routines for the 68HC11 to interface to the AD7715 and the sample

program sets the various registers and then reads 1000 samples from the part. */

#include <math.h>

#include <io6811.h>

#define NUM_SAMPLES 1000 /* change the number of data samples */

#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */

Writetoreg (int);

Read (int,char);

char *datapointer = store;

char store[NUM_SAMPLES*MAX_REG_LENGTH + 30];

void main()

{

/* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit

of PORTC is made as an output */

char a;

DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */

PORTC | = 0x04; /* make the /CS line high */

Writetoreg(0x10); /* set the gain to 1, standby off and set the next operation as write to the setup

register */

Writetoreg(0x68); /* set bipolar mode, buffer off, no filter sync, confirm clock as 2.4576MHz, set

output rate to 60Hz and do a self calibration */

while(PORTC & 0x10); /* wait for /DRDY to go low */

for(a=0;a<NUM_SAMPLES;a++);

{

Writetoreg(0x38); /*set the next operation for 16 bit read from the data register */

Read(NUM_SAMPLES,2);

}

Writetoreg(int byteword);

{

int q;

SPCR = 0x3f;

SPCR = 0X7f; /* this sets the WiredOR mode(DWOM=1), Master mode(MSTR=1), SCK idles high(CPOL=1), /SS

can be low always (CPHA=1), lowest clock speed(slowest speed which is master clock /32 */

DDRD = 0x18; /* SCK, MOSI outputs */

q = SPSR;

q = SPDR; /* the read of the staus register and of the data register is needed to clear the interrupt

which tells the user that the data transfer is complete */

PORTC &= 0xfb; /* /CS is low */

SPDR = byteword; /* put the byte into data register */

while(!(SPSR & 0x80)); /* wait for /DRDY to go low */

PORTC |= 0x4; /* /CS high */

}

Read(int amount, int reglength)

{

int q;

SPCR = 0x3f;

SPCR = 0x7f; /* clear the interrupt */

DDRD = 0x10; /* MOSI output, MISO input, SCK output */

while(PORTC & 0x10); /* wait for /DRDY to go low */

PORTC & 0xfb ; /* /CS is low */

for(b=0;b<reglength;b++)

{

SPDR = 0;

while(!(SPSR & 0x80)); /* wait until port ready before reading */

*datapointer++=SPDR; /* read SPDR into store array via datapointer */

}

PORTC|=4; /* /CS is high */

}

REV. C

–26–

AD7715

APPLICATIONS

+20 mV to 0 V to +2.5 V and bipolar inputs of ±20 mV to

±2.5 V. Because the part operates from a single supply, these

bipolar ranges are with respect to a biased-up differential input.

The AD7715 provides a low cost, high resolution analog-to-

digital function. Because the analog-to-digital function is pro-

vided by a sigma-delta architecture, it makes the part more

immune to noisy environments thus making the part ideal for

use in industrial and process control applications. It also

provides a programmable gain amplifier, a digital filter and

calibration options. Thus, it provides far more system level

functionality than off-the-shelf integrating ADCs without the

disadvantage of having to supply a high quality integrating ca-

pacitor. In addition, using the AD7715 in a system allows the

system designer to achieve a much higher level of resolution

because noise performance of the AD7715 is significantly better

than that of the integrating ADCs.

Pressure Measurement

One typical application of the AD7715 is pressure measurement.

Figure 12 shows the AD7715 used with a pressure transducer,

the BP01 from Sensym. The pressure transducer is arranged in a

bridge network and gives a differential output voltage between

its OUT(+) and OUT(–) terminals. With rated full-scale pres-

sure (in this case 300 mmHg) on the transducer, the differential

output voltage is 3 mV/V of the input voltage (i.e., the voltage

between its IN(+) and IN(–) terminals).

Assuming a 5 V excitation voltage, the full-scale output range

from the transducer is 15 mV. The excitation voltage for the

bridge is also used to generate the reference voltage for the

AD7715. Therefore, variations in the excitation voltage do not

introduce errors in the system. Choosing resistor values of 24 kΩ

and 15 kΩ as per the diagram give a 1.92 V reference voltage for

the AD7715 when the excitation voltage is 5 V.

The on-chip PGA allows the AD7715 to handle an analog input

voltage range as low as 10 mV full-scale with V_REF= +1.25 V.

The differential inputs of the part allow this analog input range

to have an absolute value anywhere between AGND and AV_DD

when the part is operated in unbuffered mode. It allows the user

to connect the transducer directly to the input of the AD7715.

The programmable gain front end on the AD7715 allows the

part to handle unipolar analog input ranges from 0 mV to

Using the part with a programmed gain of 128 results in the full-

scale input span of the AD7715 being 15 mV which corresponds

with the output span from the transducer.

+5V

EXCITATION VOLTAGE = +5V

AV

DV

DD

AD7715

IN+

CHARGE BALANCING A/D

CONVERTER

AIN(+)

AIN(–)

OUT–

OUT+

PGA

BUFFER

AUTO-ZEROED

DIGITAL

FILTER

IN–

A = 1–128

MODULATOR

MCLK IN

24k⍀

CLOCK

GENERATION

MCLK OUT

SERIAL INTERFACE

REGISTER BANK

REF IN (+)

REF IN (–)

RESET

DRDY

15k⍀

AGND

DGND

DOUT

DIN

SCLK

CS

Figure 12. Pressure Measurement Using the AD7715

REV. C

–27–

AD7715

Temperature Measurement

resistances R_L1and R_L4, but these simply shift the common-

mode voltage. There is no voltage drop across lead resistances

R_L2and R_L3as the input current to the AD7715 is very low_.The

lead resistances present a small source impedance so it would

not generally be necessary to turn on the buffer on the AD7715.

If the buffer is required, the common-mode voltage should be

set accordingly by inserting a small resistance between the bot-

tom end of the RTD and AGND of the AD7715. In the appli-

cation shown an external 400 µA current source provides the

excitation current for the PT100 and it also generates the refer-

ence voltage for the AD7715 via the 6.25 kΩ resistor. Variations

in the excitation current do not affect the circuit as both the

input voltage and the reference voltage vary ratiometrically with

the excitation current. However, the 6.25 kΩ resistor must have

a low temperature coefficient to avoid errors in the reference

voltage over temperature.

Another application area for the AD7715 is in temperature

measurement. Figure 13 outlines a connection from a thermo-

couple to the AD7715. In this application, the AD7715 is oper-

ated in its buffered mode to allow large decoupling capacitors

on the front end to eliminate any noise pickup which there may

have been in the thermocouple leads. When the AD7715 is

operated in buffered mode, it has a reduced common-mode

range. In order to place the differential voltage from the thermo-

couple on a suitable common-mode voltage, the AIN(–) input of

the AD7715 is biased up at the reference voltage, +2.5 V.

Figure 14 shows another temperature measurement application

for the AD7715. In this case, the transducer is an RTD (Resis-

tive Temperature Device), a PT100. The arrangement is a 4-

lead RTD configuration. There are voltage drops across the lead

+5V

AV

DD

DV

DD

AD7715

THERMOCOUPLE

CHARGE BALANCING A/D

CONVERTER

JUNCTION

R

AIN (+)

AIN (–)

PGA

BUFFER

AUTO-ZEROED

MODULATOR

DIGITAL

FILTER

A = 1–128

C

MCLK IN

+5V

CLOCK

GENERATION

+V

IN

MCLK OUT

SERIAL INTERFACE

REGISTER BANK

V

OUT

REF IN (+)

REF IN (–)

REF192

GND

RESET

DRDY

AGND

DGND

DOUT

DIN

SCLK

CS

Figure 13. Thermocouple Measurement Using the AD7715

+5V

AV

DV

400␮A

REF IN (+)

DD

6.25k⍀

AD7715

R

L1

REF IN (–)

AIN(+)

L2

CHARGE BALANCING A/D

CONVERTER

PGA

BUFFER

RTD

AUTO-ZEROED

MODULATOR

DIGITAL

FILTER

R

L3

AIN(–)

A = 1–128

MCLK IN

R

L4

CLOCK

GENERATION

SERIAL INTERFACE

REGISTER BANK

MCLK OUT

RESET

AGND

DGND

DRDY

DIN

DOUT

SCLK

CS

Figure 14. RTD Measurement Using the AD7715

REV. C

–28–

AD7715

Smart Transmitters

The AD7715 consumes only 450 µA, leaving 3 mA available for

the rest of the transmitter. Figure 15 shows a block diagram of a

smart transmitter which includes the AD7715. Not shown in

Figure 15 is the isolated power source required to power the

front end.

Another area where the low power, single supply, three-wire

interface capabilities is of benefit is in smart transmitters. Here,

the entire smart transmitter must operate from the 4 mA to

20 mA loop. Tolerances in the loop mean that the amount of

current available to power the transmitter is as low as 3.5 mA.

ISOLATION

BARRIER

MAIN TRANSMITTER ASSEMBLY

3V

ISOLATED SUPPLY

VOLTAGE

REGULATOR

VOLTAGE

REFERENCE

V

CC

AV

DD

DV

DD

REF IN

INPUT/OUTPUT

D/A

CONVERTER

STAGE

MICROCONTROLLER UNIT

4–20mA

SIGNAL

SENSORS

RTD

mV

ohm

CONDITIONER

*PID

LOOP

RTN

AD7715

MCLK

IN

*RANGE SETTING

*CALIBRATION

*LINEARIZATION

*OUTPUT CONTROL

*SERIAL COMMUNICATION

*HART PROTOCOL

COM

3V

TC

WAVEFORM

SHAPER

BANDPASS

FILTER

HART

MODEM

BELL 202

MCLK

OUT

AGND

ISOLATED GROUND

COM

DGND

Figure 15. Smart Transmitter Using the AD7715

REV. C

–29–

AD7715

PAGE INDEX

Topic

Page

CODE FOR SETTING UP AD7715 . . . . . . . . . . . . . . . . . 25

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 28

Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 31

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

AD7715-5 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 2

AD7715-3 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . 9

Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

OUTPUT NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AD7715-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

AD7715-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CALIBRATION SEQUENCES . . . . . . . . . . . . . . . . . . . . . 14

CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 14

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DIGITAL FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Post-Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ANALOG FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . . 19

USING THE AD7715 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 19

System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Evaluating the AD7715 Performance . . . . . . . . . . . . . . . . 21

DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CONFIGURING THE AD7715 . . . . . . . . . . . . . . . . . . . . . 23

MICROCOMPUTER/MICROPROCESSOR

TABLE INDEX

Table

Table I

Title

Communications Register . . . . . . . . . . . . . . . . . . 9

Table II

Register Selection . . . . . . . . . . . . . . . . . . . . . . . . 9

Table III Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table IV Output Update Rates . . . . . . . . . . . . . . . . . . . . 11

Table V

Output RMS Noise vs. Gain and Output Update

Rate for AD7715-5 (Unbuffered Mode) . . . . . . 12

Table VI Peak-to-Peak Resolution vs. Gain and Output

Update Rate for AD7715-5 (Unbuffered Mode) . . 12

Table VII Output RMS Noise vs. Gain and Output Update

Rate for AD7715-5 (Buffered Mode) . . . . . . . . . 12

Table VIII Peak-to-Peak Resolution vs. Gain and Output

Update Rate for AD7715-5 (Buffered Mode) . . 12

Table IX Output RMS Noise vs. Gain and Output Update

Rate for AD7715-3 (Unbuffered Mode) . . . . . . 13

Table X

Peak-to-Peak Resolution vs. Gain and Output

Update Rate for AD7715-3 (Unbuffered Mode) . . 13

Table XI Output RMS Noise vs. Gain and Output Update

Rate for AD7715-5 (Buffered Mode) . . . . . . . . 13

Table XII Peak-to-Peak Resolution vs. Gain and Output

Update Rate for AD7715-3 (Buffered Mode) . . 13

Table XIII Calibration Sequences . . . . . . . . . . . . . . . . . . . . 14

Table XIV External R, C Combination for No 16-Bit

Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table XV Input Sampling Frequency vs. Gain . . . . . . . . . 15

Table XVI C Code for Interfacing AD7715 to 68HC11 . . . 26

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AD7715 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 24

AD7715 to 8XC51 Interface . . . . . . . . . . . . . . . . . . . . . . 25

AD7715 to ADSP-2103/ADSP-2105 Interface . . . . . . . . 25

REV. C

–30–

AD7715

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Plastic DIP

(N-16)

0.840 (21.33)

0.745 (18.93)

16

1

9

0.280 (7.11)

0.240 (6.10)

8

0.325 (8.25)

0.195 (4.95)

0.115 (2.93)

0.300 (7.62)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.070 (1.77) SEATING

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

PLANE

0.045 (1.15)

16-Lead SOIC

(R-16)

0.4133 (10.50)

0.3977 (10.00)

16

9

1

8

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

PIN 1

؋

45°

0.0118 (0.30)

0.0040 (0.10)

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

8

0

0.0192 (0.49)

0.0500

(1.27)

BSC

0.0125 (0.32)

0.0091 (0.23)

SEATING

PLANE

0.0138 (0.35)

16-Lead TSSOP

(RU-16)

0.201 (5.10)

0.193 (4.90)

16

9

8

1

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

8°

0°

0.0256 0.0118 (0.30)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

(0.65)

0.0075 (0.19)

BSC

REV. C

–31–


型号：	AD7715ACHIPS-3
厂家：	ADI
描述：	3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC 3 V / 5 V ， 450 uA的16位， Σ-Δ ADC 转换器模数转换器
文件：	总31页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7715ACHIPS-3 [ADI]

相关型号：

AD7715ACHIPS-5

AD7715AN-3

AD7715AN-5

AD7715ANZ-3

AD7715ANZ-31

AD7715ANZ-5

AD7715ANZ-51

AD7715AR-3

AD7715AR-3REEL

AD7715AR-5

AD7715AR-5REEL

AD7715AR5