AD7716BSZ [ADI]
LC2MOS 22-Bit Data Acquisition System; LC2MOS 22位数据采集系统
| 型号： | AD7716BSZ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 22-Bit Data Acquisition System |
| 文件： | 总16页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
a
22-Bit Data Acquisition System
AD7716
FUNCTIONAL BLOCK DIAGRAM
FEATURES
22-Bit Sigma-Delta ADC
AV
AV
SS
DV
RESET
CLKIN CLKOUT
A0 A1 A2
DD
DD
Dynamic Range of 105 dB (146 Hz Input)
؎0.003% Integral Nonlinearity
On-Chip Low-Pass Digital Filter
Cutoff Programmable from 584 Hz to 36.5 Hz
Linear Phase Response
AD7716
CLOCK
GENERATION
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
A
A
1
2
3
4
IN
MODE
CONTROL
CASCIN
CASCOUT
Five Line Serial I/O
LOGIC
Twos Complement Coding
Easy Interface to DSPs and Microcomputers
Software Control of Filter Cutoff
؎5 V Supply
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
IN
RFS
OUTPUT
SHIFT
SDATA
REGISTER
SCLK
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
Low Power Operation: 50 mW
A
IN
DRDY
APPLICATIONS
Biomedical Data Acquisition
ECG Machines
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
CONTROL
REGISTER
A
IN
TFS
EEG Machines
Process Control
High Accuracy Instrumentation
Seismic Systems
V
D
1
D
2
D
1
AGND DGND
REF
OUT
OUT
IN
GENERAL DESCRIPTION
There are 22 bits of data corresponding to the analog input.
Two bits contain the channel address and 3 bits are the device
address. Thus, each channel in a 32-channel system would have
a discrete 5-bit address. The device also has a CASCOUT pin
and a CASCIN pin that allow simple networking of multiple
devices.
The AD7716 is a signal processing block for data acquisition
systems. It is capable of processing four channels with band-
widths of up to 584 Hz. Resolution is 22 bits and the usable
dynamic range varies from 111 dB with an input bandwidth of
36.5 Hz to 99 dB with an input bandwidth of 584 Hz.
The device consists of four separate A/D converter channels that
are implemented using sigma-delta technology. Sigma-delta
ADCs include on-chip digital filtering and, thus, the system
filtering requirements are eased.
The on-chip control register is programmed using the SCLK,
SDATA and TFS pins. Three bits of the Control Register set
the digital filter cutoff frequency for the device. Selectable fre-
quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A
further 2 bits appear as outputs DOUT1 and DOUT2 and can be
used for controlling calibration at the front end. The device is
available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin
PLCC.
Three address pins program the device address. This allows a
data acquisition system with up to 32 channels to be set up in a
simple fashion. The output word from the device contains 32
bits of data. One bit is determined by the state of the DIN1 in-
put and may be used, for example, in an ECG system with an
external pacemaker detect circuit to indicate that the output
word is invalid because of the presence of a pacemaker pulse.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7716–SPECIFICATIONS1, 2
(fCLKIN = 8 MHz; MODE Pin Is High (Slave Mode Operation); AVDD = DVDD = +5 V
؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V; VREF = 2.5 V; Filter Cutoff = 146 Hz; Noise Measurement Bandwidth = 146 Hz; AIN Source
Resistance = 750 ⍀2 with 1 nF to AGND at each AIN. TA = TMIN to TMAX, unless otherwise noted.)
Parameter
B Version
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Integral Linearity Error
22
Bits
0.003
0.006
1
0.5
30
0.2
0.1
4
% FSR typ
% FSR max
% FSR max
% FSR max
µV/°C typ
% FSR max
% FSR max
µV/°C typ
µV rms max
Guaranteed No Missed Codes to 21 Bits3
Gain Error
Gain Match Between Channels
Gain TC
Offset Error
Offset Match Between Channels
Offset TC
Noise
11
See Table I for Typical Noise Performance vs. Programmed
Cutoff Frequency
DYNAMIC PERFORMANCE
Sampling Rate
f
CLKIN/14
570 kHz for fCLKIN = 8 MHz
N Is Decimal Equivalent of FC2, FC1, FC0 in Control Register
Output Update Rate
Filter Cutoff Frequency
Settling Time
fCLKIN/(14 ϫ 256 ϫ 2N)
fCLKIN/(3.81 ϫ 14 ϫ 256 ϫ 2N)
(3 ϫ 14 ϫ 256 ϫ 2N/fCLKIN
)
Usable Dynamic Range4
Total Harmonic Distortion
See Table I
–90
dB typ
dB typ
Input Frequency = 35 Hz
AIN = ±10 mV p-p
–100
Absolute Group Delay3
(3 ϫ 14 ϫ 256 ϫ 2N)/2fCLKIN
Differential Group Delay3
Channel-to-Channel Isolation
10
–85
ns typ
dB typ
Feedthrough from Any One Channel to the Other Three, with
35 Hz Full-Scale Sine Wave Applied to that Channel
ANALOG INPUT
Input Range
Input Capacitance
Input Bias Current
±2.5
10
1
Volts
pF typ
nA typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIN, Input Current
SDATA, RFS
2.4
0.8
V min
V max
+10/-130
+10/-650
±10
µA max
µA max
µA max
pF max
Internal 50 kΩ Pull-Up Resistors
Internal 10 kΩ Pull-Up Resistor
TFS
All Other Inputs
CIN, Input Capacitance3
10
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
2.4
0.4
V min
V max
|IOUT| ≤ 40 µA
|IOUT| ≤ 1.6 mA
POWER SUPPLIES
Reference Input
AVDD
DVDD
AVSS
2.4/2.6
4.75/5.25
4.75/5.25
–4.75/–5.25
7.5
V min/V max
V min/V max
V min/V max
V min/V max
mA max
IDD
4.8 mA typ
1.8 mA typ
35 mW typ
ISS
2.5
50
–70
mA max
mW max
dB typ
Power Consumption
Power Supply Rejection5
NOTES
1Operating temperature ranges as follows : B Version; –40°C to +85°C.
2The AIN pins present a very high impedance dynamic load which varies with clock frequency.
3Guaranteed by design and characterization. Digital filter has linear phase.
4Usable dynamic range is guaranteed by measuring noise and relating this to the full-scale input range.
5100 mV p-p, 120 Hz sine wave applied to each supply.
Specifications subject to change without notice.
–2–
REV. A
AD7716
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
Programmed Cutoff Output Update Usable Dynamic RMS Noise Filter Settling Time to Absolute Group
N
Frequency (Hz)
Rate (Hz)
Range (dB)
(V)
؎0.0007% FS (ms)
Delay (ms)
0
1
2
3
4
584
292
146
73
2232
1116
558
279
140
99
21
14
10
7
1.35
2.7
5.4
10.8
21.6
0.675
1.35
2.7
5.4
10.8
102
105
108
111
36.5
5
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND =
DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Limit at TMIN, TMAX
(B Version)
Parameter
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
1/fCLKIN
77
30
20
10
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Period
SCLK Width
TFS Setup Time
SDATA Setup Time
SDATA Hold Time
TFS Hold Time
20
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figure 2.
3CLKIN Duty Cycle range is 40% to 60%.
I
1.6mA
OL
TO
OUTPUT
PIN
+2.1V
C
L
50pF
I
200µA
OH
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
t
2
t
1
SCLK (I)
TFS (I)
t
2
t
6
t
3
t
4
t
5
DB0
(DB8)
DB1
(DB9)
DB2
(DB10)
DB3
(DB11)
DB4
(DB12)
DB5
(DB13)
DB6
(DB14)
DB7
(DB15)
SDATA (I)
Figure 2. Control Register Timing Diagram
REV. A
–3–
AD7716
MASTER MODE TIMING CHARACTERISTICS1, 2
(AVDD = DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Limit at TMIN, TMAX
(B Version)
Parameter
Units
Conditions/Comments
3, 4
fCLKIN
400
8
40
40
1/fCLKIN
1/fCLKIN
1/2fCLKIN + 30
50
40
50
1/fCLKIN
40
1/fCLKIN
45
1/2fCLKIN + 50
1/2fCLKIN + 10
1/2fCLKIN + 60
50
kHz min
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns
CLKIN Frequency
tr5
tf5
t7
t8
t9
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
CASCIN to DRDY Setup Time
DRDY Low to SCLK Low Delay
CLKIN High to DRDY Low, SCLK Active, RFS Active
CLKIN High to SCLK High Delay
SCLK Width
SCLK Period
SCLK High to RFS High Delay
RFS Pulse Width
SCLK High to SDATA Valid Delay
SCLK Low to SDATA High Impedance Delay
t10
t11
t12
t13
t14
t15
ns max
ns
6
t16
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns
7
t17
t18
t19
CLKIN High to DRDY High Delay
CLKIN High to RFS High Impedance, SCLK High Impedance
20
t20
t21
1/2fCLKIN + 50
2/fCLKIN
SCLK Low to CASCOUT High Delay
CASCOUT Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 3.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
5Specified using 10% and 90% points on waveform of interest.
6t16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
t7
CASCIN (I)
t8
CLKIN (I)
t9
t18
t11
DRDY (O)
SCLK (O)
t19
t10
t12
t13
t12
t14
t19
t15
RFS (O)
t17
DB0
t16
DB31
CH1
DB30
CH1
DB29
CH1
DB25
CH1
DB24
CH1
DB23
CH1
DB2
CH4
DB1
CH4
SDATA (O)
CH4
t21
t20
CASCOUT (O)
Figure 3. Master Mode Timing Diagram
–4–
REV. A
AD7716
SLAVE MODE TIMING CHARACTERISTICS1, 2
(AVDD = DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
(B Version)
Units
Conditions/Comments
3, 4
fCLKIN
400
8
40
40
1/fCLKIN
50
125
1/fCLKIN +30
30
50
50
50
0
60
2/fCLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns max
CLKIN Frequency
tr5
tf5
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
SCLK Width
SCLK Period
CASCIN High to RFS Setup Time
RFS Low to SCLK High Setup Time
SCLK High to SDATA Valid Delay
RFS Hold Time After SCLK High
SCLK High to SDATA High Impedance Delay
t23
t24
t25
t26
t27
6
t28
t29
t30
7
t31
t32
SCLK High to CASCOUT High Delay.
CASCOUT Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 4.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
t23
CASCIN (I)
t24
t25
SCLK (I)
t24
t26
t29
t27
RFS (I)
t28
t30
DB31
CH1
DB30
CH1
DB29
CH1
DB27
CH1
DB2
CH4
DB0
CH4
DB28
CH1
DB1
CH4
SDATA (O)
t32
t31
CASCOUT (O)
Figure 4. Slave Mode Timing Diagram
REV. A
–5–
AD7716
ABSOLUTE MAXIMUM RATINGS1
PQFP Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . .500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Lead Temperature, Soldering
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Inputs to AGND . . . . . . AVSS – 0.3 V to AVDD + 0.3 V
VREF to AGND . . . . . . . . . . . .AVSS – 0.3 V to AVDD + 0.3 V
Digital Inputs to DGND2 . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
Commercial Plastic (B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PLCC PINOUT
PQFP PINOUT
6
5
4
3
2
1
44 43 42 41 40
NC
NC
1
7
8
9
39 MODE
38 NC
NC
NC
1
33 MODE
32 NC
D
OUT
37 NC
2
3
D
1
OUT
31 NC
DGND 10
NC 11
36 DV
DD
30 DV
DD
DGND
NC
4
5
6
7
8
9
35
D 1
IN
AD7716
TOP VIEW
(Not to Scale)
29 D
1
IN
AD7716
TOP VIEW
(Not to Scale)
RFS 12
34 NC
28 NC
RFS
SCLK 13
RESET 14
AGND 15
33 CASCIN
27 CASCIN
SCLK
RESET
AGND
32 CASCOUT
26 CASCOUT
31
V
REF
25 V
REF
24 AV
AV 10
SS
AV
16
17
30 AV
DD
DD
SS
A
IN
1 11
23 AGND
A
IN
1
29 AGND
18 19
21 22
24 25 26
28
27
20
23
NC = NO CONNECT
NC = NO CONNECT
ORDERING GUIDE
Temperature
Range
Output Noise
(Filter: 146 Hz)
Package
Option*
Model
AD7716BP
AD7716BS
–40°C to +85°C
–40°C to +85°C
11 µV rms
11 µV rms
P-44A
S-44
*P = PLCC (Plastic Leaded Chip Carrier); S = PQFP (Plastic Quad Flatpack).
–6–
REV. A
AD7716
PIN DESCRIPTION
Pin
Description
AVDD
Analog Positive Supply, +5 V Nominal. This supplies +ve power to the analog modulators. AVDD & DVDD
must be tied together externally.
DVDD
AVSS
Digital Positive Supply, +5 V Nominal. This supplies +ve power to the digital filter and input/output registers.
Analog Negative Supply, –5 V nominal. This supplies –ve power to the analog modulators.
RESET
A high pulse on this input pin synchronizes the sampling point on the four input channels. It can be used in a
multichannel system to ensure simultaneous sampling. This also resets the digital interface to a known state.
The three address input pins, A0, A1 and A2 give the device a unique address. This information is contained in
the output data stream from the device.
A0–A2
CLKIN
Clock Input for External Clock.
CLKOUT
Clock Output which is used to generate an internal master clock by connecting a crystal between CLKOUT and
CLKIN. If an external clock is used then CLKOUT is not connected.
MODE
This digital input determines the device interface mode. If it is hardwired low, then the Master Mode interface is
enabled whereas if it is high, the Slave Mode interface is enabled.
CASCIN
CASCOUT
This is an active-high, level-triggered digital input which is used to enable the output data stream. This input
may be used to cascade several devices in a multichannel system.
Digital output which goes high at the end of a complete 4-channel data transfer. This can be connected to the
CASCIN of the next device in a multichannel system to ensure proper control of the data transfer.
RFS
Receive Frame Synchronization signal for the serial output data stream. This can be an input or output depending
on the interface mode.
SDATA
SCLK
Serial Data Input/Output Pin.
Serial Clock Input/Output. The SCLK pin is configured as an input or output, depending on the state of the
Mode pin.
DRDY
Data Ready Output. A falling edge indicates that a new word is available for transmission. It will return high
when 4, 32-bit words have been transmitted. It also goes high for one clock cycle, when a new word is being
loaded into the output register. Data should not be read during this period.
TFS
Transmit Frame Sync input for programming the on-chip Control Register.
DIN1
Digital Data Input. This is contained in the digital data stream sent from the device.
D
OUT1, DOUT
2
Digital Outputs. These two digital outputs can be programmed from the on-chip Control Register. They can
be used to control calibration signals at the front end.
VREF
Reference Input, Nominally 2.5 V.
AGND
DGND
AIN1–AIN
Analog Ground. Ground reference for analog circuitry.
Digital Ground. Ground return for digital circuitry.
Analog Input Pins. The analog input range is ±2.5 V.
4
REV. A
–7–
AD7716
OUTPUT UPDATE RATE
TERMINOLOGY
This is the rate at which the digital filter updates the output shift
register. It is a function of the master clock frequency and the
programmed filter cutoff frequency.
LINEARITY ERROR
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with Bipolar Zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full scale, a point
0.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full
scale.
FILTER CUTOFF FREQUENCY
The digital filter of the AD7716 can be programmed, in binary
steps, to 5 discrete cutoff frequencies, ranging from 584 Hz to
36.5 Hz (for a CLKIN frequency of 8 MHz).
SETTLING TIME
This is the settling time of the on-chip digital filter, to 0.0007%
of FSR, in response to a full-scale step at the input of the ADC.
It is proportional to the master clock frequency and the filter
cutoff frequency.
DIFFERENTIAL LINEARITY ERROR/NO MISSED CODES
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees no missed codes to the full resolution of the device.
The AD7716 has no missed codes guaranteed to 21 bits with a
cutoff frequency of 146 Hz.
USABLE DYNAMIC RANGE
The usable dynamic range is the ratio of the rms full-scale
reading (sine wave input) to the rms noise of the converter,
expressed in dBs. It determines the level to which it is possible
to resolve the input signal. For example, at a bandwidth of
146 Hz, the rms noise of the converter is 11 µV. The full-scale
rms is 1.77 volts. So, the usable dynamic range is 104 dB. Any
signal below this level will be indistinguishable from noise unless
extra post-filtering techniques are employed.
GAIN ERROR
Gain Error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 1) from the ideal (VREF –3/2 LSBs). It
is expressed as a percentage of full scale.
GAIN TC
This is the variation of gain error with temperature and is ex-
pressed in µV/°C.
TOTAL HARMONIC DISTORTION
Total harmonic distortion (THD) is the ratio of the rms sum
of the harmonics to the fundamental. For the AD7716, it is
defined as:
OFFSET ERROR
Offset Error is the deviation of the first code transition from the
ideal (–VREF + 0.5 LSB). It is expressed as a percentage of full
scale.
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD (dB) = 20 log
V1
OFFSET TC
This is the variation of offset error with temperature and is ex-
pressed in µV/°C.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through
sixth harmonics.
NOISE
This is the converter rms noise expressed in µV. Because of the
digital filtering in the sigma delta converter, the noise perfor-
mance is a function of the programmed filter cutoff.
ABSOLUTE GROUP DELAY
Absolute group delay is the rate of change of phase versus fre-
quency, dφ/df and is expressed in seconds. For the AD7716,
it is dependent on master clock frequency and filter cutoff
frequency.
SAMPLING RATE
This is the modulator sampling rate. For the AD7716, it is
fCLKIN/14.
DIFFERENTIAL GROUP DELAY
Differential group delay is the total variation in absolute group
delay in the specified bandwidth. Since the digital filter in the
AD7716 has perfectly linear phase, the differential group delay
is almost zero. This is important in many signal processing ap-
plications where excessive differential group delay can cause
phase distortion.
–8–
REV. A
AD7716
GENERAL DESCRIPTION
The output of the comparator provides the digital input for the
1-bit DAC, so the system functions as a negative feedback loop
which minimizes the difference signal. The digital data that rep-
resents the analog input voltage is in the duty cycle of the pulse
train appearing at the output of the comparator. It can be re-
trieved as a parallel binary data word using a digital filter.
The AD7716 is a 4-channel 22-bit A/D converter with on-chip
digital filtering, intended for the measurement of wide dynamic
range, low frequency signals such as those representing ECG,
EEG, chemical, physical or biological processes. It contains
four sigma delta ADCs, a clock oscillator and a serial communi-
cations port.
C
CLOCK
Each of the analog input signals to the AD7716 is continuously
sampled at a rate determined by the frequency of the master
clock, CLKIN. Four sigma-delta modulators convert the
sampled signals into digital pulse trains whose duty cycles con-
tain the digital information. These are followed by low-pass fil-
ters to process the output of the modulators and update the
output register at a maximum rate of 2.2 kHz. The output data
can be read from the serial port at any rate up to this.
R
A
IN
EN
TO
DIGITAL
FILTER
INTEGRATOR
STROBED
COMPARATOR
R
+V
–V
REF
REF
1-BIT DAC
THEORY OF OPERATION
The general block diagram of a delta-sigma ADC is shown in
Figure 5. It contains the following elements:
Figure 5. First Order Modulator
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 5. This contains only a first-
order low-pass filter or integrator.
1. Continuously Sampling Integrator
2. A Differential Amplifier or Subtracter
3. A 1-Bit A/D Converter (Comparator)
4. A 1-Bit DAC
The AD7716 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up or if there is a step change in the input
voltage, there is a settling time before valid data is obtained.
5. A Digital Low-Pass Filter
In operation, the sampled analog signal is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, whose output samples the differ-
ence signal at a frequency many times that of the analog signal
frequency (oversampling).
DIGITAL FILTERING
The AD7716’s digital filter behaves like an analog filter, with a
few minor differences.
First, since digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion pro-
cess. Analog filtering cannot do this.
Oversampling is fundamental to the operation of delta-sigma
ADCs. Using the quantization noise formula for an ADC:
SNR = (6.02 ϫ number of bits + 1.76) dB,
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. If noise signals cause the input signal to exceed
the specified range, consideration should be given to analog in-
put filtering, or to reducing the gain in the input channel to
bring the combination of signal and noise spike within the speci-
fied input range.
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
When operating with a master clock of 8 MHz, the AD7716
samples the input signal at 570 kHz, which spreads the quanti-
zation noise from 0 kHz to 285 kHz. Since the specified analog
input bandwidth of the AD7716 is only 584 Hz maximum (it
can be programmed to be lower), the noise energy in this band-
width would be only 1/488 of the total quantization noise, as-
suming that the noise energy was spread evenly throughout the
spectrum. This very high sampling with respect to the input
bandwidth is known as oversampling, and the ratio of 488:1 is
called the oversampling ratio. The noise is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies above 584 Hz. The SNR performance in the 0 Hz
to 584 Hz range is conditioned to the 99 dB level in this fashion
(see Table I). As the programmed bandwidth is reduced, the
oversampling ratio increases and the usable dynamic range also
increases. Thus, for example, with a programmed bandwidth
of 73 Hz, the oversampling ratio is 3904:1, and the usable dy-
namic range is 108 dB which corresponds to greater than 17-bit
resolution.
Filter Characteristics
The cutoff frequency of the digital filter is determined by bits
FC2, FC1 and FC0 in the control register (See Table IV). The
cutoff frequency of the filter is fCLKIN /(3.81 ϫ 14 ϫ 256 ϫ 2N),
where N is the decimal equivalent of FC2, FC1, FC0. At the
maximum clock frequency of 8 MHz, with all 0s loaded to FC2,
FC1, FC0, the cutoff frequency of the filter is 584 Hz and the
data update rate is 2232 Hz.
Since the AD7716 contains low-pass filtering, there is a settling
time associated with step function inputs, and data will be in-
valid after a step change until the settling time has elapsed. The
REV. A
–9–
AD7716
relationship between input bandwidth and settling is given in
Table I. Because of this settling time, most sigma delta ADCs
are unsuitable for high speed multiplexing, where channels are
switched and converted sequentially at high rates, as switching
between channels can cause a step change in the input. How-
ever, the AD7716 is a sigma-delta solution to multichannel ap-
plications, since it can process four channels simultaneously. In
addition, it is easy to cascade several devices in order to increase
the number of channels being processed.
Post Filtering
In the AD7716, the on-chip modulator provides the digital filter
with samples at a rate of 570 kHz. The filter decimates these
samples to provide data at an output rate which corresponds to
the programmed first notch frequency of the filter.
If the user wants to reduce the output noise from the device for
bandwidths less than 36.5 Hz, then it is possible to employ extra
filtering after the AD7716. This extra digital filtering is called
post filtering. If a straight averaging filter is used, for example, a
reduction in bandwidth by a factor of 2 results in √2 reduction
in the rms noise. This additional filtering will also result in a
longer settling time.
0
–20
–40
Antialias Considerations
–60
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sampling frequency (n ϫ 570 kHz,
where n = 1, 2, 3, . . .). This means that there are frequency
bands, ±f3dB wide (f3dB is the cutoff frequency selected by FC0
to FC2) where noise passes unattenuated to the output. How-
ever, due to the AD7716’s high oversampling ratio, these bands
occupy only a small fraction of the spectrum and most broad-
band noise is filtered.
–80
–100
–120
–140
–160
–180
–200
–220
–240
In spectral analysis applications, it is important to note that at-
tenuation at half the output update rate is 16 dB. Extra front-
end filtering or post filtering may be required to keep aliases in
this frequency band at an acceptable level.
0
73
278
556
834
1112
1390
1668
FREQUENCY – Hz
Figure 6. Frequency Response of AD7716 Filter
USING THE AD7716
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 73 Hz. This is a (sinx/x)3 response (also called sinc3)
that provides greater than 100 dB rejection at the notch fre-
quencies. The relationship between the programmed cutoff
frequency and the first notch is constant (fNOTCH = 3.81 ϫ
fCUTOFF). The first notch frequency is also the output data rate.
The settling time to a full-scale step input is four times the out-
put data period. Programming a different cutoff frequency via
FC0–FC2 does not alter the profile of the filter response, it sim-
ply changes the frequency of the notches.
SYSTEM DESIGN CONSIDERATIONS
The AD7716 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the sig-
nal continuously, like a tracking ADC, there is no need for a
start convert command. The output register is updated at a rate
dependent on the programmed cutoff frequency, and the output
can be read at any time.
Input Signal Conditioning
The input range for the AD7716 is ±VREF, where VREF = 2.5 V
± 10%. Other input ranges can be accommodated by input sig-
nal conditioning. This may take the form of gain to increase a
smaller signal range, or passive attenuation to reduce a larger in-
put voltage range.
In Figure 6, the first notch is at 278 Hz. This is also the output
data rate. Settling time to a full-scale step input is 10.8 ms.
The digital filter can be defined by the following equations.
3
1
N
1– Z –N
1– Z –1
H (z)=
×
sinπf/fS ) 3
πf/fS )
H ( f ) =
where N = Ratio of Modulator Sampling Frequency to Output
Rate
and
fS = Output Rate.
–10–
REV. A
AD7716
–0.125
–0.25
Source Resistance
If passive attenuators are used in front of the AD7716, care
must be taken to ensure that the source impedance is suffi-
ciently low. The dc input resistance for the AD7716 is greater
than 1 GΩ. In parallel with this there is a small sampling ca-
pacitor. The dynamic load presented by this varies with the
clock frequency. The modulator sampling rate determines the
amount of time available for the sampling capacitor to be
charged. Any extra external impedances result in a longer over-
all charge time resulting in extra gain errors on the analog input.
The AD7716 has a quite large gain error (1% FSR) due to the
fact that there is no on-chip calibration. Thus, even an extra
10 kΩ source resistance and 50 pF source capacitance will have
no significant effect on this.
–0.375
–0.500
–0.625
20
30
40
50
60
70
80
90
TEMPERATURE – °C
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their
open-loop output resistance is normally only tens of ohms and,
in any case, most modern general purpose op amps have
sufficiently fast closed-loop settling time for this not to be a
problem.
Figure 7. Typical Offset Drift
Voltage Reference
The voltage applied to the VREF pin defines the analog input
range. The specified reference voltage is 2.5 V ± 10%.
Accuracy
The reference input presents exactly the same dynamic load as
the analog input, but in the case of the reference input, source
resistance and long settling time introduce gain errors rather
than offset errors. Most precision references however have suffi-
ciently low output impedance and wide enough bandwidth to
settle to the required accuracy in the time allowed by the
AD7716.
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance.
The AD7716 achieves excellent linearity by the use of high
quality, on-chip silicon dioxide capacitors, which have a very
low capacitance/voltage coefficient.
The reference should be chosen to have minimal noise in the
programmed passband. Recommended references are the
AD780 or the REF43 from Analog Devices. These low noise
references have typical noise spectral densities of 100 nV/√Hz at
600 Hz. This corresponds to an rms noise of 2.5 µV in this
band and is more than adequate for the AD7716.
Drift Considerations
The AD7716 uses autozeroing techniques to minimize input
offset drift. Charge injection in the analog switches and leakage
currents at the sampling node are the primary sources of offset
voltage drift in the converter. Figure 7 indicates the typical off-
set due to temperature changes. Drift is relatively flat up to
85°C. Above this temperature, leakage current becomes the
main source of offset drift. Since leakage current doubles ap-
proximately every 10°C, the offset drifts accordingly. The value
of the voltage on the sample capacitor is updated at a rate deter-
mined by the master clock, therefore the amount of offset drift
which occurs will be proportional to the elapsed time between
samples.
Clock Generation
The device operates from a master clock which must be pro-
vided either from a crystal source or an external clock source. If
a crystal is used, it must be connected across the CLKIN and
CLKOUT pins. Typical loading capacitors of 15 pF are re-
quired on CLKIN, CLKOUT. The crystal manufacturers data
should be consulted for more information. An external clock
can also be used to drive the CLKIN input directly with a
CMOS compatible clock. In this case, CLKOUT is left uncon-
nected. The nominal clock frequency for the device is 8 MHz.
Gain drift within the converter depends mainly upon the tem-
perature tracking of the internal capacitors. It is not affected by
leakage currents.
REV. A
–11–
AD7716
CONTROL REGISTER DESCRIPTION
Control register bit, DB15 (A3), acts as an extra address bit
which must always be set to 1 to enable programming of the
AD7716. If it is set to 0, then the programmed word is ignored.
This allows the user to bypass the AD7716 control register and
use the serial stream from the DSP or microcomputer to pro-
gram other serial peripheral devices.
The 16-bit control register is programmed in two 8-bit bytes;
the low byte is programmed first and the high byte second. The
loading format is LSB first (DB0 for the Least Significant Byte;
DB8 for the Most Significant Byte). Three control lines are
used: TFS, SCLK and SDATA. On initial application of
power to the AD7716, the control register will come up in an
undetermined state. Programming the control register requires
an SCLK input, a TFS input and an SDATA input. The
MODE pin on the device determines whether it is in the master
interface mode or the slave interface mode. In either mode, a
falling edge on TFS causes the part to relinquish control of the
SDATA and SCLK lines. When TFS goes low, data on the
SDATA line is clocked into the control register on each suc-
ceeding falling edge of SCLK. When 8 bits have been clocked
in, the transfer automatically stops. Only when another negative
going edge is detected on TFS will new information be written
into the control register. The control register programming
model is shown in Table II. Bits DB8 and DB0 allow the con-
trol register to identify whether the MS Byte or the LS Byte has
been programmed. Only when DB8 is a 1 and DB0 is a 0 will
the register recognize that a complete valid word has been
programmed.
When a valid word has been received, the device interrogates
the M0 bit. If this is 0, then the digital filter cutoff frequencies
are programmed to the appropriate value if the device address
pins correspond to the A2, A1, A0 bits in the control register. If
the device address pins do not correspond to the A2, A1, A0
bits then the FC2, FC1, FC0 bits are ignored. If M0 is 1, then
the digital filter cutoff frequencies are programmed to the FC2,
FC1, FC0 value irrespective of the address bits. In a multi-
channel system this allows the user to either program all
AD7716s to have the same cutoff frequency or else to give each
device a separate cutoff frequency.
Control register bits FC2, FC1, FC0 program the digital filter
cutoff frequency, see Table VI.
Control register bits D2, D1 control the digital output pins D2
and D1. These are programmed in the same way as FC2, FC1,
FC0.
Table II. Control Register Programming Model
Most Significant Byte
Least Significant Byte
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4 DB3
DB2 DB1
DB0
A3
A2
A1
A0
M0
FC2
FC1
1
FC0
DOUT2 DOUT1
X
X
X
X
0
Table IV. Cutoff Frequency Truth Table
Table III. M0 Truth Table
Programming Mode
FC2
FC1
FC0
Cutoff Frequency (Hz)
M0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
584
292
146
73
0
A2, A1, A0 determine which device is addressed and
programmed with cutoff frequency and digital output.
A2, A1, A0 ignored. All devices are addressed and
programmed with common cutoff frequency and digital
output.
1
36.6
–12–
REV. A
AD7716
RESET
Master Mode Interface
The AD7716 has a hardware reset which can be used to synchro-
nize many devices. When the RESET pin goes low after being
high for at least four CLKIN cycles, the modulator sampling
points and digital filter starting points are all synchronized. This
synchronizes all devices which receive the RESET pulse and
gives simultaneous sampling of all channels. It does not affect
the control register but restarts the interface. Also, it is necessary
to wait the requisite settling time after applying Reset to get valid
data from the device.
The device may be placed in the Master Mode by tying the
MODE pin low. In this mode, data is clocked out of the
AD7716 by an internally generated serial clock and frame syn-
chronization pulse. Two signals initiate the transfer. These are
the input CASCIN and the internally generated DRDY signal.
When a high level is detected on CASCIN, the device checks
the state of DRDY. Note, that on initial power-up or after a re-
set has been applied, the CASCIN input is not necessary on de-
vice 000 for the first data transfer but is required thereafter. If
DRDY is low, then the 3-state output, RFS goes high on the
next rising edge of CLKIN and stays high for one CLKIN cycle
before going low again. The 3-state SCLK output is also acti-
vated on the same rising edge. As RFS goes low, DB31 is
clocked out on the rising edge of SCLK and is valid on the fall-
ing edge of SCLK. Data is transmitted in 8-bit bytes. For each
AIN, there are 4, 8-bit bytes and 4 RFS pulses. When DB0 of
AIN 4 has been clocked out, SCLK goes back into 3-state and
the CASCOUT output goes high for one master clock cycle.
DRDY also goes high at this point. Successive devices can be
networked together by tying the CASCOUT of one device to
the CASCIN on the next one.
CASCADING DEVICES
The AD7716 provides a facility for connecting multiple devices
in series. The CASCIN and CASCOUT pins allow this. Con-
necting CASCOUT to CASCIN of the succeeding device means
that the SDATA output of the second device will be disabled un-
til the output register of the first device is empty.
In the case of the first device in the system, it is possible to drive
CASCIN from CASCOUT of the last device or, alternatively,
invert DRDY to drive it. If CASCIN is driven by CASCOUT,
then a reset must be applied after every write to the control
register. This also applies in single device systems that use
CASCOUT to drive CASCIN
Note that on device 0 (A2, A1, A0 tied low), the CASCIN input
should be driven by the inverse of the DRDY output. This is
shown in the interface diagram of Figure 8.
DATA OUTPUT INTERFACE MODES
When the control register has been programmed, the device be-
gins conversion. There is an initial delay to allow the digital fil-
ters to settle. As already stated, these filters are Sinc3, and so the
filter output update rate is directly related to the programmed
cutoff frequency. The ratio between these is 3.81. So, for a filter
cutoff frequency of 584 Hz, the output update is 2.22 kHz. The
falling edge of the DRDY output indicates that the output shift
register has been updated. There are two interface modes. One
is the master mode, where the AD7716 is the master in the sys-
tem and the processor to which it is communicating is the slave.
The other mode is the slave mode, where the AD7716 is the
slave and the processor is the system master. In both of these
modes the data output stream contains 4 ϫ 32 bits, correspond-
ing to the four input channels. The output data format is given
in Table V. The conversion result DB21–DB0 occupies location
DB31–DB10 of the output register. DB21 is the MSB and is
transmitted first as shown in the timing diagrams. The channel
address is given by CA0 and CA1 which occupy DB9 and DB8
of the output register. The channel address format is given in
Table VI.
The Master Mode interface is very suitable for loading data into
a serial-to-parallel shift register or for DSPs which can accept a
continuous stream of 8-bit bytes.
Slave Mode Interface
The device may be placed in the slave interface mode by tying
the MODE pin high. In this mode, the master processor con-
trols the transfer of data from the signal processing block. It
starts the transfer by sending a frame synchronizations pulse and
serial clock to the AD7716. This could be in response to an in-
terrupt generated by the DRDY output on the AD7716. If the
device has detected a high level on CASCIN or is device 000 on
its first transfer, it starts to send out data on the next rising edge
of SCLK. This data is then valid on the falling edge of SCLK.
When all the data bits have been clocked out, the CASCOUT
pin goes high for one CLKIN cycle and DRDY also goes high.
The slave mode interface is suited to both microcomputers like
the 8051 and 68HC11 and also DSPs like the TMS320C25,
ADSP-2101 family and the DSP56000 family.
Table V. Output Data Word Format
DB31 . . . DB10
DB9
DB8
DB7
A0
DB6 DB5
A1 A2
DB4
DIN1
DB3
DB2
DB1 DB0
DB21 . . . DB0
CA0
CA1
OVFL
X
X
X
Conversion Result
Channel Address
Device Address
Pace Detect
Overflow
Indeterminate
Table VI. Channel Address Format
CA1 (DB8)
Channel
CA0 (DB9)
AIN
AIN
AIN
AIN
1
2
3
4
0
0
1
1
0
1
0
1
REV. A
–13–
AD7716
MICROPROCESSOR INTERFACING
The SPORT0 Control Register setting is “7FCF.” This sets the
receive section for internal SCLK, continuous receive with al-
ternate inverted framing.
Interfacing the AD7716 to the ADSP-2100 Family
The ADSP-2100 family of microcomputers from Analog De-
vices are high speed, high performance digital signal processors.
Many members of the family have serial ports (known as
SPORTs) which are compatible with the AD7716. These in-
clude the ADSP-2101, ADSP-2105, ADSP-2111 and ADSP-
2115. Full details of these are available in the ADSP-2100
Family User’s Manual available from Analog Devices.
The SPORT0 SCLKDIV Register (0 ϫ 3FF5) determines the
SCLK frequency from the ADSP-2101. With “0000” loaded,
the SCLK output is at its maximum (1/2 the master clock of
12.5 MHz).
In normal operation, a SPORT generates an interrupt when it
has received a data word. Autobuffering provides a mechanism
for receiving or transmitting an entire block of serial data before
an interrupt is generated. Service routines can operate on the
entire block of data, rather than on a single word, reducing over-
head significantly. This is ideal for use with a device like the
AD7716 where there is a requirement to read many bits of data
(256 in this case) for each sampling instant. The SPORT0
Autobuffer Control Register (0 ϫ 3FF3) is loaded with “0001”
to enable the Receive Autobuffering.
Figure 8 shows the hardware interface between two AD7716s
and SPORT 0 of the ADSP-2101 DSP. This yields a very effi-
cient 8-channel data acquisition system. The AD7716 is set up
for slave interface mode by tying the MODE pin high. This
means that the ADSP-2101 is the master in the system and sup-
plies the necessary frame synchronization and SCLK Signals to
the AD7716s when writing to and reading from the device.
On power up, the user should write to the AD7716 control reg-
ister in order to set the filter cutoff frequencies. The appropri-
ate SPORT 0 Control Register (0 ϫ 3FF6) setting is “7EC7.”
This sets the transmit section for alternate inverted framing with
a word length of 8 bits. Two 8-bit words should then be written
to each AD7716 to program the filter cutoff frequencies. The
control register programming model is given in Table II. Note
that the LSB (DB0) must be loaded first as in the timing dia-
gram of Figure 2.
The SPORT0 RFSDIV Register (0 ϫ 3FF4) should be set to
the minimum value of “000F.” Finally the IRQ2 interrupt
should be enabled.
The DSP will now wait for an interrupt from the AD7716. This
interrupt is generated by the AD7716 DRDY line going low. If
the interrupt service routine is set for autobuffered mode with a
length of 16 (16-bit) words, then the DSP will read in the 256
bits from the two AD7716s in one continuous stream and then
stop. The data from the two devices will be contained in the
designated data memory area and the DSP can now go and op-
erate on this as is necessary. Note that, because of the ADSP-
2101 framing, a one-bit shift left will be necessary on the data in
memory. For 16 data words, this will require 22 instruction
cycles.
When the write operation is complete, a reset pulse should be
applied to both devices. This ensures that the sampling and in-
terface timing of the device are synchronized. The reset can be
under DSP control, in which case a flag output could be used.
After reset, the processor should jump to the read routine. For
this read routine, there are several registers that need to be set.
+5V
A0 A1 A2
CASCIN
4.7kΩ
4.7kΩ
ADSP-2101
DRDY
IRQ2 (–VE EDGE TRIGGERED)
AD7716 #1
RFS
RFS
SCLK
SCLK
RESET
TFS
TFS
DT
SDATA
CASCOUT
CASCIN
MODE
+5V
DR
+5V
A0 A1
A2
SCLK
AD7716 #2
TFS
SDATA
RESET
CONTROL
RESET
DRDY
RFS
CASCOUT
MODE
+5V
Figure 8. 8-Channel Data Acquisition System Using the ADSP-2101 Digital Signal Processor
–14–
REV. A
AD7716
When the AD7716 is programmed for the maximum cutoff fre-
quency of 584 Hz, the output data rate is 2.25 kHz. This
means that there is 440 µs available to read the data and do the
necessary number crunching before the next sample must be
read. Assuming that the ADSP-2101 is running from a master
clock of 12.5 MHz means that the maximum SCLK available is
6.25 MHz (1/2 the master clock frequency). It will then take 40
µs to transfer the 256 bits of data from the ADC to the DSP.
This leaves 400 µs for number crunching in the DSP. If the
programmed cutoff frequency is lower then this allows even
more time to the DSP.
The optimum setup for reading all four channels of the AD7716
into the DSP56001 is six 24-bit reads. This will provide 144 clock
edges to shift out the 128 bits of data in the AD7716 output shift
register. The first clock applied to the AD7716 will clock out
DB21 of AIN1. DRDY from the AD7716 can be used as an
interrupt input to the DSP56001 to control the data transfer.
Either IRQA or IRQB of the DSP56001 can be used to detect the
interrupt.
RESET
CONTROL
+5V
MC68HC11 Interface
RESET
MODE
CASCIN
The MC68HC11 microcomputer can be interfaced to the
AD7716 using the slave mode interface. Figure 9 shows a typi-
cal setup. The MODE pin on the AD7716 is tied high for slave
mode operation. The SPI port of the MC68HC11 is used. The
microcomputer is in its single chip mode. DRDY from the
AD7716 is connected to the IRQ input of the MC68HC11.
MISO and MOSI on the MC68HC11 should be configured for
wired-or operation. Depending on the interface configuration,
it may be necessary to provide bidirectional buffers between
these lines.
SC2
SC1
SCK
SC0
STD
SRD
IRQ
TFS
RFS
SCLK
DSP56001
AD7716
SDATA
DRDY
CASCOUT
Figure 10. DSP56001 Interface
TMS320C25 Interface
+5V
+5V
CASCIN
Figure 11 shows the AD7716 interfaced to the TMS320C25
DSP using the master mode interface. For initial programming
of the AD7716 control register, the external gated clock is re-
quired. FSX going low enables this. When the two 8-bit bytes
have been sent to the AD7716, the FSX should go permanently
high. The external gated clock will now be disabled and the
AD7716 will take control of the SDATA line. It will begin
transmitting data as soon as it becomes available. It also pro-
vides the clock and frame synchronization signals required by
the DSP.
MODE
RFS
TFS
SS
PC0
PC1
DRDY
RESET
SCLK
AD7716
IRQ
MC68HC11
PC2
SCK
MISO
MOSI
SDATA
CASCOUT
Figure 9. MC68HC11 to AD7716 Interface
Reset for the AD7716 is provided by one of the DSP flag
outputs.
The MC68HC11 is configured in the master mode with its
CPOL bit set to a logic zero and its CPHA bit set to a logic one.
With an 8 MHz CLKIN input on the AD7716, the device will
operate with all four serial clock rates of the MC68HC11.
RESET CONTROL
FLAG
OUTPUT
Sixteen, 8-bit read operations are necessary to read the 128 bits
from the AD7716 output register. An extra read is necessary to
reset the output register. This means a total of 17 read opera-
tions are needed from the MC68HC11.
RESET CASCIN
AD7716
MODE
TMS320C25
FSR
RFS
DR
DT
SDATA
TFS
DSP56001 Interface
FSX
Figure 10 shows an interface to the DSP56001 digital signal
processor. The AD7716 is set up for the slave interface mode.
The DSP56001 is set up for asynchronous operation with gated
clock and normal framing. Data must be written to the
AD7716 control register in two 8-bit bytes. The first byte is
written to the DSP56001 SSI transmit data register (TX) and
this is automatically transferred to the transmit shift register
when the frame sync occurs. Data is shifted out to the STD pin
by the internal bit clock (SCK) when the associated frame sync
output is asserted.
SCLK
CLKR
CLKX
CASCOUT
GATED
CLOCK
EN
Figure 11. TMS320C25 to AD7716 Interface
REV. A
–15–
AD7716
Multibandwidth System
OUTLINE DIMENSIONS
Some applications may require multiple AD7716’s with differ-
ent bandwidths programmed to each device. The best way to
accomplish this is shown in Figure 12. The master mode inter-
face is used for this example but the slave mode may also be
used. The example shows an 8-channel system with Device #0
in the system programmed for a 292 Hz cutoff frequency and
Device #1 programmed for a 146 Hz cutoff frequency.
Dimensions shown in inches and (mm).
44-Lead PLCC
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
6
40
39
7
PIN 1
CASCIN
0.021 (0.53)
0.013 (0.33)
IDENTIFIER
0.048 (1.21)
0.042 (1.07)
TFS
#0
0.63 (16.00)
0.59 (14.99)
(292 Hz)
RFS
SCLK
SDATA
DRDY
0.032 (0.81)
TOP VIEW
0.026 (0.66)
RESET
RESET
CASCOUT MODE
0.050
(1.27)
BSC
29
28
17
18
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.656 (16.66)
0.650 (16.51)
CASCIN
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
#1
(146 Hz)
44-Lead Plastic Quad Flatpack
(S-44)
DRDY
RESET
MODE
0.557 (14.148)
0.537 (13.640)
0.096 (2.44)
MAX
0.398 (10.11)
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8
°
°
Figure 12. Multibandwidth System
0.8
33
23
22
The resultant output signals are also shown. Since Device #0
has a higher bandwidth it will also have a higher update rate.
The receiving processor will be getting samples from this device
at twice the rate of Device #1.
34
0.398 (10.11)
TOP VIEW
0.390 (9.91)
RESET
DRDY #0
DRDY #1
PIN 1
44
12
11
1
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.083 (2.11)
0.077 (1.96)
0.016 (0.41)
0.012 (0.30)
0.033 (0.84)
0.029 (0.74)
#0
#0 #1
#0
#0 #1
#0
#0 #1
SDATA
Figure 13. Output Signals for Figure 12
–16–
REV. A
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