AD7747ARUZ-REEL7 [ADI]
24-Bit Capacitance-to-Digital Converter with Temperature Sensor;
| 型号： | AD7747ARUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 24-Bit Capacitance-to-Digital Converter with Temperature Sensor 光电二极管 转换器 |
| 文件： | 总29页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24-Bit Capacitance-to-Digital Converter
with Temperature Sensor
AD7747
FEATURES
GENERAL DESCRIPTION
Capacitance-to-digital converter
New standard in single chip solutions
The AD7747 is a high-resolution, Σ-Δ capacitance-to-digital
converter (CDC). The capacitance to be measured is connected
Interfaces to single or differential grounded sensors
Resolution down to 20 aF (that is, up to 19.5-bit ENOB)
Accuracy: 10 fF
directly to the device inputs. The architecture features inherent
high resolution (24-bit no missing codes, up to 19.5-bit effective
resolution), high linearity (±±.±1%), and high accuracy (±1± fF
factory calibrated). The AD7747 capacitance input range is
±ꢀ pF (changing), and it can accept up to 17 pF common-mode
capacitance (not changing), which can be balanced by a program-
mable on-chip digital-to-capacitance converter (CAPDAC).
Linearity: 0.01%
Common-mode (not changing) capacitance up to 17 pF
Full-scale (changing) capacitance range 8 pF
Update rate: 5 Hz to 45 Hz
Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update
Active shield for shielding sensor connection
Temperature sensor on-chip
Resolution: 0.1°C, accuracy: 2°C
Voltage input channel
The AD7747 is designed for single-ended or differential
capacitive sensors with one plate connected to ground. For
floating (not grounded) capacitive sensors, the AD7745 or
AD7746 are recommended.
The part has an on-chip temperature sensor with a resolution of
±.1°C and accuracy of ±2°C. The on-chip voltage reference and
the on-chip clock generator eliminate the need for any external
components in capacitive sensor applications. The part has a
standard voltage input that, together with the differential reference
input, allows easy interface to an external temperature sensor,
such as an RTD, thermistor, or diode.
Internal clock oscillator
2-wire serial interface (I2C® compatible)
Power
2.7 V to 5.25 V single-supply operation
0.7 mA current consumption
Operating temperature: −40°C to +125°C
16-lead TSSOP package
The AD7747 has a 2-wire, I2C-compatible serial interface. The
part can operate with a single power supply of 2.7 V to 5.25 V.
It is specified over the automotive temperature range of
−4±°C to +125°C and is housed in a 16-lead TSSOP package.
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Proximity sensing
Level sensing
Flow metering
Impurity detection
FUNCTIONAL BLOCK DIAGRAM
VDD
TEMP
SENSOR
CLOCK
GENERATOR
AD7747
VIN(+)
2
VIN(–)
SDA
SCL
I C
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
MUX
SERIAL
INTERFACE
CIN1(+)
CIN1(–)
SHLD
CONTROL LOGIC
RDY
CALIBRATION
VOLTAGE
REFERENCE
CAP DAC 1
EXCITATION
CAP DAC 2
GND
REFIN(+)
REFIN(–)
Figure 1.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD7747* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
EVALUATION KITS
DESIGN RESOURCES
• AD7747 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AD7747 Evaluation Kit
DOCUMENTATION
Application Notes
• AN-1301: Using CDCs to Control Motion for Sample
Aspiration
Data Sheet
DISCUSSIONS
View all AD7747 EngineerZone Discussions.
• AD7747: 24-Bit Capacitance-to-Digital Converter with
Temperature Sensor Data Sheet
Product Highlight
SAMPLE AND BUY
Visit the product page to see pricing options.
• Leading Inside Advertorials: Providing an Edge in
Capacitive Sensor Applications
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7746 - Microcontroller No-OS Driver
• AD7746 IIO Capacitance to Digital Converter Linux Driver
DOCUMENT FEEDBACK
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AD7747
TABLE OF CONTENTS
Features .............................................................................................. 1
Cap DAC A Register .................................................................. 19
Cap DAC B Register................................................................... 19
Cap Offset Calibration Register ............................................... 2±
Cap Gain Calibration Register.................................................. 2±
Volt Gain Calibration Register ................................................. 2±
Circuit Description......................................................................... 21
Overview ..................................................................................... 21
Capacitance-to-Digital Converter............................................ 21
Active AC Shield Concept......................................................... 21
CAPDAC ..................................................................................... 21
Single-Ended Capacitive Configuration ................................. 22
Differential Capacitive Configuration..................................... 22
Parasitic Capacitance ................................................................. 23
Parasitic Resistance .................................................................... 23
Parasitic Serial Resistance ......................................................... 23
Capacitive Gain Calibration ..................................................... 23
Capacitive System Offset Calibration...................................... 24
Internal Temperature Sensor .................................................... 24
External Temperature Sensor ................................................... 24
Voltage Input............................................................................... 25
VDD Monitor................................................................................ 25
Typical Application Diagram.................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. ꢀ
Output Noise and Resolution Specifications .............................. 11
Serial Interface ................................................................................ 12
Read Operation........................................................................... 12
Write Operation.......................................................................... 12
AD7747 Reset.............................................................................. 13
General Call................................................................................. 13
Register Descriptions ..................................................................... 14
Status Register............................................................................. 15
Cap Data Register....................................................................... 15
VT Data Register ........................................................................ 15
Cap Setup Register ..................................................................... 16
VT Setup Register....................................................................... 16
EXC Setup Register .................................................................... 17
Configuration Register .............................................................. 1ꢀ
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7747
SPECIFICATIONS
VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = VDD × 3/8; −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
8.ꢀ12
Max
Unit
Test Conditions/Comments
CAPACITIVE INPUT
Conversion Input Range
Integral Nonlinearity (INL)2
No Missing Codes2
Resolution, p-p
pFꢀ
% of FSRꢀ
Bit
Bit
Factory calibrated
0.0ꢀ
24
Conversion time ≥ ꢀ24 ms
ꢀ6.5
ꢀ1.ꢀ
ꢀꢀ.0
Conversion time ꢀ24 ms, see Table 5
Conversion time ꢀ24 ms, see Table 5
Conversion time ꢀ24 ms, see Table 5
25°C, VDD = 5 V, after offset calibration
After system offset calibration,
excluding effect of noise4
Resolution Effective
Output Noise, rms
Absolute Error3
Bit
aF/√Hz
fFꢀ
aFꢀ
ꢀ0
32
Offset Error4, 5
System Offset Calibration Range5
Offset Deviation over Temperature2
Gain Error6
Gain Drift vs. Temperature2
Power Supply Rejection2
Normal Mode Rejection5
ꢀ
pF
fF
0.4
0.02
−26
0.5
72
See Figure 6
25°C, VDD = 5 V
0.ꢀꢀ
−21
4
% of FSꢀ
ppm of FS/°C
fF/V
dB
dB
−23
ꢀ7
50 Hz ꢀ%, conversion time ꢀ24 ms
60 Hz ꢀ%, conversion time ꢀ24 ms
60
CAPDAC
Full Range
Differential Nonlinearity (DNL)
Drift vs. Temperature2
EXCITATION
2ꢀ
0.3
26
pF
LSB
ppm of FS/°C
6-bit CAPDAC
See Figure ꢀ6
Frequency
ꢀ6
VDD × 3/8
VDD/2
kHz
V
V
AC Voltage Across Capacitance
Average DC Voltage Across Capacitance
TEMPERATURE SENSOR7
Resolution
To be configured via digital interface
VREF internal
0.ꢀ
0.5
2
°C
°C
°C
Error2
2
Internal temperature sensor
External sensing diode8
VREF internal or VREF = 2.5 V
VOLTAGE INPUT7
Differential VIN Voltage Range
Absolute VIN Voltage2
Integral Nonlinearity (INL)
No Missing Codes2
VREF
3
V
V
GND − 0.03
24
VDD + 0.03
ꢀ5
ppm of FS
Bit
Conversion time = ꢀ22.ꢀ ms
Resolution, p-p
ꢀ6
3
Bits
Conversion time = 62 ms,
see Table 6 and Table 7
Conversion time = 62 ms,
see Table 6 and Table 7
Output Noise
μV rms
Offset Error
Offset Drift vs. Temperature
Full-Scale Error2, 1
3
ꢀ5
0.025
5
μV
nV/°C
% of FS
0.ꢀ
Full-Scale Drift vs. Temperature
ppm of FS/°C Internal reference
0.5
300
50
80
10
ppm of FS/°C External reference
nA/V
pA/V/°C
Average VIN Input Current
Analog VIN Input Current Drift
Power Supply Rejection
dB
dB
Internal reference, VIN = VREF/2
External reference, VIN = VREF/2
Rev. 0 | Page 3 of 28
AD7747
Parameter
Min
Typ
75
50
Max
Unit
dB
dB
Test Conditions/Comments
50 Hz ꢀ%, conversion time = ꢀ22.ꢀ ms
60 Hz ꢀ%, conversion time = ꢀ22.ꢀ ms
VIN = ꢀ V
Normal Mode Rejection5
Common-Mode Rejection2
INTERNAL VOLTAGE REFERENCE
Voltage
15
dB
ꢀ.ꢀ61
ꢀ.ꢀ7
5
ꢀ.ꢀ7ꢀ
V
TA = 25°C
Drift vs. Temperature
ppm/°C
EXTERNAL VOLTAGE REFERENCE INPUT
Differential REFIN Voltage2
Absolute REFIN Voltage2
Average REFIN Input Current
Average REFIN Input Current Drift
Common-Mode Rejection
SERIAL INTERFACE LOGIC INPUTS (SCL, SDA)
VIH Input High Voltage
0.ꢀ
GND − 0.03
2.5
VDD
VDD + 0.03
V
V
400
50
80
nA/V
pA/V/°C
dB
2.ꢀ
V
VIL Input Low Voltage
Hysteresis
Input Leakage Current (SCL)
OPEN-DRAIN OUTPUT (SDA)
VOL Output Low Voltage
0.8
ꢀ
V
mV
μA
ꢀ50
0.ꢀ
0.4
ꢀ
V
μA
ISINK = −6.0 mA
VOUT = VDD
IOH Output High Leakage Current
0.ꢀ
RDY
LOGIC OUTPUT (
)
VOL Output Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
VOH Output High Voltage
POWER REQUIREMENTS
VDD-to-GND Voltage
0.4
0.4
V
V
V
V
ISINK = ꢀ.6 mA, VDD = 5 V
ISOURCE = 200 μA, VDD = 5 V
ISINK = ꢀ00 μA, VDD = 3 V
ISOURCE = ꢀ00 μA, VDD = 3 V
4.0
VDD − 0.6
4.75
2.7
5.25
3.6
850
V
V
μA
μA
μA
μA
VDD = 5 V, nominal
VDD = 3.3 V, nominal
Digital inputs equal to VDD or GND
VDD = 5 V
VDD = 3.3 V
Digital inputs equal to VDD or GND
IDD Current
750
700
0.5
IDD Current Power-Down Mode
2
ꢀ Capacitance units: ꢀ pF = ꢀ0−ꢀ2 F; ꢀ fF = ꢀ0−ꢀ5 F; ꢀ aF = ꢀ0−ꢀ8 F. Full scale (FS) = 8.ꢀ12 pF; full-scale range (FSR) = 8.ꢀ12 pF.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C.
At different temperatures, compensation for gain drift over temperature is required.
4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ꢀ pF; the larger
offset can be removed using CAPDACs.
5 Specification is not production tested, but guaranteed by design.
6 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
7 The VTCHOP bit in the VT SETUP register must be set to ꢀ for the specified temperature sensor and voltage input performance.
8 Using an external temperature sensing diode 2N3106, with nonideality factor nf = ꢀ.008, connected as in Figure 37, with total serial resistance <ꢀ00 Ω.
1 Full-scale error applies to both positive and negative full scale.
Rev. 0 | Page 4 of 28
AD7747
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = ± V; Input Logic ± = ± V; Input Logic 1 = VDD; −4±°C to +125°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
Min
Typ
Max Unit
Test Conditions/Comments
See Figure 2
SCL Frequency
0
0.6
1.3
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
0.3
0.3
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Condition, tBUF
0.6
0.6
0.1
0.6
0
After this period, the first clock is generated
Relevant for repeated start condition
)
1.3
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
tR
tF
tHD;STA
tLOW
SCL
SDA
tHIGH
tSU;STA
tSU;STO
tHD;DAT
t
SU;DAT
tHD;STA
tBUF
P
S
S
P
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 28
AD7747
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Positive Supply Voltage VDD to GND
Voltage on any Input or Output Pin to
GND
ESD Rating (ESD Association Human Body 2000 V
Model, S5.1)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−0.3 V to +6.5 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
ESD CAUTION
TSSOP Package θJA
128°C/W
(Thermal Impedance-to-Air)
TSSOP Package θJC
14°C/W
(Thermal Impedance-to-Case)
Peak Reflow Soldering Temperature
Pb Free (20 sec to 40 sec)
260°C
Rev. 0 | Page 6 of 28
AD7747
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL
RDY
1
2
3
4
5
6
7
8
16 SDA
15 NC
SHLD
14 VDD
13 GND
12 VIN(–)
11 VIN(+)
10 NC
AD7747
TOP VIEW
(Not to Scale)
TST
REFIN(+)
REFIN(–)
CIN1(–)
CIN1(+)
9
NC
NC = NO CONNECT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCL
Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided
in the system.
2
3
RDY
SHLD
TST
Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished
and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the
relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit.
Capacitive Input Active AC Shielding. To eliminate the CIN parasitic capacitance to ground, the SHLD signal
can be used for shielding the connection between the sensor and CIN. If not used, this pin should be left as an
open circuit.
4
This pin must be left as an open circuit for proper operation.
5, 6
REFIN(+),
REFIN(−)
Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference
can be used for the voltage channel. These reference input pins are not used for conversion on capacitive
channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND.
7
8
CIN1(−)
CIN1(+)
NC
CDC Negative Capacitive Input. The measured capacitance is connected between the CIN1(−) pin and GND. If
not used, this pin should be left as an open circuit.
CDC Positive Capacitive Input. The measured capacitance is connected between the CIN1(+) pin and GND. If not
used, this pin should be left as an open circuit.
9, 10
Not Connected. These pins should be left as an open circuit.
11, 12
VIN(+), VIN(−) Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external
temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND.
13
14
GND
VDD
Ground Pin.
Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in
combination with a 10 μF tantalum and a 0.1 μF multilayer ceramic.
15
16
NC
Not Connected. This pin should be left as an open circuit.
SDA
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided
elsewhere in the system.
Rev. 0 | Page 7 of 28
AD7747
TYPICAL PERFORMANCE CHARACTERISTICS
80
10
0
60
40
–10
–20
–30
–40
–50
20
0
–20
–40
–60
–80
2.7V
3.0V
3.3V
5.0V
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
0
50 100 150 200 250 300 350 400 450 500 550 600
CAPACITANCE SHLD TO GND (pF)
INPUT CAPACITANCE (pF)
Figure 4. Capacitance Input Integral Nonlinearity;
VDD = 5 V, CAPDAC = 0x3F
Figure 7. Capacitance Input Error vs. Capacitance Between SHLD and GND;
CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V
10
2000
1000
0
GAIN TC ≈ –28ppm/ºC
0
–10
–20
–1000
–2000
–3000
–30
2.7V
3.0V
–40
3.3V
5.0V
–50
0
50 100 150 200 250 300 350 400 450 500 550 600
CAPACITANCE SHLD TO GND (pF)
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (ºC)
Figure 5. Capacitance Input Gain Drift vs. Temperature;
DD = 5 V, CIN(+) to GND = 8 pF
Figure 8. Capacitance Input Error vs. Capacitance Between SHLD and GND;
CIN(+) to GND = 25 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V
V
.20
.15
10
0
.10
.050
–10
–20
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–30
2.7V
3.0V
–40
3.3V
5.0V
–50
–50
–25
0
25
50
75
100
125
150
0
50 100 150 200 250 300 350 400 450 500 550 600
CAPACITANCE CIN TO SHLD (pF)
TEMPERATURE (ºC)
Figure 9. Capacitance Input Error vs. Capacitance Between CIN(+) and SHLD;
CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5V
Figure 6. Capacitance Input Offset Drift vs. Temperature;
VDD = 5 V, CIN(+) Open
Rev. 0 | Page 8 of 28
AD7747
150
100
50
1.0
0.8
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
–100
–150
0
10
100
1k
0.01
100
0.1
1.0
10.0
PARALLEL RESISTANCE (MΩ)
SHLD TO GND RESISTANCE (MΩ)
Figure 10. Capacitance Input Error vs. Parallel Resistance;
CIN(+) to GND = 8 pF, VDD = 5 V
Figure 13. Capacitance Input Error vs. Resistance Between SHLD and GND;
CIN(+) to GND = 8 pF; VDD = 5 V
0
10
0
–100
8 pF
–10
–20
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–30
–40
–50
–60
–70
–80
–90
–100
25 pF
0
25
50
75
100
125
150
175
200
1
100
10
SERIAL RESISTANCE (kΩ)
CIN TO SHLD RESISTANCE (kΩ)
Figure 11. Capacitance Input Error vs. Resistance Between CIN1(+) and SHLD;
CIN(+) to GND = 8 pF, VDD= 5 V
Figure 14. Capacitance Input Error vs. Serial Resistance;
CIN(+) to GND = 8 pF and 25pF, VDD = 5 V
100
0
0.2
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
0
–0.2
–0.4
–0.6
0.091
0.27
0.48
0.96
5
25
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
CIN TO SHLD RESISTANCE (MΩ)
VDD (V)
Figure 12. Capacitance Input Error vs. Resistance Between CIN(+) and SHLD;
CIN(+) to GND = 25 pF, VDD = 5 V
Figure 15. Capacitance Input Power Supply Rejection (PSR);
CIN(+) to GND = 8 pF
Rev. 0 | Page 9 of 28
AD7747
200
150
100
50
0
–20
–40
0
–60
–50
–100
–150
–80
–100
–120
–200
0
8
16
24
32
40
48
56
64
0
100 200 300 400 500 600 700 800 900
INPUT SIGNAL FREQUENCY (Hz)
1k
CAPDAC CODE
Figure 16. CAPDAC Differential Nonlinearity (DNL)
Figure 19. Capacitive Channel Frequency Response;
Conversion Time = 22 ms
0
–20
2.0
1.5
1.0
–40
0.5
–60
0
–0.5
–1.0
–1.5
–2.0
–80
–100
–120
0
25
50
75
100
125
150
175
200
–50
–25
0
25
50
75
100
125
150
INPUT SIGNAL FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Internal Temperature Sensor Error vs. Temperature
Figure 20. Capacitive Channel Frequency Response;
Conversion Time = 124 ms
1.0
0.5
0
–20
0
–40
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–60
–80
–100
–120
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
350
400
TEMPERATURE (°C)
INPUT SIGNAL FREQUENCY (Hz)
Figure 18. External Temperature Sensor Error vs. Temperature
Figure 21. Voltage Channel Frequency Response;
Conversion Time = 122.1 ms
Rev. 0 | Page 10 of 28
AD7747
OUTPUT NOISE AND RESOLUTION SPECIFICATIONS
The AD7747 resolution is limited by noise. The noise
performance varies with the selected conversion time.
Table 6 and Table 7 show typical noise performance and
resolution for the voltage channel. These numbers were
generated from 1000 data samples acquired in continuous
conversion mode with ±IN pins shorted to ground.
Table 5 shows typical noise performance and resolution for the
capacitive channel. These numbers were generated from 1000
data samples acquired in continuous conversion mode, at an
excitation of 16 kHz, ±±DD × 3/8, and with all CIN and SHLD
pins connected only to the evaluation board (no external
capacitors).
RMS noise represents the standard deviation and p-p noise
represents the difference between minimum and maximum
results in the data. Effective resolution is calculated from rms
noise, and p-p resolution is calculated from p-p noise.
Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time (Bold line represents default setting)
Conversion
Time (ms)
Output Data −3 dB Frequency
RMS Noise RMS
P-P
Noise (aF)
Effective Resolution P-P Resolution
Rate (Hz)
45.5
41.9
25.0
13.2
8.1
(Hz)
43.6
39.5
21.8
10.9
6.9
(aF/√Hz)
Noise (aF)
(Bits)
16.4
16.8
18.3
18.7
19.1
19.3
19.6
19.9
(Bits)
14.3
14.5
15.3
15.9
16.5
16.5
16.8
17.0
22.0
23.9
40.0
76.0
124.0
154.0
184.0
219.3
28.8
23.2
11.1
190
146
52
821
725
411
262
174
173
141
126
11.2
37
11.0
10.4
29
24
6.5
5.3
5.4
4.4
10.0
21
4.6
4.0
9.0
18
Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference
Conversion
Time (ms)
Output Data −3 dB Frequency
RMS Noise
(μV)
P-P Noise
(μV)
Effective Resolution P-P Resolution
Rate (Hz)
(Hz)
26.4
15.9
8.0
(Bits)
17.6
18.3
19.1
19.5
(Bits)
15.2
15.7
16.3
16.8
20.1
32.1
62.1
122.1
49.8
31.2
16.1
11.4
7.1
4.0
62
42
28
20
8.2
4.0
3.0
Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference
Conversion
Time (ms)
Output Data −3 dB Frequency
RMS Noise
(μV)
P-P Noise
(μV)
Effective Resolution P-P Resolution
Rate (Hz)
(Hz)
26.4
15.9
8.0
(Bits)
18.3
19.6
20.5
21.1
(Bits)
15.6
16.8
17.7
18.3
20.1
32.1
62.1
122.1
49.8
31.2
16.1
14.9
6.3
3.3
95
42
22
15
8.2
4.0
2.1
Rev. 0 | Page 11 of 28
AD7747
SERIAL INTERFACE
The AD7747 supports an I2C-compatible 2-wire serial interface.
The two wires on the I2C bus are called SCL (clock) and SDA
(data). These two wires carry all addressing, control, and data
information one bit at a time over the bus to all connected
peripheral devices. The SDA wire carries the data, while the
SCL wire synchronizes the sender and receiver during the data
transfer. I2C devices are classified as either master or slave devices.
A device that initiates a data transfer message is called a master,
while a device that responds to this message is called a slave.
In continuous conversion mode, the address pointer’s auto-
incrementer should be used for reading a conversion result.
That means the three data bytes should be read using one
multibyte read transaction rather than three separate single byte
transactions. The single byte data read transaction may result in
the data bytes from two different results being mixed. The same
applies for six data bytes if both the capacitive and the
voltage/temperature channel are enabled.
The user can also access any unique register (address) on a one-
to-one basis without having to update all the registers. The
address pointer register’s contents cannot be read.
To control the AD7747 device on the bus, the following
protocol must be followed. First, the master initiates a data
transfer by establishing a start condition, defined by a high-to-
low transition on SDA while SCL remains high. This indicates
that the start byte follows. This ꢀ-bit start byte is made up of a
7-bit address plus an R/W bit indicator.
If an incorrect address pointer location is accessed, or if the user
allows the auto-incrementer to exceed the required register
address, the following applies:
•
In read mode, the AD7747 continues to output various
internal register contents until the master device issues a
no acknowledge, start, or stop condition. The address
pointer auto-incrementer’s contents are reset to point to
the status register at Address ±x±± when a stop condition is
received at the end of a read operation. This allows the
status register to be read (polled) continually without
having to constantly write to the address pointer.
All peripherals connected to the bus respond to the start
condition and shift in the next ꢀ bits (7-bit address + R/W bit).
The bits arrive MSB first. The peripheral that recognizes the
transmitted address responds by pulling the data line low
during the ninth clock pulse. This is known as the acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. An exception to this is the general
call address, which is described later in this document. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the start condition and the correct address byte. The
R/W bit determines the direction of the data transfer. A Logic ±
LSB in the start byte means that the master writes information
to the addressed peripheral. In this case, the AD7747 becomes a
slave receiver. A Logic 1 LSB in the start byte means that the
master reads information from the addressed peripheral. In this
case, the AD7747 becomes a slave transmitter. In all instances, the
AD7747 acts as a standard slave device on the I2C bus.
•
In write mode, the data for the invalid address is not
loaded into the AD7747 registers, but an acknowledge is
issued by the AD7747.
WRITE OPERATION
When a write is selected, the byte following the start byte is
always the register address pointer (subaddress) byte, which
points to one of the internal registers on the AD7747. The
address pointer byte is automatically loaded into the address
pointer register and acknowledged by the AD7747. After the
address pointer byte acknowledge, a stop condition, a repeated
start condition, or another data byte can follow from the master.
The start byte address for the AD7747 is ±x9± for a write and
±x91 for a read.
READ OPERATION
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is ever encountered
by the AD7747, it returns to its idle condition and the address
pointer is reset to Address ±x±±.
When a read is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted on to
the SDA line by the AD7747. This is then clocked out by the
master device and the AD7747 awaits an acknowledge from the
master.
If a data byte is transmitted after the register address pointer
byte, the AD7747 loads this byte into the register that is
currently addressed by the address pointer register, sends an
acknowledge, and the address pointer auto-incrementer
automatically increments the address pointer register to the
next internal register address. Thus, subsequent transmitted
data bytes are loaded into sequentially incremented addresses.
If an acknowledge is received from the master, the address auto-
incrementer automatically increments the address pointer
register and outputs the next addressed register content on to
the SDA line for transmission to the master. If no acknowledge
is received, the AD7747 returns to the idle state and the address
pointer is not incremented.
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as outlined above for a start condition, that is, a repeated
start condition is treated the same as a start condition. When a
master device issues a stop condition, it relinquishes control of
The address pointer’s auto-incrementer allows block data to be
written or read from the starting address and subsequent
incremental addresses.
Rev. 0 | Page 12 of 28
AD7747
the bus, allowing another master device to take control of the
bus. Therefore, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
GENERAL CALL
When a master issues a slave address consisting of seven ±s with
the eighth bit (R/W bit) set to ±, this is known as the general call
address. The general call address is for addressing every device
connected to the I2C bus. The AD7747 acknowledges this
address and read in the following data byte.
AD7747 RESET
To reset the AD7747 without having to reset the entire I2C bus,
an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7747 does not respond to the
I2C bus commands (do not acknowledge) during the default
values upload for approximately 15± μs (max 2±± μs).
If the second byte is ±x±6, the AD7747 is reset, completely
uploading all default values. The AD7747 does not respond to
the I2C bus commands (do not acknowledge) during the default
values upload for approximately 15± μs (2±± μs maximum).
The AD7747 does not acknowledge any other general call
commands.
The reset command address word is ±xBF.
SDATA
SCLOCK
S
1–7
8
9
1–7
8
9
1–7
DATA
8
9
P
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 22. Bus Data Transfer
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
A(S)
DATA
A(M)
P
LSB = 1
READ
SEQUENCE
A(M)
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 23. Write and Read Sequences
Rev. 0 | Page 13 of 28
AD7747
REGISTER DESCRIPTIONS
The master can write to or read from all of the AD7747 registers
except the address pointer register, which is a write-only
register. The address pointer register determines which register
the next read or write operation accesses. All communications
with the part through the bus start with an access to the address
pointer register. After the part has been accessed over the bus
and a read/write operation is selected, the address pointer
register is set up. The address pointer register determines from
or to which register the operation takes place. A read/write
operation is performed from/to the target address, which then
increments to the next address until a stop command on the bus
is performed.
Table 8. Register Summary
Address
Pointer
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
(Dec) (Hex) Dir
Default Value
Status
0
0x00
R
–
0
–
0
–
0
–
0
–
0
RDY
1
RDYVT
1
RDYCAP
1
Cap Data H
Cap Data M
Cap Data L
VT Data H
VT Data M
VT Data L
1
2
3
4
5
6
7
0x01
0x02
0x03
0x04
0x05
0x06
0x07
R
R
R
R
R
R
Capacitive channel data—high byte, 0x00
Capacitive channel data—middle byte, 0x00
Capacitive channel data—low byte, 0x00
Voltage/temperature channel data—high byte, 0x00
Voltage/temperature channel data—middle byte, 0x00
Voltage/temperature channel data—low byte, 0x00
Cap Setup
R/W CAPEN
–
CAPDIFF
–
–
–
–
0
–
0
R/W VTEN
0
0
0
0
0
0
0
VT Setup
8
9
0x08
0x09
0x0A
0x0B
0x0C
VTMD1
0
VTMD0
EXTREF
–
–
VTSHORT VTCHOP
0
0
0
0
0
0
EXC Setup
R/W
–
0
–
0
–
–
EXCDAC
EXCEN
EXCLVL1
1
EXCLVL0
1
0
0
0
0
Configuration 10
R/W VTFS1
VTFS0
CAPFS2
1
CAPFS1
0
CAPFS0
0
MD2
0
MD1
0
MD0
0
1
0
–
0
–
0
Cap DAC A
Cap DAC B
11
12
R/W DACAENA
DACA—6-Bit Value
0x00
0
R/W DACBENB
DACB—6-Bit Value
0x00
0
R/W
Cap Offset H
Cap Offset L
Cap Gain H
Cap Gain L
Volt Gain H
Volt Gain L
13
14
15
16
17
18
0x0D
0x0E
0x0F
0x10
0x11
0x12
Capacitive offset calibration—high byte, 0x80
Capacitive offset calibration—low byte, 0x00
R/W
R/W
Capacitive gain calibration—high byte, factory calibrated
Capacitive gain calibration—low byte, factory calibrated
Voltage gain calibration—high byte, factory calibrated
Voltage gain calibration—low byte, factory calibrated
R/W
R/W
R/W
Rev. 0 | Page 14 of 28
AD7747
STATUS REGISTER
Address Pointer 0x00, Read Only, Default Value 0x07
This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished
conversion.
RDY
RDY
pin high-to-low transition can be used as an alternative indication of
The
pin reflects the status of the RDY bit. Therefore, the
the finished conversion.
Table 9. Status Register Bit Map
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RDY
1
Bit 1
RDYVT
1
Bit 0
RDYCAP
1
Mnemonic
Default
–
0
–
0
–
0
–
0
–
0
Table 10.
Bit
7 to 3
2
Mnemonic
Description
–
Not used, always read 0.
RDY
RDY = 0 indicates that conversion on the enabled channel(s) is complete and new unread data is available.
If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion
on both channels is complete. The RDY bit returns to 1 either when data is read or prior to finishing the next
conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit.
1
0
RDYVT
RDYVT = 0 indicates that a conversion on the voltage/temperature channel is complete and new unread data
is available.
RDYCAP
RDYCAP = 0 indicates that a conversion on the capacitive channel is complete and new unread data is available.
CAP DATA REGISTER
VT DATA REGISTER
24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only,
Default Value 0x000000
24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only,
Default Value 0x000000
This register contains the capacitive channel output data. The
register is updated after finished conversion on the capacitive
channel, with one exception: When the serial interface read
operation from the Cap Data register is in progress, the data
register is not updated and the new capacitance conversion
result is lost.
This register contains the voltage/temperature channel output
data. The register is updated after finished conversion on the
voltage channel or temperature channel, with one exception:
When the serial interface read operation from the VT Data
register is in progress, the data register is not updated and the
new voltage/temperature conversion result is lost.
The stop condition on the serial interface is considered to be the
end of the read operation. Therefore, to prevent data corruption,
all three bytes of the data register should be read sequentially
using the register address pointer auto-increment feature of the
serial interface.
The stop condition on the serial interface is considered to be the
end of the read operation. Therefore, to prevent data corruption,
all three bytes of the data register should be read sequentially
using the register address pointer auto-increment feature of the
serial interface.
To prevent losing some of the results, the Cap Data register
should be read before the next conversion on the capacitive
channel is finished.
For voltage input, Code 0 represents negative full scale (−VREF),
the 0x800000 code represents zero scale (0 V), and the
0xFFFFFF code represents positive full scale (+VREF).
The 0x000000 code represents negative full scale (−8.192 pF),
the 0x800000 code represents zero scale (0 pF), and the
0xFFFFFF code represents positive full scale (+8.192 pF).
To prevent losing some of the results, the VT Data register
should be read before the next conversion on the voltage/
temperature channel is complete.
For the temperature sensor, the temperature can be calculated
from code using the following equation:
Temperature (°C) = (Code/2048) − 4096
Rev. 0 | Page 15 of 28
AD7747
CAP SETUP REGISTER
Address Pointer 0x07, Default Value 0x00
Capacitive channel setup.
Table 11. Cap Setup Register Bit Map
Bit
Bit 7
CAPEN
0
Bit 6
Bit 5
CAPDIFF
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
–
0
–
0
–
0
–
0
–
0
–
0
Table 12.
Bit
Mnemonic
Description
7
CAPEN
CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration.
This bit must be 0 for proper operation.
6
–
5
CAPDIFF
–
This bit must be set to 1 for proper operation.
4 to 0
These bits must be 0 for proper operation.
VT SETUP REGISTER
Address Pointer 0x08, Default Value 0x00
Voltage/Temperature channel setup.
Table 13. VT Setup Register Bit Map
Bit
Bit 7
VTEN
0
Bit 6
VTMD1
0
Bit 5
VTMD0
0
Bit 4
EXTREF
0
Bit 3
Bit 2
Bit 1
Bit 0
VTCHOP
0
Mnemonic
Default
–
0
–
0
VTSHORT
0
Table 14.
Bit
Mnemonic
Description
7
VTEN
VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration.
Voltage/temperature channel input configuration.
6
5
VTMD1
VTMD0
VTMD1
VTMD0
Channel Input
0
0
1
1
0
1
0
1
Internal temperature sensor
External temperature sensor diode
VDD monitor
External voltage input (VIN)
4
EXTREF
EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(−) for the voltage input or the
VDD monitor.
EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal
temperature sensor for proper operation.
3 to 2
–
These bits must be 0 for proper operation.
1
0
VTSHORT
VTCHOP = 1
VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes.
VTCHOP = 1 sets internal chopping on the voltage/temperature channel.
The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance.
Rev. 0 | Page 16 of 28
AD7747
EXC SETUP REGISTER
Address Pointer 0x09, Default Value 0x03
Capacitive channel excitation setup.
Table 15. EXC Setup Bit Map
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EXCDAC
0
Bit 2
EXCEN
0
Bit 1
EXCLVL1
1
Bit 0
EXCLVL0
1
Mnemonic
Default
–
0
–
0
–
0
–
0
Table 16.
Bit
7 to 4
3
Mnemonic
Description
–
These bits must be 0 for proper operation.
EXCDAC
EXCEN
CAPDAC excitation. This bit must be set to 1 for the proper capacitive channel operation.
CIN and AC SHLD excitation. This bit must be set to 1 for the proper capacitive channel operation.
Excitation Voltage Level. Must be set to VDD × 3/8 to allow operation for specified performance.
2
1
0
EXCLVL1,
EXCLVL0
EXCLVL1
EXCLVL0
Voltage on Cap
VDD/8
EXC Low Level
VDD × 3/8
VDD × 1/4
VDD × 1/8
0
EXC High Level
0
0
1
1
0
1
0
1
VDD × 5/8
VDD × 3/4
VDD × 7/8
VDD
VDD/4
VDD × 3/8
VDD/2
Rev. 0 | Page 17 of 28
AD7747
CONFIGURATION REGISTER
Address Pointer 0x0A, Default Value 0xA0
Converter update rate and mode of operation setup.
Table 17. Configuration Register Bit Map
Bit
Bit 7
VTFS1
0
Bit 6
VTFS0
0
Bit 5
CAPFS2
0
Bit 4
CAPFS1
0
Bit 3
CAPFS0
0
Bit 2
MD2
0
Bit 1
MD1
0
Bit 0
MD0
0
Mnemonic
Default
Table 18.
Bit
Mnemonic
Description
7
6
VTFS1
VTFS0
Voltage/temperature channel digital filter setup—conversion time/update rate setup.
VTCHOP = 1
VTFS1
VTFS0
Conversion Time (ms)
Update Rate (Hz)
−3 dB Frequency (Hz)
0
0
1
1
0
1
0
1
20.1
32.1
62.1
122.1
49.8
31.2
16.1
8.2
26.4
15.9
8.0
4.0
5
4
3
CAPFS2
CAPFS1
CAPFS0
Capacitive channel digital filter setup—conversion time/update rate setup.
CAPFS2 CAPFS1
CAPFS0
Conversion Time (ms)
Update Rate
−3 dB Frequency (Hz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
22.0
45.5
41.9
25.0
13.2
8.1
43.6
39.5
21.8
10.9
6.9
23.9
40.0
76.0
124.0
154.0
184.0
219.3
6.5
5.3
5.5
4.4
4.6
4.0
2
1
0
MD2
MD1
MD0
Converter mode of operation setup.
MD2
MD1
MD0
Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Idle
Continuous conversion
Single conversion
Power-down
–
Capacitance system offset calibration
Capacitance or voltage system gain calibration
–
Rev. 0 | Page 18 of 28
AD7747
CAP DAC A REGISTER
Address Pointer 0x0B, Default Value 0x00
Capacitive DAC setup.
Table 19. Cap DAC A Register Bit Map
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
DACAENA
0
–
0
DACA—6-Bit Value
0x00
Table 20.
Bit
Mnemonic
Description
7
DACAENA
–
DACAENA = 1 connects capacitive DACA to the positive capacitance input.
This bit must be 0 for proper operation.
6
5 to 1 DACA
DACA value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range.
CAP DAC B REGISTER
Address Pointer 0x0C, Default Value 0x00
Capacitive DAC setup.
Table 21. Cap DAC B Register Bit Map
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
Default
DACBENB
0
–
0
DACB—6-Bit Value
0x00
Table 22.
Bit
Mnemonic
Description
7
DACBENB
–
DACBENB = 1 connects capacitive DACB to the negative capacitance input.
This bit must be 0 for proper operation.
6
5 to 1 DACB
DACB value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range.
Rev. 0 | Page 19 of 28
AD7747
CAP OFFSET CALIBRATION REGISTER
CAP GAIN CALIBRATION REGISTER
16 Bits, Address Pointer 0x0D, 0x0E,
Default Value 0x8000
16 Bits, Address Pointer 0x0F, 0x10,
Default Value 0xXXXX
The capacitive offset calibration register holds the capacitive
channel zero-scale calibration coefficient. The coefficient is
used to digitally remove the capacitive channel offset. The
register value is updated automatically following the execution
of a capacitance offset calibration. The capacitive offset calibra-
tion resolution (cap offset register LSB) is less than 32 aF; the
full range is ±1 pF.
Capacitive gain calibration register. The register holds the
capacitive channel full-scale factory calibration coefficient.
VOLT GAIN CALIBRATION REGISTER
16 Bits, Address Pointer 0x11,0x12,
Default Value 0xXXXX
Voltage gain calibration register. The register holds the voltage
channel full-scale factory calibration coefficient.
Rev. 0 | Page 20 of 28
AD7747
CIRCUIT DESCRIPTION
VDD
ACTIVE AC SHIELD CONCEPT
The AD7747 measures capacitance between CIN and ground.
That means any capacitance to ground on signal path between
the AD7747 CIN pin(s) and sensor is included in the AD7747
conversion result.
TEMP
SENSOR
CLOCK
AD7747
GENERATOR
VIN(+)
VIN(–)
2
SDA
SCL
I C
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
MUX
SERIAL
INTERFACE
CIN1(+)
CIN1(–)
SHLD
The parasitic capacitance of the sensor connections can easily
be in the same, if not even higher, order as the capacitance of
the sensor itself. If that parasitic capacitance is stable, it can be
treated as a nonchanging capacitive offset. However, the para-
sitic capacitance of sensor connections is often changing as a
result of mechanical movement, changing ambient temperature,
ambient humidity, etc. These changes are seen as drift in the
conversion result and may significantly compromise the system
accuracy.
CONTROL LOGIC
RDY
CALIBRATION
VOLTAGE
REFERENCE
CAP DAC 1
EXCITATION
CAP DAC 2
GND
REFIN(+)
REFIN(–)
Figure 24. AD7747 Block Diagram
OVERVIEW
To eliminate the CIN parasitic capacitance to ground, the
AD7747 SHLD signal can be used for shielding the connection
between the sensor and CIN, as shown in Figure 25. The SHLD
output is basically the same signal waveform as the excitation of
the CIN pin; the SHLD is driven to the same voltage potential
as the CIN pin. Therefore, there is no ac current between CIN
and SHLD pins, and any capacitance between these pins does
not affect the CIN charge transfer. Ideally, the CIN to SHLD
capacitance does not have any contribution to the AD7747 result.
The AD7747 core is a high precision converter consisting of a
second-order (Σ-Δ or charge balancing) modulator and a third-
order digital filter. It works as a CDC for the capacitive inputs
and as a classic ADC for the voltage input or for the voltage
from a temperature sensor.
In addition to the converter, the AD7747 integrates a multi-
plexer, an excitation source and CAPDACs for the capacitive
inputs, a temperature sensor and a voltage reference for the
voltage and temperature inputs, a complete clock generator,
a control and calibration logic, and an I2C-compatible serial
interface.
To get the best result, locate the AD7747 as close as possible to
the capacitive sensor. Keep the connection between the sensor
and AD7747 CIN pin, and also the return path between sensor
ground and the AD7747 GND pin, short. Shield the PCB track
to the CIN pin and connect the shielding to the AD7747 SHLD
pin. In addition, if a shielded cable is used for sensor connection,
the shield should be connected to the AD7747 SHLD pin.
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 25 shows the CDC simplified functional diagram. The
measured capacitance CX is connected between the Σ-Δ modu-
lator input and ground. A square-wave excitation signal is
applied on the CX during the conversion and the modulator
continuously samples the charge going through the CX. The
digital filter processes the modulator output, which is a stream
of ±s and 1s containing the information in ± and 1 density. The
data from the digital filter is scaled, applying the calibration
coefficients, and the final result can be read through the serial
interface.
CAPDAC
The AD7747 CDC full-scale input range is ±ꢀ.192 pF. For sim-
plicity of calculation, however, the following text and figures use
±ꢀ pF. The part can accept a higher capacitance on the input
and the common-mode or offset (nonchanging component)
capacitance can be balanced by programmable on-chip CAPDACs.
CAPDAC(+)
CIN(+)
CAPACITANCE TO DIGITAL CONVERTER
(CDC)
CLOCK
GENERATOR
CDC
DATA
CIN(–)
DATA
CIN
24-BIT Σ-Δ
MODULATOR
DIGITAL
FILTER
CAPDAC(–)
C
C
Y
X
EXCITATION
C
X
SHLD
SHLD
Figure 26. Using a CAPDAC
Figure 25. CDC Simplified Block Diagram
Rev. 0 | Page 21 of 28
AD7747
The CAPDAC can be understood as a negative capacitance
connected internally to the CIN pin. There are two independent
CAPDACs, one connected to the CIN(+) and the second con-
nected to the CIN(−). The relation between the capacitance
input and output data can be expressed as
Figure 29 shows how to shift the input range further, up to
25 pF absolute value of capacitance connected to the CIN(+).
0x000000
TO
0xFFFFFF
CAPDAC(+)
17pF
CIN(+)
DATA
DATA ≈
(
CX − CAPDAC(+)
)
−
(
CY − CAPDAC(−)
)
±8pF
CDC
CAPDIFF = 1
CIN(–)
The CAPDACs have a 6-bit resolution, monotonic transfer
function, are well matched to each other, and have a defined
temperature coefficient. The CAPDAC full range (absolute
value) is not factory calibrated and can vary up to ±2±% with
the manufacturing process. See the Specifications section and
Figure 16 of the typical performance characteristics.
CAPDAC(–)
0pF
C
X
9...25pF
(17pF ± 8pF)
SHLD
Figure 29. Using CAPDAC in Single-Ended Configuration
SINGLE-ENDED CAPACITIVE CONFIGURATION
DIFFERENTIAL CAPACITIVE CONFIGURATION
The AD7747 can be used for interfacing to a single-ended
capacitive sensor. In this configuration the sensor should be
connected to one of the AD7747 CIN pins, for example CIN(+)
and the other pin should be left open circuit. Note that the
CAPDIFF bit in the Cap Setup register must be set to 1 at all
times for the correct operation.
When the AD7747 is used for interfacing to a differential
capacitive sensor, each of the two input capacitances, CX and CY,
must be less than ꢀ pF (without using the CAPDACs) or must
be less than 25 pF and balanced by the CAPDACs. Balancing
by the CAPDACs means that both CX − CAPDAC(+) and
CY − CAPDAC(−) are less than ꢀ pF.
It is recommended to guard the unused CIN input with the
active shield to ensure the best performance in terms of noise,
offset, and offset drift.
If the unbalanced capacitance connected to CIN pins is higher
than ꢀ pF, the CDC introduces a gain error, an offset error, and
nonlinearity error.
The CDC (without using the CAPDACs) measure the positive
(or the negative) input capacitance in the range of ± pF to ꢀ pF
(see Figure 27).
See the examples shown in Figure 3±, Figure 31, and Figure 32.
0x000000
TO
0xFFFFFF
CAPDAC(+)
OFF
0x800000
TO
0xFFFFFF
CAPDAC(+)
OFF
CIN(+)
DATA
CIN(+)
±8pF
CDC
DATA
CAPDIFF = 1
CIN(–)
CAPDIFF = 1
0...8pF
CDC
CIN(–)
CAPDAC(–)
OFF
C
C
Y
0...8pF
X
CAPDAC(–)
OFF
0...8pF
C
X
0...8pF
SHLD
SHLD
Figure 30. CDC Differential Input Configuration
Figure 27. CDC Single-Ended Input Configuration
The CAPDAC can be used for programmable shifting of the
input range. The example in Figure 2ꢀ shows how to use the full
±ꢀ pF CDC span to measure capacitance between ± pF to 16 pF.
0x000000
TO
0xFFFFFF
CAPDAC(+)
17pF
CIN(+)
CIN(–)
DATA
0x000000
TO
±8pF
CDC
CAPDAC(+)
8pF
CAPDIFF = 1
0xFFFFFF
CIN(+)
DATA
±8pF
CDC
CAPDAC(–)
17pF
CAPDIFF = 1
CIN(–)
C
C
Y
X
13...21pF
13...21pF
(17pF ± 4pF) (17pF ± 4pF)
CAPDAC(–)
0pF
C
X
SHLD
0...16pF
Figure 31. Using CAPDAC in Differential Configuration
SHLD
Figure 28. Using CAPDAC in Single-Ended Configuration
Rev. 0 | Page 22 of 28
AD7747
Parasitic resistances, as shown in Figure 34, cause leakage
0x000000
TO
0xFFFFFF
CAPDAC(+)
17pF
currents, which affect the CDC result. The AD7747 CDC
measures the charge transfer between the CIN pin and ground.
Any resistance connected in parallel to the measured
capacitance, CX, such as the parasitic resistance, RP1, also
transfers charge. Therefore, the parallel resistor is seen as an
additional capacitance in the output data. A resistance in the
range of RP1 ≥ 1± MΩ causes an offset error in the CDC result.
An offset calibration can be used to compensate for the effect of
small leakage currents. A higher leakage current to ground,
RP1 ≤ 1± MΩ, results in a gain error, an offset error, and a
nonlinearity error. See Figure 1± in the Typical Performance
Characteristics section.
CIN(+)
CIN(–)
DATA
±8pF
CDC
CAPDIFF = 1
CAPDAC(–)
17pF
C
C
Y
17pF
X
9 TO 25pF
(17pF ± 8pF)
SHLD
Figure 32. Using CAPDAC in Differential Configuration
PARASITIC CAPACITANCE
A parasitic resistance, RP2, between SHLD and ground, as well
as RP3 between the CIN pin and the active shield, as shown in
Figure 34, cause a leakage current, which affects the CDC result
and is seen as an offset in the data. An offset calibration can be
used to compensate for effect of the small leakage current
caused by a resistance RP2 and RP3 ≥ 2±± kΩ. See Figure 11,
Figure 12, and Figure 13 in the Typical Performance
Characteristics section.
The CDC architecture used in the AD7747 measures the
capacitance CX connected between the CIN pin and ground.
Most applications use the active shield to avoid external influ-
ences during the CDC. However, any parasitic capacitance, CP,
as shown in Figure 33, can affect the CDC result.
DATA
CIN
CDC
C
C
C
C
P3
PARASITIC SERIAL RESISTANCE
P1
X
P2
SHLD
DATA
CIN
R
S
CDC
Figure 33. Parasitic Capacitance
C
X
A parasitic capacitance, CP1, coupled in between CIN and
ground adds directly to the value of the capacitance CX and,
therefore, the CDC result is: DATA ≈ CX + CP1. An offset cali-
bration might be sufficient to compensate for a small parasitic
capacitance (CP1 ≤ 1pF). For a larger parasitic capacitance, the
CAPDAC can be used to compensate, followed by an offset
calibration to ensure the full range of ±ꢀpF is available for
the system.
SHLD
Figure 35. Parasitic Serial Resistance
The AD7747 CDC result is affected by a resistance in series
with the measured capacitance. The serial resistance should be
less than 1± kꢁ for the specified performance. See Figure 14 in
the Typical Performance Characteristics section.
Other parasitic capacitances, such as CP2 between active shield
and ground as well as CP3 between the CIN pin and SHLD,
could influence the conversion result. However, the graphs in
the Typical Performance Characteristics section show that the
effect of parasitic capacitance of type CP2/CP3 below 25± pF is
insignificant to the CDC result. Figure 7 and Figure ꢀ show the
gain error caused by CP2. Figure 9 shows the gain error caused
by CP3.
CAPACITIVE GAIN CALIBRATION
The AD7747 gain is factory calibrated for the full scale of
±ꢀ.192 pF in the production for each part individually. The
factory gain coefficient is stored in a one-time programmable
(OTP) memory and is copied to the capacitive gain register at
power-up or after reset.
The gain can be changed by executing a capacitance gain calibra-
tion mode, for which an external full-scale capacitance needs
to be connected to the capacitance input, or by writing a user
value to the capacitive gain register. This change would be only
temporary, and the factory gain coefficient would be reloaded
back after power-up or reset. The part is tested and specified for
use only with the default factory calibration coefficient.
PARASITIC RESISTANCE
DATA
CIN
CDC
R
C
X
R
R
P3
P1
P2
SHLD
Figure 34. Parasitic Resistance on CIN
Rev. 0 | Page 23 of 28
AD7747
where:
CAPACITIVE SYSTEM OFFSET CALIBRATION
K is Boltzmann’s constant (1.3ꢀ × 1±−23).
T is the absolute temperature in Kelvin.
q is the charge on the electron (1.6 × 1±−19 coulombs).
N is the ratio of the two currents.
The capacitive offset is dominated by the parasitic offset in the
application, such as the initial capacitance of the sensor, any
parasitic capacitance of tracks on the board, and the capacitance
of any other connections between the sensor and the CDC.
Therefore, the AD7747 is not factory calibrated for capacitive
offset. It is the user’s responsibility to calibrate the system
capacitance offset in the application.
nf is the ideality factor of the thermal diode.
The AD7747 uses an on-chip transistor to measure the
temperature of the silicon chip inside the package. The Σ-Δ
ADC converts the ꢂVBE to digital; the data are scaled using
factory calibration coefficients. Thus, the output code is
proportional to temperature.
Any offset in the capacitance input larger than ±1 pF should
first be removed using the on-chip CAPDACs. The small offset
within ±1 pF can then be removed by using the capacitance
offset calibration register.
Code
2±4ꢀ
Temperature
(
°C
)
=
− 4±96
One method of adjusting the offset is to connect a zero-scale
capacitance to the input and execute the capacitance offset
calibration mode. The calibration sets the midpoint of the
±ꢀ.192 pF range (that is, Output Code ±xꢀ±±±±±) to that
zero-scale input.
The AD7747 has a low power consumption resulting in only a
small effect due to the part self-heating (less than ±.5°C at
VDD = 5 V).
If the capacitive sensor can be considered to be at the same
temperature as the AD7747 chip, the internal temperature
sensor can be used as a system temperature sensor. That means
the complete system temperature drift compensation can be
based on the AD7747 internal temperature sensor without need
for any additional external components. See Figure 17 in the
Typical Performance Characteristics section.
Another method is to calculate and write the offset calibration
register value; the LSB value is 31.25 aF (ꢀ.192 pF/217).
The offset calibration register is reloaded by the default value at
power-on or after reset. Therefore, if the offset calibration is not
repeated after each system power-up, the calibration coefficient
value should be stored by the host controller and reloaded as
part of the AD7747 setup.
EXTERNAL TEMPERATURE SENSOR
INTERNAL TEMPERATURE SENSOR
VDD
EXTERNAL
INTERNAL TEMPERATURE SENSOR
TEMPERATURE
I ... N × I
SENSOR
VDD
I
N × I
CLOCK
GENERATOR
CLOCK
GENERATOR
R
R
VIN(+)
VIN(–)
2N3906
ΔV
S1
DATA
DIGITAL
FILTER
AND
24-BIT Σ-Δ
MODULATOR
BE
S2
DATA
SCALING
DIGITAL
FILTER
AND
24-BIT Σ-Δ
MODULATOR
ΔV
BE
VOLTAGE
REFERENCE
SCALING
VOLTAGE
REFERENCE
Figure 37. Transistor as an External Temperature Sensor
The AD7747 provides the option of using an external transistor
as a temperature sensor in the system. The ꢂVBE method, which
is similar to the internal temperature sensor method, is used.
However, it is modified to compensate for the serial resistance
of connections to the sensor. Total serial resistance (RS1 + RS2 in
Figure 37) up to 1±± ꢁ is compensated. The VIN(−) pin must
be grounded for proper external temperature sensor operation.
Figure 36. Internal Temperature Sensor
The temperature sensing method used in the AD7747 is to
measure a difference in ꢂVBE voltage of a transistor operated at
two different currents (see Figure 36). The ꢂVBE change with
temperature is linear and can be expressed as
KT
q
ΔVBE = (nf )
× ln(N)
The AD7747 is factory calibrated for Transistor 2N39±6 with
the ideality factor nf = 1.±±ꢀ.
See Figure 1ꢀ in the Typical Performance Characteristics section.
Rev. 0 | Page 24 of 28
AD7747
The AD7747 Σ-Δ core can work as a high resolution (up to
VOLTAGE INPUT
21 ENOB) classic ADC with a fully differential voltage input.
The ADC can be used either with the on-chip high precision,
low drift, 1.17 V voltage reference, or with an external reference
connected to the fully differential reference input pins.
VDD
ANALOG TO DIGITAL CONVERTER
(ADC)
The voltage and reference inputs are continuously sampled by
a Σ-Δ modulator during the conversion. Therefore, the input
source impedance should be kept low. See the application
example in Figure 3ꢀ.
CLOCK
GENERATOR
VIN(+)
DATA
24-BIT Σ-Δ
MODULATOR
DIGITAL
FILTER
R
T
RTD
VIN(–)
VDD MONITOR
Along with converting external voltages, the AD7747 Σ-Δ ADC
can be used for monitoring the VDD voltage. The voltage from
the VDD pin is internally attenuated by 6.
REFIN(+)
REFIN(–)
VOLTAGE
REFERENCE
R
REF
GND
Figure 38. Resistive Temperature Sensor Connected to the Voltage Input
Rev. 0 | Page 25 of 28
AD7747
TYPICAL APPLICATION DIAGRAM
3V/5V
+
POWER SUPPLY
0.1µF
10µF
10kΩ
10kΩ
VDD
TEMP
SENSOR
HOST
SYSTEM
CLOCK
GENERATOR
AD7747
VIN(+)
SDA
SCL
2
VIN(–)
I C
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
MUX
SERIAL
INTERFACE
CIN1(+)
RDY
CIN1(–)
SHLD
CONTROL LOGIC
CALIBRATION
VOLTAGE
REFERENCE
CAP DAC 1
EXCITATION
CAP DAC 2
GND
REFIN(+)
REFIN(–)
Figure 39. Basic Application Diagram for a Differential Capacitive Sensor
Rev. 0 | Page 26 of 28
AD7747
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7747ARUZ1
AD7747ARUZ-REEL1
AD7747ARUZ-REEL71
EVAL-AD7747EBZ1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Package Option
RU-16
RU-16
RU-16
1 Z = Pb-free part.
Rev. 0 | Page 27 of 28
AD7747
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05469-0-1/07(0)
Rev. 0 | Page 28 of 28
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