AD7763BCP [ADI]
IC 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, QCC48, LFCSP-48, Analog to Digital Converter;
| 型号： | AD7763BCP |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, QCC48, LFCSP-48, Analog to Digital Converter |
| 文件： | 总32页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24-Bit, 625 kSPS, 109 dB Σ-Δ ADC
with On-Chip Buffers, Serial Interface
AD7763
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
IN– IN+
MULTIBIT
AV
AV
AV
AV
DIFF
DD1
DD2
DD3
DD4
Σ-Δ
MODULATOR
107 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable oversampling rate (32× to 256×)
Flexible serial interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
V
REF+
RECONSTRUCTION
BUF
REFGND
DECAPA
DECAPB
PROGRAMMABLE
DECIMATION
AD7763
R
BIAS
AGND
MCLK
Low-pass finite impulse response (FIR) filter with default
or user-programmable coefficients
Overrange alert bit
MCLKGND
V
DRIVE
CONTROL LOGIC
I/O
OFFSET AND GAIN
REGISTERS
SYNC
RESET
SH2:0
DV
DD
FIR FILTER
ENGINE
DGND
ADR2:0
CDIV
Digital offset and gain correction registers
Low power and power-down modes
SYNC
Synchronization of multiple devices via
I2S interface mode
pin
Figure 1.
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series
of low-pass filters, the final filter having default or user-
programmable coefficients. The sample rate, filter corner
frequencies, and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7763.
The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital
converter (ADC) combines wide input bandwidth and high
speed with the benefits of Σ-Δ conversion, as well as performance
of 107 dB SNR at 625 kSPS, making it ideal for high speed data
acquisition. A wide dynamic range, combined with significantly
reduced antialiasing requirements, simplifies the design process.
An integrated buffer to drive the reference, a differential ampli-
fier for signal buffering and level shifting, an overrange flag,
internal gain and offset registers, and a low-pass, digital FIR
filter make the AD7763 a compact, highly integrated data
acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable
decimation rates and a digital FIR filter, which can be user-
programmed to ensure that its characteristics are tailored for the
user’s application. The AD7763 is ideal for applications demanding
high SNR without necessitating the design of complex, front-
end signal processing.
The reference voltage supplied to the AD7763 determines the
analog input range. With a 4 V reference, the analog input range
is 3.2 V differential-biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.
The AD7763 is available in an exposed paddle, 64-lead TQFP_EP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No.
AD7760
AD7762
Description
24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface
24-bit, 625 kSPS, 109 dB Σ-Δ, parallel interface
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD7763
TABLE OF CONTENTS
Features .............................................................................................. 1
Driving the AD7763....................................................................... 20
Using the AD7763...................................................................... 21
Bias Resistor Selection ............................................................... 21
Decoupling and Layout Recommendations................................ 22
Supply Decoupling ..................................................................... 23
Additional Decoupling .............................................................. 23
Reference Voltage Filtering ....................................................... 23
Differential Amplifier Components ........................................ 23
Exposed Paddle........................................................................... 23
Layout Considerations............................................................... 23
Programmable FIR Filter............................................................... 24
Downloading a User-Defined Filter ............................................ 25
Example Filter Download ......................................................... 26
Registers........................................................................................... 27
Control Register 1—Address 0x001......................................... 27
Control Register 2—Address 0x002......................................... 27
Status Register (Read Only) ...................................................... 28
Offset Register—Address 0x003............................................... 28
Gain Register—Address 0x004................................................. 28
Overrange Register—Address 0x005....................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
AD7763 Interface............................................................................ 15
Reading Data Using the SPI Interface ..................................... 15
Synchronization.......................................................................... 15
Sharing the Serial Bus ................................................................ 15
Writing to the AD7763 .............................................................. 16
Reading Status and Other Registers......................................... 17
Reading Data Using the I2S Interface....................................... 18
Clocking the AD7763..................................................................... 19
Example 1 .................................................................................... 19
Example 2 .................................................................................... 19
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7763
SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V; AVDD2 = AVDD3 = AVDD4 = 5 V; VREF = 4.096 V; MCLK amplitude = 5 V; TA = 25°C; normal mode,
using on-chip amplifier with components as shown in Table 10, unless otherwise noted.1
Table 2.
Parameter
Test Conditions/Comments
Specification
Unit
DYNAMIC PERFORMANCE
Decimate × 256
Dynamic Range
MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz
Modulator inputs shorted
119
120.5
112
59
126
77
−105
−106
−75
dB min
dB typ
dB typ
dBc typ
dBc typ
dBc typ
dB typ
dBc typ
dBc typ
Signal-to-Noise Ratio (SNR)2
Input amplitude = −0.5 dBFS
Input amplitude = −60 dB
Nonharmonic, input amplitude = −6 dB
Input amplitude = −60 dB
Input amplitude = −0.5 dBFS
Input amplitude = −6 dB
Input amplitude = −60 dB
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Decimate × 64
Dynamic Range
MCLK = 40 MHz, ODR = 312.5 kHz, FIN = 1 kHz
Modulator inputs shorted
112
113
109.5
126
dB min
dB typ
dB typ
dBc typ
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)
Decimate × 32
Input amplitude = −0.5 dBFS
Nonharmonic, input amplitude = −6 dB
MCLK = 40 MHz, ODR = 625 kHz, FIN = 100 kHz
Modulator inputs shorted
Dynamic Range
108
109.5
107
120
−105
−107
dB min
dB typ
dB typ
dBc typ
dB typ
dBc typ
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Input amplitude = −0.5 dBFS
Nonharmonic, input amplitude = −6 dB
Input amplitude = −0.5 dBFS
Input amplitude = −6 dB
DC ACCURACY
Resolution
24
Bits
Differential Nonlinearity
Integral Nonlinearity
Zero Error
Guaranteed monotonic to 24 bits
0.00076
0.014
0.02
% typ
% typ
% max
Gain Error
0.018
10
0.0002
% typ
μ%FS/°C typ
%FS/°C typ
Zero Error Drift
Gain Error Drift
DIGITAL FILTER RESPONSE
Decimate × 32
Group Delay
Decimate × 64
Group Delay
Decimate × 256
Group Delay
MCLK = 40 MHz
MCLK = 40 MHz
MCLK = 40 MHz
47
ꢀs typ
ꢀs typ
ꢀs typ
91.5
358
ANALOG INPUT
Differential Input Voltage
VIN(+) – VIN(−), VREF = 2.5 V
VIN(+) – Vin(−), VREF = 4.096 V
At internal buffer inputs
At modulator inputs
2
3.25
5
V p-p
V p-p
pF typ
pF typ
Input Capacitance
55
Rev. 0 | Page 3 of 32
AD7763
Parameter
Test Conditions/Comments
Specification
Unit
REFERENCE INPUT
VREF Input Voltage
VDD3 = 3.3 V 5%
VDD3 = 5 V 5%
+2.5
+4.096
V max
V max
VREF Input DC Leakage Current
VREF Input Capacitance
1
5
ꢀA max
pF max
POWER DISSIPATION
Total Power Dissipation
Normal power mode
Low power mode
Clock stopped
955.5
651
6.35
mW max
mW max
mW typ
Standby Mode
POWER REQUIREMENTS
AVDD1 (Modulator Supply)
AVDD2 (General Supply)
AVDD3 (Differential Amplifier Supply)
AVDD4 (Reference Buffer Supply)
DVDD
5%
5%
+2.5
+5
+3.15/+5.25
+3.15/+5.25
+2.5
V
V
V min/max
V min/max
V
5%
VDRIVE
+1.65/+2.7
V min/max
Normal Mode
AIDD1 (Modulator)
AIDD2 (General)
AIDD4 (Reference Buffer)
Low Power Mode
AIDD1 (Modulator)
AIDD2 (General)
AIDD4 (Reference Buffer)
AIDD3 (Diff Amp)
DIDD
49/52
40/43
35/37
mA typ/max
mA typ/max
mA typ/max
AVDD4 = 5 V
26/28
20/23
10/11
41/45
56/62
mA typ/max
mA typ/max
mA typ/max
mA typ/max
mA typ/max
AVDD4 = 5 V
AVDD3 = 5 V, both modes
Both modes
DIGITAL I/O
MCLK Input Amplitude3
Input Capacitance
Input Leakage Current
Three-State Leakage Current (SDO)
VINH
5
7.3
V typ
pF typ
μA/pin max
μA max
V min
V max
V min
1
1
0.7 × VDRIVE
0.3 × VDRIVE
1.5
VINL
4
VOH
VOL
0.1
V max
1 See the Terminology section.
2 SNR specifications in dB are referred to a full-scale input, FS, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3 While the AD7763 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.
4 Tested with a 400 μA load current.
Rev. 0 | Page 4 of 32
AD7763
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMCLK
1
40
500
20
MHz min
MHz max
kHz min
MHz max
typ
Applied master clock frequency
fICLK
Internal modulator clock derived from MCLK
1
2
2
t1
t2
1 × tICLK or 0.5 × tICLK
1 × tICLK or 0.5 × tICLK
tSCO
SCO high period
SCO low period
DRDY low period
1
typ
typ
3
t3
4
t3A
2
3
ns typ
ns typ
typ
SCO rising edge to DRDY falling edge
SCO rising edge to DRDY rising edge
FSO low period
4
t3B
5
3
t4
32 × tSCO
4, 5
t4A
1
ns typ
ns typ
ns max
ns max
ns min
typ
SCO rising edge to FSO falling edge
SCO falling edge to FSO rising edge
Initial data access time
SCO rising edge to SDO valid
SDO valid after SCO falling edge
DRDY rising edge to SDL falling edge
SDL pulse width
4, 5
t4B
2
t5
t6
6.5
5
0.5 × tSCO
4
3
t7
t8
3
16 × tSCO
3
t9
tSCO
typ
t10
t11
t12
t13
t14
t15
5.5
1 × tSCO
ns max
min
SDO three-state to SCO rising edge
FSI low period
3
12
10
12
ns min
ns min
ns min
typ
SDI setup time
SDI hold time
FSI setup time
3
16 × tSCO
SDL falling edge to SDL falling edge
1 tICLK = 1/fICLK
.
2
CDIV
SCO frequency selected by SCR and
pins.
3 tSCO = t1 + t2.
4 All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
5
CDIV
CDIV
and SCR in decimate × 32 mode, the FSO
In decimate × 32 mode, this time specification applies only when
signal is constantly logic low.
= 0 and SCR =1. For all other combinations of
Rev. 0 | Page 5 of 32
AD7763
TIMING DIAGRAMS
t4
FSO (O)
t4A
t4B
t1
SCO (O)
t3B
t2
t3A
DRDY (O)
t3
t10
t5
t6
t7
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ST6 ST5 ST4 ST3 ST2 ST1 ST0
SDO (O)
SDL (O)
t8
t9
t15
Figure 2. SPI® Interface Serial Read Timing Diagram
32 × tSCO
SCO (O)
FSI (I)
t1
t2
t14
t13
t11
t12
RA11
SDI (I)
ALL
ADR2
ADR1
ADR0
RA10
RA1
RA0
D15
D14
D1
D0
Figure 3. Register Write
32 × tSCO
32 × tSCO
32 × tSCO
32 × tSCO
SCO (O)
DRDY A (O)
SDO (O)
SERIAL DATA FROM ADC A
SERIAL DATA FROM ADC B
SERIAL DATA FROM ADC C
SERIAL DATA FROM ADC D
FSO A
FSO B
FSO C
FSO D
Figure 4. SPI Interface Serial Read Timing with Multiple AD7763 Devices Sharing the Serial Bus
Rev. 0 | Page 6 of 32
AD7763
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD1 to GND
(AVDD2, AVDD3, AVDD4) to GND
DVDD to GND
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to +3 V
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +6 V
−0.3 V to AVDD4 + 0.3 V
−0.3 V to +0.3 V
10 mA
VDRIVE to GND
VIN+, VIN– to GND
Digital Input Voltage to GND1
MCLK to MCLKGND
VREF to GND2
AGND to DGND
Input Current to Any Pin
Except Supplies3
Operating Temperature Range
Commercial
−40°C to +85°C
Storage Temperature Range
Junction Temperature
TQFP_EP Exposed Paddle
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
−65°C to +150°C
150°C
92.7°C/W
5.1°C/W
215°C
220°C
600 V
ESD
1 Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,
whichever is lower.
2 Absolute maximum voltage on VREF input is 6.0 V or AVDD4 + 0.3 V,
whichever is lower.
3 Transient currents of up to 200 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 32
AD7763
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DGND
ADR0
ADR1
ADR2
SH0
PIN 1
2
MCLKGND
3
4
MCLK
AV
DD2
AGND2
AV
5
V
DRIVE
6
DGND
DGND
DD1
AD7763
TOP VIEW
(Not to Scale)
7
AGND1
DECAPA
REFGND
8
DV
DD
9
SH1
10
11
12
13
14
15
16
V
SH2
REF+
AGND4
AV
DRDY
RESET
SYNC
DGND
AGND1
DD4
AGND2
AV
AV
DD2
DD2
AGND2
AV
DD1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
6, 33
AVDD1
Power Supply for Modulator, 2.5 V. These pins should be decoupled to AGND1 with 100 nF and
10 ꢀF capacitors on each pin.
4, 14, 15, 27
AVDD2
AVDD3
AVDD4
Power Supply, 5 V. These pins should be decoupled to AGND2 with 100 nF capacitors on each of
Pin 4, Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via an 8.2 nH inductor.
Power Supply for Differential Amplifier, 3.3 V to 5 V. This pin should be decoupled to AGND3
with a 100 nF capacitor.
24
12
Power Supply for Reference Buffer, 3.3 V to 5 V. This pin should be decoupled to AGND4
with a 10 nF capacitor in series with a 10 Ω resistor.
7, 34
5, 13, 16, 18, 28
23, 29, 31, 32
11
9
AGND1
AGND2
AGND3
AGND4
REFGND
DVDD
Power Supply Ground for Analog Circuitry Powered by AVDD1
Power Supply Ground for Analog Circuitry Powered by AVDD2
Power Supply Ground for Analog Circuitry Powered by AVDD3
Power Supply Ground for Analog Circuitry Powered by AVDD4
Reference Ground. Ground connection for the reference voltage.
Power Supply for Digital Circuitry and FIR Filter, 2.5 V. This pin should be decoupled to DGND
with a 100 nF capacitor.
.
.
.
.
41
44, 63
VDRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines
the operating voltage of the logic interface. These pins must be connected together and
tied to the same supply. Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43, 53, 57, 59, DGND
62, 64
Ground Reference for Digital Circuitry.
19
20
21
22
25
26
10
VINA+
VINA−
VOUTA−
VOUTA+
VIN+
Positive Input to Differential Amplifier.
Negative Input to Differential Amplifier.
Negative Output from Differential Amplifier.
Positive Output from Differential Amplifier.
Positive Input to the Modulator.
Negative Input to the Modulator.
Reference Input. The input range of this pin is determined by the reference buffer
supply voltage (AVDD4). See the Reference Voltage Filtering section for more details.
VIN−
VREF+
8
30
DECAPA
DECAPB
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
Rev. 0 | Page 8 of 32
AD7763
Pin No.
Mnemonic
Description
17
RBIAS
Bias Current Setting. A resistor must be inserted between this pin and AGND.
See the Bias Resistor Selection section.
37
3
RESET
MCLK
A falling edge on this pin resets all internal digital circuitry. Holding this pin low
keeps the AD7763 in a reset state.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate
depends on the frequency of this clock. See the Clocking the AD7763 section.
2
36
MCLKGND
SYNC
Master Clock Ground Sensing Pin.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used
to synchronize multiple devices in a system.
38
DRDY
SH2:0
Data Ready Output. Each time new conversion data is available, an active low pulse,
½ ICLK period wide, is produced on this pin. See the AD7763 Interface section.
Share Pins 2:0. For multiple AD7763 devices sharing a common serial bus. Each device is wired
with the binary value that represents the number of devices sharing the serial bus. SH2 is the
MSB. See the Sharing the Serial Bus section.
39, 40, 45
46 to 48
49
ADR2:0
SCP
Address 2:0. Allows multiple AD7763 devices to share a common serial bus. Each device must be
programmed with an individual address using these three pins. See the Sharing the Serial Bus
section.
Serial Clock Polarity. Determines on which edge of SCO the data bits are clocked out and on
which edge they are valid. All timing diagrams are shown with SCP = 0, and all SCO edges
shown should be inverted for SCP = 1.
50
SDL
FSI
Serial Data Latch. A pulse is output on this pin after every 16 data bits. The pulse is one SCO
period wide and can be used in conjunction with FSO as an alternative framing method for
serial transfers requiring a framing signal more frequent than every 32 bits.
Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low, then
the first data bit is latched in on the next SCO falling edge when SCP = 0 or on the rising edge of
SCO if SCP = 1.
51
52
SDI
Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge when SCP = 0
(or SCO rising edge SCP = 1) after the FSI event has been latched. Each write requires 32 bits: the
ALL bit, 3 address bits, and 12 register address bits, followed by the remaining 16 bits of data to
be written to the device.
54
SDO
Serial Data Out. Address, status, and data bits are clocked out on this line during each serial
transfer.
If SCP = 0, each bit is clocked out on an SCO rising edge and is valid on the falling edge. When
the I2S pin is set to logic high, this pin outputs the signal defined as SD in the I2S bus
specification. See the Reading Data Using the I2S Interface section for details.
55
56
SCO
FSO
Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of SCO
is equal to either ICLK or ICLK/2, depending on the state of the CDIV and SCR pins (see the
AD7763 Interface section). When the I2S pin is logic high, this pin outputs the signal defined as
SCK by the I2S bus specification. See the Reading Data Using the I2S Interface section.
Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. The
FSO
exception to the framing behavior of
FSO
occurs in decimate × 32 mode, where, for certain
signal is constantly logic low. See the Reading Data
combinations of CDIV and SCR, the
Using the SPI Interface section. When the I2S pin is set to logic high, this pin outputs the signal
defined as WS in the I2S bus specification. See the Reading Data Using the I2S Interface section.
58
CDIV
Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the AD7763 Interface
section.
60
61
SCR
I2S
Serial Clock Rate. This pin and the CDIV pin program the SCO frequency (see Table 7).
I2S Select. A Logic 1 on this pin changes the serial data-out mode from SPI to I2S. The SDO pin
FSO
outputs as the SD signal, the SCO pin outputs the SCK signal, and the
pin outputs the WS
signal. When writing to the AD7763, the I2S pin is set to logic low and the SPI interface is used.
See the Reading Data Using the I2S Interface section for further details.
Rev. 0 | Page 9 of 32
AD7763
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Integral Nonlinearity (INL)
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7763, it is defined as
Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
V22 +V32 +V42 +V52 +V62
THD
where:
dB = 20 log
( )
V1
Zero Error Drift
The change in the actual zero error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at room
temperature.
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
to the sixth harmonic.
Gain Error
The first transition (from 100…000 to 100…001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.
Dynamic Range
The ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.
Gain Error Drift
The change in the actual gain error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at
room temperature.
Rev. 0 | Page 10 of 32
AD7763
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All FFTs
are generated from 65536 samples using a 7-term Blackman-Harris window.
0
0
–50
–50
–100
–150
–200
–250
–100
–150
–200
–250
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
Figure 6. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation
Figure 9. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation
0
0
–50
–100
–150
–200
–250
–50
–100
–150
–200
–250
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
Figure 7. Normal Mode FFT, 1 kHz, −0.6 dB Input Tone, 256× Decimation
Figure 10. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation
0
0
–50
–100
–150
–200
–250
–50
–100
–150
–200
–250
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
0
5000 10000 15000 20000 25000 30000 35000
FREQUENCY (Hz)
Figure 8. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation
Figure 11. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation
Rev. 0 | Page 11 of 32
AD7763
0
0
–50
–50
–100
–150
–200
–100
–150
–200
–250
–250
0
50000
100000
150000 200000
250000
300000
0
50000
100000
150000 200000
250000
300000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation
Figure 15. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation
0
0
–50
–100
–150
–200
–250
–50
–100
–150
–200
–250
0
50000
100000
150000 200000
250000
300000
0
50000
100000
150000 200000
250000
300000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation
Figure 16. Low Power FFT, 100 kHz, −6 dB Input Tone, 32× Decimation
120
116
–60dB
–60dB
118
114
–6dB
116
112
–6dB
–0.5dB
114
110
112
–0.5dB
108
106
104
110
108
106
0
64
128
192
256
0
64
128
192
256
DECIMATION RATE (×)
DECIMATION RATE (×)
Figure 14. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone
Figure 17. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone
Rev. 0 | Page 12 of 32
AD7763
4500
4000
3500
3000
6000
5000
4000
3000
2000
2500
2000
1500
1000
500
1000
0
0
8385341 8385351 8385361 8385371 8385381 8385391 8385401
8383091
8383111
8383131
8383151
8383171
8383191
24-BIT CODE
24-BIT CODE
Figure 18. Normal Mode, 24-Bit Histogram, 256× Decimation
Figure 21. Low Power 24-Bit Histogram, 256× Decimation
0.0010
0.0005
0
0.0015
0.0010
0.0005
0
+85°C
+85°C
+25°C
+25°C
–40°C
–40°C
–0.0005
–0.0010
–0.0005
–0.0010
0
4194304
8388608
12582912
16777216
0
4194304
8388608
12582912
16777216
24-BIT CODE
24-BIT CODE
Figure 19. 24-Bit INL, Normal Power Mode
Figure 22. 24-Bit INL, Low Power Mode
0.65
0.4
0.2
0
–0.2
–0.4
–0.6
0
4194304
8388608
12582912
16777216
24-BIT CODE
Figure 20. 24-Bit DNL
Rev. 0 | Page 13 of 32
AD7763
THEORY OF OPERATION
The AD7763 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
The second filter allows the decimation rate to be chosen from
8× to 32×. The third filter has a fixed decimation rate of 2x, is
user programmable, and has a default configuration (see the
Programmable FIR Filter section). This filter can be bypassed.
Due to the high oversampling rate, which spreads the quanti-
zation noise from 0 to fICLK, the noise energy contained in the
band of interest is reduced (see Figure 23). To further reduce
quantization noise, a high order modulator is employed to shape
the noise spectrum; thus, most of the noise energy is shifted out
of the band of interest (see Figure 24).
Table 6 shows some characteristics of the default filter. The group
delay of the filter is defined as the delay to the center of the
impulse response and is equal to the computation plus filter
delays. The delay until valid data is available (the DVALID status bit
is set) is equal to 2× the filter delay plus the computation delay.
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 25), while
also reducing the data rate from fICLK at the input of the filter
to fICLK/32 or less at the output of the filter, depending on the
decimation rate used.
QUANTIZATION NOISE
f
/2
ICLK
BAND OF INTEREST
Figure 23. Σ-Δ ADC, Quantization Noise
Digital filtering has certain advantages over analog filtering.
It does not introduce significant noise or distortion and can
be made perfectly linear phase.
NOISE SHAPING
f
/2
ICLK
BAND OF INTEREST
The AD7763 employs three finite impulse response (FIR) filters
in series. By using different combinations of decimation ratios
and filter selection, data can be obtained from the AD7763 at
four different data rates. The first filter receives data from the
modulator at ICLK MHz, where it is decimated × 4 to output
data at (ICLK/4) MHz.
Figure 24. Σ-Δ ADC, Noise Shaping
DIGITAL FILTER CUTOFF FREQUENCY
f
/2
ICLK
BAND OF INTEREST
Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency
Table 6. Configuration With Default Filter
ICLK
Frequency
Filter
1
Filter
2
Computation
Delay
Filter
Delay
Pass Band
Bandwidth
Output Data Rate
(ODR)
Filter 3
Data State
20 MHz
20 MHz
4×
4×
4×
8×
2×
Fully filtered 1.775 ꢀs
44.4 ꢀs
10.8 ꢀs
250 kHz
140.625 kHz
625 kHz
625 kHz
Bypassed Partially
filtered
2.6 ꢀs
20 MHz
20 MHz
4×
4×
8×
16×
2×
Fully filtered 2.25 ꢀs
87.6 ꢀs
20.4 ꢀs
125 kHz
70.3125 kHz
312.5 kHz
312.5 kHz
Bypassed Partially
filtered
4.175 ꢀs
20 MHz
20 MHz
4×
4×
16×
32×
2×
Fully filtered 3.1 ꢀs
174 ꢀs
39.6 ꢀs
62.5 kHz
35.156 kHz
156.25 kHz
156.25 kHz
Bypassed Partially
filtered
7.325 ꢀs
20 MHz
4×
4×
4×
4×
32×
8×
16×
32×
2×
2×
2×
Fully filtered 4.65 ꢀs
Fully filtered 3.66 ꢀs
Fully filtered 5.05 ꢀs
346.8 ꢀs
142.6 ꢀs
283.2 ꢀs
64.45 ꢀs
31.25 kHz
76.8 kHz
38.4 kHz
21.6 kHz
78.125 kHz
192 kHz
96 kHz
12.288 MHz
12.288 MHz
12.288 MHz
Bypassed Partially
filtered
11.92 ꢀs
96 kHz
12.288 MHz
4×
32×
2×
Fully filtered 7.57 ꢀs
564.5 ꢀs
19.2 kHz
48 kHz
Rev. 0 | Page 14 of 32
AD7763
AD7763 INTERFACE
READING DATA USING THE SPI INTERFACE
The timing diagram in Figure 2 shows how the AD7763 transmits
its conversion results using the SPI-compatible serial interface.
The AD7763 also features a serial data latch output, SDL, which
outputs a pulse every 16 data bits. The SDL output offers an
alternative framing signal for serial transfers, which require
a framing signal more frequent than every 32 bits.
The data being read from the AD7763 is clocked out using the
serial clock output, SCO. The SCO frequency is dependent on
the state of the serial clock output rate pin, SCR, and the clock
SYNCHRONIZATION
CDIV
divider mode chosen by the state of the clock divider pin,
SYNC
The
input to the AD7763 provides a synchronization
(see the Clocking the AD7763 section). Table 7 shows both the
SCO frequency and the ICLK frequency for the AD7763, resulting
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
CDIV
from the states of both the
and SCR pins.
SYNC
The
function allows multiple AD7763s, operated from
SYNC
Table 7. SCO Frequency
the same master clock and using the same
synchronized so that each ADC simultaneously updates its
output register.
signal, to be
Clock Divide
Mode
SCO
ICLK
Frequency
CDIV
SCR Frequency
Divide by 1
1
0
1
0
1
MCLK
MCLK
MCLK/2
MCLK1
MCLK
MCLK
MCLK/2
MCLK/2
SYNC
Using a common
system allows synchronization to occur. On the falling edge of
SYNC
signal to all AD7763 devices in a
Divide by 2
0
the
signal, the digital filter sequencer is reset to 0. The
1
CDIV
FSO
pulses low for
In decimate × 32 mode, when
= 0 and SCR = 1,
filter is held in reset state until a rising edge of the SCO senses
CDIV
32 SCO clock cycles, as shown in Figure 2. For all other combinations of
FSO
and SCR in decimate × 32 mode,
is continuously low.
SYNC
SYNC
high. Thus, to perform a synchronization of devices, a
pulse of a minimum of 2.5 ICLK cycles in length can be
An active low pulse of one SCO period on the data-ready output,
DRDY
applied, synchronous to the falling edge of SCO. On the first
SYNC
, indicates a new conversion result is available at the
rising edge of SCO after
goes logic high, the filter is taken
AD7763 serial data output, SDO.
out of reset, and the multiple parts gather input samples
synchronously.
Each bit of the new conversion result is clocked onto the SDO
line on the rising SCO edge and is valid on the falling SCO edge
(for SCP = 0). The conversion result spans 32 SCO clock cycles
and consists of 24 data bits in twos complement form, followed
by 7 status bits.
SYNC
Following a
, the digital filter needs time to settle before
valid data can be read from the AD7763. The user knows there
is valid data on the SDO line by checking the DVALID status bit
(see D3 in the status bits listing) that is output with each conversion
result. The time from the rising edge of SYNC until the DVALID
bit is asserted is dependent on the filter configuration used. See the
Theory of Operation section and the figures listed in Table 6 for
details on calculating the time until DVALID is asserted.
D6
D5
D4
D3
D2
D1
D0
ADR2 ADR1 ADR0 DVALID OVR LPWR FILTER_OK
The conversion result output on the SDO line is framed by the
frame synchronization output,
, which is sent logic low for
FSO
DRDY
32 SCO cycles following the rising edge of the
Note that the SDO line is in three-state for one clock cycle
before the signal returns to logic high, which means that
signal.
SHARING THE SERIAL BUS
The AD7763 functionality allows up to eight devices to share
the same serial bus, SDO, depending on the decimation rate
that is chosen.
FSO
only 31 actual data bits are output in each conversion.
The first three status bits, ADR[2:0], are the device address bits.
The DVALID bit is asserted when the data being clocked out on
the SDO line is valid. Table 19 contains descriptions of the other
status bits: OVR, LPWR, and FILTER_OK.
Table 8 details the maximum number of devices that can share
the same SDO line for each decimation rate (×32, ×64, ×128,
×256).
Table 8. Maximum Number of Devices Sharing SDO
There is an exception to the behavior of
when the AD7763
FSO
operates in decimate × 32 mode (see Endnote 1 of Table 7). If SCR
CDIV
Decimation Rate
SCO
(MHz)
and
are chosen so that the SCO frequency output has the
×32 ×64 ×128 ×256
capability to clock through only 32 SCO cycles before the MSB
Maximum Number of
Devices Sharing SDO
40
20
2
N/A
4
2
8
4
8
8
of the next conversion result is output, then
continuously.
stays logic low
FSO
The Share Pins SH[2:0] of all the devices sharing the serial bus
must be programmed with the number of devices that are
sharing the serial bus.
Rev. 0 | Page 15 of 32
AD7763
Using the Address Pins ADR[2:0], all devices that share the
serial bus are assigned binary addresses from 000 to 111
(depending on the number of devices in the share scheme). The
address assigned to each device must not have a value greater
than the number of devices sharing the serial bus. Thus,
ADR[2:0] ≤ SH[2:0]. This applies to all the devices that share the
serial bus. Note also that each of the devices in the share scheme
must have a different individual address.
AD7763
DEVICE
ADDRESS
000
(000)
ADR[2:0]
FSO
SDO
FSO A
DRDY
A
SH[2:0]
SH[2:0]
100
DRDY
MCLK
MCLK
For the device in the share scheme with an address of 000, the
SDO line comes out of three-state on the first rising edge of SCO
AD7763
DEVICE
ADDRESS
001
(001)
ADR[2:0]
FSO
SDO
FSO B
DRDY
after the
pulse and returns to three-state 5.5 ns before
B
SH[2:0]
the 31st SCO rising edge. For the next device sharing the serial
bus, Address 001, the SDO line comes out of three-state on the
33rd SCO rising edge (that is, the first SCO rising edge of the
next conversion output cycle). Thus, the SDO line goes into tri-
state for one SCO cycle in between data being clocked onto SDO
by two different devices that share the SDO line. This means
that a bus contention issue is avoided. This pattern of behavior
continues for the rest of the devices sharing the serial bus.
MCLK
SHARED
SERIAL DATA OUTPUT
(SDO)
AD7763
DEVICE
ADDRESS
010
(010)
ADR[2:0]
FSO
SDO
FSO C
C
SH[2:0]
Each AD7763 device sharing the serial bus outputs its own
signal.
FSO
MCLK
Figure 26 shows an example of four devices sharing the same
serial bus. All the devices in the share chain shown in Figure 26
operate in decimate × 64 mode (selected by writing to Control
Register 1—Address 0x001) and use a maximum SCO signal of
40 MHz (see the Clocking the AD7763 section).
AD7763
DEVICE
ADDRESS
011
(011)
ADR[2:0]
FSO
SDO
FSO D
D
The Share Pins SH[2:0] of all the devices shown in Figure 26
are set to 011, corresponding to the four devices that are in the
share configuration. Each AD7763 is hardwired with a different
binary address ranging from 000 to 011, using the Address Pins
ADR[2:0].
SH[2:0]
MCLK
Figure 26. Four AD7763 Devices Sharing the Serial Bus
The timing diagram for the share configuration shown in
Figure 26 is detailed in Figure 4. Device A outputs its 32-bit
conversion result on the SDO line during the first 32 SCO
cycles (as per the format shown in the Reading Data Using the
SPI Interfacesection). Device B then outputs its conversion
result during the next 32 SCO cycles, and so on for Device C
and Device D. Note the way in which the SDO line is three-
stated, separating data from each of the devices sharing the
FSI
The active edge of the
signal should be set to occur at a position
when the SCO signal is high or low and which also allows setup
and hold time from the SCO falling edge to be met. The width
FSI
of the
signal can be set to between 1 SCO period and 32 SCO
FSI
periods wide. A second or subsequent
falling edge, which
occurs before 32 SCO periods have elapsed, is ignored.
Figure 3 also shows the format for the serial data written to the
AD7763. A write operation requires 32 bits. The first 16 bits select
the device and register address for which the data written is
intended. The second 16 bits contain the data for the selected
register. When using multiple devices that share the same serial bus,
DRDY
serial bus. The provision of two framing signals,
and
FSO
, ensures that the AD7763 offers flexible data output
framing options, which are further enhanced by the availability
of the SDL output. The user can select the framing output that
best suits the application.
FSO
all
and SDI pins can be tied together and each device written
WRITING TO THE AD7763
to individually by setting the appropriate address bits in the serial
32-bit word. The exception to this is when all devices can be written
to at the same time by setting the ALL bit to logic high.
Figure 3 shows the AD7763 write operation. The serial writing
operation is synchronous to the SCO signal. The status of the
FSI
frame sync input,
, is checked on the falling edge of the SCO
line is low, then the first data is latched in on
the next SCO falling edge.
FSI
signal. If the
Rev. 0 | Page 16 of 32
AD7763
Thus, if this bit is set to logic high, every device on the serial
bus accepts the data written, regardless of the address bits. This
feature is particularly attractive if, for example, four devices are
being configured with the same user-defined filter. Instead of
having to download the filter configuration four times, only one
write is required. See the Downloading a User-Defined Filter
section for further details.
READING STATUS AND OTHER REGISTERS
The AD7763 features a number of programmable registers. To
read back the contents of these registers or the status register,
the user must first write to the control register of the device,
setting a bit corresponding to the register to be read. The next
read operation then outputs the contents of the selected register
instead of a conversion result.
Writing to AD7763 is allowed at any time, even while reading a
conversion result. Note that after writing to the devices, valid
data is not output until after the settling time for the filter has
elapsed. The DVALID status bit is asserted at this point to
indicate that the filter has settled and that valid data is available
at the output.
To ensure that the next read cycle contains the contents of the
register that has been written to, the write operation to the register
in question must be completed a minimum of 8 × tSCO before
DRDY
the falling edge of
read cycle.
, which indicates the start of the next
More information on the relevant bits in the control register is
provided in the Registers section.
Rev. 0 | Page 17 of 32
AD7763
READING DATA USING THE I2S INTERFACE
The AD7763 has the capability of operating using an I2S
interface. The interface is functional only for the output of
stereo data and does not apply to writing to control registers,
programming coefficients for the digital filter, or the reading of
any information contained in the AD7763 onboard registers.
All of these operations must be undertaken using the normal
serial interface.
The I2S interface operates using two AD7763 devices. The pins
shown in Table 9 are used as the output pins for the SCK (serial
clock), SD (serial data), and WS (word select) signals for the I2S
interface.
LEFT CHANNEL
AD7763
(000)
DEVICE
ADDRESS
000
ADR[2:0]
FSO
SCO
2
A
I S
1
WS
SH[2:0]
SDO
MCLK
MCLK
3-WIRE
I S INTERFACE
SCK
2
001
SH[2:0]
MCLK
SD
SH[2:0]
SDO
2
B
I S
1
Table 9.
SPI Pins
I2S Signals
WS
DEVICE
ADDRESS
001
ADR[2:0]
FSO
AD7763
(001)
SDO
SD
RIGHT CHANNEL
SCO
SCK
Figure 27. Two AD7763 Devices Operating Using the I2S Interface
To enable the I2S interface, the I2S pin is set to logic high. The
Share Pins SH[2:0] of both AD7763 devices that use the I2S
interface are set to 001. The Address Pins ADR[2:0] of the two
devices must also be set to 000 and 001, respectively.
Conversion results from Device B, assigned Address 001, are
clocked out on the SD line when WS is logic high. The SD line
goes into three-state on the falling edge of the 32nd SCK after
the falling edge of WS (left channel data) and also on the falling
edge of the 32nd SCK after the rising edge of WS (right channel
data). This permits swapping of the SD bus between the left and
right channel devices without contention.
The WS and SCK signals that are used for the interface can be
taken from either AD7763 device. Note that the device that is
assigned Address 000 is defined as the left channel, and its data
is output on the SD line when WS is logic low.
In decimate × 32 mode the I2S interface is operational only
The WS and SCK signals can be taken from the appropriate
pins on either of the AD7763 devices using the I2S interface.
The SD pins of both devices must be connected together, as
shown in Figure 27.
CDIV
when
= 0 and SCR = 1. The interface operates for all
CDIV
combinations of SCR and
decimation.
in all other modes of
Data is clocked out on the SD line in accordance with Figure 28.
Because Device A is assigned Address 000, it is defined as the
left channel. The 32-bit conversion result from the left channel
is clocked out when WS is logic low, with the MSB being clocked
out first. Each 32-bit result consists of 24 data bits in twos
complement format, followed by eight status bits, as shown in
the following bit map.
DRDY
The
pulse still operates as in the normal serial SPI-type
interface, pulsing low immediately prior to the falling edge of
WS but having no meaning in the I2S interface specification.
D7
D6
D5
D4
D3
D2
D1 D0
0
Three-
DVALID OVR UFILTER LPWR FILTER_OK ADR0
State
SCK A (O)
WS A (O)
THREE-
STATE
THREE-
STATE
THREE-
STATE
D23
D22
D21
ST2
ST1
D23
D22
D21
ST2
ST1
SD (O)
RIGHT CHANNEL
DEVICE B
LEFT CHANNEL
DEVICE A
RIGHT CHANNEL
LEFT CHANNEL
DEVICE A
DEVICE B
(WORD n – 1)
(WORD n)
(WORD n + 1)
(WORD n + 2)
Figure 28. Timing Diagram for I2S Interface
Rev. 0 | Page 18 of 32
AD7763
CLOCKING THE AD7763
The AD7763 requires an external, low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7763. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
EXAMPLE 2
Following is a second example from Table 6, where:
ODR = 48 kHz.
fICLK = 12.288 MHz.
fIN (maximum) = 19.2 kHz.
SNR = 120 dB.
256
tj(rms)
=
= 133ps
2×π×19.2×103 ×106
ICLK = MCLK (
= 1)
CDIV
ICLK = MCLK/2 (
= 0)
CDIV
The input amplitude also has an effect on these jitter figures.
If, for example, the input level is 3 dB below full scale, the allowable
jitter is increased by a factor of √2, increasing the first example
to 2.53 ps rms. This happens when the maximum slew rate is
decreased by a reduction in amplitude. Figure 29 and Figure 30
illustrate this point, showing the maximum slew rate of a sine
wave of the same frequency but with different amplitudes.
This option is pin selectable (Pin 58). On power-up, the default
is ICLK = MCLK/2 to ensure that the part can handle the maxi-
mum MCLK frequency of 40 MHz. For output data rates equal to
those used in audio systems, a 12.288 MHz ICLK frequency can
be used. As shown in Table 6, output data rates of 192 kHz, 96 kHz,
and 48 kHz are achievable with this ICLK frequency. As mentioned
previously, this ICLK frequency can be derived from different
MCLK frequencies.
1.0
0.5
0
The MCLK jitter requirements depend on a number of factors
and are determined by
OSR
t j(rms)
=
SNR(dB)
20
2×π× fIN ×10
Where:
OSR = oversampling ratio =
–0.5
fICLK
ODR
.
fIN = maximum input frequency.
SNR(dB) = target SNR.
–1.0
Figure 29. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
EXAMPLE 1
1.0
This example is taken from Table 6, where:
ODR = 625 kHz.
fICLK = 20 MHz.
0.5
fIN (maximum) = 250 kHz.
SNR = 108 dB.
0
32
t j(rms)
=
= 3.6 ps
2 ×π × 250 ×103 ×106
–0.5
–1.0
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
Figure 30. Maximum Slew Rate of Same Frequency Sine Wave
with Amplitude of 1 V p-p
Rev. 0 | Page 19 of 32
AD7763
DRIVING THE AD7763
+2.5V
0V
+3.685V
+2.048V
+0.410V
The AD7763 has an on-chip differential amplifier that operates
with a supply voltage (AVDD3) from 3.15 V to 5.25 V. For a 4.096 V
reference, the supply voltage must be 5 V.
V
+
IN
A
To achieve the specified performance in normal mode, the
differential amplifier should be configured as a first-order
antialias filter, as shown in Figure 31. Any additional filtering
should be carried out in previous stages using low noise, high
performance op amps, such as the AD8021.
–2.5V
+2.5V
0V
+3.685V
+2.048V
+0.410V
B
V
–
IN
Suitable component values for the first-order filter are shown in
Table 10. The values in Table 10 yield a 10 dB attenuation at the
first alias point of 19 MHz.
–2.5V
Figure 32. Differential Amplifier Signal Conditioning
C
FB
C
FB
R
FB
R
2R
FB
R
R
R
R
IN
M
M
2R
A
B
V
V
–
+
V
IN
IN
R
R
R
IN
M
M
C
A1
S
AD8021
V
V
–
+
IN
C
A1
S
IN
R
IN
R
IN
R
FB
R
IN
FB
C
FB
C
FB
Figure 31. Differential Amplifier Configuration
Figure 33. Single-Ended-to-Differential Conversion
Table 10. Normal Mode Component Values
V
+
VREF
RIN
RFB
RM
CS
CFB
IN
CS1
SS1
SH1
4.096 V
1 kΩ
655 Ω
18 Ω
5.6 pF
33 pF
SH3
CPA
SS3
CPB1
Figure 32 shows the signal conditioning that occurs using the
circuit in Figure 18 with a 2.5 V input signal biased around
ground and having the component values and conditions in
Table 10.
ANALOG
MODULATOR
CS2
SS2
SH2
SH4
The differential amplifier always biases the output signal to sit
on the optimum common mode of VREF/2, in this case, 2.048 V.
The signal is also scaled to give the maximum allowable voltage
swing with this reference value. This is calculated as 80% of
VREF; that is, 0.8 × 4.096 V ≈ 3.275 V p-p on each input.
SS4
CPB2
Figure 34. Equivalent Input Circuit
The AD7763 employs a double sampling front end, as shown in
Figure 34. For simplicity, only the equivalent input circuit for
VIN+ is shown. The equivalent input circuitry for VIN− is the same.
To obtain maximum performance from the AD7763, it is
advisable to drive the ADC with differential signals. Figure 33
shows how a bipolar, single-ended signal biased around ground
can drive the AD7763 with the use of an external op amp, such as
the AD8021.
With a 4.096 V reference, a 5 V supply must be provided to the
reference buffer (AVDD4). With a 2.5 V reference, a 3.3 V supply
must be provided to AVDD4
.
Rev. 0 | Page 20 of 32
AD7763
SYNC
The following are conditions for applying the
SYNC
pulse:
Sampling Switch SS1 and Sampling Switch SS3 are driven by ICLK,
whereas Sampling Switch SS2 and Sampling Switch SS4 are driven
• The issuing of a
pulse to the part must not coincide
by
. When ICLK is high, the analog input voltage is connected
ICLK
with a write to the part.
to CS1. On the falling edge of ICLK, the SS1 and SS3 switches
open, and the analog input is sampled on CS1. Similarly, when
ICLK is low, the analog input voltage is connected to CS2. On
the rising edge of ICLK, the SS2 and SS4 switches open, and the
analog input is sampled on CS2.
SYNC
• The
of 2.5 ICLK cycles after the
to the part has returned to logic high.
pulse should be applied a minimum
FSI
signal for the previous write
SYNC
• Ensure that the
2.5 ICLK cycles.
pulse is taken low for a minimum of
Capacitor CPA, Capacitor CPB1, and Capacitor CPB2 represent
parasitic capacitances that include the junction capacitances
associated with the MOS switches.
Data can now be read from the part using the default filter,
offset, gain, and overrange threshold values. The conversion
data read is not valid, however, until the settling time of the
filter has passed. When this has occurred, the DVALID bit read
is set, indicating that the data is indeed valid.
Table 11. Equivalent Component Values
Mode
CS1
CS2
CPA
CPB1/CPB2
20 pF
5 pF
Normal
Low Power
51 pF
13 pF
51 pF
13 pF
12 pF
12 pF
The user can then download a user-defined filter, if required
(see Downloading a User-Defined Filter). Values for gain, offset,
and overrange threshold registers can also be written or read at
this stage.
USING THE AD7763
Following is the recommended sequence for powering up and
using the AD7763.
1. Apply power.
BIAS RESISTOR SELECTION
The AD7763 requires a resistor to be connected between the
2. Start clock oscillator, applying MCLK.
RBIAS pin and AGND. The value for this resistor is dependent on
RESET
3. Take
low for a minimum of 1 MCLK cycle.
the reference voltage being applied to the device. The resistor
value should be selected to give a current of 25 μA through the
resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 kΩ; for a 4.096 V reference voltage, the
correct resistor value is 160 kΩ.
RESET
4. Wait a minimum of 2 MCLK cycles after
released.
has been
5. Write to Control Register 2 to power up the ADC and the
differential amplifier, as required.
6. Write to Control Register 1 to set up the output data rate.
7. In circumstances where multiple parts are being
SYNC
synchronized, a
SYNC
pulse must be applied to the parts;
pulse is required.
otherwise, no
Rev. 0 | Page 21 of 32
AD7763
DECOUPLING AND LAYOUT RECOMMENDATIONS
Due to the high performance nature of the AD7763, correct decoupling and layout techniques are required to obtain the performance as
stated within this data sheet. Figure 35 shows a simplified connection diagram for the AD7763.
U2
61
19
20
21
22
2
2
I S
I S
INA+
INA–
V
V
V
V
A+
A–
60
58
IN
SCR
SCR
CDIV
IN
CDIV
OUTA–
OUTA+
A–
A+
OUT
OUT
56
55
54
FSO
SCO
SDO
FSO
SCO
SDO
8
DECAPA
DECAPB
30
52
51
SDI
FSI
SDI
FSI
25
26
VIN+
VIN–
V
V
+
–
IN
C7
100nF
C64
33pF
50
49
SDL
SCP
IN
SDL
SCP
AD7763BSV
48
47
46
10
9
ADR0
ADR1
ADR2
ADR0
ADR1
ADR2
VREF
V
+
REF
REFGND
17
R
45
40
39
BIAS
SH0
SH1
SH2
1
35
42
43
53
57
59
62
64
SH0
SH1
SH2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
37
36
38
RESET
SYNC
DRDY
RESET
SYNC
DRDY
R19
160kΩ
3
2
MCLK
MCLK
MCLKGND
AV
DD2
AV
AV
DD1
AV
DD3
V
DV
DD
DD4
DRIVE
PIN 12
(VBUF)
L4
L1
L3
L2
L5
L11
L6
L7
L12
C57
L8
PIN 4
(RHS)
PIN 15
(VBIAS)
PIN 14
(LHS)
PIN 5
(VMOD1)
PIN 33
(VMOD2)
PIN 24
(VDIF1)
PIN 44
(VDRV1)
PIN 63
PIN 41
(DVDD)
PIN 27
(VDRV2)
L9
R38
10Ω
C48
100nF
C50
100nF
C62
100nF
C59
10nF
C52
100nF
C53
100nF
C54
100nF
C56
100nF
C58
100nF
100nF
Figure 35. Simplified Connection Diagram
Rev. 0 | Page 22 of 32
AD7763
SUPPLY DECOUPLING
DIFFERENTIAL AMPLIFIER COMPONENTS
Every supply pin must be connected to the appropriate supply
via a ferrite bead and decoupled to the correct ground pin with
a 100 nF, 0603 case size, X7R dielectric capacitor. There are two
exceptions
The correct components for use around the on-chip differential
amplifier are shown in Table 10. Matching the components on
both sides of the differential amplifier is important to minimize
distortion of the signal applied to the amplifier. A tolerance of
0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving stated performance.
• Pin 12 (AVDD4) must have a 10 Ω resistor inserted between
the pin and a 10 nF decoupling capacitor.
• Pin 27 (AVDD2) does not require a separate decoupling
capacitor or a direct connection to the supply; instead,
it is connected to Pin 14 via an 8.2 nH inductor.
EXPOSED PADDLE
The AD7763 64-lead TQFP_EP employs a 6 mm × 6 mm exposed
paddle (see Figure 39). The paddle reduces the thermal
resistance of the package by providing a path of low thermal
resistance to the PCB and, in turn, increases the heat transfer
efficiency from the AD7763 package. Soldering the exposed
paddle to the AGND plane of the PCB is fundamental in
creating the conditions that allow the AD7763 package to
perform to the highest specifications possible.
The ferrite beads that are used to connect each supply pin to the
appropriate power supply should have a characteristic impedance
of 600 Ω to 1 MΩ at frequencies around 100 MHz, a dc impedance
of 1 Ω or less, and a rated current of 200 mA.
ADDITIONAL DECOUPLING
There are two other decoupling pins on the AD7763: Pin 8
(DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled
with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor.
LAYOUT CONSIDERATIONS
While using the correct components is essential to achieve
optimum performance, the correct layout is just as important.
The Design Tools section of the AD7763 product page on
the Analog Devices website contains the Gerber files for the
AD7763 evaluation board. These files should be used as a
reference when designing any system using the AD7763.
REFERENCE VOLTAGE FILTERING
A low noise reference source, such as the ADR431 (2.5 V) or
ADR434 (4.096 V), is suitable for use with the AD7763. The
reference voltage supplied to the AD7763 should be decoupled
and filtered, as shown in Figure 36.
The location and orientation of some of the components
mentioned in previous sections are critical, and particular
attention must be paid to the components that are located close
to the AD7763. Locating these components farther away from
the devices can have a direct impact on the maximum
performance achievable.
The recommended scheme for the reference voltage supply
is a 100 Ω series resistor connected to a 100 ꢀF tantalum
capacitor, followed by a series resistor of 10 Ω, and finally, a
10 nF decoupling capacitor very close to the VREF pin.
U3
R30
100Ω
R17
10Ω
ADR434
+VIN VOUT
2
6
12V
PIN 10
The use of ground planes should also be carefully considered.
To ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground
side of the capacitors should be as close as possible to the ground
pin associated with that supply. A ground plane should not be
relied upon as the sole return path for decoupling capacitors,
because the return current path using ground planes is not
easily predicted.
+
+
GND
4
C15
10μF
C9
100nF
C10
100nF
C11
100μF
C46
10nF
Figure 36. Reference Connection
Rev. 0 | Page 23 of 32
AD7763
PROGRAMMABLE FIR FILTER
As discussed in the Theory of Operation section, the third FIR
filter on the AD7763 can be programmed by the user. The default
coefficients that are loaded on reset are shown in Table 12. This
gives the frequency response shown in Figure 37. The frequencies
shown in Figure 37 scale directly with the output data rate.
To create a user-defined filter, note the following:
• The filter must be even, symmetrical FIR.
• The coefficients are 27 bits in length. All coefficients are
in sign-and-magnitude format. The sign bit coded as
positive = 0 is followed by 26 magnitude bits.
Table 12. Default Filter Coefficients
Decimal
Value
Hex
Value
Decimal
Value
Hex
Value
• The filter length must be between 12 taps and 96 taps in
steps of 12.
#
0
1
2
3
4
5
6
7
8
9
#
+53656736
+25142688
−4497814
−11935847
−1313841
+6976334
+3268059
−3794610
−3747402
+1509849
332BCA0 24 +700847
17FA5A0 25 −70922
444A196 26 −583959
4B62067 27 −175934
4140C31 28 +388667
AB1AF
401150A
408E917
402AF3E
5EE3B
47C70
402CBD2
4049E05
3EA2
3A2EB
158CA
4022F65
401F797
CA52
1DC13
402A
401619C
400F99B
B0B2
1C020
18FD5
CDBD
• Because the filter is symmetrical, the number of coefficients
that must be downloaded is half the filter length. The default
filter coefficients are an example of this, with only 48
coefficients listed for a 96-tap filter.
6A734E
29 +294000
31DDDB 30 −183250
439E6B2 31 −302597
4392E4A 32 +16034
1709D9
344EF8
1397F
• Coefficients are written from the center of impulse response
(adjacent to the point of symmetry) outward.
33 +238315
34 +88266
35 −143205
• The coefficients are scaled so that the in-band gain
of the filter is equal to 134217726, with the coefficients
rounded to the nearest integer. For a low-pass filter, this is the
equivalent of having the coefficients sum arithmetically
(including sign) to +67108863 (0x3FFFFFF) positive value
over the half-impulse-response coefficient set (maximum 48
coefficients). Any deviation from this results in the
introduction of a gain error.
10 +3428088
11 +80255
12 −2672124
13 −1056628
14 +1741563
15 +1502200
16 −835960
17 −1528400
18 +93626
19 +1269502
20 +411245
21 −864038
22 −664622
23 +434489
428C5FC 36 −128919
4101F74
1A92FB
16EBF8
37 +51794
38 +121875
39 +16426
40CC178 40 −90524
4175250 41 −63899
0
–20
PASS-BAND RIPPLE = 0.05dB
–0.1dB FREQUENCY = 251kHz
–3dB FREQUENCY = 256kHz
STOP BAND = 312.5kHz
16DBA
135EFE
6466D
42 +45234
43 +114720
44 +102357
–40
40D2F26 45 +52669
40A242E 46 +15559
–60
3CC7
7AB
6A139
47 +1963
–80
–100
–120
–140
–160
The default filter should be sufficient for most applications.
It is a standard brick wall filter with a symmetrical impulse
response. The default filter has a length of 96 taps and is
nonaliasing, with 120 dB of attenuation at Nyquist. This filter
not only performs signal antialiasing but also suppresses out-of-
band quantization noise produced by the analog-to-digital
conversion process. Any significant relaxation in the stop-band
attenuation or transition bandwidth relative to the default filter
can result in failure to meet the SNR specifications.
0
100
200
300
400
500
600
FREQUENCY (kHz)
Figure 37. Default Filter Frequency Response (625 kHz ODR)
To download a user-defined filter, see the Downloading a User-
Defined Filter section.
Rev. 0 | Page 24 of 32
AD7763
DOWNLOADING A USER-DEFINED FILTER
As discussed in the Programmable FIR Filter section, each of
the filter coefficients is 27 bits in length: one sign bit and 26 magni-
tude bits. To download coefficients for a user-specific FIR filter, a
32-bit word is written to the AD7763 for each coefficient.
To download a user-defined filter:
1. Write to Control Register 1, setting the DL Filt bit. The
correct Filter Length Bits FLEN[3:0] correspond
to the length of the filter about to be downloaded
(see Table 13) and the correct decimation rate.
D31
D30
D29
D28
D27
D26
D[25:0]
ALL
ADR2 ADR1 ADR0
0
Sign
Magnitude
2. Write the 32-bit word (as per format specified). The
first coefficient to be written must be the one adjacent
to the point of filter symmetry.
When a user writes coefficients to one device, the address of that
particular device (as assigned by the ADR[2:0] pins) must be
specified in the bits labeled ADR[2:0].
3. Repeat Step 2 for each coefficient.
In a configuration where more than one device shares the same SDI
line, setting the ALL bit to logic high and leaving Address Bits
ADR[2:0] logic low enables the user to write each coefficient to all
devices simultaneously.
4. Implement the checksum write as per the specified
format.
5. Use the following methods to verify that the filter
coefficients have been downloaded correctly:
To ensure that a filter is downloaded correctly, a checksum must
be generated and downloaded following the download of the final
coefficient. The checksum is a 16-bit word generated by splitting
each 32-bit word into 4 bytes and summing all bytes from all
coefficients up to a maximum of 192 bytes (maximum number
of coefficients = 48 bytes × 4 bytes written for each coefficient).
•
•
Read the status register, checking the DL_OK bit.
Start reading data and observe the status of the
DL_OK bit.
Note that because the user coefficients are stored in RAM, they
RESET
The checksum is written to the device in the form of a 32-bit word
in the following format:
are cleared after a
operation or a loss of power.
Table 13. Filter Length Values
D31
D30
D29
D28
D[27:16]
D[15:0]
FLEN[3:0]
0000
Number of Coefficients
Filter Length
ALL
ADR2
ADR1
ADR0
0
Checksum
Default
6
Default
12
Note that when writing the checksum, the addressing requirements
are as before, and Bit 27 to Bit 16 are all set to 0.
0001
0011
12
24
The same checksum is generated internally in the AD7763 and
compared with the checksum downloaded. The DL_OK bit in
the status register is set if these two checksums agree.
0101
18
36
0111
24
48
1001
30
60
1011
36
72
1101
42
84
1111
48
96
Rev. 0 | Page 25 of 32
AD7763
Table 15 shows the 32-bit word (as per the format shown in the
Downloading a User-Defined Filter section) in hexadecimal for
each of the coefficients that must be written to the AD7763 to
realize this filter. The table is also split into the bytes that are all
summed to produce the checksum. The checksum generated
from these coefficients is 0x0E6B.
EXAMPLE FILTER DOWNLOAD
The following is an example of downloading a short, user-defined
filter with 24 taps. The frequency response is shown in Figure 38.
10
0
Table 15. Filter Hex Values1
–10
–20
–30
–40
–50
–60
–70
–80
32-Bit Word Written to Download Coefficient
Coefficient Byte 1
Byte 2
2B
BF
15
A8
5F
2C
50
10
2F
37
Byte 3
96
18
66
1E
2A
49
E9
DB
DE
44
7D
3B
Byte 4
88
3C
26
6A
96
C2
F6
D8
54
5A
6E
1
03
01
00
04
04
00
00
00
04
04
04
04
2
3
4
5
6
7
8
9
0
100
200
300
400
500
600
FREQUENCY (kHz)
Figure 38. 24-Tap FIR Frequency Response
10
11
12
1B
04
The coefficients for the filter in Table 14 are shown from the center
of symmetry outward; that is, Coefficient 1 is the coefficient at the
center of symmetry. The raw coefficients were generated using a
commercial filter design tool and scaled appropriately so their
sum equals 67108863 (0x3FF FFFF).
5F
1 All values of words listed are with reference to writing to one device only
(ALL = 0) with Address 000 (as assigned to the device using the ADR[2:0]
pins).
Table 14. 24-Tap FIR Coefficients
Table 16 lists in hexadecimal format the sequence of 32-bit
words the user writes to the AD7763 to set up the ADC and
download this filter, assuming selection of an output data rate
of 625 kHz.
Coefficient
Raw
Scaled
1
2
3
4
5
6
7
8
+0.365481974
+0.201339905
+0.009636604
−0.075708848
−0.042856209
+0.019944246
+0.036437914
+0.007592007
−0.021556583
−0.024888355
−0.012379538
−0.001905756
+53188232
+29300796
+1402406
−11017834
−6236822
+2902466
+5302774
+1104856
−3137108
−3621978
−1801582
−277343
Table 16.
Word1
Description
0x0001807A Address of Control Register 1. Control register
data. DL filter, set filter length = 24, set output
data rate = 625 kHz.
0x032B9688 First coefficient.
0x01BF183C Second coefficient.
9
10
11
12
Other coefficients.
…
0x04043B5F Twelfth (final) coefficient.
0x00000E6B Checksum. Wait (0.5 × tICLK × number of unused
coefficients) for AD7763 to fill remaining unused
coefficients with 0s.
0x0001087A Address of Control Register. Control register data.
Set read status and maintain filter length and
decimation settings. Read contents of status
register. Check Bit 7 (DL_OK) to determine that
the filter downloaded correctly.
1 All values of words listed are with reference to writing to one device only
(ALL = 0) with Address 000 (as assigned to the device using the ADR[2:0]
pins).
Rev. 0 | Page 26 of 32
AD7763
REGISTERS
The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration,
the low power option, and the control of the differential amplifier. There are also digital gain, offset, and overrange threshold registers.
Writing to these registers involves writing the register address first, followed by a 16-bit data-word. Register addresses, details of individual bits,
and default values are shown here.
CONTROL REGISTER 1—ADDRESS 0X001
Default Value 0x001A
MSB
LSB
BYP F3
DL Filt RD Ovr RD Gain RD Off RD Stat
0
SYNC FLEN3 FLEN2 FLEN1 FLEN0
1
DEC2 DEC1 DEC0
Table 17.
Bit
Mnemonic Comment
DL Filt1
15
Download Filter. Before downloading a user-defined filter, this bit must be set. The filter length bits must also
be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until
all the coefficients and the checksum have been written.
Read Overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
14
RD Ovr1, 2
13
12
11
10
9
RD Gain1, 2
RD Off 1, 2
RD Stat1, 2
0
Read Gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
Read Offset. If this bit is set, the next read operation outputs the contents of the digital offset register.
Read Status. If this bit is set, the next read operation outputs the contents of the status register.
0 must be written to this bit.
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously
on multiple devices synchronizes all filters.
SYNC1
8 to 5 FLEN[3:0]
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
Bypass Filter 3. If this bit is a 0, Filter 3 (programmable FIR) is bypassed.
1 must be written to this bit.
4
3
BYP F3
1
2 to 0 DEC[2:0]
Decimation Rate. These bits set the decimation rate of Filter 2. Writing a value of 0, 1, or 2 corresponds to
4× decimation. A value of 3 corresponds to 8× decimation; a value of 4 corresponds to 16×; and the
maximum value of 5 corresponds to 32× decimation.
1 Bit 15 to Bit 9 are all self-clearing bits.
2 Only one of these bits can be set in any write operation, because they all determine the contents of the next operation.
CONTROL REGISTER 2—ADDRESS 0X002
Default Value 0x009B
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
PD
LPWR
1
D1PD
Table 18.
Bit Mnemonic Comment
3
2
PD
LPWR
Power Down. Setting this bit powers down the AD7763, reducing the power consumption to 6.35 mW.
Low Power. If this bit is set, the AD7763 operates in a low power mode. The power consumption is reduced for a 3 dB
reduction in noise performance.
1
0
1
1 must be written to this bit.
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
D1PD
Rev. 0 | Page 27 of 32
AD7763
STATUS REGISTER (READ ONLY)
MSB
LSB
BYP F3
PART 1 PART 0 DIE 2 DIE 1 DIE 0
0
LPWR OVR DL_OK FILTER_OK UFILTER
1
DEC2 DEC1 DEC0
Table 19.
Bit
Mnemonic
Comment
Part Number. These bits are constant for the AD7763.
15,14
PART[1:0]
13 to 11 DIE[2:0]
Die Number. These bits reflect the current AD7763 die number for identification purposes within a system.
0 must be written to this bit.
Low Power. If the AD7763 is operating in low power mode, this bit is set to 1.
If the current analog input exceeds the current overrange threshold, this bit is set.
When downloading a user filter to the AD7763, a checksum is generated. This checksum is compared to
the one downloaded following the coefficients. If these checksums agree, this bit is set.
10
9
0
LPWR
OVR
DL_OK
8
7
6
FILTER_OK
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through
the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set.
5
4
UFILTER
BYP F3
1
If a user-defined filter is in use, this bit is set.
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
1 must be written to this bit.
3
2 to 0
DEC[2:0]
Decimation Rate. These bits correspond to the bits set in Control Register 1.
OFFSET REGISTER—ADDRESS 0X003
OVERRANGE REGISTER—ADDRESS 0X005
Non Bit-Mapped, Default Value 0x0000
Non Bit-Mapped, Default Value 0xCCCC
The offset register uses twos complement notation and is scaled so
that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.390625% and
−0.390625%, respectively. Offset correction is applied after any gain
correction. Using the default gain value of 1.25 and assuming a
reference voltage of 4.096 V, the offset correction range is
approximately 25 mV.
The overrange register value is compared with the output of the
first decimation filter to obtain an overload indication with
minimum propagation delay. This is prior to any gain scaling or
offset adjustment. The default value is 0xCCCC, which
corresponds to 80% of VREF (the maximum permitted analog
input voltage). Assuming VREF = 4.096 V, the bit is then set when
the input voltage exceeds approximately 6.55 V p-p differential.
Note that the overrange bit is also set immediately if the analog
input voltage exceeds 100% of VREF for more than 4 consecutive
samples at the modulator rate.
GAIN REGISTER—ADDRESS 0X004
Non Bit-Mapped, Default Value 0xA000
The gain register is scaled so that 0x8000 corresponds to a gain
of 1.0. The default value of this register is 1.25 (0xA000). This
gives a full-scale digital output when the input is at 80% of VREF
This ties in with the maximum analog input range of 80% of
VREF p-p.
.
Rev. 0 | Page 28 of 32
AD7763
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
1.20
MAX
0.75
0.60
0.45
64
49
49
64
1
1
48
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
EXPOSED
PAD
6.00
BSC SQ
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
16
16
33
33
3.5°
17
32
32
17
0.15
0.05
0°
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.50
BSC
LEAD PITCH
0.38
0.32
0.22
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD
Figure 39. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
AD7763BSVZ1
−40°C to +85°C
−40°C to +85°C
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-2
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-2
Evaluation Board
AD7763BSVZ-REEL1
EVAL-AD7763EB
1 Z = Pb-free part.
Rev. 0 | Page 29 of 32
AD7763
NOTES
Rev. 0 | Page 30 of 32
AD7763
NOTES
Rev. 0 | Page 31 of 32
AD7763
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05476-0-10/05(0)
Rev. 0 | Page 32 of 32
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