AD7776 [ADI]
LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs; LC2MOS ，高速1 ，4和8通道10位ADC
| 型号： | AD7776 |
| 厂家： | 
ADI |
| 描述： | LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs |
| 文件： | 总12页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS, High Speed
1-, 4- & 8-Channel 10-Bit ADCs
a
AD7776/AD7777/AD7778*
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
AD7776: Single Channel
AD7777: 4-Channel
AD7778: 8-Channel
Fast 10-Bit ADC: 2.5 s Worst Case
+5 V Only
V
CC
CLKIN
CONTROL
REGISTER
10
Half-Scale Conversion Option
Fast Interface Port
Pow er-Dow n Mode
ADCREG1
DB0–DB9
10-BIT
ADC
A
IN
1
MUX
T/H
10
C
REFIN
V
BIAS
APPLICATIONS
HDD Servos
Instrum entation
REFIN
REFIN
RTN
REF
REFOUT
V
SWING
CONTROL LOGIC
GENERAL D ESCRIP TIO N
AD7776
AGND
T he AD7776, AD7777 and AD7778 are a family of high speed,
multichannel, 10-bit ADCs primarily intended for use in R/W
head positioning servos found in high density hard disk drives.
T hey have unique input signal conditioning features that make
them ideal for use in such single supply applications.
DGND
AGND
CS RD WR
BUSY/INT
V
CC
CLKIN
A
IN
A
IN
A
IN
A
IN
1
2
3
4
CONTROL
REGISTER
By setting a bit in a control register within both the four-channel
version, AD7777, and the eight-channel version, AD7778, the
input channels can either be independently sampled or any two
channels of choice can be simultaneously sampled. For all ver-
MUX
10
T/H
1
ADCREG2
ADCREG1
1
DB0–DB9
10-BIT
ADC
10
C
REFIN
sions the specified input signal range is of the form VBIAS
±
VSWING. H owever, if the RT N pin is biased at, say, 2 V the
V
BIAS
analog input signal range becomes 0 V to +2 V for all input
channels. T his is covered in more detail under the section
Changing the Analog Input Voltage Range. T he voltage VBIAS
is the offset of the ADC’s midpoint code from ground and is
supplied either by an onboard reference available to the user
(REFOUT ) or by an external voltage reference applied to
REFIN. T he full-scale range (FSR) of the ADC is equal to
2 VSWING where VSWING is nominally equal to REFIN/2. Addi-
tionally, when placed in the half-scale conversion mode, the
value of REFIN is converted. T his allows the channel offset(s)
to be measured.
REFIN
T/H
2
MUX
2
V
SWING
REF
REFOUT
RTN
AGND
AD7777
CONTROL LOGIC
REFIN
DGND AGND
V
CC
CLKIN
A 1
IN
A 2
IN
A 3
IN
A 4
IN
A 5
IN
CONTROL
REGISTER
Control register loading and ADC register reading, channel se-
lect and conversion start are under the control of the µP. T he
twos complemented coded ADCs are easily interfaced to a stan-
dard 16-bit MPU bus via their 10-bit data port and standard
microprocessor control lines.
MUX
1
10
T/H
1
ADCREG2
ADCREG1
A 6
IN
A 7
IN
A 8
IN
DB0–DB9
10-BIT
ADC
10
C
REFIN
V
BIAS
T he AD7776/AD7777/AD7778 are fabricated in linear compat-
ible CMOS (LC2MOS), an advanced, mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. T he AD7776 is available in a 24-pin SOIC package; the
AD7777 is available in both 28-pin DIP and 28-pin SOIC pack-
ages; the AD7778 is available in a 44-pin PQFP package.
REFIN
T/H
2
MUX
2
V
SWING
REF
REFOUT
RTN
AGND
AD7778
CONTROL LOGIC
REFIN
*P r otected by U.S. P atent No. 4,990,916.
DGND AGND
RD
BUSY/INT
WR
CS
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = +5 V ؎ 5%; AGND = DGND = O V;
CLKIN = 8 MHz; RTN = O V; CREFIN = 10 nF; all specifications TMIN to TMAX unless otherwise noted.)
AD7776/AD7777/AD7778–SPECIFICATIONS
CC
P aram eter
A Versions1
Units
Conditions/Com m ents
DC ACCURACY
Resolution2
10
Bits
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Error Match
Plus or Minus Full-Scale Error
Plus or Minus Full-Scale Error Match 10
±1
±1
±12
10
±12
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
See T erminology
No Missing Codes; See T erminology
See T erminology
Between Channels, AD7777/AD7778 Only; See T erminology
See T erminology
Between Channels, AD7777/AD7778 Only; See T erminology
ANALOG INPUT S
Input Voltage Range
All Inputs
VBIAS ± VSWING
V min/V max
Input Current
+200
µA max
VIN = VBIAS ± VSWING; Any Channel
REFERENCE INPUT
REFIN
REFIN Input Current
1.9/2.1
+200
V min/V max For Specified Performance
µA max
REFERENCE OUT PUT
REFOUT
DC Output Impedance
Reference Load Change
1.9/2.1
5
±2
V min/V max Nominal REFOUT = 2.0 V
Ω typ
mV max
mV max
For Reference Load Current Change of 0 to ±500 µA
±5
For Reference Load Current Change of 0 to ±1 mA
Reference Load Should Not Change During Conversion
See T erminology
Short Circuit Current3
20
mA max
LOGIC OUT PUT S
DB0–DB9, BUSY/INT
VOL, Output Low Voltage
VOH , Output High Voltage
Floating State Leakage Current
Floating State Capacitance3
ADC Output Coding
0.4
4.0
±10
10
V max
V min
µA max
pF max
ISINK = 1.6 mA
ISOURCE = 200 µA
T wos Complement
LOGIC INPUT S
DB0–DB9, CS, WR, RD, CLKIN
Input Low Voltage, VINL
Input High Voltage, VINH
Input Leakage Current
Input Capacitance3
0.8
2.4
10
V max
V min
µA max
pF max
10
CONVERSION T IMING
Acquisition T ime
4.5 tCLKIN
5.5 tCLKIN + 70
14 tCLKIN
28 tCLKIN
125/500
50
ns min
ns max
ns max
ns max
See T erminology
Single Conversion
Double Conversion
tCLKIN
tCLKIN High
tCLKIN Low
ns min/ns max Period of Input Clock CLKIN
ns min
ns min
Minimum High T ime for CLKIN
Minimum Low T ime for CLKIN
40
POWER REQUIREMENT S
VCC Range
+4.75/+5.25
V min/V max For Specified Performance
ICC, Normal Mode
15
1.5
mA max
mA max
CS = RD = +5 V, CR8 = 0
CR8 = 1. All Linear Circuitry OFF
ICC, Power-Down Mode
Power-Up T ime to Operational
Specifications
500
µs max
From Power-Down Mode
See T erminology
DYNAMIC PERFORMANCE
Signal to Noise and Distortion
S/(N+D) Ratio
T otal Harmonic Distortion (T HD)
Intermodulation Distortion (IMD)
–57
–60
–75
dB min
dB min
dB typ
VIN = 99.88 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz
VIN = 99.88 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz
fa = 103.2 kHz, fb = 96.5 kHz with fSAMPLING = 380.95 kHz. Both
Signals Are Sine Waves at Half-Scale Amplitude
Channel-to-Channel Isolation
NOT ES
–90
dB typ
VIN = 100 kHz Full-Scale Sine Wave with fSAMPLING = 380.95 kHz
1T emperature range as follows: A = –40°C to +85°C.
21 LSB = (2 × VSWING)/1024 = 1.95 mV for VSWING = 1.0 V.
3Guaranteed by design, not production tested.
Specifications subject to change without notice.
–2–
REV. 0
AD7776/AD7777/AD7778
1, 2
TIMING SPECIFICATIONS (V = +5 V ؎ 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX unless otherwise noted.)
CC
P aram eter
Label
Lim it at TMIN to TMAX Units
Test Conditions/Com m ents
INT ERFACE T IMING
CS Falling Edge to WR or RD Falling Edge
WR or RD Rising Edge to CS Rising Edge
WR Pulse Width
t1
t2
t3
t4
t5
0
0
53
60
10
45
55
10
ns min
ns min
ns min
ns m ax
ns m in
ns m ax
ns min
ns min
ns min
ns max
CS or RD Active to Valid D ata3
Bus Relinquish Tim e after RD4
Tim ed fr om Whichever O ccur s Last
Data Valid to WR Rising Edge
Data Valid after WR Rising Edge
WR Rising Edge to BUSY Falling Edge
t6
t7
t8
1.5 tCLKIN
2.5 tCLKIN + 70
CR9 = 0
WR Rising Edge to BUSY Rising Edge or
INT Falling Edge
t9
t10
t11
19.5 tCLKIN + 70
33.5 tCLKIN + 70
60
ns max
ns max
ns max
Single Conversion, CR6 = 0
Double Conversion, CR6 = 1
CR9 = 1
WR or RD Falling Edge to INT Rising Edge
NOT ES
1See Figures 1 to 3.
2T iming specifications in bold print are 100% production tested. All other times are guaranteed by design, not production tested. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3t4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. T he measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. T his means that the time t 5 quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
FIRST
CONVERSION
FINISHED
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
(CR6 = 0)
t3
WR, RD
t1
t9
t2
t8
CS
RD
BUSY
(CR8 = 0)
t10
t11
t9
t5
t4
INT
(CR8 = 1)
DB0–DB9
t10
Figure 1. Read Cycle Tim ing
Figure 3. BUSY/INT Tim ing
I
OL
t1
t2
1.6mA
CS
WR
t3
DB n
+2.1V
t6
t7
C
OUT
100pF
DB0–DB9
I
OH
200µA
Figure 2. Write Cycle Tim ing
Figure 4. Load Circuit for Bus Tim ing Characteristics
REV. 0
–3–
AD7776/AD7777/AD7778
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise noted)
VCC to AGND or DGND . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
AGND, RT N to DGND . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
CS, RD, WR, CLKIN, DB0–DB9,
BUSY/INT to DGND . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
Analog Input Voltage to AGND . . . . . . . –0.3 V, VCC + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
Operating T emperature Range
SOIC Packages, Power Dissipation . . . . . . . . . . . . . . 875 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . 500 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
All Versions . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . +260°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7776/AD7777/AD7778 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO NS
24-P in SO IC
44-P in P Q FP
DB0
DB1
1
2
3
4
5
24
23
C
REFIN
AGND
44 43 42 41 40 39 38 37 36 35 34
DB2
22 RTN
1
33
A
A
8
NC
NC
IN
21 REFIN
DB3
20
A
IN
DGND
DB4
7
6
5
4
3
2
3
32
31
30
29
28
27
26
IN
AD7776
19 AGND
6
DB2
A
IN
IN
IN
TOP VIEW
(Not to Scale)
18
17
DB5
7
REFOUT
A
A
A
DB3
DGND
DB4
DB5
DB6
DB7
NC
4
5
V
DB6
8
9
CC
AD7778
TOP VIEW
(Not to Scale)
16 CLKIN
15 WR
14 CS
DB7
6
IN
IN
10
11
12
DB8
7
A
2
1
(MSB) DB9
BUSY/INT
8
A
IN
13 RD
9
25 AGND
10
11
24
23
REFOUT
28-P in D IP & SO IC
V
NC
CC
DB0
DB1
NC
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
C
REFIN
12
13 14 15 16 17 18 19 20 21 22
AGND
RTN
DB2
DB3
DGND
DB4
DB5
DB6
REFIN
NC = NO CONNECT
A
4
3
IN
IN
A
O RD ERING GUID E
A 2
IN
AD7777
TOP VIEW
A
IN
1
Tem perature
Range
No. of
Channels
P ackage
O ption1
(Not to Scale)
AGND
Model
DB7 10
DB8 11
19
18
17
REFOUT
AD7776AR2
AD7777AN
AD7777AR2
AD7778AS2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1
4
4
8
R-24
N-28
R-28
S-44
V
CC
CLKIN
(MSB) DB9 12
BUSY/INT 13
RD 14
16 WR
15 CS
NOT ES
NC = NO CONNECT
1R = SOIC, N = Plastic DIP, S = PQFP.
2Analog Devices reserves the right to ship devices branded with a J in place of
the A, e.g., AD7776JR instead of AD7776AR. T emperature range remains
–40°C to +85°C.
REV. 0
–4–
AD7776/AD7777/AD7778
P IN FUNCTIO N D ESCRIP TIO N
Mnem onic
D escription
VCC
+5 V Power Supply.
Analog Ground.
AGND
DGND
DB0–DB9
Digital Ground. Ground reference for digital circuitry.
Input/Output Data Bus. T his is a bidirectional data port from which ADC output data may be read and to which
control register data may be written.
BUSY/INT
Busy/Interrupt Output. Active low logic output indicating A/D converter status. T his logic output has two modes
of operation depending on whether location CR9 of the control register has been set low or high:
If CR9 is set low, then the BUSY/INT output will behave as a BUSY signal. T he BUSY signal will go low and stay
low for the duration of a single conversion, or if simultaneous sampling has been selected, BUSY will stay low for
the duration of both conversions.
If CR9 is set high, then the BUSY/INT output behaves as an INT ERRUPT signal. T he INT signal will go low
and remain low after either a single conversion is completed or after a double conversion is completed if simulta-
neous sampling has been selected. With CR9 high, the falling edge of WR or RD resets the INT line high.
CS
Chip Select Input. T he device is selected when this input is low.
WR
Write Input (Active Low). It is used in conjunction with CS to write data to the control register. Data is latched to the
registers on the rising edge of WR. Following the rising edge of WR, the analog input is acquired and a conversion is
started.
RD
Read Input (Active Low). It is used in conjunction with CS to enable the data outputs from the ADC registers.
AIN1–8
Analog Inputs 1–8. T he analog input range is VBIAS ± VSWING where VBIAS and VSWING are defined by the reference
voltage applied to REFIN. Input resistance between any of the analog input pins and AGND is 10 kΩ or greater.
REFIN
Voltage Reference Input. T he AD7776/AD7777/AD7778 are specified over a voltage reference range of 1.9 V to 2.1 V
with a nominal value of 2.0 V. T his REFIN voltage provides the VBIAS and VSWING levels for the input channel(s).
VBIAS is equal to REFIN and VSWING is nominally equal to REFIN/2. Input resistance between this REFIN pin and
AGND is 10 kΩ or greater.
REFOUT
CREFIN
RT N
Voltage Reference Output. T he internal voltage reference, which is nominally 2.0 V and can be used to provide the
bias voltage (VBIAS) for the input channel(s), is provided at this pin.
Reference Decoupling Capacitor. A 10 nF capacitor must be connected from this pin to AGND to ensure correct
operation of the high speed ADC.
Signal Return Path for the input channel(s). Normally RT N is connected to AGND at the package.
CIRCUIT D ESCRIP TIO N
AD C Tr ansfer Function
1FF
1FE
For all versions, an input signal of the form VBIAS ± VSWING is
expected. T his VBIAS signal level operates as a pseudo ground to
which all input signals must be referred. T he VBIAS level is de-
termined by the voltage applied to the REFIN pin. T his can be
driven by an external voltage source or, alternatively, the on-
board 2 V reference, available at REFOUT , can be used. T he
magnitude of the input signal swing is equal to VBIAS/2 (or
REFIN/2) and is set internally. With a REFIN of 2 V, the analog
input signal level varies from 1 V up to 3 V i.e., 2 ± 1 V. Fig-
ure 5 shows the transfer function of the ADC and its relation-
ship to VBIAS and VSWING. T he half-scale twos complement code
of the ADC, 000 Hex (00 0000 0000 Binary), occurs at an input
voltage equal to VBIAS. T he input full-scale range of the ADC is
equal to 2 VSWING, so that the Plus Full-Scale transition (1FE to
1FF) occurs at a voltage equal to VBIAS + VSWING – 1.5 LSBs
and the minus full-scale code transition (200 to 201) occurs at
a voltage VBIAS – VSWING + 0.5 LSBs.
ADC
OUTPUT
CODE
(HEX)
000
202
201
200
VBIAS
VBIAS–VSWING
VBIAS+VSWING
ANALOG INPUT, VIN
Figure 5. ADC Transfer Function
REV. 0
–5–
AD7776/AD7777/AD7778
CO NTRO L REGISTER
CR6: Determines whether operation is on a single channel or
simultaneous sampling on two channels. Location CR6 is a
“don’t care” for the AD7776.
T he control register is 10-bits wide and can only be written to.
On power-on, all locations in the control register are automati-
cally loaded with 0s. For the single channel AD7776, locations
CR0 to CR6 of the control register are “don’t cares.” For the
quad channel AD7777, locations CR2 and CR5 are “don’t
cares.” Individual bit functions are described below.
CR6 Function
0
Single channel operation. Channel select
address is contained in locations CR0–CR2.
T wo channels simultaneously sampled
and sequentially converted. Channel
select addresses contained in locations
CR0–CR2 and CR3–CR5.
1
CR0–CR2: Channel Address Locations. Determines which channel
will be selected and converted for single channel operation. For si-
multaneous sampling operation CR0–CR2 holds the address of one
of the two channels to be sampled.
CR7: Determines whether the device is in the normal operating
mode or in the half-scale test mode.
AD 7776
CR2 CR1 CR0 Function
CR7 Function
X*
X
X
Select AIN
1
0
1
Normal Operating Mode
Half-Scale T est Mode
*X = Don’t Care
In the half-scale test mode REFIN is internally connected as an
analog input(s). In this mode locations CR0–CR2 and CR3–
CR5 are all “don’t cares” since it is REFIN which will be con-
verted. For the AD7777 and AD7778, the contents of location
CR6 still determine whether a single or a double conversion is
carried out on the REFIN level.
AD 7777
CR2 CR1 CR0 Function
X*
X
X
0
0
1
1
0
1
0
1
Select AIN1
Select AIN2
Select AIN3
Select AIN4
X
CR8: Determines whether the device is in the normal operating
*X = Don’t Care
mode or in the powerdown mode.
AD 7778
CR8 Function
CR2 CR1 CR0 Function
0
1
Normal Operating Mode
Powerdown Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Select AIN1
Select AIN2
Select AIN3
Select AIN4
Select AIN5
Select AIN6
Select AIN7
Select AIN8
In the powerdown mode all linear circuitry is turned off and the
REFOUT output is weakly (5 kΩ) pulled to AGND. T he input
impedance of the analog inputs and of the REFIN input re-
mains the same in either normal mode or powerdown mode. See
under Circuit Description—Powerdown Mode.
CR9: Determines whether BUSY/INT output flag goes low and
remains low during conversion(s) or else goes low and remains
low after the conversion(s) is (are) complete.
CR3–CR5: Channel Address Locations. Only applicable for simul-
taneous sampling with the AD7777 or AD7778 when CR3–CR5
holds the address of the second channel to be sampled.
CR9 BUSY/INT Functionality
0
Output goes low and remains low during
conversion(s).
AD 7777
1
Output goes low and remains low after conversion(s)
is (are) complete.
CR5 CR4 CR3 Function
AD C Conver sion Star t Tim ing
X*
X
X
0
0
1
1
0
1
0
1
Select AIN1
Select AIN2
Select AIN3
Select AIN4
Figure 6 shows the operating waveforms for the start of a con-
version cycle. On the rising edge of WR, the conversion cycle
starts with the acquisition and tracking of the selected ADC
channel, AIN1–8. T he analog input voltage is held 40 ns (typi-
cally) after the first rising edge of CLKIN following four com-
plete CLKIN cycles. If tD in Figure 6 is greater than 12 ns, the
falling edge of CLKIN as shown will be seen as the first falling
clock edge. If tD is less than 12 ns, the first falling clock edge to
be recognized will not occur until one cycle later.
X
*X = Don’t Care
AD 7778
CR5 CR4 CR3 Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Select AIN1
Select AIN2
Select AIN3
Select AIN4
Select AIN5
Select AIN6
Select AIN7
Select AIN8
Following the “hold” on the analog input(s), two complete
CLKIN cycles are allowed for settling purposes before the MSB
decision is made. The actual decision point occurs approximately
40 ns after the rising edge of CLKIN as shown in Figure 6. A
further two CLKIN cycles are allowed for the second MSB
decision. T he succeeding bit decisions are made approximately
40 ns after each rising edge of CLKIN until the conversion is
complete. At the end of conversion, if a single conversion
has been requested (CR6 = 0), the BUSY/INT line changes
REV. 0
–6–
AD7776/AD7777/AD7778
state (as programmed by CR9), and the SAR contents are trans-
ferred to the first register ADCREG1. T he SAR is then reset in
readiness for a new conversion. If simultaneous sampling has
been requested (CR6 = 1), no change occurs in the status of the
BUSY/INT output and the ADC automatically starts the second
conversion. At the end of this conversion the BUSY/INT line
changes state (as programmed by CR9) and the SAR contents
are transferred to the second register, ADCREG2.
Control inputs CS, WR and RD retain their purpose while the
AD7776/ AD7777/AD7778 is in powerdown. If no conversions
are in progress when the AD7776/AD7777/AD7778 is placed
into the powerdown modes, the contents of the ADC registers,
ADCREG1 and ADCREG2, are retained during powerdown
and can be read as normal. On returning to normal operating
mode a new conversion (or conversions, dependent on CR6) is
automatically started. On completion, the invalid conversion
results are loaded into the ADC registers losing the previous
valid results.
WR
tD*
In order to achieve the lowest possible power consumption in
the powerdown mode special attention must be paid to the state
of the digital and analog inputs and outputs:
CLKIN
40ns
TYP
40ns
TYP
• Because each analog input channel sees a resistive divider to
AGND, the input resistance of which does not change be-
tween normal and powerdown modes, driving the analog input
signals to 0 V or as close as possible to 0 V will minimize the
power dissipated in the input signal conditioning circuitry.
VIN
CHANNEL ACQUISITION
'HOLD'
TIMING SHOWN FOR tD GREATER THAN 12ns
DB9 (MSB)
*
• Similarly, the REFIN input sees a resistive divider to AGND,
the input resistance of which does not change between normal
and powerdown modes. If an external reference is being used,
then driving this reference input to 0 V or as close as possible
to 0 V will minimize the power dissipated in the input signal
conditioning circuitry.
Figure 6. ADC Conversion Start Tim ing
Tr ack-and-H old
T he track-and-hold (T /H) amplifiers on the analog input(s) of
the AD7776/AD7777/AD7778 allow the ADC to accurately
convert an input sine wave of 2 V peak-peak amplitude up to a
frequency of 189 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 378 kHz. T his
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the track-
and-hold is much greater than 189 kHz, the input signal should
be band limited to avoid folding unwanted signals into the band
of interest.
• Since the REFOUT pin is pulled to AGND via, typically, a
5 kΩ resistor, any voltage above 0 V that this output may be
pulled to by external circuitry will dissipate unnecessary
power.
• Digital inputs CS, WR & RD should all be held at VCC or as
close as possible. CLKIN should be held as close as possible
to either 0 V or VCC.
P ower down
T he AD7776/AD7777/AD7778 can be placed in a powerdown
mode simply by writing a logic high to location CR8 of the con-
trol register. T he following changes are effected immediately on
writing a “1” to location CR8:
• Since the BUSY/INT output is actively driven to a logic high,
any loading on this pin to 0 V will dissipate power.
T he AD7776/AD7777/AD7778 comes out of the powerdown
mode when a Logic “0” is written to location CR8 of the con-
trol register. Note that the contents of the other locations in the
control register are retained when the device is placed in
powerdown and are valid when power is restored. H owever,
coming out of powerdown provides an opportunity to reload
the complete contents of the control register without any extra
instructions.
• Any conversion in progress is terminated.
• If a conversion is in progress, the leading edge of WR immedi-
ately drives the BUSY/INT output high.
• All the linear circuitry is turned off.
• T he REFOUT output stops being driven and is weakly (5 kΩ)
pulled to analog ground.
REV. 0
–7–
AD7776/AD7777/AD7778
Figure 10 shows the interface with the 80C196KB @ 12 MHz
and the 80C196KC @ 16 MHz. One wait state is required with
the 16 MHz machine. T he 80C196 is configured to operate
with a 16-bit multiplexed address/data bus.
Micr opr ocessor Inter facing Cir cuits
T he AD7776/AD7777/AD7778 family of ADCs is intended to
interface to DSP machines such as the ADSP-2101, ADSP-2105,
the T MS320 family and microcontrollers such as the 80C196
family.
T able I gives a truth table for the AD7776/AD7777/AD7778
and summarizes their microprocessor interfacing features. Note
that a read instruction to any of the devices while a conversation
is in progress will immediately stop that conversion and return
unreliable data over the data bus.
Figure 7 shows the AD7776/AD7777/AD7778 interfaced to the
TMS320C10 @ 20.5 MHz and the TMS320C14 @ 25 MHz.
Figure 8 shows the interface with the TMS320C25 @ 40 MHz.
Note that one wait state is required with this interface. The
ADSP-2101-50 and the ADSP-2105-40 interface is shown in
Figure 9. One wait state is required with either of these machines.
A13–A0
ADDRESS BUS
A11–A0
ADDRESS BUS
ADDR
DECODE
ADDR
DECODE
TMS320C10-20.5
TMS320C14-25
CS
CS
EN
DMS
AD7776/7/8*
AD7776/7/8*
WR
WR
WE
WR
RD
RD
(C10) DEN
(C14) REN
RD
DB9–DB0
ADSP-2101-50
ADSP-2105-40
DB9–DB0
D23–D6
DATA BUS
D15–D0
DATA BUS
*
ADDITIONAL PINS OMITTED FOR CLARITY
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD7776/AD7777/AD7778 to ADSP-2101 and
ADSP-2105 Interface
Figure 7. AD7776/AD7777/AD7778 to TMS320C10 and
TMS320C14 Interface
AD15–AD6
ADDRESS BUS
(PORT 4)
A15–A0
IS
ADDRESS BUS
'373
LATCH
ADDR
DECODE
ALE
READY
MSC
AD7776/7/8*
CS
80C196KB-12
80C196KC-16
ADDR
AD7776/7/8*
CS
DECODER
STRB
R/W
WR
WR
WR
RD
RD
RD
TMS320C25-40
DB9–DB0
DATA BUS (10)
DB9–DB0
AD7–AD0
(PORT 3)
D15–D0
DATA BUS
*
ADDITIONAL PINS OMITTED FOR CLARITY
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. AD7776/AD7777/AD7778 to 80C196 Interface
Figure 8. AD7776/AD7777/AD7778 to TMS320C25 Interface
REV. 0
–8–
AD7776/AD7777/AD7778
Table I. AD 7776/AD 7777/AD 7778 Truth Table for Microprocessor Interfacing
CS
RD
WR
D B0–D B9 Function/Com m ents
1
0
0
X*
1
X*
j
1
High Z
Data Port High Impedance
CR Data
Load control register (CR) data to control register and start a conversion.
k
ADC Data ADC data placed on data bus. Depending upon location CR6 of the control register, one or two
Read instructions will be required.
If CR6 is low, i.e., single channel conversion selected, a read instruction returns the contents of
ADCREG1. Succeeding read instructions continue to return the contents of ADCREG1.
If CR6 is high, i.e., simultaneous sampling (double conversion) selected, the first read instruction
returns the contents of ADCREG1 while the second read instruction returns the contents of
ADCREG2. A third read instruction returns ADCREG1 again, the fourth ADCREG2, etc.
*X = Don’t Care
D ESIGN INFO RMATIO N
TERMINO LO GY
Layout H ints
Relative Accur acy
Ensure that the layout for the printed circuit board has the digi-
tal and analog grounds separated as much as possible. T ake care
not to run any digital track alongside an analog signal track.
Guard (screen) the analog input(s) with RT N.
For the AD7776, AD7777 and AD7778, relative accuracy or
endpoint nonlinearity is the maximum deviation, in LSBs, of the
ADC’s actual code transition points from a straight line drawn
between the endpoints of the ADC transfer function.
Establish a single point analog ground separate from the logic
system ground and as close as possible to the AD7776/AD7777/
AD7778. Both the RT N and AGND pins on the AD7776/
AD7777/AD7778 and all other signal grounds should be con-
nected to this single point analog ground. In turn, this star
ground should be connected to the digital ground at one point
only—preferably at the low impedance power supply itself.
D iffer ential Nonlinear ity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified maximum differential nonlinearity of ±1 LSB
ensures no missed codes.
Bias O ffset Er r or
For an ideal 10-bit ADC, the output code for an input voltage
equal to VBIAS should be midscale. T he bias offset error is the
difference between the actual midpoint voltage for midscale
code and VBIAS, expressed in LSBs.
Low impedance analog and digital power supply common re-
turns are important for correct operation of the devices, so make
the foil width for these tracks as wide as possible.
In order to ensure a low impedance +5 V power supply at the
actual VCC pin, it will be necessary to employ bypass capacitors
from the pin itself to DGND. A 4.7 µF tantalum capacitor in
parallel with a 0.1 µF ceramic capacitor is sufficient.
Bias O ffset Er r or Match
T his is a measure of how closely the bias offset errors of all
channels track each other. T he bias offset error match of any
channel must be no further away than 10 LSBs from the bias
offset error of any other channel, regardless of whether the
channels are independently sampled or simultaneously sampled.
AD C Cor r uption
Executing a read instruction to the AD7776/AD7777/AD7778
while a conversion is in progress will immediately halt the con-
version and return invalid data over the data bus. T he BUSY/
INT output pin should be monitored closely and all read in-
structions to the AD7776/AD7777/AD7778 prevented while
this output shows that a conversion is in progress.
P lus and Minus Full-Scale Er r or
T he input channels of the ADC can be considered to have
bipolar (positive and negative) input ranges, but which are re-
ferred to VBIAS (or REFIN) instead of AGND. Positive full-scale
error for the ADC is the difference between the actual input
voltage required to produce the plus full-scale code transition
and the ideal input voltage (VBIAS + VSWING –1.5 LSB), ex-
pressed in LSBs. Minus full-scale error is similarly specified for
the minus full-scale code transition, relative to the ideal input
voltage for this transition (VBIAS – VSWING + 0.5 LSB). Note that
the full-scale errors for the ADC input channels are measured
after their respective bias offset errors have been adjusted out.
Executing a write instruction to the AD7776/AD7777/AD7778
while a conversion is in progress immediately halts the conver-
sion, the falling edge of WR driving the BUSY/INT output high.
T he analog input(s) is sampled as normal and a new conversion
sequence (dependent upon CR6) is started.
AD C Conver sion Tim e
Although each conversion takes only 14 CLKIN cycles, it can
take between 4.5 to 5.5 CLKIN cycles to acquire the analog
input(s) after the WR input goes high and before any conver-
sions start.
P lus and Minus Full-Scale Er r or Match
T his is a measure of how closely the full-scale errors of all chan-
nels track each other. T he full-scale error match of any channel
must be no further away than 10 LSBs from the respective full-
scale error of any other channel, regardless of whether the chan-
nels are independently sampled or simultaneously sampled.
REV. 0
–9–
AD7776/AD7777/AD7778
Shor t Cir cuit Cur r ent
Figure 11 shows a 2048 point FFT plot for a single channel of
the AD7778 with an input signal of 99.88 kHz. T he SNR is
58.71 dB. It can be seen that most of the harmonics are buried
in the noise floor. It should be noted that the harmonics are
taken into account when calculating the S/(N+D).
T his is defined as the maximum current which will flow either
into or out of the REFOUT pin if this pin is shorted to any
potential between 0 V and VCC. T his condition can be allowed
for up to 10 seconds provided that the power dissipation of the
package is not exceeded.
0
Signal-to-Noise and D istor tion Ratio, S/(N+D )
Signal-to-noise and distortion ratio, S/(N+D), is the ratio of the
rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc. T he value for S/(N+D) is given
in decibels.
INPUT FREQUENCY =
99.88 kHz
SAMPLE FREQUENCY =
380.95 kHz
SNR = 58.7 dB
–20
T
A = +25°C
–40
–60
Total H ar m onic D istor tion, TH D
T otal harmonic distortion is the ratio of the rms sum of the first
five harmonic components to the rms value of a full-scale input
signal and is expressed in decibels. For the AD7776/AD7777/
AD7778, total harmonic distortion (T HD) is defined as:
–80
–90
2
2
2
2
(V2 + V3 + V4 + V52 + V6 )1/2
0
99.88
20 log =
FREQUENCY – kHz
V1
Figure 11. ADC FFT Plot
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the individual
harmonics.
T he relationship between S/(N+D) and resolution (n) is ex-
pressed by the following equation:
Inter m odulation D istor tion, IMD
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies of
mfa + nfb, where m, n = 0, 1, 2, 3. Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb) and the third
order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa –
2 fb).
S/(N+D) = (6.02n + 1.76) dB
T his is for an ideal part with no differential or integral linearity
errors. T hese errors will cause a degradation in S/(N+D). By
working backwards from the above equation, it is possible to get
a measure of ADC performance expressed in effective number
of bits (n).
Channel-to-Channel Isolation
S/(N+D) (dB) – 1.76
n(effective) =
Channel-to-channel isolation is a measure of the level of cross-
talk between channels. It is measured by applying a full-scale
100 kHz sine wave signal to any one of the input channels and
monitoring the remaining channels. T he figure given is the
worst case across all channels.
6.02
T he effective number of bits plotted vs. frequency for a single
channel of the AD7778 is shown in Figure 12. T he effective
number of bits is typically 9.5.
10
9.5
9
D IGITAL SIGNAL P RO CESSING AP P LICATIO NS
In digital signal processing (DSP) application areas like voice
recognition, echo cancellation and adaptive filtering, the dy-
namic characteristics S/(N+D), T HD & IMD of the ADC are
critical. T he AD7776/AD7777/AD7778 are specified dynami-
cally as well as with standard dc specifications. Because the
track/hold amplifier has a wide bandwidth, an antialiasing filter
should be placed on the analog inputs to avoid aliasing of high
frequency noise back into the bands of interest.
SAMPLE FREQUENCY = 378.4 kHz
8.5
T
= +24°C
A
T he dynamic performance of the ADC is evaluated by applying
a sine wave signal of very low distortion to a single analog input
which is sampled at a 380.95 kHz sampling rate. A fast Fourier
transform (FFT ) plot or histogram plot is then generated from
which the signal to noise and distortion, harmonic distortion
and dynamic differential nonlinearity data can be obtained.
Similarly, for intermodulation distortion, an input signal con-
sisting of two pure sine waves at different frequencies is applied
to the AD7776/AD7777/AD7778.
8
7.5
0
189.2
INPUT FREQUENCY – kHz
Figure 12. Effective Num ber of Bits vs. Frequency
REV. 0
–10–
AD7776/AD7777/AD7778
Changing the Analog Input Voltage Range
RT N is tied to REFOUT then the analog input range becomes
0 V to 2 V. T he fixed 2 V analog input voltage span of the ADC
can range from 1 V to 3 V (RT N = 0 V) to 0 V to 2 V (RT N =
2 V), i.e., with proper biasing, an input signal range from 0.3 V
to 2.3 V can be covered. Both the relative accuracy and differen-
tial nonlinearity performance remains essentially unchanged in
this mode while the SNR and T HD performance are typically
2 dB to 3 dB worse than standard.
By biasing the RT N pin above AGND it is possible to change
the analog input voltage range from its VBIAS ± VSWING format to
a more traditional 0 V to VREF range. T he new input range can
be described as
VOFFSET to (VOFFSET + REFIN)
where 0 V ≤ VOFFSET
≤ 1 V. T o produce this range the RT N pin
must be biased to (REFIN – 2 VOFFSET). For instance if
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
R-24
24-Lead Wide-Body SO IC
24
13
0.299 (7.6)
0.291 (7.4)
0.419 (10.65)
0.394 (10.00)
PIN 1
1
12
0.614 (15.6)
0.598 (15.2)
0.104 (2.65)
0.093 (2.35)
0.013 (0.32)
0.012 (0.3)
0.004 (0.1)
0.050 (1.27)
BSC
0.005 (1.27)
0.015 (0.40)
0.019 (0.49)
0.014 (0.35)
0.009 (0.23)
R-28
28-Lead Wide-Body SO IC
28
15
0.299 (7.60)
0.291 (7.39)
0.414 (10.52)
0.398 (10.10)
PIN 1
1
14
0.03 (0.76)
0.02 (0.51)
0.708 (18.02)
0.696 (17.67)
0.096 (2.44)
0.089 (2.26)
0.01 (0.254)
0.006 (0.15)
0.013 (0.32)
0.009 (0.23)
0.050 (1.27)
BSC
0.042 (1.067)
0.018 (0.457)
0.019 (0.49)
0.014 (0.35)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OF SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
REV. 0
–11–
AD7776/AD7777/AD7778
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
N-28
28-Lead P lastic D IP
28
15
0.550 (13.97)
0.530 (13.462)
PIN 1
14
1
0.606 (15.39)
0.594 (15.09)
1.450 (36.83)
1.440 (36.576)
0.200
(5.080)
MAX
0.160 (4.06)
0.140 (3.56)
0.175 (4.45)
0.120 (3.05)
0.012 (0.305)
0.008 (0.203)
15
°
0
°
0.020 (0.508)
0.015 (0.381)
0.105 (2.67)
0.095 (2.41)
0.065 (1.65)
0.045 (1.14)
SEATING
PLANE
S-44
44-P in P Q FP
0.547 ± 0.01 SQ
(13.9 ± 0.25)
0.096 (2.45) MAX
0.394 ± 0.004 SQ
(10 ± 0.1)
0.031 ± 0.006
(0.8 ± 0.15)
4°± 4°
23
33
34
22
0.394 ± 0.004
TOP VIEW
(10 ± 0.1)
PIN 1
44
12
1
11
0.036 ± 0.004
(0.92 ± 0.1)
0.036 ± 0.004
(0.92 ± 0.1)
0.079 + 0.004/–0.002
(2 + 0.1/–0.05)
0.014 ± 0.002
(0.35 ± 0.05)
0.031 ± 0.002
(0.8 ± 0.05)
REV. 0
–12–
相关型号：
AD7776AR-REEL
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24, MS-013AD, SOIC-24
ROCHESTER
AD7776JR
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, SOIC-24, Analog to Digital Converter
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