AD7785_技术文档

3-Channel, Low Noise, Low Power, 20-Bit ∑-Δ

ADC with On-Chip In-Amp and Reference

AD7785

Industrial process control

FEATURES

Instrumentation

Portable instrumentation

Blood analysis

Smart transmitters

Liquid/gas chromatography

6-digit DVM

Up to 20 bits effective resolution

RMS noise

40 nV @ 4.17 Hz

85 nV @ 16.7 Hz

Current: 400 μA typical

Power-down: 1 μA maximum

Low noise programmable gain instrumentation amp

Band gap reference with 4 ppm/°C drift typical

Update rate: 4.17 Hz to 470 Hz

3 differential inputs

GENERAL DESCRIPTION

The AD7785 is a low power, low noise, complete analog front

end for high precision measurement applications. The AD7785

contains a low noise 20-bit ∑-Δ ADC with three differential

analog inputs. The on-chip, low noise instrumentation amplifier

means that signals of small amplitude can be interfaced directly

to the ADC. With a gain setting of 64, the rms noise is 40 nV

when the update rate equals 4.17 Hz.

Internal clock oscillator

Simultaneous 50 Hz/60 Hz rejection

Programmable current sources

On-chip bias voltage generator

Burnout currents

The device contains a precision low noise, low drift internal

band gap reference and can accept an external differential

reference. Other on-chip features include programmable

excitation current sources, burnout currents, and a bias voltage

generator. The bias voltage generator sets the common-mode

voltage of a channel to AV_DD/2.

Power supply: 2.7 V to 5.25 V

–40°C to +105°C temperature range

Independent interface power supply

16-lead TSSOP package

Interface

3-wire serial

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

The AD7785 can be operated with either the internal clock

or an external clock. The output data rate from the device is

software-programmable and can be varied from 4.17 Hz to 470

Hz. The device operates with a power supply from 2.7 V to

5.25 V. It consumes a current of 400 μA typical and is housed in

a 16-lead TSSOP package.

APPLICATIONS

Thermocouple measurements

RTD measurements

Thermistor measurements

Gas analysis

FUNCTIONAL BLOCK DIAGRAM

DD

GND

AV

REFIN(+)/AIN3(+) REFIN(–)/AIN3(–)

V

BIAS

BAND GAP

REFERENCE

GND

AV

DD

AIN1(+)

AIN1(–)

AIN2(+)

AIN2(–)

DOUT/RDY

DIN

SERIAL

INTERFACE

AND

CONTROL

LOGIC

MUX

Σ-Δ

ADC

BUF

IN-AMP

SCLK

CS

AV

DD

GND

DV

DD

IOUT1

IOUT2

INTERNAL

CLOCK

AD7785

CLK

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7785

TABLE OF CONTENTS

Features .............................................................................................. 1

Offset Register ............................................................................ 19

Full-Scale Register...................................................................... 19

ADC Circuit Information.............................................................. 20

Overview ..................................................................................... 20

Digital Interface.......................................................................... 21

Circuit Description......................................................................... 25

Analog Input Channel ............................................................... 25

Instrumentation Amplifier........................................................ 25

Bipolar/Unipolar Configuration .............................................. 25

Data Output Coding .................................................................. 25

Burnout Currents ....................................................................... 26

Excitation Currents.................................................................... 26

Bias Voltage Generator .............................................................. 26

Reference ..................................................................................... 26

Reset............................................................................................. 26

AV_DDMonitor ............................................................................. 27

Calibration................................................................................... 27

Grounding and Layout .............................................................. 27

Applications Information.............................................................. 29

Temperature Measurement using a Thermocouple............... 29

Temperature Measurement using an RTD.............................. 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Output Noise and Resolution Specifications .............................. 11

External Reference...................................................................... 11

Internal Reference ...................................................................... 12

Typical Performance Characteristics ........................................... 13

On-Chip Registers.......................................................................... 14

Communications Register......................................................... 14

Status Register............................................................................. 15

Mode Register ............................................................................. 15

Configuration Register .............................................................. 17

Data Register............................................................................... 18

ID Register................................................................................... 18

IO Register................................................................................... 18

REVISION HISTORY

4/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7785

SPECIFICATIONS

AV_DD= 2.7 V to 5.25 V; DV_DD= 2.7 V to 5.25 V; GND = 0 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

AD7785B¹

Unit

Test Conditions/Comments

ADC CHANNEL

Output Update Rate

No Missing Codes²

Resolution

Output Noise and Update Rates

Integral Nonlinearity

Offset Error³

4.17 to 470

20

Hz nom

Bits min

See Output Noise and Resolution Specifications

1ꢀ

1

ppm of FSR max

μV typ

Offset Error Drift vs. Temperature⁴

Full-Scale Error^{3, ꢀ}

10

1

3

100

nV/°C typ

μV typ

ppm/°C typ

dB min

Gain Drift vs. Temperature⁴

Gain = 1 to 16, external reference

Gain = 32 to 128, external reference

AIN = 1 V/gain, gain ≥ 4, external reference

Power Supply Rejection

ANALOG INPUTS

Differential Input Voltage Ranges

V_REF/Gain

V nom

V_REF= REFIN(+) − REFIN(−) or internal reference,

gain = 1 to 128

Absolute AIN Voltage Limits²

Unbuffered Mode

GND – 30 mV

AV_DD+ 30 mV

GND + 100 mV

AV_DD– 100 mV

GND + 300 mV

AV_DD– 1.1

V min

V max

V min

V max

V min

V max

V min

Gain = 1 or 2

Buffered Mode

In-Amp Active

Gain = 1 or 2

Gain = 4 to 128

Common-Mode Voltage, V_CM

Analog Input Current

0.ꢀ

V_CM= (AIN(+) + AIN(−))/2, gain = 4 to 128

Buffered Mode or In-Amp Active

Average Input Current²

1

2ꢀ0

2

nA max

pA max

pA/°C typ

Gain = 1 or 2, update rate < 100 Hz

Gain = 4 to 128, update rate < 100 Hz

Average Input Current Drift

Unbuffered Mode

Average Input Current

Average Input Current Drift

Normal Mode Rejection²

Internal Clock

Gain = 1 or 2

Input current varies with input voltage

400

ꢀ0

nA/V typ

pA/V/°C typ

@ ꢀ0 Hz, 60 Hz

@ ꢀ0 Hz

@ 60 Hz

6ꢀ

80

90

dB min

80 dB typ, ꢀ0 1 Hz, 60 1 Hz, FS[3:0] = 1010⁶

90 dB typ, ꢀ0 1 Hz, FS[3:0] = 1001⁶

100 dB typ, 60 1 Hz, FS[3:0] = 1000⁶

External Clock

@ ꢀ0 Hz, 60 Hz

@ ꢀ0 Hz

@ 60 Hz

80

94

90

dB min

90 dB typ, ꢀ0 1 Hz, 60 1 Hz, FS[3:0] = 1010⁶

100 dB typ, ꢀ0 1 Hz, FS[3:0] = 1001⁶

100 dB typ, 60 1 Hz, FS[3:0] = 1000⁶

Common-Mode Rejection

@ DC

@ ꢀ0 Hz, 60 Hz²

100

dB min

AIN = 1 V/gain, gain ≥ 4

ꢀ0 1 Hz, 60 1 Hz, FS[3:0] = 1010⁶

ꢀ0 1 Hz (FS[3:0] = 1001)⁶, 60 1 Hz

(FS[3:0] = 1000)⁶

Rev. 0 | Page 3 of 32

AD7785

Parameter

AD7785B¹

Unit

Test Conditions/Comments

REFERENCE

Internal Reference

Internal Reference Initial Accuracy

Internal Reference Drift²

1.17 0.01ꢁ

4

1ꢀ

8ꢀ

V min/max

ppm/°C typ

ppm/°C max

dB typ

AV_DD= 4 V, T_A= 2ꢀ°C

Power Supply Rejection

External Reference

External REFIN Voltage

Reference Voltage Range²

2.ꢀ

V nom

V min

V max

REFIN = REFIN(+) − REFIN(−)

0.1

AV_DD

When V_REF= AV_DD, the differential input must be

limited to 0.9 × V_REF/gain if the in-amp is active

Absolute REFIN Voltage Limits²

Average Reference Input Current

Drift

V min

GND − 30 mV

AV_DD+ 30 mV

400

V max

nA/V typ

nA/V/°C typ

0.03

Normal Mode Rejection

Common-Mode Rejection

EXCITATION CURRENT SOURCES

(IEXC1 and IEXC2)

Same as for analog inputs

100

dB typ

Output Current

Initial Tolerance at 2ꢀ°C

Drift

10/210/1000

ꢀ

200

0.ꢀ

μA nom

ꢁ typ

ppm/°C typ

ꢁ typ

Current Matching

Matching between IEXC1 and IEXC2; V_OUT= 0 V

AV_DD= ꢀ V ꢀꢁ

Drift Matching

Line Regulation (V_DD)

Load Regulation

ꢀ0

2

0.2

ppm/°C typ

ꢁ/V typ

V max

Output Compliance

10 μA or 210 μA currents selected

1 mA currents selected

AV_DD− 0.6ꢀ

AV_DD− 1.1

GND − 30 mV

V max

V min

TEMPERATURE SENSOR

Accuracy

Sensitivity

2

0.81

°C typ

mV/°C typ

Applies if user calibrates the temperature sensor

BIAS VOLTAGE GENERATOR

V_BIAS

AV_DD/2

V nom

V_BIASGenerator Start-Up Time

INTERNAL/EXTERNAL CLOCK

Internal Clock

See Figure 10

ms/nF typ

Dependent on the capacitance on the AIN pin

Frequency²

64 3ꢁ

ꢀ0:ꢀ0

kHz min/max

ꢁ typ

Duty Cycle

External Clock

Frequency

64

kHz nom

ꢁ typ

A 128 kHz external clock can be used if the

divide-by-2 function is used

(Bit CLK1 = CLK0 = 1)

Applies for external 64 kHz clock; a 128 kHz

clock can have a less stringent duty cycle

Duty Cycle

4ꢀ:ꢀꢀ to ꢀꢀ:4ꢀ

LOGIC INPUTS

CS²

V_INL, Input Low Voltage

0.8

V max

DV_DD= ꢀ V

0.4

2.0

V max

V min

DV_DD= 3 V

DV_DD= 3 V or ꢀ V

V_INH, Input High Voltage

Rev. 0 | Page 4 of 32

AD7785

Parameter

AD7785B¹

Unit

Test Conditions/Comments

SCLK, CLK, and DIN (Schmitt-

Triggered Input)²

V_T(+)

V_T(–)

1.4/2

V min/V max

DV_DD= ꢀ V

DV_DD= 3 V

0.8/1.7

0.1/0.17

0.9/2

0.4/1.3ꢀ

0.06/0.13

V_T(+) − V_T(−)

V_T(+)

V_T(–)

V_T(+) − V_T(−)

Input Currents

Input Capacitance

10

μA max

pF typ

V_IN= DV_DDor GND

All digital inputs

LOGIC OUTPUTS (INCLUDING CLK)

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V min

V max

V min

V max

DV_DD= 3 V, I_SOURCE= 100 μA

DV_DD= 3 V, I_SINK= 100 μA

DV_DD= ꢀ V, I_SOURCE= 200 μA

DV_DD= ꢀ V, I_SINK= 1.6 mA (DOUT/RDY)/

800 μA (CLK)

DV_DD− 0.6

0.4

4

0.4

Floating-State Leakage Current

Floating-State Output Capacitance

Data Output Coding

10

Offset binary

μA max

pF typ

SYSTEM CALIBRATION²

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

+1.0ꢀ × FS

−1.0ꢀ × FS

0.8 × FS

V max

V min

V max

2.1 × FS

POWER REQUIREMENTS⁷

Power Supply Voltage

AV_DDto GND

2.7/ꢀ.2ꢀ

V min/max

DV_DDto GND

Power Supply Currents

I_DDCurrent

140

18ꢀ

400

ꢀ00

1

μA max

110 μA typ @ AV_DD= 3 V, 12ꢀ μA typ @ AV_DD= ꢀ V,

unbuffered mode, external reference

130 μA typ @ AV_DD= 3 V, 16ꢀ μA typ @ AV_DD= ꢀ V,

buffered mode, gain = 1 or 2, external reference

300 μA typ @ AV_DD= 3 V, 3ꢀ0 μA typ @ AV_DD= ꢀ V,

gain = 4 to 128, external reference

400 μA typ @ AV_DD= 3 V, 4ꢀ0 μA typ @ AV_DD= ꢀ V,

gain = 4 to 128, internal reference

I_DD(Power-Down Mode)

¹Temperature range is –40°C to +10ꢀ°C.

²Specification is not production tested, but is supported by characterization data at initial product release.

³Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

⁴Recalibration at any temperature removes these errors.

^ꢀFull-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV_DD= 4 V, gain = 1, T_A= 2ꢀ°C).

⁶FS[3:0] are the four bits used in the mode register to select the output word rate.

⁷Digital inputs equal to DV_DDor GND with excitation currents and bias voltage generator disabled.

Rev. 0 | Page ꢀ of 32

AD7785

TIMING CHARACTERISTICS

AV_DD= 2.7 V to 5.25 V, DV_DD= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV_DD, unless otherwise noted.

Table 2.

Parameter^{1, 2}

Limit at T_MIN, T_MAX(B Version)

Unit

Conditions/Comments

SCLK high pulse width

SCLK low pulse width

t₃

t₄

100

ns min

Read Operation

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

DV_DD= 4.7ꢀ V to ꢀ.2ꢀ V

DV_DD= 2.7 V to 3.6 V

SCLK active edge to data valid delay⁴

DV_DD= 4.7ꢀ V to ꢀ.2ꢀ V

DV_DD= 2.7 V to 3.6 V

Bus relinquish time after CS inactive edge

60

80

0

60

80

10

80

0

3

t₂

ꢀ, 6

t_ꢀ

t₆

SCLK inactive edge to CS inactive edge

SCLK inactive edge to DOUT/RDY high

t₇

10

Write Operation

t₈

0

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

30

2ꢀ

0

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= ꢀ ns (10ꢁ to 90ꢁ of DV_DD) and timed from a voltage level of 1.6 V.

²See Figure 3 and Figure 4.

³These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴SCLK active edge is the falling edge of SCLK.

^ꢀThese numbers are derived from the measured time taken by the data output to change 0.ꢀ V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the ꢀ0 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

⁶RDY

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

is high,

although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read

only once.

I

(1.6mA WITH DV = 5V,

DD

SINK

100µA WITH DV = 3V)

DD

TO

OUTPUT

1.6V

50pF

I

(200µA WITH DV = 5V,

DD

SOURCE

100µA WITH DV = 3V)

DD

Figure 2. Load Circuit for Timing Characterization

Rev. 0 | Page 6 of 32

AD7785

TIMING DIAGRAMS

CS (I)

t₆

t₁

t₅

MSB

LSB

t₇

DOUT/RDY (O)

t₂

t₃

SCLK (I)

t₄

NOTES

1. I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

NOTES

1. I = INPUT, O = OUTPUT

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 32

AD7785

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

AV_DDto GND

−0.3 V to +7 V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

10 mA

DV_DDto GND

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

TSSOP

ESD CAUTION

−40°C to +10ꢀ°C

−6ꢀ°C to +1ꢀ0°C

1ꢀ0°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Reflow

1ꢀ0.4°C/W

27.6°C/W

260°C

Rev. 0 | Page 8 of 32

AD7785

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SCLK

CLK

DIN

DOUT/RDY

CS

DV

AV

DD

IOUT1

AIN1(+)

AIN1(–)

AIN2(+)

AIN2(–)

AD7785

TOP VIEW

(Not to Scale)

DD

GND

IOUT2

REFIN(–)/AIN3(–)

REFIN(+)/AIN3(+)

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous

clock with the information being transmitted to or from the ADC in smaller batches of data.

2

3

CLK

CS

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can

be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a

common clock, allowing simultaneous conversions to be performed.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in communicating

with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.

4

IOUT1

Output of Internal Excitation Current Source. The internal excitation current source can be made available at

this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.

Either IEXC1 or IEXC2 can be switched to this output.

ꢀ

6

7

8

9

AIN1(+)

AIN1(−)

AIN2(+)

AIN2(−)

Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−).

Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−).

Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−).

Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−).

REFIN(+)/AIN3(+) Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and

REFIN(−). REFIN(+) can lie anywhere between AV_DDand GND + 0.1 V. The nominal reference voltage

REFIN(+) − REFIN(−) is 2.ꢀ V, but the part functions with a reference from 0.1 V to AV_DD. Alternatively, this

pin can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog input pair

AIN3(+)/AIN3(−).

10

11

REFIN(−)/AIN3(−) Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference

input can lie anywhere between GND and AV_DD− 0.1 V. This pin also functions as AIN3(−), which is the

negative terminal of the differential analog input pair AIN3(+)/AIN3(−).

IOUT2

Output of Internal Excitation Current Source. The internal excitation current source can be made available at

this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.

Either IEXC1 or IEXC2 can be switched to this output.

12

13

14

GND

AV_DD

DV_DD

Ground Reference Point.

Supply Voltage, 2.7 V to ꢀ.2ꢀ V.

Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which

is between 2.7 V and ꢀ.2ꢀ V. The DV_DDvoltage is independent of the voltage on AV_DD; therefore, AV_DDcan

equal ꢀ V with DV_DDat 3 V or vice versa.

Rev. 0 | Page 9 of 32

AD7785

Pin No.

Mnemonic

Description

1ꢀ

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output

pin to access the output shift register of the ADC. The output shift register can contain data from any of the

on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate

the completion of a conversion. If the data is not read after the conversion, the pin goes high before the

next update occurs.

The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.

With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control

word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK

rising edge.

16

DIN

Serial Data Input. This serial data input is to the input shift register on the ADC. Data in this shift register is

transferred to the control registers within the ADC; the register selection bits of the communications

register identify the appropriate register.

Rev. 0 | Page 10 of 32

AD7785

OUTPUT NOISE AND RESOLUTION SPECIFICATIONS

EXTERNAL REFERENCE

Table 5 shows the output rms noise of the AD7785 for some of

the update rates and gain settings. The numbers given are for

the bipolar input range with an external 2.5 V reference. These

numbers are typical and are generated with a differential input

voltage of 0 V. Table 6 shows the effective resolution, with the

output peak-to-peak (p-p) resolution shown in parentheses. It is

important to note that the effective resolution is calculated

using the rms noise, while the p-p resolution is based on the p-p

noise. The p-p resolution represents the resolution for which

there is no code flicker. These numbers are typical and are

rounded to the nearest LSB.

Table 5. Output RMS Noise (μV) vs. Gain and Output Update Rate Using an External 2.5 V Reference

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

0.22

0.26

0.36

0.ꢀ

0.ꢀ8

1

1.96

1.79

Gain of 16

Gain of 32

0.06ꢀ

0.078

0.11

0.17

0.2

0.32

0.4ꢀ

0.63

Gain of 64

0.039

0.0ꢀ7

0.087

0.124

0.1ꢀ3

0.26ꢀ

0.379

0.ꢀ68

Gain of 128

0.041

0.0ꢀꢀ

0.086

0.118

0.144

0.283

0.397

0.ꢀ93

4.17

8.33

16.7

33.2

62

123

242

470

0.64

1.04

1.ꢀꢀ

2.3

2.9ꢀ

4.89

11.76

11.33

0.6

0.29

0.38

0.ꢀ4

0.74

0.92

1.49

4.02

3.07

0.1

0.13

0.18

0.23

0.29

0.48

0.88

0.99

0.96

1.4ꢀ

2.13

2.8ꢀ

4.74

9.ꢀ

9.44

Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate Using an External 2.5 V Reference

Update Rate (Hz)

Gain of 1

Gain of 2

20 (19.ꢀ)

20 (19)

Gain of 4

20 (19.ꢀ)

20 (19)

20 (18.ꢀ)

20 (18)

Gain of 8

Gain of 16

Gain of 32

20 (18.ꢀ)

20 (18)

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

Gain of 64

20 (18.ꢀ)

20 (18)

20 (17.ꢀ)

19 (16.ꢀ)

18 (1ꢀ.ꢀ)

17.ꢀ (1ꢀ)

17 (14.ꢀ)

Gain of 128

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

17 (14.ꢀ)

16.ꢀ (14)

16 (13.ꢀ)

4.17

8.33

16.7

33.2

62

123

242

470

20 (20)

20 (19.ꢀ)

20 (19)

20 (18.ꢀ)

20 (18)

20 (17.ꢀ)

18.ꢀ (16)

20 (19)

20 (18.ꢀ)

20 (18)

20 (17.ꢀ)

19 (16.ꢀ)

18 (1ꢀ.ꢀ)

18.ꢀ (16)

20 (19)

20 (18.ꢀ)

20 (18)

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18 (1ꢀ.ꢀ)

20 (18)

20 (17.ꢀ)

19.ꢀ (17)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

19.ꢀ (17)

18 (1ꢀ.ꢀ)

18.ꢀ (16)

Rev. 0 | Page 11 of 32

AD7785

INTERNAL REFERENCE

Table 7 shows the output rms noise of the AD7785 for some of

the update rates and gain settings. The numbers given are for

the bipolar input range with the internal 1.17 V reference. These

numbers are typical and are generated with a differential input

voltage of 0 V. Table 8 shows the effective resolution, with the

output peak-to-peak (p-p) resolution given in parentheses. It is

important to note that the effective resolution is calculated

using the rms noise, while the p-p resolution is calculated based

on p-p noise. The p-p resolution represents the resolution for

which there is no code flicker. These numbers are typical and

are rounded to the nearest LSB.

Table 7. Output RMS Noise (μV) vs. Gain and Output Update Rate Using the Internal Reference

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

0.06ꢀ

0.078

0.11

0.17

0.2

0.32

0.4ꢀ

0.63

Gain of 64

0.04

0.0ꢀ8

0.088

0.13

0.1ꢀ

0.2ꢀ

0.3ꢀ

0.ꢀ0

Gain of 128

0.039

0.0ꢀ9

0.088

0.12

0.1ꢀ

0.26

0.34

0.49

4.17

8.33

16.7

33.2

62

123

242

470

0.81

1.18

1.96

2.99

3.6

ꢀ.83

11.22

12.46

0.67

1.11

1.72

2.48

3.2ꢀ

ꢀ.01

8.64

10.ꢀ8

0.32

0.41

0.ꢀꢀ

0.83

1.03

1.69

2.69

4.ꢀ8

0.2

0.13

0.16

0.2ꢀ

0.33

0.46

0.67

1.04

1.27

0.2ꢀ

0.36

0.48

0.6ꢀ

0.96

1.9

2

Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate Using the Internal Reference

Update Rate (Hz)

Gain of 1

Gain of 2

20.ꢀ (18)

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

17 (14.ꢀ)

Gain of 4

20 (18.ꢀ)

20.ꢀ (18)

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18.ꢀ (16)

17.ꢀ (1ꢀ)

17 (14.ꢀ)

Gain of 8

20.ꢀ (18)

20 (17.ꢀ)

19.ꢀ (17)

19 (16.ꢀ)

18 (1ꢀ.ꢀ)

17 (14.ꢀ)

Gain of 16

20 (17.ꢀ)

19 (16.ꢀ)

18.ꢀ (16)

17.ꢀ (1ꢀ)

17 (14.ꢀ)

Gain of 32

20 (17.ꢀ)

19.ꢀ (17)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

17.ꢀ (1ꢀ)

17 (14.ꢀ)

Gain of 64

20 (17.ꢀ)

19 (16.ꢀ)

18.ꢀ (16)

18 (1ꢀ.ꢀ)

17 (14.ꢀ)

16.ꢀ (14)

16 (13.ꢀ)

Gain of 128

19 (16.ꢀ)

18 (1ꢀ.ꢀ)

17.ꢀ (1ꢀ)

17 (14.ꢀ)

16 (13.ꢀ)

1ꢀ.ꢀ (13)

1ꢀ (12.ꢀ)

4.17

8.33

16.7

33.2

62

123

242

470

20 (19)

20 (18.ꢀ)

20 (17.ꢀ)

19.ꢀ (17)

18.ꢀ (16)

17.ꢀ (1ꢀ)

Rev. 0 | Page 12 of 32

AD7785

TYPICAL PERFORMANCE CHARACTERISTICS

8388800

8388750

8388700

8388650

8388600

8388550

8388500

8388450

20

10

0

–1.75 –1.05 –0.70 –0.35

0

0.35 0.70 1.05 1.40 1.75

0

200

400

600

800

1000

MATCHING (%)

READING NUMBER

Figure 6. Typical Noise Plot (Internal Reference, Gain = 64,

Update Rate = 16.7 Hz)

Figure 9. Excitation Current Matching (1 mA) at Ambient Temperature

90

80

70

60

50

40

30

20

10

0

16

14

12

10

8

6

4

2

0

8388482 8388520 8388560 8388600 8388640 8388680 8388720 8388750

CODE

0

200

400

600

800

1000

LOAD CAPACITANCE (nF)

Figure 10. Bias Voltage Generator Power-Up Time vs. Load Capacitance

Figure 7. Noise Distribution Histogram

(Internal Reference, Gain = 64, Update Rate = 16.7 Hz)

3.0

V

= 5V

DD

UPDATE RATE = 16.6Hz

= 25°C

T

A

2.5

2.0

1.5

1.0

0.5

0

20

10

0

–2.0 –1.2 –0.8 –0.4

0

0.4

0.8

1.2

1.6

2.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

MATCHING (%)

REFERENCE VOLTAGE (V)

Figure 11. RMS Noise vs. Reference Voltage (Gain = 1)

Figure 8. Excitation Current Matching (210 μA) at Ambient

Temperature

Rev. 0 | Page 13 of 32

AD7785

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described on the following pages. In the

following descriptions, set implies a Logic 1 state and cleared

implies a Logic 0 state, unless otherwise stated.

write operation to the selected register is complete, the interface

returns to where it expects a write operation to the communica-

tions register. This is the default state of the interface and,

on power-up or after a reset, the ADC is in this default state

waiting for a write operation to the communications register. In

situations where the interface sequence is lost, a write operation

of at least 32 serial clock cycles with DIN high returns the ADC

to this default state by resetting the entire part. Table 9 outlines

the bit designations for the communications register. CR0

through CR7 indicate the bit location, CR denoting the bits are

in the communications register. CR7 denotes the first bit of the

data stream. The number in parentheses indicates the power-

on/reset default status of that bit.

COMMUNICATIONS REGISTER

RS2, RS1, RS0 = 0, 0, 0

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation, and to which register this operation takes

place. For read or write operations, once the subsequent read or

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R/W(0)

RS2(0)

RS1(0)

RS0(0)

CREAD(0)

0(0)

Table 9. Communications Register Bit Designations

Bit Location

Bit Name Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually

occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this

bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to

the communications register.

CR6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CRꢀ to CR3

CR2

RS2 to RS0 Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected

during this serial interface communication. See Table 10.

CREAD

Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read. For example, the contents of the

data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY pin

goes low to indicate that a conversion is complete. The communications register does not have to be written

to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the

communications register. To exit the continuous read mode, the instruction 01011000 must be written to the

communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity

on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs

if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an

instruction is to be written to the device.

CR1 to CR0

0

These bits must be programmed to Logic 0 for correct operation.

Table 10. Register Selection

RS2

RS1

RS0

Register

Register Size

0

1

Communications Register During a Write Operation

Status Register During a Read Operation

Mode Register

8-bit

16-bit

0

1

0

1

Configuration Register

Data Register

16-bit

24-bit (20-bit conversion followed by four 1s)

1

0

ID Register

8-bit

1

0

1

IO Register

8-bit

1

0

1

Offset Register

Full-Scale Register

24-bit

Rev. 0 | Page 14 of 32

AD7785

STATUS REGISTER

RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x88

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status

register. SR0 through SR7 indicate the bit locations, and SR denotes that the bits are in the status register. SR7 denotes the first bit of the

data stream. The number in parentheses indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

0(0)

1 (1)

CH2(0)

CH1(0)

CH0(0)

Table 11. Status Register Bit Designations

Bit Location

Bit Name

Description

SR7

RDY

Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

after the ADC data register has been read or a period before the data register is updated with a new

conversion result to indicate to the user not to read the conversion data. It is also set when the part is

placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can

be used as an alternative to the status register for monitoring the ADC for conversion data.

SR6

ERR

ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to

the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.

Cleared by a write operation to start a conversion.

SRꢀ to SR4

SR3

0

1

These bits are automatically cleared.

This bit is automatically set on the AD778ꢀ.

SR2 to SR0

CH2 to CH0

These bits indicate which channel is being converted by the ADC.

MODE REGISTER

RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A

The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, update rate, and clock source. Table 12 outlines the bit designations for the mode register. MR0 through MR15 indicate

the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses

RDY

indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the

bit.

MR15

MD2(0)

MR7

MR14

MD1(0)

MR6

MR13

MD0(0)

MR5

MR12

0(0)

MR11

0(0)

MR10

0(0)

MR9

0(0)

MR8

0(0)

MR4

0(0)

MR3

FS3(1)

MR2

FS2(0)

MR1

FS1(1)

MR0

FS0(0)

CLK1(0)

CLK0(0)

0(0)

Table 12. Mode Register Bit Designations

Bit Location Bit Name Description

MR1ꢀ to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD778ꢀ (see Table 13).

MR12 to MR8

MR7 to MR6

0

These bits must be programmed with a Logic 0 for correct operation.

CLK1 to CLK0 These bits are used to select the clock source for the AD778ꢀ. Either an on-chip 64 kHz clock or an external

clock can be used. The ability to override using an external clock allows several AD778ꢀ devices to be

synchronized. In addition, ꢀ0 Hz/60 Hz is improved when an accurate external clock drives the AD778ꢀ.

CLK1

CLK0

ADC Clock Source

0

1

0

1

0

Internal 64 kHz Clock. Internal clock is not available at the CLK pin.

Internal 64 kHz Clock. This clock is made available at the CLK pin.

External 64 kHz Clock Used. An external clock gives better ꢀ0 Hz/60 Hz rejection. See

specifications for external clock.

1

External Clock Used. The external clock is divided by 2 within the AD778ꢀ.

MRꢀ to MR4

MR3 to MR0

0

These bits must be programmed with a Logic 0 for correct operation.

Filter Update Rate Select Bits (see Table 14).

FS3 to FS0

Rev. 0 | Page 1ꢀ of 32

AD7785

Table 13. Operating Modes

MD2 MD1 MD0 Mode

0

Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data

register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in

continuous read mode, whereby the conversions are automatically placed on the DOUT line when SCLK pulses are

applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications

register. After power-on, a channel change, or a write to the mode, configuration, or IO registers, the first conversion

is available after a period of 2/f_ADC. Subsequent conversions are available at a frequency of f_ADC

.

0

1

Single Conversion Mode.

When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator

requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f_ADC. The

conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The

conversion remains in the data register, and RDY remains active low until the data is read or another conversion is

performed.

0

1

0

1

Idle Mode.

In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are still provided.

Power-Down Mode.

In power-down mode, all the AD778ꢀ circuitry is powered down, including the current sources, burnout currents,

bias voltage generator, and CLKOUT circuitry.

1

0

1

Internal Zero-Scale Calibration.

An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to

complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The

ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of

the selected channel.

Internal Full-Scale Calibration.

A full-scale input voltage is automatically connected to the selected analog input for this calibration.

When the gain equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles

are required to perform the full-scale calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel.

Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-

scale calibration can be performed.

A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.

1

0

1

System Zero-Scale Calibration.

The user should connect the system zero-scale input to the channel input pins as selected by the CH2 to CH0 bits. A

system offset calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel.

System Full-Scale Calibration.

The user should connect the system full-scale input to the channel input pins as selected by the CH2 to CH0 bits.

A calibration takes 2 conversion cycles to complete. RDY goes high when the calibration is initiated and returns low

when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale

coefficient is placed in the full-scale register of the selected channel.

A full-scale calibration is required each time the gain of a channel is changed.

Table 14. Update Rates Available

FS3

FS2

FS1

FS0

f_ADC(Hz)

x

t_SETTLE(ms)

Rejection @ 50 Hz/60 Hz (Internal Clock)

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

470

242

123

62

ꢀ0

39

4

8

16

32

40

48

60

101

33.2

19.6

90 dB (60 Hz only)

Rev. 0 | Page 16 of 32

AD7785

FS3

1

FS2

0

1

FS1

0

1

0

1

FS0

1

0

1

0

1

0

1

f_ADC(Hz)

16.7

12.ꢀ

10

8.33

6.2ꢀ

4.17

t_SETTLE(ms)

120

160

200

240

320

480

Rejection @ 50 Hz/60 Hz (Internal Clock)

80 dB (ꢀ0 Hz only)

6ꢀ dB (ꢀ0 Hz and 60 Hz)

66 dB (ꢀ0 Hz and 60 Hz)

69 dB (ꢀ0 Hz and 60 Hz)

70 dB (ꢀ0 Hz and 60 Hz)

72 dB (ꢀ0 Hz and 60 Hz)

74 dB (ꢀ0 Hz and 60 Hz)

CONFIGURATION REGISTER

RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710

The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to con-

figure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and

select the analog input channel. Table 15 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit

locations; CON denotes that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in

parentheses indicates the power-on/reset default status of that bit.

CON15

CON14

VBIAS0(0)

CON6

CON13

BO(0)

CON5

0(0)

CON12

U/B(0)

CON4

BUF(1)

CON11

BOOST(0)

CON3

CON10

G2(1)

CON9

G1(1)

CON8

G0(1)

VBIAS1(0)

CON7

CON2

CH2(0)

CON1

CH1(0)

CON0

CH0(0)

REFSEL(0)

0(0)

Table 15. Configuration Register Bit Designations

Bit Location Bit Name Description

CON1ꢀ to

CON14

VBIAS1 to

VBIAS0

Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AV_DD/2. These

bits are used in conjunction with the boost bit.

VBIAS1

VBIAS0

Bias Voltage

0

1

0

1

0

1

Bias voltage generator disabled

Bias voltage connected to AIN1(−)

Bias voltage connected to AIN2(−)

Reserved

CON13

CON12

BO

Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path

are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only

when the buffer or in-amp is active. The burnout currents are available on Channels AIN1 and AIN2.

Unipolar/Bipolar Bit. Set by user to enable unipolar coding. Therefore, a zero differential input results in

0x00000 output, and a full-scale differential input results in 0xFFFFF output. Cleared by the user to enable

bipolar coding. Negative full-scale differential input results in an output code of 0x00000, zero differential

input results in an output code of 0x80000, and a positive full-scale differential input results in an output code

of 0xFFFFF.

U/B

CON11

BOOST

This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias

voltage generator is increased. This reduces its power-up time.

CON10 to

CON8

G2 to G0

Gain Select Bits.

Written by the user to select the ADC input range as follows:

G2

0

G1

0

G0

0

Gain

ADC Input Range (2.5 V Reference)

1 (In-amp not used)

2.ꢀ V

0

1

2 (In-amp not used)

1.2ꢀ V

0

1

0

1

0

1

0

1

0

1

4

8

16

32

64

128

62ꢀ mV

312.ꢀ mV

1ꢀ6.2 mV

78.12ꢀ mV

39.06 mV

19.ꢀ3 mV

Rev. 0 | Page 17 of 32

AD7785

Bit Location Bit Name

Description

CON7

REFSEL

Reference Select Bit. The reference source for the ADC is selected using this bit.

REFSEL

Reference Source

0

1

External Reference Applied between REFIN(+) and REFIN(–).

Internal Reference Selected.

CON6 to

CONꢀ

0

These bits must be programmed with a Logic 0 for correct operation.

CON4

BUF

Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered

mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the

user to place source impedances on the front end without contributing gain errors to the system. The buffer

can be disabled when the gain equals 1 or 2. For higher gains, the buffer is automatically enabled.

With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above

AV_DD. When the buffer is enabled, it requires some headroom, so the voltage on any input pin must be limited

to 100 mV within the power supply rails.

CON3

0

This bit must be programmed with a Logic 0 for correct operation.

CON2 to

CON0

CH2 to

CH0

Channel Select Bits. Written by the user to select the active analog input channel to the ADC.

CH2

0

1

CH1 CH0

Channel

Calibration Pair

0

1

0

1

0

1

0

1

0

1

0

1

AIN1(+) – AIN1(–)

AIN2(+) – AIN2(–)

AIN3(+) – AIN3(–)

AIN1(−) – AIN1(−)

Reserved

Temp Sensor

AV_DDMonitor

0

1

2

0

Automatically selects gain = 1 and internal reference

Automatically selects gain = 1/6 and 1.17 V

reference

DATA REGISTER

RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x00000F

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

RDY

this register, the

bit/pin is set. This is a 24-bit register. The 20-bit conversion is contained in the 20 MSBs. The 4 LSBs are set to 1.

ID REGISTER

RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXB

The identification number for the AD7785 is stored in the ID register. This is a read-only register.

IO REGISTER

RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00

The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable and select

the value of the excitation currents. Table 16 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations;

IO denotes that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in parentheses indicates the power-

on/reset default status of that bit.

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

0(0)

IEXCDIR1(0)

IEXCDIR0(0)

IEXCEN1(0)

IEXCEN0(0)

Rev. 0 | Page 18 of 32

AD7785

Table 16. IO Register Bit Designations

Bit Location

IO7 to IO4

IO3 to IO2

Bit Name

Description

0

These bits must be programmed with a Logic 0 for correct operation.

Direction of current sources select bits.

IEXCDIR1 to

IEXCDIR0

IEXCDIR1 IEXCDIR0 Current Source Direction

0

1

0

1

0

1

Current Source IEXC1 connected to Pin IOUT1, Current Source IEXC2

connected to Pin IOUT2.

Current Source IEXC1 connected to Pin IOUT2, Current Source IEXC2

connected to Pin IOUT1.

Both current sources connected to Pin IOUT1. Permitted when the current

sources are set to 10 μA or 210 μA only.

Both current sources connected to Pin IOUT2. Permitted when the current

sources are set to 10 μA or 210 μA only.

IO1 to IO0

IEXCEN1 to

IEXCEN0

These bits are used to enable and disable the current sources along with selecting the value of the

excitation currents.

IEXCEN1

IEXCEN0

Current Source Value

0

1

0

1

0

1

Excitation Current Disabled

10 μA

210 μA

1 mA

OFFSET REGISTER

FULL-SCALE REGISTER

RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000

RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX00

Each analog input channel has a dedicated offset register that

holds the offset calibration coefficient for the channel. This

register is 24 bits wide and its power-on/reset value is

0x8000(00). The offset register is used in conjunction with its

associated full-scale register to form a register pair. The power-

on reset value is automatically overwritten if an internal or

system zero-scale calibration is initiated by the user. The offset

register is a read/write register. However, the AD7785 must be

in idle mode or power-down mode when writing to the

offset register.

The full-scale register is a 24-bit register that holds the full-scale

calibration coefficient for the ADC. The AD7785 has 3 full-scale

registers, each channel having a dedicated full-scale register.

The full-scale registers are read/write registers; however, when

writing to the full-scale registers, the ADC must be placed in

power-down mode or idle mode. These registers are configured

on power-on with factory-calibrated full-scale calibration coef-

ficients, the calibration being performed at gain = 1. Therefore,

every device has different default coefficients. The coefficients

are different depending on whether the internal reference or an

external reference is selected. The default value is automatically

overwritten if an internal or system full-scale calibration is

initiated by the user, or the full-scale register is written to.

Rev. 0 | Page 19 of 32

AD7785

ADC CIRCUIT INFORMATION

The AD7785 uses slightly different filter types, depending on

the output update rate so that the rejection of quantization

noise and device noise is optimized. When the update rate is

from 4.17 Hz to 12.5 Hz, a Sinc3 filter, along with an averaging

filter, is used. When the update rate is from 16.7 Hz to 39 Hz, a

modified Sinc3 filter is used. This filter provides simultaneous

50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A

Sinc4 filter is used when the update rate is from 50 Hz to

242 Hz. Finally, an integrate-only filter is used when the update

rate equals 470 Hz.

OVERVIEW

The AD7785 is a low power ADC that incorporates a ∑-Δ

modulator, a buffer, reference, in-amp, and an on-chip digital

filter intended for the measurement of wide dynamic range, low

frequency signals such as those in pressure transducers, weigh

scales, and temperature measurement applications.

The part has three differential inputs that can be buffered or

unbuffered. The device can be operated with the internal 1.17 V

reference, or an external reference can be used. Figure 12 shows

the basic connections required to operate the part.

Figure 13 to Figure 16 show the frequency response of the

different filter types for several update rates.

The output rate of the AD7785 (f_ADC) is user-programmable. The

allowable update rates, along with their corresponding settling

times, are listed in Table 14. Normal mode rejection is the major

function of the digital filter. Simultaneous 50 Hz and 60 Hz

rejection is optimized when the update rate equals 16.7 Hz or

less as notches are placed at both 50 Hz and 60 Hz with these

update rates (see Figure 14.)

GND

AV

DD

V

BIAS

REFIN(+) REFIN(–)

THERMOCOUPLE

BAND GAP

REFERENCE

JUNCTION

R

AIN1(+)

AIN1(–)

GND

AV

DD

R

C

DOUT/RDY

SERIAL

MUX

AIN2(+)

AIN2(–)

DIN

INTERFACE

AND

Σ-Δ

ADC

BUF

IN-AMP

SCLK

CS

CONTROL

LOGIC

REFIN(+)

R

GND

AV

REF

DV

DD

INTERNAL

CLOCK

REFIN(–)

IOUT2

DD

AD7785

CLK

Figure 12. Basic Connection Diagram

0

–20

–40

–60

–80

–100

0

20

40

60

80

100

120

FREQUENCY (Hz)

Figure 13. Filter Profile with Update Rate = 4.17 Hz

Rev. 0 | Page 20 of 32

AD7785

0

–20

DIGITAL INTERFACE

The programmable functions of the AD7785 are controlled

using a set of on-chip registers. Data is written to these registers

via the serial interface of the device; read access to the on-chip

registers is also provided by this interface. All communications

with the device must start with a write to the communications

register. After power-on or reset, the device expects a write to

its communications register. The data written to this register

determines whether the next operation is a read operation or a

write operation and determines to which register this read or

write operation occurs. Therefore, write access to any of the

other registers on the part begins with a write operation to the

communications register followed by a write to the selected

register. A read operation from any other register (except when

continuous read mode is selected) starts with a write to the

communications register followed by a read operation from the

selected register.

–40

–60

–80

–100

0

20

40

60

80

100 120 140 160 180 200

FREQUENCY (Hz)

Figure 14. Filter Profile with Update Rate = 16.7 Hz

0

–20

CS

The serial interface of the AD7785 consists of four signals:

RDY

,

DIN, SCLK, and DOUT/

. The DIN line is used to transfer

RDY

–40

data into the on-chip registers, and DOUT/

accessing from the on-chip registers. SCLK is the serial clock

input for the device, and all data transfers (either on DIN or

is used for

–60

RDY

DOUT/

) occur with respect to the SCLK signal. The

RDY

DOUT/

pin operates as a data-ready signal also; the line

–80

going low when a new data-word is available in the output

register. It is reset high when a read operation from the data

register is complete. It also goes high prior to the updating of

the data register to indicate when not to read from the device to

ensure that a data read is not attempted while the register is

–100

500

1000

1500

2000

2500

3000

FREQUENCY (Hz)

Figure 15. Filter Profile with Update Rate = 242 Hz

CS

being updated.

is used to select a device. It can be used to

0

–10

–20

–30

–40

–50

–60

decode the AD7785 in systems where several components are

connected to the serial bus.

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

FREQUENCY (Hz)

Figure 16. Filter Response at 470 Hz Update Rate

Rev. 0 | Page 21 of 32

AD7785

Figure 3 and Figure 4 show timing diagrams for interfacing to

Single Conversion Mode

CS

the AD7785 with

being used to decode the part. Figure 3

In single conversion mode, the AD7785 is placed in shutdown

mode between conversions. When a single conversion is initi-

ated by setting MD2, MD1, MD0 to 0, 0, 1 in the mode register,

the AD7785 powers up, performs a single conversion, and then

returns to power-down mode. The on-chip oscillator requires

1 ms to power up. A conversion requires a time period of

shows the timing for a read operation from the AD7785 output

shift register, and Figure 4 shows the timing for a write opera-

tion to the input shift register. It is possible to read the same

word from the data register several times, even though the

RDY

DOUT/

line returns high after the first read operation.

However, care must be taken to ensure that the read operations

have been completed before the next output update occurs. In

continuous read mode, the data register can be read only once.

RDY

2 × t_ADC. DOUT/

conversion. When the data-word has been read from the data

RDY CS RDY

goes low to indicate the completion of a

register, DOUT/

goes high. If

is low, DOUT/

remains high until another conversion is initiated and com-

pleted. The data register can be read several times, if required,

CS

The serial interface can operate in 3-wire mode by tying

low.

RDY

In this case, the SCLK, DIN, and DOUT/

lines are used

RDY

even when DOUT/

has gone high.

to communicate with the AD7785. The end of the conversion

RDY

can be monitored using the

scheme is suitable for interfacing to microcontrollers. If

bit in the status register. This

CS

Continuous Conversion Mode

is

This is the default power-up mode. The AD7785 continuously

required as a decoding signal, it can be generated from a port

pin. For microcontroller interfaces, it is recommended that

SCLK idle high between data transfers.

RDY

converts, the

pin in the status register going low each time

CS RDY

a conversion is completed. If

is low, the DOUT/

line

also goes low when a conversion is complete. To read a conver-

sion, the user writes to the communications register indicating

that the next operation is a read of the data register. The digital

CS

The AD7785 can be operated with

synchronization signal. This scheme is useful for DSP interfaces.

CS

being used as a frame

In this case, the first bit (MSB) is effectively clocked out by

CS

,

RDY

conversion is placed on the DOUT/

pin as soon as SCLK

RDY

because

would normally occur after the falling edge of SCLK

pulses are applied to the ADC. DOUT/

returns high when

in DSPs. The SCLK can continue to run between data transfers,

provided the timing numbers are obeyed.

the conversion is read. The user can read this register additional

times, if required. However, the user must ensure that the data

register is not being accessed at the completion of the next

conversion, otherwise the new conversion word is lost.

The serial interface can be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the AD7785 line for at least

32 serial clock cycles, the serial interface is reset. This ensures

that the interface can be reset to a known state if the interface

gets lost due to a software error or some glitch in the system.

Reset returns the interface to the state in which it is expecting

a write to the communications register. This operation resets

the contents of all registers to their power-on values. Following

a reset, the user should allow a period of 500 μs before

addressing the serial interface.

The AD7785 can be configured to continuously convert or to

perform a single conversion. See Figure 17 through Figure 19.

Rev. 0 | Page 22 of 32

AD7785

CS

0x08

0x200A

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 17. Single Conversion

CS

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 18. Continuous Conversion

Rev. 0 | Page 23 of 32

AD7785

Continuous Read

read before the next conversion is complete. If the user has

not read the conversion before the completion of the next

conversion, or if insufficient serial clocks are applied to the

AD7785 to read the word, the serial output register is reset

when the next conversion is completed, and the new conversion

is placed in the output serial register.

Rather than write to the communications register to access

the data each time a conversion is complete, the AD7785

can be configured so that the conversions are placed on the

RDY

DOUT/

line automatically. By writing 01011100 to the

communications register, the user needs only to apply the 24

SCLK cycles to the ADC, and the 20-bit result followed by four

1s is automatically placed on the DOUT/

conversion is complete. The ADC should be configured for

continuous conversion mode.

To exit the continuous read mode, the instruction 01011000

must be written to the communications register while the

RDY

line when a

RDY

DOUT/

pin is low. While in the continuous read mode,

the ADC monitors activity on the DIN line so that it can receive

the instruction to exit the continuous read mode. Additionally,

a reset occurs if 32 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is written to the device.

RDY

When DOUT/

sion, sufficient SCLK cycles must be applied to the ADC, and

RDY

goes low to indicate the end of a conver-

the data conversion is placed on the DOUT/

line. When

returns high until the next

RDY

the conversion is read, DOUT/

conversion is available. In this mode, the data can be read only

once. In addition, the user must ensure that the data-word is

CS

0x5C

DIN

DATA

DOUT/RDY

SCLK

Figure 19. Continuous Read

Rev. 0 | Page 24 of 32

AD7785

CIRCUIT DESCRIPTION

For example, when the gain is set to 64, the rms noise is 40 nV

typically, which is equivalent to 20 bits effective resolution or

18.5 bits peak-to-peak resolution.

ANALOG INPUT CHANNEL

The AD7785 has three differential analog input channels. These

are connected to the on-chip buffer amplifier when the device is

operated in buffered mode and directly to the modulator when

the device is operated in unbuffered mode. In buffered mode

(the BUF bit in the mode register is set to 1), the input channel

feeds into a high impedance input stage of the buffer amplifier.

Therefore, the input can tolerate significant source impedances

and is tailored for direct connection to external resistive-type

sensors, such as strain gauges or resistance temperature

detectors (RTDs).

The AD7785 can be programmed to have a gain of 1, 2, 4, 8, 16,

32, 64, and 128 using Bit G2 to Bit G0 in the configuration

register. Therefore, with an external 2.5 V reference, the

unipolar ranges are from 0 mV to 20 mV to 0 V to 2.5 V while

the bipolar ranges are from 20 mV to 2.5 V. When the

in-amp is active (gain ≥ 4), the common-mode voltage (AIN(+)

+ AIN(–))/2 must be greater than or equal to 0.5 V.

If the AD7785 is operated with an external reference that has a

value equal to AV_DD, the analog input signal must be limited to

90% of V_REF/gain when the in-amp is active, for correct

operation.

When BUF = 0, the part is operated in unbuffered mode.

This results in a higher analog input current. Note that this

unbuffered input path provides a dynamic load to the driving

source. Therefore, resistor/capacitor combinations on the input

pins can cause gain errors, depending on the output impedance

of the source that is driving the ADC input. Table 17 shows the

allowable external resistance/capacitance values for unbuffered

mode such that no gain error at the 20-bit level is introduced.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7785 can accept either unipolar or

bipolar input voltage ranges. A bipolar input range does not

imply that the part can tolerate negative voltages with respect to

system GND. Unipolar and bipolar signals on the AIN(+) input

are referenced to the voltage on the AIN(–) input. For example,

if AIN(−) is 2.5 V, and the ADC is configured for unipolar mode

and a gain of 1, the input voltage range on the AIN(+) pin is

2.5 V to 5 V.

Table 17. External R-C Combination for 20-Bit No Gain Error

C (pF)

ꢀ0

R (Ω)

9 k

100

6 k

If the ADC is configured for bipolar mode, the analog input

range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar

ꢀ00

1000

ꢀ000

1.ꢀ k

900

200

B

option is chosen by programming the U/ bit in the configura-

tion register.

The AD7785 can be operated in unbuffered mode only when

the gain equals 1 or 2. At higher gains, the buffer is automati-

cally enabled. The absolute input voltage range in buffered

mode is restricted to a range between GND + 100 mV and

AV_DD– 100 mV. When the gain is set to 4 or higher, the in-amp

is enabled. The absolute input voltage range when the in-amp is

active is restricted to a range between GND + 300 mV and

AV_DD− 1.1 V. Take care in setting up the common-mode voltage

so that these limits are not exceeded to avoid degradation in

linearity and noise performance.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00000 hex, a midscale voltage

resulting in a code of 80000, and a full-scale input voltage

resulting in a code of FFFFF. The output code for any analog

input voltage can be represented as

Code = (2^N× AIN × GAIN)/V_REF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 00000 hex, a zero differential input voltage resulting

in a code of 80000 hex, and a positive full-scale input voltage

resulting in a code of FFFFF hex. The output code for any

analog input voltage can be represented as

The absolute input voltage in unbuffered mode includes the

range between GND – 30 mV and AV_DD+ 30 mV as a result of

being unbuffered. The negative absolute input voltage limit does

allow the possibility of monitoring small true bipolar signals

with respect to GND.

INSTRUMENTATION AMPLIFIER

Code = 2^{N – 1}× [(AIN × GAIN /V_REF) + 1]

Amplifying the analog input signal by a gain of 1 or 2 is

performed digitally within the AD7785. However, when the

gain equals 4 or higher, the output from the buffer is applied

to the input of the on-chip instrumentation amplifier. This low

noise in-amp means that signals of small amplitude can be

gained within the AD7785 while still maintaining excellent

noise performance.

where:

AIN is the analog input voltage.

GAIN is the in-amp setting (1 to 128).

N = 20.

Rev. 0 | Page 2ꢀ of 32

AD7785

The current consumption of the AD7785 increases by 40 μA

when the bias voltage generator is enabled, and boost equals 0.

With the boost function enabled, the current consumption

increases by 250 μA.

BURNOUT CURRENTS

Burnout currents are available on Channels AIN1 and AIN2.

The burnout currents are 100 nA constant current generators,

one sourcing current from AV_DDto AIN(+) and one sinking

current from AIN(–) to GND. The currents are switched to the

selected analog input pair. Both currents are either on or off,

depending on the burnout current enable (BO) bit in the

configuration register. These currents can be used to verify that

an external transducer is still operational before attempting to

take measurements on that channel. Once the burnout currents

are turned on, they flow in the external transducer circuit, and a

measurement of the input voltage on the analog input channel

can be taken. If the resultant voltage measured is full scale, the

user needs to verify why this is the case. A full-scale reading

could mean that the front-end sensor is open circuit. It could

also mean that the front-end sensor is overloaded and is

justified in outputting full scale, or the reference may be absent,

thus clamping the data to all 1s.

REFERENCE

The AD7785 has an embedded 1.17 V reference that can be

used to supply the ADC, or an external reference can be

applied. The embedded reference is a low noise, low drift

reference, the drift being 4 ppm/°C typically. For external

references, the ADC has a fully differential input capability for

the channel. The reference source for the AD7785 is selected

using the REFSEL bit in the configuration register. When the

internal reference is selected, it is internally connected to the

modulator. It is not available on the REFIN pins.

The common-mode range for these differential inputs is from

GND to AV_DD. The reference input is unbuffered; therefore,

excessive R-C source impedances introduce gain errors. The

reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V

nominal, but the AD7785 is functional with reference voltages

When reading all 1s from the output, the user needs to check

these three cases before making a judgment. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. For normal operation, these burnout currents are

turned off by writing a 0 to the BO bit in the configuration

register. The current sources work over the normal absolute

input voltage range specifications with buffers on.

from 0.1 V to AV_DD

.

In applications where the excitation (voltage or current) for the

transducer on the analog input also drives the reference voltage

for the part, the effect of the low frequency noise in the excitation

source is removed because the application is ratiometric. If the

AD7785 is used in a nonratiometric application, a low noise

reference should be used.

EXCITATION CURRENTS

The AD7785 also contains two matched, software-configurable,

constant current sources that can be programmed to equal

10 μA, 210 μA, or 1 mA. Both source currents from the AV_DD

are directed to either the IOUT1 or IOUT2 pin of the device.

These current sources are controlled via bits in the IO register.

The configuration bits enable the current sources, direct the

current sources to IOUT1 or IOUT2, and select the value of the

current. These current sources can be used to excite external

resistive bridge or RTD sensors.

Recommended 2.5 V reference voltage sources for the AD7785

include the ADR381 and ADR391, which are low noise, low

power references. Also, note that the reference inputs provide a

high impedance, dynamic load. Because the input impedance of

each reference input is dynamic, resistor/capacitor combinations

on these inputs can cause dc gain errors, depending on the output

impedance of the source that is driving the reference inputs.

Reference voltage sources like those recommended previously

(such as the ADR391) typically have low output impedances

and are, therefore, tolerant to having decoupling capacitors

on REFIN(+) without introducing gain errors in the system.

Deriving the reference input voltage across an external resistor

means that the reference input sees a significant external source

impedance. External decoupling on the REFIN pins is not

recommended in this type of circuit configuration.

BIAS VOLTAGE GENERATOR

A bias voltage generator is included on the AD7785. This biases

the negative terminal of the selected input channel to AV_DD/2.

It is useful in thermocouple applications, because the voltage

generated by the thermocouple must be biased about some dc

voltage if the gain is greater than 2. This is necessary because

the instrumentation amplifier requires headroom to ensure that

signals close to GND or AV_DDare converted accurately.

RESET

The circuitry and serial interface of the AD7785 can be reset

by writing 32 consecutive 1s to the device. This resets the logic,

the digital filter, and the analog modulator while all on-chip

registers are reset to their default values. A reset is automatically

performed on power-up. When a reset is initiated, the user

must allow a period of 500 μs before accessing any of the on-

chip registers. A reset is useful if the serial interface becomes

asynchronous due to noise on the SCLK line.

The bias voltage generator is controlled using the VBIAS1 and

VBIAS0 bits in conjunction with the boost bit in the configura-

tion register. The power-up time of the bias voltage generator is

dependent on the load capacitance. To accommodate higher

load capacitances, the AD7785 has a boost bit. When this bit is

set to 1, the current consumed by the bias voltage generator

increases, so that the power-up time is considerably reduced.

Figure 10 shows the power-up time when boost equals 0 and 1

for different load capacitances.

Rev. 0 | Page 26 of 32

AD7785

The ADC is placed in idle mode following a calibration. The

AV_DDMONITOR

measured full-scale coefficient is placed in the full-scale register

of the selected channel. Internal full-scale calibrations cannot be

performed when the gain equals 128. With this gain setting, a

system full-scale calibration can be performed. A full-scale

calibration is required each time the gain of a channel is

changed to minimize the full-scale error.

Along with converting external voltages, the ADC can be

used to monitor the voltage on the AV_DDpin. When Bit CH2 to

Bit CH0 equal 1, the voltage on the AV_DDpin is internally

attenuated by 6, and the resultant voltage is applied to the ∑-Δ

modulator using an internal 1.17 V reference for analog-to-

digital conversion. This is useful, because variations in the

power supply voltage can be monitored.

An internal full-scale calibration can be performed at specified

update rates only. For gains of 1, 2, and 4, an internal full-scale

calibration can be performed at any update rate. However, for

higher gains, internal full-scale calibrations can be performed

when the update rate is less than or equal to 16.7 Hz, 33.2 Hz,

and 50 Hz only. However, the full-scale error does not vary with

the update rate, so a calibration at one update rate is valid for all

update rates (assuming the gain or reference source is not

changed).

CALIBRATION

The AD7785 provides four calibration modes that can be

programmed via the mode bits in the mode register. These are

internal zero-scale calibration, internal full-scale calibration,

system zero-scale calibration, and system full-scale calibration,

which effectively reduces the offset error and full-scale error to

the order of the noise. After each conversion, the ADC con-

version result is scaled using the ADC calibration registers

before being written to the data register. The offset calibration

coefficient is subtracted from the result prior to multiplication

by the full-scale coefficient.

A system full-scale calibration takes 2 conversion cycles to

complete, irrespective of the gain setting. A system full-scale

calibration can be performed at all gains and all update rates.

If system offset calibrations are being performed along with

system full-scale calibrations, the offset calibration should be

performed before the system full-scale calibration is initiated.

To start a calibration, write the relevant value to the MD2 to

MD0 bits in the mode register. After the calibration is complete,

the contents of the corresponding calibration registers are

GROUNDING AND LAYOUT

RDY

updated, the

pin goes low (if

bit in the status register is set, the DOUT/

Because the analog inputs and reference inputs of the ADC are

differential, most of the voltages in the analog modulator are

common-mode voltages. The excellent common-mode reject-

ion of the part removes common-mode noise on these inputs.

The digital filter provides rejection of broadband noise on the

power supply, except at integer multiples of the modulator

sampling frequency. The digital filter also removes noise from

the analog and reference inputs, provided that these noise

sources do not saturate the analog modulator. As a result, the

AD7785 is more immune to noise interference than a conventional

high resolution converter. However, because the resolution of

the AD7785 is so high, and the noise levels from the AD7785 is

so low, care must be taken with regard to grounding and layout.

CS

is low), and the AD7785 reverts to idle mode.

During an internal zero-scale or full-scale calibration, the

respective zero input and full-scale input are automatically

connected internally to the ADC input pins. A system calibration,

however, expects the system zero-scale and system full-scale

voltages to be applied to the ADC pins before the calibration

mode is initiated. In this way, external ADC errors are removed.

From an operational point of view, a calibration should be

treated like another ADC conversion. A zero-scale calibration

(if required) should always be performed before a full-scale

RDY

calibration. System software should monitor the

bit in

pin to determine the

RDY

the status register or the DOUT/

end of calibration via a polling sequence or an interrupt-driven

routine.

The printed circuit board that houses the AD7785 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. A minimum etch

technique is generally best for ground planes because it provides

the best shielding.

Both an internal offset calibration and a system offset

calibration take two conversion cycles. An internal offset

calibration is not needed, as the ADC itself removes the offset

continuously.

It is recommended that the GND pins of the AD7785 be tied

to the AGND plane of the system. In any layout, it is important

to keep in mind the flow of currents in the system, ensuring

that the return paths for all currents are as close as possible to

the paths the currents took to reach their destinations. Avoid

forcing digital currents to flow through the AGND sections of

the layout.

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. When the gain equals 1, a calibration takes

2 conversion cycles to complete. For higher gains, 4 conversion

cycles are required to perform the full-scale calibration.

RDY

DOUT/

goes high when the calibration is initiated and

returns low when the calibration is complete.

Rev. 0 | Page 27 of 32

AD7785

The ground planes of the AD7785 should be allowed to run

under the device to prevent noise coupling. The power supply

lines to the AD7785 should use as wide a trace as possible to

provide low impedance paths and reduce the effects of glitches

on the power supply line. Fast switching signals such as clocks

should be shielded with digital ground to avoid radiating noise

to other sections of the board, and clock signals should never be

run near the analog inputs.

Good decoupling is important when using high resolution

ADCs. AV_DDshould be decoupled with 10 μF tantalum in

parallel with 0.1 μF capacitors to GND. DV_DDshould be

decoupled with 10 μF tantalum in parallel with 0.1 μF

capacitors to the system’s DGND plane, with the system’s

AGND to DGND connection being close to the AD7785.

To achieve the best from these decoupling components, they

should be placed as close as possible to the device, ideally right

up against the device. All logic chips should be decoupled with

0.1 μF ceramic capacitors to DGND.

Avoid crossover of digital and analog signals. Traces on oppo-

site sides of the board should run at right angles to each other.

This reduces the effects of feedthrough through the board.

A microstrip technique is by far the best, but it is not always

possible with a double-sided board. In this technique, the

component side of the board is dedicated to ground planes, and

signals are placed on the solder side.

Rev. 0 | Page 28 of 32

AD7785

APPLICATIONS INFORMATION

The AD7785 provides a low cost, high resolution analog-to-

digital function. Because the analog-to-digital function is

provided by a ∑-Δ architecture, the part is more immune to

noisy environments, making it ideal for use in sensor

measurement and industrial and process control applications.

decoupling capacitors can be placed on the front end to

eliminate any noise pickup that may be present in the

thermocouple leads. The AD7785 has a reduced common-

mode range with the in-amp enabled, so the bias voltage

generator provides a common-mode voltage so that the voltage

generated by the thermocouple is biased up to AV_DD/2.

TEMPERATURE MEASUREMENT USING A

THERMOCOUPLE

The cold junction compensation is performed using a thermis-

tor. The on-chip excitation current supplies the thermistor. In

addition, the reference voltage for the cold junction

measurement is derived from a precision resistor in series with

the thermistor. This allows a ratiometric measure-ment so that

variation of the excitation current has no effect on the

measurement (it is the ratio of the precision reference resistance

to the thermistor resistance that is measured).

Figure 20 outlines a connection from a thermocouple to the

AD7785. In a thermocouple application, the voltage generated

by the thermocouple is measured with respect to an absolute

reference, so the internal reference is used for this conversion.

The cold junction measurement uses a ratiometric configuration,

so the reference is provided externally.

Because the signal from the thermocouple is small, the AD7785

is operated with the in-amp enabled to amplify the signal from

the thermocouple. As the input channel is buffered, large

GND

AV

DD

V

BIAS

REFIN(+) REFIN(–)

THERMOCOUPLE

BAND GAP

REFERENCE

JUNCTION

R

AIN1(+)

AIN1(–)

GND

AV

DD

R

C

DOUT/RDY

SERIAL

MUX

AIN2(+)

AIN2(–)

DIN

INTERFACE

AND

Σ-Δ

ADC

BUF

IN-AMP

SCLK

CS

CONTROL

LOGIC

REFIN(+)

R

GND

AV

REF

DV

DD

INTERNAL

CLOCK

REFIN(–)

IOUT2

DD

AD7785

CLK

Figure 20. Thermocouple Measurement Using the AD7785

Rev. 0 | Page 29 of 32

AD7785

length), and IOUT1 and IOUT2 match, the error voltage across

RL2 equals the error voltage across RL1, and no error voltage

is developed between AIN1(+) and AIN1(–). The voltage is

developed twice across RL3. However, because this is a

common- mode voltage, it does not introduce errors. The

reference voltage for the AD7785 is also generated using one of

these matched current sources. It is developed using a precision

resistor and applied to the differential reference pins of the

ADC. This scheme ensures that the analog input voltage span

remains ratiometric to the reference voltage. Any errors in the

analog input voltage due to the temperature drift of the excita-

tion current are compensated by the variation of the reference

voltage.

TEMPERATURE MEASUREMENT USING AN RTD

To optimize a 3-wire RTD configuration, two identically

matched current sources are required. The AD7785, which

contains two well-matched current sources, is ideally suited to

these applications. One possible 3-wire configuration is shown

in Figure 21. In this 3-wire configuration, the lead resistances

result in errors if only one current is used, as the excitation

current flows through RL1, developing a voltage error between

AIN1(+) and AIN1(–). In the scheme outlined, the second RTD

current source is used to compensate for the error introduced

by the excitation current flowing through RL1. The second RTD

current flows through RL2. Assuming RL1 and RL2 are equal

(the leads would normally be of the same material and of equal

GND

AV

DD

REFIN(+) REFIN(–)

GND

BAND GAP

REFERENCE

IOUT1

AV

DD

RL1

RTD

AIN1(+)

DOUT/RDY

SERIAL

AIN1(–)

IOUT2

DIN

INTERFACE

AND

Σ-Δ

RL2

RL3

BUF

IN-AMP

ADC

SCLK

CS

CONTROL

LOGIC

REFIN(+)

REFIN(–)

GND

DV

R

DD

REF

INTERNAL

AD7785

CLOCK

CLK

Figure 21. RTD Application Using the AD7785

Rev. 0 | Page 30 of 32

AD7785

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

–40°C to +10ꢀ°C

Package Description

16-Lead TSSOP

Package Option

AD778ꢀBRUZ¹

RU-16

AD778ꢀBRUZ-REEL¹

EVAL-AD778ꢀEBZ¹

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 31 of 32

AD7785

NOTES

registered trademarks are the property of their respective owners.

D06721-0-4/07(0)

Rev. 0 | Page 32 of 32


型号：	AD7785
厂家：	ADI
描述：	3-Channel, Low Noise, Low Power, 20-Bit ⒉-ツ ADC with On-Chip In-Amp and Reference 3通道，低噪声，低功耗， 20位⒉-ツADC，具有片内仪表放大器和基准仪表放大器
文件：	总32页 (文件大小：626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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