AD7795_技术文档

6-Channel, Low Noise, Low Power, 24-/16-Bit

∑-Δ ADC with On-Chip In-Amp and Reference

AD7794/AD7795

Industrial process control

Instrumentation

Blood analysis

FEATURES

Up to 23 effective bits

RMS noise: 40 nV @ 4.17 Hz, 85 nV @ 16.7 Hz

Current: 400 μA typical

Smart transmitters

Liquid/gas chromatography

6-digit DVM

Power-down: 1 μA maximum

Low noise, programmable gain, instrumentation amp

Band gap reference with 4 ppm/°C drift typical

Update rate: 4.17 Hz to 470 Hz

Six differential analog inputs

Internal clock oscillator

Simultaneous 50 Hz/60 Hz rejection

Reference detect

Programmable current sources

On-chip bias voltage generator

Burnout currents

Low-side power switch

Power supply: 2.7 V to 5.25 V

Temperature range:

B grade: –40°C to +105°C

C grade: –40°C to +125°C

GENERAL DESCRIPTION

The AD7794/AD7795 are low power, low noise, complete

analog front ends for high precision measurement applications.

They contain a low noise, 24-/16-bit ∑-Δ ADC with six

differential inputs. The on-chip low noise instrumentation

amplifier means that signals of small amplitude can be

interfaced directly to the ADC.

Each device contains a precision, low noise, low drift internal

band gap reference, and can also accept up to two external

differential references. Other on-chip features include

programmable excitation current sources, burnout currents,

and a bias voltage generator that is used to set the common-

mode voltage of a channel to AV_DD/2. The low-side power

switch can be used to power down bridge sensors between

conversions, minimizing the system’s power consumption. The

AD7794/AD7795 can operate with either an internal clock or

an external clock. The output data rate from each part can vary

from 4.17 Hz to 470 Hz.

Independent interface power supply

24-lead TSSOP

3-wire serial interface

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

Both parts operate with a power supply from 2.7 V to 5.25 V.

The B-grade parts (AD7794 and AD7795) are specified for a

temperature range of −40°C to +105°C while the C-grade part

(AD7794) is specified for a temperature range of −40°C to

+125°C. They consume a current of 400 μA typical and are

housed in a 24-lead TSSOP.

APPLICATIONS

Temperature measurement

Pressure measurement

Weigh scales

Strain gage transducers

Gas analysis

FUNCTIONAL BLOCK DIAGRAM

AIN4(+)/REFIN2(+) REFIN1(+) AIN4(–)/REFIN2(–) REFIN1(–)

GND

AV

DD

REFERENCE

DETECT

V

BIAS

BAND GAP

REFERENCE

V

DD

GND

AIN1(+)

AIN1(–)

DOUT/RDY

DIN

SERIAL

INTERFACE

AND

Σ-Δ

ADC

AIN2(+)

BUF

IN-AMP

SCLK

CS

AIN2(–)

LOGIC

CONTROL

AIN3(+)

MUX

AIN3(–)

GND

V

AIN5(+)/IOUT2

AIN5(–)/IOUT1

AIN6(+)/P1

AIN6(–)/P2

TEMP

SENSOR

INTERNAL

CLOCK

DV

DD

AD7794/AD7795

AD7794: 24-BIT ADC

AD7795: 16-BIT ADC

DD

PSW

GND

CLK

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

IMPORTANT LINKS for the AD7794_7795*

Last content update 12/19/2013 07:19 pm

SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES

DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE

Sigma-Delta ADC Tutorial

Find Similar Products By Operating Parameters

Sigma Delta ADCs (Less than 15 kSPS)

Digital Filter Model Spreadsheets

DOCUMENTATION

SUGGESTED COMPANION PRODUCTS

Recommended High Accuracy, Precision References - 2.5V

AN-968: Current Sources: Options and Circuits

AN-311: How to Reliably Protect CMOS Circuits Against Power Supply

Overvoltaging

For applications requiring the lowest noise performance and

low power output trim adjust, we recommend the ADR441.

For high output current applications, we recommend the

ADR431.

For wide supply applications, we recommend the AD780.

For cost sensitive applications, we suggest the ADR381,

AD1582, or the ADR391.

(For the AD7795) For low noise and and low power

applications, we recommend the ADR381 or ADR391.

AN-880: ADC Requirements for Temperature Measurement Systems

AN-607: Selecting a Low Bandwidth Sigma-Delta ADC

AN-615: Peak-to-Peak Resolution Versus Effective Resolution

AN-101: Cross Plot Generator Allows Quick A/D Converter Evaluation

AN-397: Electrically Induced Damage to Standard Linear Integrated

Circuits

Recommended Digital Isolators for the AD7794 and AD7795

AN-347: Shielding and Guarding

AN-202: An IC Amplifier User‘s Guide to Decoupling, Grounding, and

For process control applications, we recommend the

ADuM1400 and the ADuM1200 icoupler.

Making Things Go Right for a Change

For cost sensitive designs, we recommend the ADuM7440,

ADuM7441, or ADuM7442.

AN-388: Using Sigma-Delta Converters-Part 1

AN-389: Using Sigma-Delta Converters-Part 2

AN-283: Sigma-Delta ADCs and DACs

For digital isolators with integrated isolated power, we suggest

the ADuM5401, ADuM5402, or the ADuM5403.

For isolated USB designs in healthcare and industrial control,

we recommend the ADuM4160.

MS-2210: Designing Power Supplies for High Speed ADC

Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter

ICs for Programmable Logic Control and Distributed Control Systems

Healthcare ICs

FAQs for the AD779x family.

DESIGN SUPPORT

Submit your support request here:

Linear and Data Converters

Embedded Processing and DSP

PRODUCT RECOMMENDATIONS & REFERENCE DESIGNS

CN-0325: (FOR THE AD7795) PLC/DCS Universal Analog Input Using

Either 4 or 6 Pin Terminal Block

Telephone our Customer Interaction Centers toll free:

Americas:

Europe:

China:

1-800-262-5643

00800-266-822-82

4006-100-006

1800-419-0108

8-800-555-45-90

India:

Russia:

EVALUATION KITS & SYMBOLS & FOOTPRINTS

Quality and Reliability

Lead(Pb)-Free Data

View the Evaluation Boards and Kits page for the AD7794

View the Evaluation Boards and Kits page for the AD7795

Symbols and Footprints for the AD7794

Symbols and Footprints for the AD7795

SAMPLE & BUY

AD7794

AD7795

DESIGN COLLABORATION COMMUNITY

View Price & Packaging

Request Evaluation Board

Request Samples Check Inventory & Purchase

Collaborate Online with the ADI support team and other designers

about select ADI products.

Find Local Distributors

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.

Note: Dynamic changes to the content on this page (labeled 'Important Links') does not

constitute a change to the revision number of the product data sheet.

This content may be frequently modified.

AD7794/AD7795

TABLE OF CONTENTS

Features .............................................................................................. 1

Full-Scale Register...................................................................... 25

ADC Circuit Information.............................................................. 26

Overview ..................................................................................... 26

Digital Interface.......................................................................... 28

Circuit Description......................................................................... 31

Analog Input Channel ............................................................... 31

Instrumentation Amplifier........................................................ 31

Bipolar/Unipolar Configuration .............................................. 31

Data Output Coding .................................................................. 32

Burnout Currents ....................................................................... 32

Excitation Currents.................................................................... 32

Bias Voltage Generator .............................................................. 32

Reference ..................................................................................... 32

Reference Detect......................................................................... 33

Reset............................................................................................. 33

AV_DDMonitor ............................................................................. 33

Calibration................................................................................... 33

Grounding and Layout .............................................................. 34

Applications Information.............................................................. 35

Flowmeter.................................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

RMS Noise and Resolution Specifications .................................. 13

Chop Enabled.............................................................................. 13

Chop Disabled ............................................................................ 15

Typical Performance Characteristics ........................................... 16

On-Chip Registers.......................................................................... 17

Communications Register......................................................... 17

Status Register............................................................................. 18

Mode Register ............................................................................. 19

Configuration Register .............................................................. 22

Data Register............................................................................... 24

ID Register................................................................................... 24

IO Register................................................................................... 24

Offset Register............................................................................. 25

REVISION HISTORY

3/07—Rev. C to Rev. D

4/05—Rev. 0 to Rev. A

Changes to Specifications Endnote 1............................................. 7

Changes to Status Register Section .............................................. 18

Changes to Ordering Guide .......................................................... 36

Changes to Absolute Maximum Ratings........................................9

Changes to Figure 21...................................................................... 25

Changes to Data Output Coding Section.................................... 28

Changes to Calibration Section.................................................... 30

Changes to Ordering Guide.......................................................... 33

10/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Added AD7794 C-Grade Part...........................................Universal

Changes to Specifications................................................................ 3

Changes to Ordering Guide .......................................................... 36

10/04—Revision 0: Initial Version

6/06—Rev. A to Rev. B

Added AD7795 ...................................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to RMS Noise and Resolution

Specifications Section..................................................................... 12

Changes to Table 19........................................................................ 20

Changes to ADC Circuit Information Section........................... 25

Changes to Ordering Guide .......................................................... 35

Rev. D | Page 2 of 36

AD7794/AD7795

SPECIFICATIONS

AV_DD= 2.7 V to 5.25 V, DV_DD= 2.7 V to 5.25 V, GND = 0 V, all specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter¹

AD7794/AD7795

Unit

Test Conditions/Comments

Settling time = 2/output update rate

f_ADC≤ 242 Hz

CHOP ENABLED

Output Update Rate

No Missing Codes²

AD7794

4.17 to 470

Hz nom

24

16

Bits min

AD7795

Resolution

RMS Noise and Update Rates

Integral Nonlinearity

See the RMS Noise and Resolution Specifications section

15

ppm of FSR

max

μV typ

nV/°C typ

μV typ

Offset Error³

1

10

1

Offset Error Drift vs. Temperature⁴

Full-Scale Error^{3, 5}

Gain Drift vs. Temperature⁴

ppm/°C typ Gain = 1 to 16, external reference

ppm/°C typ Gain = 32 to 128, external reference

3

Power Supply Rejection

ANALOG INPUTS

100

dB min

AIN = 1 V/gain, gain ≥ 4, external reference

Differential Input Voltage Ranges

VREF/gain

V nom

V_REF= REFIN(+) − REFIN(−), or internal reference,

gain = 1 to 128

Absolute AIN Voltage Limits²

Unbuffered Mode

GND − 30 mV

AV_DD+ 30 mV

GND + 100 mV

AV_DD− 100 mV

GND + 300 mV

AV_DD− 1.1

V min

V max

V min

V max

V min

V max

V min

Gain = 1 or 2

Buffered Mode

In-Amp Active

Gain = 1 or 2

Gain = 4 to 128

Common-Mode Voltage, V_CM

Analog Input Current

0.5

VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128

Buffered Mode or In-Amp

Active

Average Input Current²

AD7794B/AD7795B

1

250

1

3

2

nA max

pA max

nA max

pA/°C typ

Gain = 1 or 2, update rate < 100 Hz

Gain = 4 to 128, update rate < 100 Hz

AIN6(+)/AIN6(−)

Gain = 1 or 2, update rate < 100 Hz

Gain = 4 to 128, update rate < 100 Hz

AIN6(+)/AIN6(−)

AD7794C

3

2

Average Input Current Drift

Unbuffered Mode

Average Input Current

Average Input Current Drift

Normal Mode Rejection^{2, 6}

Internal Clock

Gain = 1 or 2

Input current varies with input voltage

400

50

nA/V typ

pA/V/°C typ

@ 50 Hz, 60 Hz

@ 50 Hz

@ 60 Hz

65

80

90

dB min

80 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010

90 dB typ, 50 1 Hz, FS[3:0] = 1001

100 dB typ, 60 1 Hz, FS[3:0] = 1000

External Clock

@ 50 Hz, 60 Hz

@ 50 Hz

@ 60 Hz

80

94

90

dB min

90 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010

100 dB typ, 50 1 Hz, FS[3:0] = 1001

100 dB typ, 60 1 Hz, FS[3:0] = 1000

Rev. D | Page 3 of 36

AD7794/AD7795

Parameter¹

AD7794/AD7795

Unit

Test Conditions/Comments

Common-Mode Rejection

AD7794B/AD7795B

@ DC

@ 50 Hz, 60 Hz²

AD7794C

100

dB min

AIN = 1 V/gain, gain ≥ 4

50 1 Hz, 60 1 Hz, FS[3:0] = 1010

50 1 Hz, FS[3:0] = 1001; 60 1 Hz, FS[3:0] = 1000

@ DC

97

dB min

AIN = 1 V/gain, gain ≥ 4

50 1 Hz, 60 1 Hz, FS[3:0] = 1010

50 1 Hz, FS[3:0] = 1001; 60 1 Hz, FS[3:0] = 1000

@ 50 Hz, 60 Hz²

CHOP DISABLED

Output Update Rate

No Missing Codes²

AD7794

4.17 to 470

Hz nom

Settling time = 1/output update rate

f_ADC≤ 123 Hz

24

16

Bits min

AD7795

Resolution

RMS Noise and Update Rates

Integral Nonlinearity

See the RMS Noise and Resolution Specifications section

15

ppm of FSR

max

μV typ

nV/°C typ

μV typ

Offset Error³

Offset Error Drift vs. Temperature⁴

100/gain

10

1

Without calibration

Gain = 1 to 16

Gain = 32 to 128

Full-Scale Error^{3, 5}

Gain Drift vs. Temperature⁴

ppm/°C typ Gain = 1 to 16, external reference

ppm/°C typ Gain = 32 to 128, external reference

3

Power Supply Rejection

ANALOG INPUTS

100

dB typ

AIN = 1 V/gain, gain ≥ 4, external reference

Differential Input Voltage Ranges

V_REF/gain

V nom

V_REF= REFIN(+) − REFIN(−), or internal reference,

gain = 1 to 128

Absolute AIN Voltage Limits²

Unbuffered Mode

GND − 30 mV

AV_DD+ 30 mV

GND + 100 mV

AV_DD− 100 mV

GND + 300 mV

AV_DD− 1.1

V min

V max

V min

V max

V min

V max

V min

Gain = 1 or 2

Buffered Mode

Gain = 1 or 2

In-Amp Active

Gain = 4 to 128

Common-Mode Voltage, V_CM

0.2 + (gain/2 × (AIN(+) −

AIN(−)))

AMP − CM = 1, VCM = (AIN(+) + AIN(–))/2, gain = 4 to 128

AV_DD− 0.2 − (gain/2 ×

(AIN(+) − AIN(−)))

V max

Analog Input Current

Buffered Mode or In-Amp

Active

Average Input Current²

AD7794B/AD7795B

1

250

1

3

2

nA max

pA max

nA max

pA/°C typ

Gain = 1 or 2

Gain = 4 to 128

AIN6(+)/AIN6(−)

Gain = 1 or 2

Gain = 4 to 128

AIN6(+)/AIN6(−)

AD7794C

3

2

Average Input Current Drift

Unbuffered Mode

Gain = 1 or 2

Average Input Current

Average Input Current Drift

400

50

nA/V typ

pA/V/°C typ

Input current varies with input voltage

Rev. D | Page 4 of 36

AD7794/AD7795

Parameter¹

AD7794/AD7795

Unit

Test Conditions/Comments

Normal Mode Rejection^{2, 6}

Internal Clock

@ 50 Hz, 60 Hz

@ 50 Hz

60

78

86

dB min

70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010

90 dB typ, 50 1 Hz, FS[3:0] = 1001

100 dB typ, 60 1 Hz, FS[3:0] = 1000

@ 60 Hz

External Clock

@ 50 Hz, 60 Hz

@ 50 Hz

60

94

90

dB min

70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010

100 dB typ, 50 1 Hz, FS[3:0] = 1001

100 dB typ, 60 1 Hz, FS[3:0] = 1000

@ 60 Hz

Common-Mode Rejection

AD7794B/AD7795B

@ DC

@ 50 Hz, 60 Hz²

AD7794C

100

dB min

AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1

50 1 Hz, 60 1 Hz, FS[3:0] = 1010

50 1 Hz, FS[3:0] = 1001; 60 1 Hz, FS[3:0] = 1000

@ DC

97

dB min

AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1

50 1 Hz, 60 1 Hz, FS[3:0] = 1010

50 1 Hz, FS[3:0] = 1001; 60 1 Hz, FS[3:0] = 1000

@ 50 Hz, 60 Hz²

CHOP ENABLED or DISABLED

REFERENCE INPUT

Internal Reference

Internal Reference Initial

Accuracy

1.17 0.01ꢀ

V min/max

AV_DD= 4 V, T_A= 25°C

Internal Reference Drift²

4

15

85

ppm/°C typ

ppm/°C max

dB typ

Power Supply Rejection

External Reference

External REFIN Voltage

Reference Voltage Range²

2.5

0.1

AV_DD

V nom

V min

V max

REFIN = REFIN(+) − REFIN(−)

When V_REF= AV_DD, the differential input must be

limited to 0.9 × V_REF/gain if the in-amp is active

Absolute REFIN Voltage Limits²

GND − 30 mV

AV_DD+ 30 mV

400

V min

V max

nA/V typ

Average Reference Input

Current

Average Reference Input

Current Drift

0.03

nA/V/°C typ

Normal Mode Rejection²

Common-Mode Rejection

Reference Detect Levels

Same as for analog inputs

100

0.3

0.65

dB typ

V min

V max

NOXREF bit active if V_REF< 0.3 V

EXCITATION CURRENT SOURCES

(IEXC1 and IEXC2)

Output Current

Initial Tolerance at 25°C

Drift

Current Matching

Drift Matching

Line Regulation (AV_DD)

Load Regulation

10/210/1000

5

200

0.5

50

2

μA nom

ꢀ typ

ppm/°C typ

ꢀ typ

ppm/°C typ

ꢀ/V typ

V max

Matching between IEXC1 and IEXC2, V_OUT= 0 V

AV_DD= 5 V 5ꢀ

0.2

Output Compliance

AV_DD− 0.65

AV_DD− 1.1

GND − 30 mV

Current sources programmed to 10 μA or 210 μA

Current sources programmed to 1 mA

V max

V min

Rev. D | Page 5 of 36

AD7794/AD7795

Parameter¹

AD7794/AD7795

Unit

Test Conditions/Comments

BIAS VOLTAGE GENERATOR

V_BIAS

AV_DD/2

V nom

V_BIASGenerator Start-Up Time

ms/nF typ

Dependent on the capacitance connected to AIN;

See Figure 11

TEMPERATURE SENSOR

Accuracy

2

°C typ

Applies if user calibrates the temperature sensor

Sensitivity

0.81

mV/°C typ

LOW-SIDE POWER SWITCH

R_ON

7

9

30

Ω max

mA max

AV_DD= 5 V

AV_DD= 3 V

Continuous current

Allowable Current²

DIGITAL OUTPUTS (P1 and P2)

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

INTERNAL/EXTERNAL CLOCK

Internal Clock

AV_DD− 0.6

0.4

4

V min

V max

V min

V max

AV_DD= 3 V, I_SOURCE= 100 μA

AV_DD= 3 V, I_SINK= 100 μA

AV_DD= 5 V, I_SOURCE= 200 μA

AV_DD= 5 V, I_SINK= 800 μA

0.4

Frequency²

64 3ꢀ

50:50

kHz

min/max

ꢀ typ

Duty Cycle

External Clock

Frequency

64

kHz nom

ꢀ typ

A 128 kHz external clock can be used if the divide-by-2

function is used (Bit CLK1 = CLK0 = 1)

Applies for external 64 kHz clock, a 128 kHz clock can

have a less stringent duty cycle

Duty Cycle

45:55 to 55:45

LOGIC INPUTS

CS²

V_INL, Input Low Voltage

0.8

0.4

2.0

V max

V min

DV_DD= 5 V

DV_DD= 3 V

DV_DD= 3 V or 5 V

V_INH, Input High Voltage

SCLK (Schmitt-Triggered Input),

CLK, and DIN²

AD7794B/AD7795B

V_T(+)

V_T(−)

V_T(+) to V_T(−)

V_T(+)

V_T(−)

V_T(+) to V_T(−)

AD7794C

V_T(+)

V_T(−)

V_T(+) to V_T(−)

V_T(+)

1.4/2

V min/max

DV_DD= 5 V

DV_DD= 3 V

0.8/1.7

0.1/0.17

0.9/2

0.4/1.35

0.06/0.13

1.35/2.05

0.8/1.9

0.1/0.19

0.9/2

0.4/1.35

0.06/0.15

10

V min/max

μA max

DV_DD= 5 V

DV_DD= 3 V

V_IN= DV_DDor GND

All digital inputs

V_T(−)

V_T(+) to V_T(−)

Input Currents

Input Capacitance

10

pF typ

Rev. D | Page 6 of 36

AD7794/AD7795

Parameter¹

AD7794/AD7795

Unit

Test Conditions/Comments

LOGIC OUTPUT (INCLUDING CLK)

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

V_OH, Output High Voltage²

V_OL, Output Low Voltage²

Floating-State Leakage Current

DV_DD− 0.6

0.4

4

0.4

10

V min

V max

V min

V max

μA max

pF typ

DV_DD= 3 V, I_SOURCE= 100 μA

DV_DD= 3 V, I_SINK= 100 μA

DV_DD= 5 V, I_SOURCE= 200 μA

DV_DD= 5 V, I_SINK= 1.6 mA (DOUT/RDY), 800 μA (CLK)

Floating-State Output Capacitance 10

Data Output Coding

SYSTEM CALIBRATION²

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

Offset binary

1.05 × FS

−1.05 × FS

0.8 × FS

V max

V min

V max

2.1 × FS

POWER REQUIREMENTS⁷

Power Supply Voltage

AV_DDto GND

2.7/5.25

V min/max

DV_DDto GND

Power Supply Currents

I_DDCurrent

140

185

400

500

μA max

110 μA typ @ AV_DD= 3 V, 125 μA typ @ AV_DD= 5 V,

unbuffered mode, external reference

130 μA typ @ AV_DD= 3 V, 165 μA typ @ AV_DD= 5 V,

buffered mode, gain = 1 or 2, external reference

300 μA typ @ AV_DD= 3 V, 350 μA typ @ AV_DD= 5 V,

gain = 4 to 128, external reference

400 μA typ @ AV_DD= 3 V, 450 μA typ @ AV_DD= 5 V,

gain = 4 to 128, internal reference

I_DD(Power-Down Mode)

1

2

μA max

AD7794B, AD7795B

AD7794C

¹Temperature range: B Grade: −40°C to +105°C, C Grade: −40°C to +125°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-

mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AV_DD– 1.6 V

typically. In addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. When this voltage is exceeded, the INL, for

example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute

voltage on the analog input pins needs to be below AVDD − 1.6 V.

²Specification is not production tested but is supported by characterization data at initial product release.

³Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

⁴Recalibration at any temperature removes these errors.

⁵Full-scale error applies to both positive and negative full-scale, and applies at the factory calibration conditions (AV_DD= 4 V, gain = 1, T_A= 25°C).

⁶FS[3:0] are the four bits used in the mode register to select the output word rate.

⁷Digital inputs equal to DV_DDor GND with excitation currents and bias voltage generator disabled.

Rev. D | Page 7 of 36

AD7794/AD7795

TIMING CHARACTERISTICS

AV_DD= 2.7 V to 5.25 V, DV_DD= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV_DD, unless otherwise noted.

Table 2.

Parameter^{1, 2}

Limit at T_MIN, T_MAX(B Version)

Unit

Conditions/Comments

SCLK high pulse width

SCLK low pulse width

t₃

t₄

100

ns min

Read Operation

t₁

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

CS falling edge to DOUT/RDY active time

DV_DD= 4.75 V to 5.25 V

DV_DD= 2.7 V to 3.6 V

SCLK active edge to data valid delay⁴

DV_DD= 4.75 V to 5.25 V

DV_DD= 2.7 V to 3.6 V

Bus relinquish time after CS inactive edge

60

80

0

60

80

10

80

0

3

t₂

5, 6

t₅

t₆

SCLK inactive edge to CS inactive edge

SCLK inactive edge to DOUT/RDY high

t₇

10

Write Operation

t₈

0

ns min

CS falling edge to SCLK active edge setup time⁴

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

30

25

0

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10ꢀ to 90ꢀ of DV_DD) and timed from a voltage level of 1.6 V.

²See Figure 3 and Figure 4.

³These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁴SCLK active edge is falling edge of SCLK.

⁵These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and, therefore, are independent of external bus loading capacitances.

⁶RDY

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

is high,

although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read

only once.

I

(1.6mA WITH DV = 5V,

DD

SINK

100µA WITH DV

= 3V)

DD

TO

OUTPUT

1.6V

50pF

I

(200µA WITH DV = 5V,

DD

SOURCE

100µA WITH DV

= 3V)

DD

Figure 2. Load Circuit for Timing Characterization

Rev. D | Page 8 of 36

AD7794/AD7795

TIMING DIAGRAMS

CS (I)

t₆

t₁

t₅

MSB

LSB

t₇

DOUT/RDY (O)

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 4. Write Cycle Timing Diagram

Rev. D | Page 9 of 36

AD7794/AD7795

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

AV_DDto GND

−0.3 V to +7 V

DV_DDto GND

−0.3 V to +7 V

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

AIN/Digital Input Current

Operating Temperature Range

B Grade

−0.3 V to AV_DD+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

10 mA

ESD CAUTION

−40°C to +105°C

−40°C to +125°C

−65°C to +150°C

150°C

C Grade

Storage Temperature Range

Maximum Junction Temperature

TSSOP

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

97.9°C/W

14°C/W

215°C

220°C

Rev. D | Page 10 of 36

AD7794/AD7795

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

1

2

3

4

5

6

7

8

9

24 DIN

CLK

23 DOUT/RDY

CS

22 DV

21 AV

DD

NC

AD7794/

AD7795

TOP VIEW

(Not to Scale)

AIN6(+)/P1

AIN6(–)/P2

AIN1(+)

AIN1(–)

AIN2(+)

20 GND

19 PSW

18 AIN4(–)/REFIN2(–)

17 AIN4(+)/REFIN2(+)

16 AIN5(–)/IOUT1

15 AIN5(+)/IOUT2

14 REFIN1(–)

AIN2(–) 10

AIN3(+) 11

AIN3(–) 12

13 REFIN1(+)

NC = NO CONNECT

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous

clock with the information being transmitted to or from the ADC in smaller batches of data.

2

3

CLK

CS

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can

be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a

common clock, allowing simultaneous conversions to be performed.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

systems with more than one device on the serial bus or as a frame synchronization signal in communicating

with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.

4

5

NC

AIN6(+)/P1

No Connect.

Analog Input/Digital Output Pin. AIN6(+) is the positive terminal of the differential analog input pair,

AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AV_DDand GND.

6

AIN6(−)/P2

Analog Input/Digital Output Pin. AIN6(−) is the negative terminal of the differential analog input pair,

AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AV_DDand GND.

7

8

9

10

11

12

13

AIN1(+)

AIN1(−)

AIN2(+)

AIN2(−)

AIN3(+)

AIN3(−)

REFIN1(+)

Analog Input. AIN1(+) is the positive terminal of the differential analog input pair, AIN1(+)/AIN1(−).

Analog Input. AIN1(−) is the negative terminal of the differential analog input pair, AIN1(+)/AIN1(−).

Analog Input. AIN2(+) is the positive terminal of the differential analog input pair, AIN2(+)/AIN2(−).

Analog Input. AIN2(−) is the negative terminal of the differential analog input pair, AIN2(+)/AIN2(−).

Analog Input. AIN3(+) is the positive terminal of the differential analog input pair, AIN3(+)/AIN3(−).

Analog Input. AIN3(−) is the negative terminal of the differential analog input pair, AIN3(+)/AIN3(−).

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)

can lie anywhere between AV_DDand GND + 0.1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is

2.5 V, but the part functions with a reference from 0.1 V to AV_DD.

14

15

REFIN1(−)

AIN5(+)/IOUT2

Negative Reference Input. This reference input can lie anywhere between GND and AV_DD− 0.1 V.

Analog Input/Output of Internal Excitation Current Source. AIN5(+) is the positive terminal of the differential

analog input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at

this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be

switched to this output.

16

17

AIN5(−)/IOUT1

Analog Input/Output of Internal Excitation Current Source. AIN5(−) is the negative terminal of the

differential analog input pair, AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be

made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either

IEXC1 or IEXC2 can be switched to this output.

AIN4(+)/REFIN2(+) Analog Input/Positive Reference Input. AIN4(+) is the positive terminal of the differential analog input pair

AIN4(+)/AIN4(−). This pin also functions as a positive reference input for REFIN2. REFIN2(+) can lie anywhere

between AV_DDand GND + 0.1 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the part

functions with a reference from 0.1 V to AV_DD.

Rev. D | Page 11 of 36

AD7794/AD7795

Pin No. Mnemonic

Description

18

AIN4(−)/REFIN2(−) Analog Input/Negative Reference Input. AIN4(−) is the negative terminal of the differential analog input pair

AIN4(+)/AIN4(−). This pin also functions as the negative reference input for REFIN2. This reference input can

lie anywhere between GND and AV_DD− 0.1 V.

19

20

21

22

PSW

GND

AV_DD

DV_DD

Low-Side Power Switch to GND.

Ground Reference Point.

Supply Voltage, 2.7 V to 5.25 V.

Serial Interface Supply Voltage, 2.7 V to 5.25 V. DV_DDis independent of AV_DD. Therefore, the serial interface

operates at 3 V with AV_DDat 5 V or vice versa.

23

24

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output

pin to access the output shift register of the ADC. The output shift register can contain data from any of the

on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate

the completion of a conversion. If the data is not read after the conversion, the pin goes high before the

next update occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating

that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With

CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is

valid on the SCLK rising edge.

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control

registers within the ADC with the register selection bits of the communications register identifying the

appropriate register.

Rev. D | Page 12 of 36

AD7794/AD7795

RMS NOISE AND RESOLUTION SPECIFICATIONS

CHOP ENABLED

External Reference

The AD7794/AD7795 can be operated with chop enabled or

chop disabled, allowing the ADC to be optimized for switching

time or drift performance. With chop enabled, the settling time

is two times the conversion time. However, the offset is

continuously removed by the ADC leading to low offset and low

offset drift. With chop disabled, the allowable update rates are

the same as in chop enable mode. However, the settling time

now equals the conversion time. With chop disabled, the offset

is not removed by the ADC, so periodic offset calibrations can

be required to remove offset due to drift.

Table 5 shows the AD7794/AD7795 rms noise for some update

rates and gain settings. The numbers given are for the bipolar

input range with an external 2.5 V reference. These numbers are

typical and are generated with a differential input voltage of 0 V.

Table 6 and Table 7 show the effective resolution, while the

output peak-to-peak (p-p) resolution is listed in brackets. It is

important to note that the effective resolution is calculated

using the rms noise, while the p-p resolution is calculated based

on peak-to-peak noise. The p-p resolution represents the

resolution for which there is no code flicker. These numbers are

typical and are rounded to the nearest LSB.

Table 5. RMS Noise (μV) vs. Gain and Output Update Rate Using an External 2.5 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

0.22

0.26

0.36

0.5

0.58

1

1.96

1.79

Gain of 16

Gain of 32

0.065

0.078

0.11

0.17

0.2

0.32

0.45

0.63

Gain of 64

Gain of 128

0.041

0.055

0.086

0.118

0.144

0.283

0.397

0.593

4.17

8.33

16.7

33.2

62

123

242

470

0.64

1.04

1.55

2.3

2.95

4.89

11.76

11.33

0.6

0.29

0.38

0.54

0.74

0.92

1.49

4.02

3.07

0.1

0.13

0.18

0.23

0.29

0.48

0.88

0.99

0.039

0.057

0.087

0.124

0.153

0.265

0.379

0.568

0.96

1.45

2.13

2.85

4.74

9.5

9.44

Table 6.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an External 2.5 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

23 (20.5)

22 (19.5)

21.5 (19)

21 (18.5)

20.5 (18)

20 (17.5)

18.5 (16)

Gain of 2

22 (19.5)

21.5 (19)

20.5 (18)

20 (17.5)

19.5 (17)

19 (16.5)

18 (15.5)

Gain of 4

22 (19.5)

21.5 (19)

21 (18.5)

20.5 (18)

19.5 (17)

18 (15.5)

18.5 (16)

Gain of 8

21.5 (19)

21 (18.5)

20.5 (18)

20 (17.5)

19 (16.5)

18 (15.5)

18.5 (16)

Gain of 16

21.5 (19)

21 (18.5)

20.5 (18)

20 (17.5)

19.5 (17)

18.5 (16)

18 (15.5)

Gain of 32

21 (18.5)

20.5 (18)

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

Gain of 64

21 (18.5)

20.5 (18)

20 (17.5)

19 (16.5)

18 (15.5)

17.5 (15)

17 (14.5)

Gain of 128

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

16.5 (14)

16 (13.5)

4.17

8.33

16.7

33.2

62

123

242

470

Table 7.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an External 2.5 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

16 (16)

Gain of 2

16 (16)

16 (15.5)

Gain of 4

16 (16)

16 (15.5)

16 (16)

Gain of 8

16 (16)

16 (15.5)

16 (16)

Gain of 16

16 (16)

16 (15.5)

Gain of 32

16 (16)

16 (15.5)

Gain of 64

Gain of 128

4.17

8.33

16.7

33.2

62

123

242

470

16 (16)

16 (15.5)

16 (15)

16 (16)

16 (15.5)

16 (14.5)

16 (14)

16 (14.5)

16 (13.5)

Rev. D | Page 13 of 36

AD7794/AD7795

Internal Reference

It is important to note that the effective resolution is calculated

using the rms noise while the p-p resolution is calculated based

on peak-to-peak noise. The p-p resolution represents the

resolution for which there is no code flicker. These numbers are

typical and rounded to the nearest LSB.

Table 8 shows the AD7794/AD7795 rms noise for some of the

update rates and gain settings. The numbers given are for the

bipolar input range with the internal 1.17 V reference. These

numbers are typical and are generated with a differential input

voltage of 0 V. Table 9 and Table 10 show the effective resolution

while the output peak-to-peak (p-p) resolution is listed in brackets.

Table 8. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

0.065

0.078

0.11

0.17

0.2

0.32

0.45

0.63

Gain of 64

Gain of 128

0.039

0.059

0.088

0.12

0.15

0.26

0.34

0.49

4.17

8.33

16.7

33.2

62

123

242

470

0.81

1.18

1.96

2.99

3.6

5.83

11.22

12.46

0.67

1.11

1.72

2.48

3.25

5.01

8.64

10.58

0.32

0.41

0.55

0.83

1.03

1.69

2.69

4.58

0.2

0.13

0.16

0.25

0.33

0.46

0.67

1.04

1.27

0.04

0.25

0.36

0.48

0.65

0.96

1.9

0.058

0.088

0.13

0.15

0.25

0.35

0.50

2

Table 9.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

21.5 (19)

21 (18.5)

20 (17.5)

19.5 (17)

18.5 (16)

17.5 (15)

Gain of 2

20.5 (18)

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

Gain of 4

21 (18.5)

20.5 (18)

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

17.5 (15)

17 (14.5)

Gain of 8

20.5 (18)

20 (17.5)

19.5 (17)

19 (16.5)

18 (15.5)

17 (14.5)

Gain of 16

20 (17.5)

19 (16.5)

18.5 (16)

17.5 (15)

17 (14.5)

Gain of 32

20 (17.5)

19.5 (17)

18.5 (16)

18 (15.5)

17.5 (15)

17 (14.5)

Gain of 64

20 (17.5)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

16.5 (14)

16 (13.5)

Gain of 128

19 (16.5)

18 (15.5)

17.5 (15)

17 (14.5)

16 (13.5)

15.5 (13)

15 (12.5)

4.17

8.33

16.7

33.2

62

123

242

470

Table 10.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Enabled

Update Rate (Hz)

Gain of 1

16 (16)

16 (15)

Gain of 2

Gain of 4

16 (16)

16 (15)

16 (14.5)

Gain of 8

Gain of 16

Gain of 32

Gain of 64

Gain of 128

4.17

8.33

16.7

33.2

62

123

242

470

16 (16)

16 (15)

16 (14.5)

16 (16)

16 (15.5)

16 (15)

16 (16)

16 (15.5)

16 (14.5)

16 (14)

16 (16)

16 (15.5)

16 (15)

16 (14.5)

16 (13.5)

15.5 (13)

15 (12.5)

16 (16)

16 (15.5)

16 (14.5)

16 (15.5)

16 (14.5)

16 (13.5)

Rev. D | Page 14 of 36

AD7794/AD7795

CHOP DISABLED

With chop disabled, the switching time or settling time is

reduced by a factor of two. However, periodic offset calibrations

may now be required to remove offset and offset drift. When

chop is disabled, the AMP-CM bit in the mode register should

be set to 1. This limits the allowable common-mode voltage that

can be used. However, the common-mode rejection degrades if

the bit is not set.

The numbers given are for the bipolar input range with the

internal 1.17 V reference. These numbers are typical and are

generated with a differential input voltage of 0 V.

Table 12 and Table 13 show the effective resolution while the

output peak-to-peak (p-p) resolution is listed in brackets. It is

important to note that the effective resolution is calculated

using the rms noise, while the p-p resolution is calculated based

on peak-to-peak noise. The p-p resolution represents the

resolution for which there is no code flicker. These numbers are

typical and rounded to the nearest LSB.

Table 11 shows the rms noise of the AD7794/AD7795 for some

of the update rates and gain settings with chop disabled.

Table 11. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

Gain of 2

Gain of 4

Gain of 8

Gain of 16

Gain of 32

0.062

0.1

0.16

0.21

Gain of 64

0.053

0.079

0.13

0.17

0.2

Gain of 128

0.051

0.07

0.12

0.16

4.17

8.33

16.7

33.2

62

1.22

1.74

2.64

4.55

0.98

1.53

2.44

3.52

0.33

0.49

0.79

1.11

0.18

0.29

0.48

0.66

0.13

0.21

0.33

0.46

5.03

4.45

1.47

0.81

0.58

0.27

0.22

123

242

470

8.13

15.12

17.18

7.24

13.18

14.63

2.27

3.77

8.86

1.33

2.09

2.96

0.96

1.45

1.92

0.48

0.64

0.89

0.36

0.5

0.69

0.37

0.47

0.7

Table 12.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

21 (18.5)

20.5 (18)

20 (17.5)

19 (16.5)

18 (15.5)

17 (14.5)

Gain of 2

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17.5 (15)

16.5 (14)

Gain of 4

21 (18.5)

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

16 (13.5)

Gain of 8

20.5 (18)

20 (17.5)

19 (16.5)

18.5 (16)

17.5 (15)

17 (14.5)

16.5 (14)

Gain of 16

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

16.5 (14)

16 (13.5)

Gain of 32

20 (17.5)

19.5 (17)

19 (16.5)

18.5 (16)

18 (15.5)

17 (14.5)

16.5 (14)

Gain of 64

19.5 (17)

19 (16.5)

18 (15.5)

17.5 (15)

16.5 (14)

16 (13.5)

15.5 (13)

Gain of 128

18.5 (16)

18 (15.5)

17 (14.5)

16.5 (14)

15.5 (13)

15 (12.5)

14.5 (12)

4.17

8.33

16.7

33.2

62

123

242

470

Table 13.

Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Disabled

Update Rate (Hz)

Gain of 1

Gain of 2

16 (16)

16 (15.5)

16 (15)

16 (14)

Gain of 4

Gain of 8

16 (16)

16 (15)

16 (14.5)

16 (14)

Gain of 16

Gain of 32

Gain of 64

Gain of 128

4.17

8.33

16.7

33.2

62

123

242

470

16 (16)

16 (15.5)

16 (14.5)

16 (14)

16 (16)

16 (15.5)

16 (14.5)

16 (14)

16 (16)

16 (15.5)

16 (15)

16 (14)

16 (13.5)

15.5 (13)

16 (16)

16 (15.5)

16 (14.5)

16 (14)

15.5 (13)

15 (12.5)

14.5 (12)

16 (16)

16 (15.5)

16 (14.5)

16 (15.5)

16 (14.5)

16 (13.5)

Rev. D | Page 15 of 36

AD7794/AD7795

TYPICAL PERFORMANCE CHARACTERISTICS

8388800

14

12

10

8

8388750

8388700

8388650

8388600

8388550

8388500

8388450

6

4

2

0

8388068 8388100

8388150

8388200

8388250

8388300

8388350

8388396

0

200

400

600

800

1000

CODE

READING NUMBER

Figure 6. Typical Noise Plot for the AD7794 (Internal Reference,

Gain = 64, Update Rate = 16.7 Hz, Chop Enabled)

Figure 9. Noise Distribution Histogram for the AD7794 (Internal Reference,

Gain = 64, Update Rate = 16.7 Hz, Chop Disabled, AMP-CM = 1)

16

14

12

10

8

20

10

0

6

4

2

0

8388482

8388520

8388560

8388600

8388640

8388680

8388720

8388750

–2.0 –1.2 –0.8 –0.4

0

0.4

0.8

1.2

1.6

2.0

CODE

MATCHING (%)

Figure 7. Noise Distribution Histogram for the AD7794 (Internal Reference,

Gain = 64, Update Rate = 16.7 Hz, Chop Enabled)

Figure 10. Excitation Current Matching (210 μA) at Ambient Temperature

8388450

8388400

8388350

8388300

8388250

8388200

8388150

8388100

8388050

90

80

70

60

50

BOOST = 0

40

30

20

10

BOOST = 1

0

200

400

600

800

1000

0

200

400

600

800

1000

READING NUMBER

LOAD CAPACITANCE (nF)

Figure 8. Typical Noise Plot for the AD7794 (Internal Reference,

Gain = 64, Update Rate = 16.7 Hz, AMP-CM = 1, Chop Disabled)

Figure 11. Bias Voltage Generator Power-Up Time vs. Load Capacitance

Rev. D | Page 16 of 36

AD7794/AD7795

ON-CHIP REGISTERS

returns to where it expects a write operation to the

The ADC is controlled and configured via a number of on-chip

registers that are described in the following sections. In the

following descriptions, set implies a Logic 1 state and cleared

implies a Logic 0 state, unless otherwise noted.

communications register. This is the default state of the

interface and, on power-up or after a reset, the ADC is in this

default state waiting for a write operation to the communications

register. In situations where the interface sequence is lost, a

write operation of at least 32 serial clock cycles with DIN high

returns the ADC to this default state by resetting the entire part.

Table 14 outlines the bit designations for the communications

register. CR0 through CR7 indicate the bit location, with CR

denoting the bits are in the communications register. CR7

denotes the first bit of the data stream. The number in brackets

indicates the power-on/reset default status of that bit.

COMMUNICATIONS REGISTER

RS2, RS1, RS0 = 0, 0, 0

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation, and to which register this operation takes

place. For read or write operations, once the subsequent read or

write operation to the selected register is complete, the interface

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R/W(0)

RS2(0)

RS1(0)

RS0(0)

CREAD(0)

0(0)

Table 14. Communications Register Bit Designations

Bit No. Mnemonic Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If

a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location

until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the

communications register.

CR6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR5 to

CR3

CR2

RS2 to RS0

CREAD

Register Address Bits. These address bits are used to select which registers of the ADC are being selected during

this serial interface communication. See Table 15.

Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be read continuously, that is, the contents of the data register

are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to

indicate that a conversion is complete. The communications register does not have to be written to for data reads.

To enable continuous read mode, the instruction 01011100 must be written to the communications register. To

exit the continuous read mode, the instruction 01011000 must be written to the communications register while

the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can receive the

instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN.

Therefore, DIN should be held low in continuous read mode until an instruction is written to the device.

CR1 to

CR0

0

These bits must be programmed to Logic 0 for correct operation.

Table 15. Register Selection

RS2

RS1

RS0

Register

Register Size

0

1

Communications Register During a Write Operation

Status Register During a Read Operation

Mode Register

8-bit

16-bit

0

1

0

1

0

Configuration Register

Data Register

ID Register

16-bit

24-bit (AD7794)/16-Bit (AD7795)

8-bit

1

0

1

IO Register

8-bit

1

0

1

Offset Register

Full-Scale Register

24-bit (AD7794)/16-Bit (AD7795)

Rev. D | Page 17 of 36

AD7794/AD7795

STATUS REGISTER

RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80

(AD7795)/0x88 (AD7794)

Table 16 outlines the bit designations for the status register. SR0

through SR7 indicate the bit locations, with SR denoting that

the bits are in the status register. SR7 denotes the first bit of the

data stream. The number in brackets indicates the power-

on/reset default status of that bit.

The status register is an 8-bit read-only register. To access the

ADC status register, the user must write to the communications

register, select the next operation to be read, and load Bit RS2,

Bit RS1, and Bit RS0 with 0.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

NOXREF(0)

0(0)

0/1

CH2(0)

CH1(0)

CH0(0)

Table 16. Status Register Bit Designations

Bit No. Mnemonic Description

SR7

RDY

Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the

ADC data register has been read or a period of time before the data register is updated with a new conversion

result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down

mode. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the

status register for monitoring the ADC for conversion data.

SR6

SR5

ERR

ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the

ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence

of a reference voltage. Cleared by a write operation to start a conversion.

No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is

below a specified threshold. When set, conversion results are clamped to all 1s. Cleared to indicate that a valid

reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the

configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid.

NOXREF

SR4

SR3

SR2 to

SR0

0

0/1

CH2 to CH0

This bit is automatically cleared.

This bit is automatically cleared on the AD7795 and is automatically set on the AD7794.

These bits indicate which channel is being converted by the ADC.

Rev. D | Page 18 of 36

AD7794/AD7795

MODE REGISTER

RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A

denoting that the bits are in the mode register. MR15 is the first

bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit. Any write to the setup

The mode register is a 16-bit read/write register that is used to

select the operating mode, the update rate, and the clock source.

RDY

register resets the modulator and filter, and sets the

bit.

Table 17 outlines the bit designations for the mode register.

MR0 through MR15 indicate the bit locations with MR

MR15

MD2(0)

MR7

MR14

MD1(0)

MR6

MR13

MD0(0)

MR5

MR12

MR11

0(0)

MR10

0(0)

MR9

MR8

0(0)

PSW(0)

MR4

AMP-CM(0)

MR1

MR3

FS3(1)

MR2

FS2(0)

MR0

FS0(0)

CLK1(0)

CLK0(0)

0(0)

CHOP-DIS(0)

FS1(1)

Table 17. Mode Register Bit Designations

Bit No. Mnemonic Description

MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operating mode of the AD7794/AD7795 (see Table 18).

MR12

PSW

Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink

up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode,

the power switch is opened.

MR11 to MR10

MR9

0

These bits must be programmed with a Logic 0 for correct operation.

AMP-CM

Instrumentation Amplifier Common-Mode Bit. This bit is used in conjunction with the CHOP-DIS bit. With

chop disabled, the user can operate with a wider range of common-mode voltages when AMP-CM is

cleared. However, the dc common-mode rejection degrades. With AMP-CM set, the span for the common-

mode voltage is reduced (see the Specifications section). However, the dc common-mode rejection is

significantly better.

MR8

0

This bit must be programmed with a Logic 0 for correct operation.

MR7 to MR6

CLK1 to CLK0 These bits are used to select the clock source for the AD7794/AD7795. Either the on-chip 64 kHz clock can

be used or an external clock can be used. The ability to use an external clock allows several AD7794/AD7795

devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock

drives the AD7794/AD7795.

CLK1

CLK0

ADC Clock Source

0

1

0

1

0

Internal 64 kHz clock. Internal clock is not available at the CLK pin.

Internal 64 kHz clock. This clock is made available at the CLK pin.

External 64 kHz. The external clock can have a 45:55 duty cycle (see the

Specifications section for the external clock).

1

External clock. The external clock is divided by 2 within the AD7794/AD7795.

MR5

MR4

0

This bit must be programmed with a Logic 0 for correct operation.

CHOP-DIS

This bit is used to enable or disable chop. On power-up or following a reset, CHOP-DIS is cleared so chop is

enabled. When CHOP-DIS is set, chop is disabled. This bit is used in conjunction with the AMP-CM bit.

When chop is disabled, the AMP-CM bit should be set. This limits the common-mode voltage that can be

used by the ADC, but the dc common-mode rejection does not degrade.

MR3 to MR0

FS3 to FS0

Filter Update Rate Select Bits (see Table 19).

Rev. D | Page 19 of 36

AD7794/AD7795

Table 18. Operating Modes

MD2 MD1 MD0 Mode

0

Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data

register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device

in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses

are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communica-

tions register. After power-on, the first conversion is available after a period of 2/f_ADCwhen chop is enabled or

1/f_ADCwhen chop is disabled. Subsequent conversions are available at a frequency of f_ADCwith chop either

enabled or disabled.

0

1

Single Conversion Mode.

When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator

requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f_ADCwhen

chop is enabled, or 1/f_ADCwhen chop is disabled. The conversion result is placed in the data register, RDY goes

low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains

active (low) until the data is read or another conversion is performed.

0

1

0

1

0

Idle Mode.

In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still

provided.

Power-Down Mode.

In power-down mode, all the AD7794/AD7795 circuitry is powered down including the current sources, power

switch, burnout currents, bias voltage generator, and clock circuitry.

Internal Zero-Scale Calibration.

An internal short is automatically connected to the enabled channel. A calibration takes two conversion cycles to

complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following

a calibration. The measured offset coefficient is placed in the offset register of the selected channel.

1

0

1

Internal Full-Scale Calibration.

A full-scale input voltage is automatically connected to the selected analog input for this calibration.

When the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and one

conversion cycle when chop is disabled.

For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled

and 2 conversion cycles when chop is disabled.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is

placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register

of the selected channel.

Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system

full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is

changed to minimize the full-scale error.

1

0

1

System Zero-Scale Calibration.

User should connect the system zero-scale input to the channel input pins as selected by the CH2 bit, CH1 bit,

and CH0 bit. A system offset calibration takes two conversion cycles to complete when chop is enabled and one

conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when

the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coeffi-

cient is placed in the offset register of the selected channel.

System Full-Scale Calibration.

User should connect the system full-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and

CH0 bit.

A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when

chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is

complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in

the full-scale register of the selected channel.

A full-scale calibration is required each time the gain of a channel is changed.

Rev. D | Page 20 of 36

AD7794/AD7795

Table 19. Update Rates Available (Chop Enabled)¹

FS3

FS2

FS1

FS0

f_ADC(Hz)

T_SETTLE(ms)

x

Rejection @ 50 Hz/60 Hz (Internal Clock)

0

x

0

1

0

1

0

1

0

1

0

470

242

123

62

4

8

16

32

0

1

0

1

50

40

0

1

0

39

48

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

33.2

19.6

16.7

12.5

10

8.33

6.25

4.17

60

101

120

160

200

240

320

480

90 dB (60 Hz only)

80 dB (50 Hz only)

65 dB (50 Hz and 60 Hz)

66 dB (50 Hz and 60 Hz)

69 dB (50 Hz and 60 Hz)

70 dB (50 Hz and 60 Hz)

72 dB (50 Hz and 60 Hz)

74 dB (50 Hz and 60 Hz)

1

¹With chop disabled, the update rates remain unchanged, but the settling time for each update rate is reduced by a factor of 2. The rejection at 50 Hz/60 Hz for a

16.6 Hz update rate degrades to 60 dB.

Rev. D | Page 21 of 36

AD7794/AD7795

CONFIGURATION REGISTER

RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710

Table 20 outlines the bit designations for the filter register.

CON0 through CON15 indicate the bit locations. CON denotes

that the bits are in the configuration register. CON15 is the first

bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

The configuration register is a 16-bit read/write register that is

used to configure the ADC for unipolar or bipolar mode, enable

or disable the buffer, enable or disable the burnout currents,

select the gain, and select the analog input channel.

CON15

CON14

CON13

BO(0)

CON12

U/B(0)

CON4

BUF(1)

CON11

BOOST(0)

CON3

CON10

G2(1)

CON9

G1(1)

CON8

G0(1)

VBIAS1(0)

CON7

VBIAS0(0)

CON6

CON5

CON2

CH2(0)

CON1

CH1(0)

CON0

CH0(0)

REFSEL1(0)

REFSEL0(0)

REF_DET(0)

CH3(0)

Table 20. Configuration Register Bit Designations

Bit No. Mnemonic Description

CON15 to VBIAS1 to VBIAS0

CON14

Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AV_DD/2.

These bits are used in conjunction with the BOOST bit.

VBIAS1

VBIAS0

Bias Voltage

0

1

0

1

0

1

Bias voltage generator disabled

Bias voltage generator connected to AIN1(−)

Bias voltage generator connected to AIN2(−)

Bias voltage generator connected to AIN3(−)

CON13

CON12

BO

Burnout Current Enable Bit. This bit must be programmed with a Logic 0 for correct operation. When this

bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the

burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active.

Unipolar/Bipolar Bit. Set by user to enable unipolar coding, that is, zero differential input results in

0x000000 output and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to

enable bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero

differential input results in an output code of 0x800000, and positive full-scale differential input results in

an output code of 0xFFFFFF.

U/B

CON11

BOOST

This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the

bias voltage generator is increased, which reduces its power-up time.

CON10 to G2 to G0

CON8

Gain Select Bits.

Written by the user to select the ADC input range as follows:

G2

G1

G0

Gain

ADC Input Range (2.5 V Reference)

0

1 (in-amp not

used)

2.5 V

0

1

2 (in-amp not

used)

1.25 V

0

1

0

1

0

1

0

1

0

1

4

625 mV

8

312.5 mV

156.2 mV

78.125 mV

39.06 mV

19.53 mV

16

32

64

128

CON7 to

CON6

REFSEL1/REFSEL0

Reference Select Bits.

The reference source for the ADC is selected using these bits.

REFSEL1 REFSEL0

Reference Source

0

1

0

1

0

1

External reference applied between REFIN1(+) and REFIN1(−)

External reference applied between REFIN2(+) and REFIN2(−)

Internal 1.17 V reference

Reserved

Rev. D | Page 22 of 36

AD7794/AD7795

Bit No.

Mnemonic

Description

CON5

REF_DET

Enables the reference detect function. When set, the NOXREF bit in the status register indicates when the

external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the reference

detect function is disabled.

CON4

BUF

Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in

unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered

mode, allowing the user to place source impedances on the front end without contributing gain errors to

the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is

automatically enabled. With the buffer disabled, the voltage on the analog input pins can be from 30 mV

below GND to 30 mV above AV_DD. When the buffer is enabled, it requires some headroom so the voltage

on any input pin must be limited to 100 mV within the power supply rails.

CON3 to

CON0

CH3 to CH0

Channel Select Bits.

Written by the user to select the active analog input channel to the ADC.

CH3

0

CH2 CH1

CH0

0

1

0

1

0

1

0

Channel

Calibration Pair

0

1

0

1

0

1

AIN1(+)/AIN1(−)

AIN2(+)/AIN2(−)

AIN3(+)/AIN3(−)

AIN4(+)/AIN4(−)

AIN5(+)/AIN5(−)

AIN6(+)/AIN6(−)

Temp Sensor

0

1

2

3

Automatically selects the internal 1.17 V reference

and sets the gain to 1

0

1

AV_DDMonitor

Automatically selects the internal 1.17 V reference

and sets the gain to 1/6

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN1(−)/AIN1(−)

Reserved

0

Reserved

Rev. D | Page 23 of 36

AD7794/AD7795

DATA REGISTER

IO REGISTER

RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset =

0x0000(AD7795), 0x000000 (AD7794)

RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00

The IO register is an 8-bit read/write register that is used

to enable the excitation currents and select the value of the

excitation currents.

The conversion result from the ADC is stored in this data

register. This is a read-only register. On completion of a read

RDY

operation from this register, the

bit/pin is set.

Table 21 outlines the bit designations for the IO register. IO0

through IO7 indicate the bit locations. IO denotes that the bits

are in the IO register. IO7 denotes the first bit of the data

stream. The number in brackets indicates the power-on/reset

default status of that bit.

ID REGISTER

RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXF

The identification number for the AD7794/AD7795 is stored in

the ID register. This is a read-only register.

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

0(0)

IOEN(0)

IO2DAT(0)

IO1DAT(0)

IEXCDIR1(0)

IEXCDIR0(0)

IEXCEN1(0)

IEXCEN0(0)

Table 21. IO Register Bit Designations

Bit No.

Mnemonic

Description

IO7

0

This bit must be programmed with a Logic 0 for correct operation.

IO6

IOEN

Configures Pin AIN6(+)/P1 and Pin AIN6(−)/P2 as analog input pins or digital output pins. When this

bit is set, the pins are configured as Digital Output Pin P1 and Digital Output Pin P2. When this bit is

cleared, these pins are configured as Analog Input Pin AIN6(+) and Analog Input Pin AIN6(−).

IO5 to IO4

IO3 to IO2

IO2DAT/IO1DAT

P2/P1 Data. When IOEN is set, the data for Digital Output Pin P1 and Digital Output Pin P2 is written

to Bit IO2DAT and Bit IO1DAT.

Direction of Current Sources Select Bits.

IEXCDIR1 to IEXCDIR0

IEXCDIR1 IEXCDIR0

Current Source Direction

0

1

0

1

0

1

Current Source IEXC1 connected to Pin IOUT1. Current Source IEXC2

connected to Pin IOUT2.

Current Source IEXC1 connected to Pin IOUT2. Current Source IEXC2

connected to Pin IOUT1.

Both current sources connected to Pin IOUT1. Permitted only when the

current sources are set to 10 μA or 210 μA.

Both current sources connected to Pin IOUT2. Permitted only when the

current sources are set to 10 μA or 210 μA.

IO3 to IO2

IEXCEN1 to IEXCEN0

These bits are used to enable and disable the current sources. They also select the value of the

excitation currents.

IEXCEN1

IEXCEN0

Current Source Value

0

1

0

1

0

1

Excitation currents disabled

10 μA

210 μA

1 mA

Rev. D | Page 24 of 36

AD7794/AD7795

OFFSET REGISTER

FULL-SCALE REGISTER

RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000

(AD7795), 0x800000 (AD7794))

RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX

(AD7795), 0x5XXX00 (AD7794)

The offset register is a 16-bit register on the AD7795 and a 24-bit

register on the AD7794. The offset register holds the offset

calibration coefficient for the ADC and its power-on reset value

is 0x8000/0x800000, for the AD7794/AD7795, respectively. The

AD7794/AD7795 each have four offset registers. Channel AIN1

to Channel AIN3 have dedicated offset registers while the

AIN4, AIN5, and AIN6 channels share an offset register. Each

of these registers is a read/write register. The register is used in

conjunction with its associated full-scale register to form a

register pair. The power-on reset value is automatically

overwritten if an internal or system zero-scale calibration is

initiated by the user. The AD7794/AD7795 must be placed in

power-down mode or idle mode when writing to the offset

register.

The full-scale register is a 16-bit register on the AD7795 and a

24-bit register on the AD7794. The full-scale register holds the

full-scale calibration coefficient for the ADC. The AD7794/

AD7795 each have four full-scale registers. The AIN1, AIN2,

and AIN3 channels have dedicated full-scale registers, while the

AIN4, AIN5, and AIN6 channels share a register. The full-scale

registers are read/write registers. However, when writing to the

full-scale registers, the ADC must be placed in power-down

mode or idle mode. These registers are configured on power-on

with factory calibrated full-scale calibration coefficients, the

calibration being performed at gain = 1. Therefore, every device

has different default coefficients. The coefficients are different,

depending on whether the internal reference or an external

reference is selected. The default value is automatically

overwritten if an internal or system full-scale calibration is

initiated by the user or the full-scale register is written to.

Rev. D | Page 25 of 36

AD7794/AD7795

ADC CIRCUIT INFORMATION

50 Hz and 60 Hz rejection is optimized when the update rate

equals 16.7 Hz or less, as notches are placed at both 50 Hz and

60 Hz with these update rates (see Figure 14).

OVERVIEW

The AD7794/AD7795 are low power ADCs that incorporate a

∑-Δ modulator, buffer, reference, in-amp, and on-chip digital

filtering, which are intended for the measurement of wide

dynamic range, low frequency signals (such as those in pressure

transducers), weigh scales, and temperature measurement

applications.

The AD7794/AD7795 use slightly different filter types,

depending on the output update rate, so that the rejection of

quantization noise and device noise is optimized. When the

update rate is 4.17 Hz to 12.5 Hz, a Sinc3 filter along with an

averaging filter is used. When the update rate is 16.7 Hz to

39 Hz, a modified Sinc3 filter is used. This filter gives

simultaneous 50 Hz/60 Hz rejection when the update rate

equals 16.7 Hz. A Sinc4 filter is used when the update rate is

50 Hz to 242 Hz. Finally, an integrate-only filter is used when

the update rate equals 470 Hz. Figure 13 to Figure 16 show the

frequency response of the different filter types for some of the

update rates when chop is enabled. In this mode, the settling

time equals twice the update rate. Figure 17 to Figure 20 show

the filter response with chop disabled.

Each part has six differential inputs that can be buffered or

unbuffered. The devices operate with an internal 1.17 V refer-

ence or by using an external reference. Figure 12 shows the

basic connections required to operate the parts.

The output rate of the AD7794/AD7795 (f_ADC) is user pro-

grammable. The allowable update rates, along with the

corresponding settling times, are listed in Table 19 for chop

enabled. With chop disabled, the allowable update rates remain

unchanged, but the settling time equals 1/f_ADC. Normal mode

rejection is the major function of the digital filter. Simultaneous

V

DD

REFIN1(+)

GND

AV

DD

IN+

OUT–

OUT+

AIN1(+)

AIN1(–)

AD7794/AD7795

IN+

IN–

V

DD

IN–

OUT–

OUT+

AIN2(+)

AIN2(–)

AIN3(+)

DOUT/RDY

SERIAL

DIN

INTERFACE

AND

Σ-Δ

ADC

MUX

BUF

IN-AMP

SCLK

CS

LOGIC

CONTROL

AIN3(–)

GND

REFIN2(+)

V

R

DD

CM

REFIN2(–)

IOUT1

DV

DD

INTERNAL

CLOCK

REFIN1(–)

PSW

GND

CLK

Figure 12. Basic Connection Diagram

Rev. D | Page 26 of 36

AD7794/AD7795

0

–20

0

–10

–20

–30

–40

–50

–60

–40

–60

–80

–100

0

20

40

60

80

100

120

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

FREQUENCY (Hz)

Figure 13. Filter Response with Update Rate = 4.17 Hz (Chop Enabled)

Figure 16. Filter Response with Update Rate = 470 Hz (Chop Enabled)

0

–20

0

–20

–40

–60

–80

–100

0

20

40

60

80

100 120 140 160 180 200

0

20

40

60

80

100

120

FREQUENCY (Hz)

Figure 14. Filter Response with Update Rate = 16.7 Hz (Chop Enabled)

Figure 17. Filter Response with Update Rate = 4.17 Hz (Chop Disabled)

0

–20

–40

–20

–40

–60

–80

–100

0

500

1000

1500

2000

2500

3000

0

20

40

60

80

100 120 140 160 180 200

FREQUENCY (Hz)

Figure 15. Filter Response with Update Rate = 242 Hz (Chop Enabled)

Figure 18. Filter Response with Update Rate = 16.7 Hz (Chop Disabled)

Rev. D | Page 27 of 36

AD7794/AD7795

RDY

0

to transfer data into the on-chip registers, while DOUT/

is

used for accessing data from the on-chip registers. SCLK is the

serial clock input for the devices, and all data transfers (either

–20

RDY

on DIN or DOUT/

) occur with respect to the SCLK signal.

RDY

The DOUT/

pin also operates as a data ready signal; the

–40

line goes low when a new data-word is available in the output

register. It is reset high when a read operation from the data

register is complete. It also goes high prior to the updating of

the data register to indicate when not to read from the device, to

ensure that a data read is not attempted while the register is

–60

–80

CS

being updated.

is used to select a device. It can be used to

decode the AD7794/AD7795 in systems where several

components are connected to the serial bus.

–100

0

500

1000

1500

2000

2500

3000

FREQUENCY (Hz)

Figure 3 and Figure 4 show timing diagrams for interfacing to the

CS

Figure 19. Filter Response at 242 Hz Update Rate (Chop Disabled)

AD7794/AD7795 with , which is being used to decode the parts.

Figure 3 shows the timing for a read operation from the output

shift register of the AD7794/AD7795, while Figure 4 shows the

timing for a write operation to the input shift register. It is

possible to read the same word from the data register several

0

–10

–20

–30

–40

–50

–60

RDY

times, even though the DOUT/

line returns high after the

first read operation. However, care must be taken to ensure that

the read operations have been completed before the next output

update occurs. In continuous read mode, the data register can

be read only once.

CS

The serial interface can operate in 3-wire mode by tying

low.

lines are used to

communicate with the AD7794/AD7795. The end of the

RDY

In this case, the SCLK, DIN, and DOUT/

conversion can be monitored using the

register. This scheme is suitable for interfacing to micro-

CS

bit in the status

0

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

FREQUENCY (Hz)

controllers. If

is required as a decoding signal, it can be

Figure 20. Filter Response at 470 Hz Update Rate (Chop Disabled)

generated from a port pin. For microcontroller interfaces, it is

recommended that SCLK idle high between data transfers.

DIGITAL INTERFACE

CS

The AD7794/AD7795 can be operated with

being used as a

As previously outlined in the On-Chip Registers section, the

programmable functions of the AD7794/AD7795 are controlled

using a set of on-chip registers. Data is written to these registers

via the serial interface. Read access to the on-chip registers is

also provided by this interface. All communications with the

parts must start with a write to the communications register.

After power-on or reset, each device expects a write to its

communications register. The data written to this register

determines whether the next operation is a read operation or a

write operation, and determines to which register this read or

write operation occurs. Therefore, write access to any of the

other registers on the parts begins with a write operation to the

communications register, followed by a write to the selected

register. A read operation from any other register (except when

continuous read mode is selected) starts with a write to the

communications register, followed by a read operation from the

selected register.

frame synchronization signal. This scheme is useful for DSP

interfaces. In this case, the first bit (MSB) is effectively clocked

CS

out by , because

normally occurs after the falling edge of

SCLK in DSPs. The SCLK can continue to run between data

transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the AD7794/AD7795 line

for at least 32 serial clock cycles, the serial interface is reset.

This ensures that the interface can be reset to a known state if

the interface gets lost due to a software error or some glitch in

the system. Reset returns the interface to the state in which it is

expecting a write to the communications register. This

operation resets the contents of all registers to their power-on

values. Following a reset, the user should allow a period of

500 μs before addressing the serial interface.

The AD7794/AD7795 can be configured to continuously convert

or perform a single conversion (see Figure 21 through Figure 23).

The serial interface of the AD7794/AD7795 consists of four

CS

RDY

signals: , DIN, SCLK, and DOUT/

. The DIN line is used

Rev. D | Page 28 of 36

AD7794/AD7795

CS

0x08

0x200A

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 21. Single Conversion

CS

0x58

DIN

DATA

DOUT/RDY

SCLK

Figure 22. Continuous Conversion

CS

0x5C

DIN

DATA

DOUT/RDY

SCLK

Figure 23. Continuous Read

Rev. D | Page 29 of 36

AD7794/AD7795

Continuous Read

Single Conversion Mode

Rather than write to the communications register each time a

conversion is complete to access the data, the AD7794/AD7795

can be configured so that the conversions are placed on the

In single conversion mode, the AD7794/AD7795 are placed in

shutdown mode between conversions. When a single

conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0

to 1 in the mode register, the AD7794/AD7795 power up,

perform a single conversion, and then return to shutdown

mode. The on-chip oscillator requires 1 ms to power up. A

RDY

DOUT/

line automatically. By writing 01011100 to the

communications register, the user need only apply the

appropriate number of SCLK cycles to the ADC. The 24-bit

RDY

word is automatically placed on the DOUT/

line when a

RDY

conversion requires a time period of 2 × t_ADC. DOUT/

low to indicate the completion of a conversion. When the data-

RDY

goes

conversion is complete. The ADC should be configured for

continuous conversion mode.

word has been read from the data register, DOUT/

goes

remains high until another

conversion is initiated and completed. The data register can be

CS RDY

high. If

is low, DOUT/

RDY

When DOUT/

goes low to indicate the end of a conversion,

sufficient SCLK cycles must be applied to the ADC, and the

RDY

read several times, if required, even when DOUT/

gone high.

has

data conversion is placed on the DOUT/

line. When the

RDY

conversion is read, DOUT/

conversion is available.

returns high until the next

Continuous Conversion Mode

In this mode, the data can be read only once. Also, the user must

ensure that the data-word is read before the next conversion is

complete. If the user has not read the conversion before the

completion of the next conversion, or if insufficient serial clocks are

applied to the AD7794/AD7795 to read the word, the serial

output register is reset when the next conversion is complete.

The new conversion is then placed in the output serial register.

This is the default power-up mode. The AD7794/AD7795

RDY

continuously convert with the

going low each time a conversion is complete. If

RDY

pin in the status register

CS

is low, the

line also goes low when a conversion is complete.

DOUT/

To read a conversion, the user writes to the communications

register, indicating that the next operation is a read of the data

RDY

register. The digital conversion is placed on the DOUT/

To exit the continuous read mode, the instruction 01011000

RDY

pin as soon as SCLK pulses are applied to the ADC. DOUT/

RDY

must be written to the communications register while the

pin is low. While in the continuous read mode, the ADC

monitors activity on the DIN line so that it can receive the

returns high when the conversion is read. The user can read this

register additional times, if required. However, the user must

ensure that the data register is not being accessed at the completion

of the next conversion, or else the new conversion word is lost.

instruction to exit the continuous read mode. Additionally, a

reset occurs if 32 consecutive 1s are seen on DIN. Therefore,

DIN should be held low in continuous read mode until an

instruction is to be written to the device.

Rev. D | Page 30 of 36

AD7794/AD7795

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

INSTRUMENTATION AMPLIFIER

Amplifying the analog input signal by a gain of 1 or 2 is

performed digitally within the AD7794/AD7795. However,

when the gain equals 4 or higher, the output from the buffer is

applied to the input of the on-chip instrumentation amplifier.

This low noise in-amp means that signals of small amplitude

can be gained within the AD7794/AD7795 while still

maintaining excellent noise performance. For example, when

the gain is set to 64, the rms noise is 40 nV typically, which is

equivalent to 21 bits effective resolution or 18.5 bits peak-to-

peak resolution.

The AD7794/AD7795 have six differential analog input

channels. These are connected to the on-chip buffer amplifier

when the devices are operated in buffered mode. When in

unbuffered mode, the channels connect directly to the

modulator. In buffered mode (the BUF bit in the configuration

register is set to 1), the input channel feeds into a high

impedance input stage of the buffer amplifier. Therefore, the

input can tolerate significant source impedances and is tailored

for direct connection to external resistive-type sensors such as

strain gages or resistance temperature detectors (RTDs).

Each AD7794/AD7795 can be programmed to have a gain of 1,

2, 4, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the

configuration register. Therefore, with an external 2.5 V

reference, the unipolar ranges are from 0 mV to 20 mV to 0 V

to 2.5 V and the bipolar ranges are from 20 mV to 2.5 V.

When the in-amp is active (gain ≥ 4), the common-mode

voltage ((AIN(+) + AIN(−))/2) must be greater than or equal to

0.5 V when chop is enabled. With chop disabled, and with the

AMP-CM bit set to 1 to prevent degradation in the common-

mode rejection, the allowable common-mode voltage is limited

to between

When BUF = 0, the parts operate in unbuffered mode. This

results in a higher analog input current. Note that this

unbuffered input path provides a dynamic load to the driving

source. Therefore, resistor/capacitor combinations on the input

pins can cause gain errors, depending on the output impedance

of the source that is driving the ADC input. Table 22 shows the

allowable external resistance/capacitance values for unbuffered

mode so that no gain error at the 20-bit level is introduced.

Table 22. External R-C Combination for 20-Bit No Gain Error

Capacitance (pF)

Resistance (Ω)

50

9 k

6 k

1.5 k

900

200

0.2 + (Gain/2 × (AIN(+) − AIN(−)))

and

100

500

1000

5000

AV_DD− 0.2 − (Gain/2 × (AIN(+) − AIN(−)))

If the AD7794/AD7795 are operated with an external reference

that has a value equal to AV_DD, for correct operation, the analog

input signal must be limited to 90% of V_REF/gain when the in-

amp is active.

The AD7794/AD7795 can be operated in unbuffered mode

only when the gain equals 1 or 2. At higher gains, the buffer

is automatically enabled. The absolute input voltage range in

buffered mode is restricted to a range between GND + 100 mV

and AV_DD− 100 mV. When the gain is set to 4 or higher, the

in-amp is enabled. The absolute input voltage range when the in-

amp is active is restricted to a range between GND + 300 mV and

AV_DD− 1.1 V. Care must be taken in setting up the common-

mode voltage so that these limits are not exceeded. Otherwise,

there is degradation in linearity and noise performance.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7794/AD7795 can accept either

unipolar or bipolar input voltage ranges. A bipolar input range

does not imply that the parts can tolerate negative voltages with

respect to system GND. Unipolar and bipolar signals on the

AIN(+) input are referenced to the voltage on the AIN(−) input.

For example, if AIN(−) is 2.5 V and the ADC is configured for

unipolar mode with a gain of 1, the input voltage range on the

AIN(+) pin is 2.5 V to 5 V.

The absolute input voltage in unbuffered mode includes the

range between GND − 30 mV and AV_DD+ 30 mV as a result of

being unbuffered. The negative absolute input voltage limit does

allow the possibility of monitoring small, true bipolar signals

with respect to GND.

If the ADC is configured for bipolar mode, the analog input

range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar

B

option is chosen by programming the U/ bit in the

configuration register.

Rev. D | Page 31 of 36

AD7794/AD7795

DATA OUTPUT CODING

EXCITATION CURRENTS

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00...00, a miscalled voltage

resulting in a code of 100...000, and a full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

The AD7794/AD7795 also contain two matched, software

configurable, constant current sources that can be programmed

to equal 10 μA, 210 μA, or 1 mA. Both source currents from

AV_DDare directed to either the IOUT1 or IOUT2 pin of the

device. These current sources are controlled via bits in the IO

register. The configuration bits enable the current sources and

direct the current sources to IOUT1 or IOUT2, along with

selecting the value of the current. These current sources can be

used to excite external resistive bridge or RTD sensors.

Code = (2^N× AIN × GAIN)/V_REF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000...000, a zero differential input voltage resulting

in a code of 100...000, and a positive full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

BIAS VOLTAGE GENERATOR

A bias voltage generator is included on the AD7794/AD7795. It

biases the negative terminal of the selected input channel to

AV_DD/2. This function is available on inputs AIN1(−) to

AIN3(−). It is useful in thermocouple applications, as the

voltage generated by the thermocouple must be biased about

some dc voltage if the gain is greater than 2. This is necessary

because the instrumentation amplifier requires headroom. If

there is no headroom, signals close to GND or AV_DDdo not

convert accurately.

Code = 2^{N – 1}× [(AIN × GAIN/V_REF) + 1]

where:

AIN is the analog input voltage.

GAIN is the in-amp setting (1 to 128).

N = 24.

The bias voltage generator is controlled using the VBIAS1 and

VBIAS0 bits in conjunction with the BOOST bit in the

BURNOUT CURRENTS

The AD7794/AD7795 contain two 100 nA constant current

generators, one sourcing current from AV_DDto AIN(+), and one

sinking current from AIN(−) to GND. The currents are

switched to the selected analog input pair. Both currents are

either on or off, depending on the burnout current enable (BO)

bit in the configuration register. These currents can be used to

verify that an external transducer is still operational before

attempting to take measurements on that channel. Once the

burnout currents are turned on, they flow in the external

transducer circuit, and a measurement of the input voltage on

the analog input channel can be taken. If the resulting voltage

measured is full scale, the user needs to verify why this is the

case. A full-scale reading could mean that the front-end sensor

is open circuit. It could also mean that the front-end sensor is

overloaded and is justified in outputting full scale, or that the

reference may be absent and the NOXREF bit is set, thus

clamping the data to all 1s.

configuration register. The power-up time of the bias voltage

generator is dependent on the load capacitance. To accommodate

higher load capacitances, each AD7794/AD7795 has a BOOST

bit. When this bit is set to 1, the current consumed by the bias

voltage generator is increased so that power-up time is reduced

considerably. Figure 11 shows the power-up times when

BOOST equals 0 and BOOST equals 1 for different load

capacitances. The current consumption of the AD7794/AD7795

increases by 40 μA when the bias voltage generator is enabled,

and BOOST equals 0. With the BOOST function enabled, the

current consumption increases by 250 μA.

REFERENCE

The AD7794/AD7795 have embedded 1.17 V references. These

references can be used to supply the ADC or external references

can be applied. The embedded references are low noise, low

drift references with 4 ppm/°C drift typically. For external

references, the ADC has a fully differential input capability for

the channel. In addition, the user has the option of selecting one

of two external reference options (REFIN1 or REFIN2). The

reference source for the AD7794/AD7795 is selected using the

REFSEL1 and REFSEL0 bits in the configuration register. When

the internal reference is selected, it is internally connected to

the modulator (it is not available on the REFIN pins).

When reading all 1s from the output, the user needs to check

these three cases before making a judgment. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. For normal operation, these burnout currents are

turned off by writing a 0 to the BO bit in the configuration

register. The current sources work over the normal absolute

input voltage range specifications with buffers on.

The common-mode range for these differential inputs is from

GND to AV_DD. The reference input is unbuffered; therefore,

excessive R-C source impedances introduce gain errors. The

reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V

nominal, but the AD7794/AD7795 are functional with reference

voltages from 0.1 V to AV_DD. In applications where the

excitation (voltage or current) for the transducer on the analog

Rev. D | Page 32 of 36

AD7794/AD7795

input also drives the reference voltage for the parts, the effect of

the low frequency noise in the excitation source is removed,

because the application is ratiometric. If the AD7794/AD7795

are used in nonratiometric applications, a low noise reference

should be used.

the on-chip registers. A reset is useful if the serial interface

becomes asynchronous due to noise on the SCLK line.

AV_DDMONITOR

Along with converting external voltages, the ADC can be

used to monitor the voltage on the AV_DDpin. When Bit CH2

to Bit CH0 equals 1, the voltage on the AV_DDpin is internally

attenuated by 6, and the resulting voltage is applied to the

∑-Δ modulator using an internal 1.17 V reference for analog-

to-digital conversion. This is useful because variations in the

power supply voltage can be monitored.

Recommended 2.5 V reference voltage sources for the

AD7794/AD7795 include the ADR381 and ADR391, which are

low noise, low power references. Also, note that the reference

inputs provide a high impedance, dynamic load. Because the

input impedance of each reference input is dynamic, resis-

tor/capacitor combinations on these inputs can cause dc gain

errors, depending on the output impedance of the source

driving the reference inputs.

CALIBRATION

The AD7794/AD7795 provide four calibration modes that can

be programmed via the mode bits in the mode register. These

are internal zero-scale calibration, internal full-scale calibration,

system zero-scale calibration, and system full-scale calibration,

which effectively reduce the offset error and full-scale error to

the order of the noise. After each conversion, the ADC

conversion result is scaled using the ADC calibration registers

before being written to the data register. The offset calibration

coefficient is subtracted from the result prior to multiplication

by the full-scale coefficient.

Reference voltage sources (for example, the ADR391) typically

have low output impedances and are, therefore, tolerant to

having decoupling capacitors on REFIN(+) without introducing

gain errors in the system. Deriving the reference input voltage

across an external resistor means that the reference input sees a

significant external source impedance. External decoupling on

the REFIN pins is not recommended in this type of circuit

configuration.

REFERENCE DETECT

To start a calibration, write the relevant value to the MD2 to

MD0 bits in the mode register. After the calibration is

completed, the contents of the corresponding calibration

The AD7794/AD7795 include on-chip circuitry to detect if they

have a valid reference for conversions or calibrations when the

user selects an external reference as the reference source. This

feature is enabled when the REF_DET bit in the configuration

register is set to 1. If the voltage between the selected REFIN(+)

and REFIN(–) pins goes below 0.3 V, or either the REFIN(+) or

REFIN(–) inputs are open circuit, the AD7794/AD7795 detect

that they no longer have valid references. In this case, the

NOXREF bit of the status register is set to 1. If the AD7794/

AD7795 are performing normal conversions and the NOXREF

bit becomes active, the conversion results revert to all 1s.

Therefore, it is not necessary to continuously monitor the status

of the NOXREF bit when performing conversions. It is only

necessary to verify its status if the conversion result read from

the ADC data register is all 1s. If the AD7794/AD7795 are

performing either offset or full-scale calibrations and the

NOXREF bit becomes active, the updating of the respective

calibration registers is inhibited to avoid loading incorrect

coefficients to these registers, and the ERR bit in the status

register is set. If the user is concerned about verifying that a

valid reference is in place every time a calibration is performed,

the status of the ERR bit should be checked at the end of the

calibration cycle.

RDY

registers are updated, the

bit in the status register is set,

RDY

CS

is low), and the

the DOUT/

pin goes low (if

AD7794/AD7795 revert to idle mode.

During an internal zero-scale or full-scale calibration, the

respective zero input and full-scale input are automatically

connected internally to the ADC input pins. A system calibration,

however, expects the system zero-scale and system full-scale

voltages to be applied to the ADC pins before initiating the

calibration mode. In this way, external ADC errors are removed.

From an operational point of view, a calibration should be

treated like another ADC conversion. A zero-scale calibration,

if required, should always be performed before a full-scale

RDY

calibration. System software should monitor the

bit in the

RDY

status register or the DOUT/

pin to determine the end of

calibration via a polling sequence or an interrupt-driven routine.

With chop enabled, both an internal offset calibration and

a system offset calibration take two conversion cycles. With

chop enabled, an internal offset calibration is not needed

because the ADC itself removes the offset continuously. With

chop disabled, an internal offset calibration or system offset

calibration takes one conversion cycle to complete. Internal

offset calibrations are required with chop disabled and should

occur before the full-scale calibration.

RESET

The circuitry and serial interface of the AD7794/AD7795 can

be reset by writing 32 consecutive 1s to the device. This resets

the logic, the digital filter, and the analog modulator, and all on-

chip registers are reset to their default values. A reset is

automatically performed on power-up. When a reset is initiated,

the user must allow a period of 500 μs before accessing any of

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. When the gain equals 1, a calibration takes

two conversion cycles to complete when chop is enabled and

Rev. D | Page 33 of 36

AD7794/AD7795

one conversion cycle when chop is disabled. For higher gains,

four conversion cycles are required to perform the full-scale

calibration when chop is enabled, and two conversion cycles

levels from the AD7794/AD7795 are so low, care must be taken

with regard to grounding and layout.

The printed circuit board that houses the AD7794/AD7795

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. A minimum

etch technique is generally best for ground planes because it

gives the best shielding.

RDY

when chop is disabled. DOUT/

goes high when the

calibration is initiated and returns low when the calibration is

complete. The ADC is placed in idle mode following a cali-

bration. The measured full-scale coefficient is placed in the full-

scale register of the selected channel. Internal full-scale

calibrations cannot be performed when the gain equals 128.

With this gain setting, a system full-scale calibration can be

performed. A full-scale calibration is required each time the

gain of a channel is changed to minimize the full-scale error.

It is recommended that the GND pin of the AD7794/AD7795

be tied to the AGND plane of the system. In any layout, it is

important that the user keep in mind the flow of currents in the

system, ensuring that the return paths for all currents are as

close as possible to the paths the currents took to reach their

destinations. Avoid forcing digital currents to flow through the

AGND sections of the layout.

An internal full-scale calibration can be performed at specified

update rates only. For gains of 1, 2, and 4, an internal full-scale

calibration can be performed at any update rate. However, for

higher gains, internal full-scale calibrations can be performed

only when the update rate is less than or equal to 16.7 Hz, 33.3 Hz,

and 50 Hz. However, the full-scale error does not vary with

update rate, so a calibration at one update is valid for all update

rates (assuming the gain or reference source is not changed).

The ground plane of the AD7794/AD7795 should be allowed to

run under the AD7794/AD7795 to prevent noise coupling. The

power supply lines to the AD7794/AD7795 should use as wide a

trace as possible to provide low impedance paths and reduce the

effects of glitches on the power supply line. Fast switching

signals, such as clocks, should be shielded with digital ground

to avoid radiating noise to other sections of the board. In

addition, clock signals should never be run near the analog

inputs. Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is the best, but it is not always

possible with a double-sided board. In this technique, the

component side of the board is dedicated to ground planes,

while signals are placed on the solder side.

A system full-scale calibration takes two conversion cycles to

complete, irrespective of the gain setting when chop is enabled

and one conversion cycle when chop is disabled. A system full-

scale calibration can be performed at all gains and all update

rates. With chop disabled, the offset calibration (internal or

system offset) should be performed before the system full-scale

calibration is initiated.

GROUNDING AND LAYOUT

Because the analog inputs and reference inputs of the ADC are

differential, most of the voltages in the analog modulator are

common-mode voltages. The excellent common-mode

rejection of the part removes common-mode noise on these

inputs. The digital filter provides rejection of broadband noise

on the power supply, except at integer multiples of the

modulator sampling frequency. The digital filter also removes

noise from the analog and reference inputs, provided that these

noise sources do not saturate the analog modulator. As a result,

the AD7794/AD7795 are more immune to noise interference

than conventional high resolution converters. However, because

the resolution of the AD7794/AD7795 is so high, and the noise

Good decoupling is important when using high resolution

ADCs. AV_DDshould be decoupled with 10 μF tantalum in

parallel with 0.1 μF capacitors to GND. DV_DDshould be

decoupled with 10 μF tantalum in parallel with 0.1 μF

capacitors to the system’s DGND plane, with the system’s

AGND to DGND connection being close to the

AD7794/AD7795. To achieve the best from these decoupling

components, they should be placed as close as possible to the

device, ideally right up against the device. All logic chips should

be decoupled with 0.1 μF ceramic capacitors to DGND.

Rev. D | Page 34 of 36

AD7794/AD7795

APPLICATIONS INFORMATION

The AD7794/AD7795 offer low cost, high resolution analog-to-

digital functions. Because the analog-to-digital function is

provided by a ∑-Δ architecture, it makes the parts more immune

to noisy environments, making them ideal for use in sensor

measurement, and industrial and process control applications.

A second advantage of using the AD7794/AD7795 in transducer-

based applications is that the low-side power switch can be fully

utilized in low power applications. The low-side power switch is

connected in series with the cold side of the bridges. In normal

operation, the switch is closed and measurements can be taken.

In applications where power is of concern, the AD7794/AD7795

can be placed in standby mode, thus significantly reducing the

power consumed in the application. In addition, the low-side

power switch can be opened while in standby mode, thus

avoiding unnecessary power consumption by the front-end

transducers. When the parts are taken out of standby mode, and

the low-side power switch is closed, the user should ensure that

the front-end circuitry is fully settled before attempting a read

from the AD7794/AD7795.

FLOWMETER

Figure 24 shows the AD7794/AD7795 being used in a

flowmeter application that consists of two pressure transducers,

with the rate of flow being equal to the pressure difference. The

pressure transducers shown are the BP01 from Sensym. The

pressure transducers are arranged in a bridge network and give

a differential output voltage between its OUT+ and OUT–

terminals. With rated full-scale pressure (in this case

300 mmHg) on the transducer, the differential output voltage is

3 mV/V of the input voltage (that is, the voltage between the

IN(+) and IN(–) terminals).

In the diagram, temperature compensation is performed using a

thermistor. The on-chip excitation current supplies the thermistor.

In addition, the reference voltage for the temperature measurement

is derived from a precision resistor in series with the thermistor.

This allows a ratiometric measurement so that variation of the

excitation current has no effect on the measurement (it is the

ratio of the precision reference resistance to the thermistor

resistance that is measured).

Assuming a 5 V excitation voltage, the full-scale output range

from the transducer is 15 mV. The excitation voltage for the

bridge can be used to directly provide the reference for the

ADC, as the reference input range includes the supply voltage.

V

DD

REFIN1(+)

GND

AV

DD

IN+

OUT–

OUT+

AIN1(+)

AIN1(–)

AD7794/AD7795

IN+

IN–

V

DD

IN–

OUT–

OUT+

AIN2(+)

AIN2(–)

AIN3(+)

DOUT/RDY

SERIAL

DIN

INTERFACE

AND

Σ-Δ

ADC

MUX

BUF

IN-AMP

SCLK

CS

LOGIC

CONTROL

AIN3(–)

GND

REFIN2(+)

V

R

DD

CM

REFIN2(–)

IOUT1

DV

DD

INTERNAL

CLOCK

REFIN1(–)

PSW

GND

CLK

Figure 24. Typical Application (Flowmeter)

Rev. D | Page 35 of 36

AD7794/AD7795

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8°

0°

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 25. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD7794BRU

Temperature Range

Package Description

Package Option

RU-24

–40°C to +105°C

–40°C to +125°C

–40°C to +105°C

24-Lead Thin Shrink Small Outline Package [TSSOP]

Evaluation Board

AD7794BRU-REEL

AD7794BRUZ¹

AD7794BRUZ-REEL¹

AD7794CRUZ¹

AD7794CRUZ-REEL¹

AD7795BRUZ¹

AD7795BRUZ-REEL¹

EVAL-AD7794EB

EVAL-AD7795EB

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D04854-0-3/07(D)

Rev. D | Page 36 of 36


型号：	AD7795
厂家：	ADI
描述：	6-Channel, Low Noise, Low Power
文件：	总37页 (文件大小：767K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7795 [ADI]

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AD7796BRUZ-REEL

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