AD7810YRZ-REEL7_技术文档

2.7 V to 5.5 V, 2.3 ␮s, 10-Bit

ADC in 8-Lead microSOIC/DIP

a

AD7810

FUNCTIONAL BLOCK DIAGRAM

FEATURES

10-Bit ADC with 2.3 ␮s Conversion Time

Small Footprint 8-Lead microSOIC Package

Specified Over a –40؇C to +105؇C Temperature Range

Inherent Track-and-Hold Functionality

Operating Supply Range: 2.7 V to 5.5 V

Specifications at 2.7 V to 5.5 V

Microcontroller-Compatible Serial Interface

Optional Automatic Power-Down

at End of Conversion

V

AGND

DD

REF

AD7810

CHARGE

REDISTRIBUTION

DAC

D

OUT

SERIAL

PORT

SCLK

CLOCK

OSC

V

+

–

IN

CONTROL

LOGIC

COMP

Low Power Operation

IN

3

/

V

DD

270 ␮W at 10 kSPS Throughput Rate

2.7 mW at 100 kSPS Throughput Rate

Analog Input Range: 0 V to V_REF

Reference Input Range: 0 V to V_DD

CONVST

APPLICATIONS

Low Power, Hand-Held Portable Applications that

Require Analog-to-Digital Conversion with 10-Bit

Accuracy; e.g., Battery Powered Test Equipment,

Battery-Powered Communications Systems

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

1. Complete, 10-Bit ADC in 8-Lead Package

The AD7810 is a high speed, low power, 10-bit A/D con-

verter that operates from a single 2.7 V to 5.5 V supply. The

part contains a 2.3 µs successive approximation A/D converter,

with inherent track/hold functionality, a pseudo differential

input and a high speed serial interface that interfaces to most

microcontrollers. The AD7810 is fully specified over a tem-

perature range of –40°C to +105°C.

The AD7810 is a 10-bit 2.3 µs ADC with inherent track/hold

functionality and a high speed serial interface—all in an

8-lead microSOIC package. V_REFmay be connected to V_DD

to eliminate the need for an external reference. The result is

a high speed, low power, space saving ADC solution.

2. Low Power, Single Supply Operation

By using a technique that samples the state of the CONVST

(convert start) signal at the end of a conversion, the AD7810

may be used in an automatic power-down mode. When used in

this mode, the AD7810 automatically powers down at the end

of a conversion and “wakes up” at the start of a new conversion.

This feature significantly reduces the power consumption of the

part at lower throughput rates. The AD7810 can also operate in

a high speed mode where the part is not powered down between

conversions. In this high speed mode of operation, the conver-

sion time of the AD7810 is 2.3 µs. The maximum throughput

rate is dependent on the speed of the serial interface of the

microcontroller.

The AD7810 operates from a single 2.7 V to 5.5 V supply

and typically consumes only 9 mW of power while convert-

ing. The power dissipation can be significantly reduced at

lower throughput rates by using the automatic power-down

mode, e.g., at a throughput rate of 10 kSPS the power

consumption is only 270 µW.

3. Automatic Power-Down

The automatic power-down mode, whereby the AD7810

powers down at the end of a conversion and “wakes up”

before the next conversion, means the AD7810 is ideal for

battery powered applications. See Power vs. Throughput

Rate section.

The part is available in a small 8-lead, 0.3" wide, plastic dual-

in-line package (mini-DIP); in an 8-lead, small outline IC

(SOIC); and in an 8-lead microSOIC package.

4. Serial Interface

An easy to use, fast serial interface allows connection to most

popular microprocessors with no external circuitry.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(GND = 0 V, V_REF= V_DD. All specifications –40؇C to +105؇C unless otherwise noted.)

AD7810–SPECIFICATIONS

Parameter

Y Version

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio¹

Total Harmonic Distortion¹

Peak Harmonic or Spurious Noise

Intermodulation Distortion²

2nd Order Terms

f_IN= 30 kHz, f_SAMPLE= 350 kHz

58

–64

dB min

dB max

fa = 48 kHz, fb = 48.5 kHz

–67

dB typ

3rd Order Terms

DC ACCURACY

Resolution

10

1

2

Bits

Relative Accuracy¹

LSB max

Differential Nonlinearity (DNL)¹

Offset Error¹

Gain Error¹

Minimum Resolution for Which

No Missing Codes Are Guaranteed

10

Bits

ANALOG INPUT

Input Voltage Range

0

V min

V_REF

1

15

V max

µA max

pF max

Input Leakage Current²

Input Capacitance²

REFERENCE INPUTS²

V_REFInput Voltage Range

1.2

V_DD

3

V min

V max

µA max

pF max

Input Leakage Current

Input Capacitance

20

LOGIC INPUTS²

V_INH, Input High Voltage

2.0

0.4

1

V min

V

_INL, Input Low Voltage

V max

µA max

pF max

Input Current, I_IN

Input Capacitance, C_IN

Typically 10 nA, V_IN= 0 V to V_DD

8

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

High Impedance Leakage Current

High Impedance Capacitance

2.4

0.4

10

V min

I_SOURCE= 200 µA

I_SINK= 200 µA

V max

µA max

pF max

15

CONVERSION RATE

Conversion Time

2.3

100

µs max

ns max

Track/Hold Acquisition Time¹

See DC Acquisition Time Section

POWER SUPPLY

V_DD

I_DD

2.7–5.5

3.5

17.5

Volts

mA max

mW max

For Specified Performance

Sampling at 350 kSPS and Logic

Inputs at V_DDor 0 V. V_DD= 5 V

Power Dissipation

Power-Down Mode

I_DD

Power Dissipation

Automatic Power Down

1 kSPS Throughput

10 kSPS Throughput

100 kSPS Throughput

1

5

µA max

µW max

V_DD= 5 V; V_DD= 3 V

27

270

2.7

µW max

mW max

NOTES

¹See Terminology section.

²Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

REV. B

–2–

AD7810

Timing Characteristics^{1, 2}

(–40؇C to +105؇C, V_REF= V_DD, unless otherwise noted)

Parameter

V_DD= 5 V ؎ 10%

V_DD= 3 V ؎ 10%

Unit

Conditions/Comments

t₁

t₂

t₃

t₄₃

t₅₃

t₆₃

t_{73, 4}

t₈

2.3

20

25

5

10

5

20

10

1.5

2.3

20

25

5

10

5

20

10

1.5

µs (max)

ns (min)

ns (max)

ns (min)

µs (max)

Conversion Time Mode 1 Operation (High Speed Mode)

CONVST Pulsewidth

SCLK High Pulsewidth

SCLK Low Pulsewidth

CONVST Rising Edge to SCLK Rising Edge Set-Up Time

SCLK Rising Edge to D_OUTData Valid Delay

Data Hold Time after Rising Edge SCLK

Bus Relinquish Time after Falling Edge of SCLK

t_{POWER UP}

Power-Up Time after Rising Edge of CONVST

NOTES

¹Sample tested to ensure compliance.

²See Figures 14, 15 and 16.

³These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V _DD= 5 V 10% and

0.4 V or 2 V for V_DD= 3 V 10%.

⁴Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t₈, quoted in the Timing Characteristics is the true bus relinquish time

of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25°C unless otherwise noted)

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND

θ

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W

Lead Temperature, Soldering

(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

Digital Output Voltage to GND

(D_OUT) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW

V

_REFto GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

Analog Inputs

θ

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

(V_IN+, V_IN–) . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W

θ

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W

Lead Temperature Soldering (10 sec) . . . . . . . . . . . 260°C

ORDERING GUIDE

Linearity

Error (LSB)

Temperature

Range

Package

Description

Package

Options

Branding

Information

Model

AD7810YN

AD7810YR

AD7810YRM

1 LSB

–40°C to +105°C

Plastic DIP

Small Outline IC (SOIC) SO-8

microSOIC RM-8

N-8

C1Y

I

OL

200␮A

TO

OUTPUT

1.6V

C

L

50pF

I

OH

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. B

–3–

AD7810

PIN FUNCTION DESCRIPTIONS

Description

Pin No.

Mnemonic

1

CONVST

Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion.

A rising edge on the CONVST pin enables the serial port of the AD7810. This is useful in multi-

package applications where a number of devices share the same serial bus. The state of this pin at

the end of conversion also determines whether the part is powered down or not. See Operating

Modes section of this data sheet.

2

3

4

5

6

7

8

V_IN+

V_IN–

Positive input of the pseudo differential analog input.

Negative input of the pseudo differential analog input.

Ground reference for analog and digital circuitry.

External reference is connected here.

Serial data is shifted out on this pin.

Serial Clock. An external serial clock is applied here.

Positive Supply Voltage 2.7 V to 5.5 V.

GND

V_REF

D_OUT

SCLK

V_DD

PIN CONFIGURATION

DIP/SOIC

1

2

3

4

8

7

6

5

V

DD

CONVST

AD7810

SCLK

V

+

IN

TOP VIEW

V

–

D

(Not to Scale)

IN

OUT

GND

V

REF

Typical Performance Characteristics

10

–15

2048 POINT FFT

SAMPLING 357.142kSPS

F

= 30kHz

IN

–35

1

–55

–75

0.1

–95

–115

0.01

0

10

20

30

40

50

FREQUENCY BINS

THROUGHPUT – kSPS

Figure 2. Power vs. Throughput

Figure 3. AD7810 SNR

REV. B

–4–

AD7810

TERMINOLOGY

Signal to (Noise + Distortion) Ratio

The AD7810 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second and third order terms are of differ-

ent significance. The second order terms are usually distanced

in frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. The calculation of the intermodulation distortion is as

per the THD specification where it is the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

fundamental expressed in dBs.

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

The ratio is dependent upon the number of quantization levels in

the digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Relative Accuracy

Thus for a 10-bit converter, this is 62 dB.

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7810 it is defined as:

Differential Nonlinearity

This is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

V₂²+V₃²+V₄²+V₅²

THD dB = 20 log

(

)

V₁

Offset Error

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆²are the rms amplitudes of the second through

the sixth harmonics.

This is the deviation of the first code transition (0000 . . . 000)

to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Gain Error

Peak Harmonic or Spurious Noise

This is the deviation of the last code transition (1111 . . . 110)

to (1111 . . . 111) from the ideal (i.e., V_REF– 1 LSB) after the

offset error has been adjusted out.

Peak harmonic or spurious noise is defined as the ratio of the

rms values of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output of

the track/hold amplifier to reach its final value, within 1/2 LSB,

after the end of conversion (the point at which the track/hold

returns to track mode). It also applies to situations where there

is a step input change on the input voltage applied to the V_IN+

input of the AD7810. It means that the user must wait for the

duration of the track/hold acquisition time, after the end of conver-

sion or after a step input change to V_IN+, before starting another

conversion to ensure that the part operates to specification.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which

neither m nor n are equal to zero. For example, the second

order terms include (fa + fb) and (fa – fb), while the third order

terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

REV. B

–5–

AD7810

SUPPLY

2.7V TO 5.5V

CIRCUIT DESCRIPTION

TWO WIRE

SERIAL

INTERFACE

10␮F

0.1␮F

Converter Operation

The AD7810 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. The ADC

can convert analog input signals in the range 0 V to V_DD. Fig-

ures 4 and 5 below show simplified schematics of the ADC.

Figure 4 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A; the comparator is held in a

balanced condition; and the sampling capacitor acquires the

V

DD

REF

0V TO V

REF

V

+

SCLK

IN

INPUT

AD7810

␮C/␮P

V

–

D

IN

OUT

AGND

CONVST

Figure 6. Typical Connection Diagram

Analog Input

signal on V_IN+

.

CHARGE

REDISTRIBUTION

DAC

Figure 7 shows an equivalent circuit of the analog input struc-

ture of the AD7810. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 200 mV. This will cause these diodes to become

forward biased and start conducting current into the substrate.

The maximum current these diodes can conduct without caus-

ing irreversible damage to the part is 20 mA. The capacitor C2

is typically about 4 pF and can be primarily attributed to pin

capacitance. The resistor R1 is a lumped component made up of

the on resistance of a multiplexer and a switch. This resistor is

typically about 125 Ω. The capacitor C1 is the ADC sampling

capacitor and has a capacitance of 3.5 pF.

SAMPLING

CAPACITOR

A

V

+

IN

CONTROL

LOGIC

SW1

B

ACQUISITION

PHASE

SW2

COMPARATOR

CLOCK

OSC

V

–

V

/3

IN

DD

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 5), SW2 will

open and SW1 will move to Position B, causing the comparator

to become unbalanced. The control logic and the charge redis-

tribution DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. Figure 11 shows the ADC transfer function.

V

DD

C1

3.5pF

R1

125⍀

D1

D2

V

/3

V

+

DD

IN

C2

4pF

CHARGE

CONVERT PHASE – SWITCH OPEN

ACQUISITION PHASE – SWITCH CLOSED

REDISTRIBUTION

DAC

SAMPLING

CAPACITOR

A

Figure 7. Equivalent Analog Input Circuit

V

+

IN

CONTROL

LOGIC

SW1

The analog input of the AD7810 is made up of a pseudo differ-

ential pair. V_IN+pseudo differential with respect to V_IN–. The

signal is applied to V_IN+, but in the pseudo differential scheme

the sampling capacitor is connected to V_IN–during conversion

(see Figure 8). This input scheme can be used to remove offsets

that exist in a system. For example, if a system had an offset of

0.5 V, the offset could be applied to V_IN–and the signal applied

to V_IN+. This has the effect of offsetting the input span by 0.5 V.

It is only possible to offset the input span when the reference

B

CONVERSION

PHASE

SW2

COMPARATOR

CLOCK

OSC

V

–

V

/3

IN

DD

Figure 5. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7810. The

serial interface is implemented using two wires; the rising edge

of CONVST enables the serial interface—see Serial Interface

section for more details. V_REFis connected to a well decoupled

voltage (V_REF) is less than V_DD– V_OFFSET

.

V

_DDpin to provide an analog input range of 0 V to V_DD. When

CHARGE

REDISTRIBUTION

DAC

V_DDis first connected, the AD7810 powers up in a low current

mode, i.e., power-down. A rising edge on the CONVST input

will cause the part to power up—see Operating Modes. If power

consumption is of concern, the automatic power-down at the

end of a conversion should be used to improve power perfor-

mance. See Power vs. Throughput Rate section of the data sheet.

SAMPLING

COMPARATOR

CAPACITOR

V

+

IN

CONTROL

LOGIC

V

(+)

IN

CONVERSION

PHASE

V

OFFSET

SW2

–

IN

CLOCK

OSC

V

/3

DD

V

OFFSET

Figure 8. Pseudo Differential Input Scheme

REV. B

–6–

AD7810

When using the pseudo differential input scheme, the signal on

_IN–must not vary by more than a 1/2 LSB during the conver-

For small values of source impedance, the settling time associated

with the sampling circuit (100 ns) is, in effect, the acquisition

time of the ADC. For example, with a source impedance (R2)

of 10 Ω, the charge time for the sampling capacitor is approxi-

mately 4 ns. The charge time becomes significant for source

impedances of 2 kΩ and greater.

V

sion process. If the signal on V_IN–varies during conversion, the

conversion result will be incorrect. For single-ended operation,

V_IN–is always connected to AGND. Figure 9 shows the AD7810

pseudo differential input being used to make a unipolar dc cur-

rent measurement. A sense resistor is used to convert the current

to a voltage and the voltage, is applied to the differential input

as shown.

AC Acquisition Time

In ac applications it is recommended to always buffer analog

input signals. The source impedance of the drive circuitry must

be kept as low as possible to minimize the acquisition time of

the ADC. Large values of source impedance will cause the THD

to degrade at high throughput rates. In addition, better perfor-

mance can generally be achieved by using an external 1 nF

V

DD

V

+

IN

R

AD7810

SENSE

capacitor on V_IN+

.

–

IN

R

L

ADC TRANSFER FUNCTION

The output coding of the AD7810 is straight binary. The

designed code transitions occur at successive integer LSB values

(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V_REF/1024. The

ideal transfer characteristic for the AD7810 is shown in Figure

11 below.

Figure 9. DC Current Measurement Scheme

DC Acquisition Time

The ADC starts a new acquisition phase at the end of a conver-

sion and ends on the falling edge of the CONVST signal. At the

end of a conversion there is a settling time associated with the

sampling circuit. This settling time lasts approximately 100 ns.

The analog signal on V_IN+is also being acquired during this

settling time; therefore, the minimum acquisition time needed is

approximately 100 ns.

111...111

111...110

Figure 10 shows the equivalent charging circuit for the sampling

capacitor when the ADC is in its acquisition phase. R2 repre-

sents the source impedance of a buffer amplifier or resistive

network; R1 is an internal multiplexer resistance and C1 is the

sampling capacitor.

111...000

011...111

1LSB = V

/1024

REF

000...010

000...001

000...000

R1

125⍀

V

+

IN

R2

C1

3.5pF

0V

+V

–1LSB

REF

1LSB

ANALOG INPUT

Figure 11. Transfer Characteristic

Figure 10. Equivalent Sampling Circuit

During the acquisition phase, the sampling capacitor must be

charged to within a 1/2 LSB of its final value. The time it takes

to charge the sampling capacitor (t_CHARGE) is given by the fol-

lowing formula:

t

_CHARGE= 7.6 × (R2 + 125 Ω) × 3.5 pF

REV. B

–7–

AD7810

POWER-UP TIMES

OPERATING MODES

The AD7810 has a 1.5 µs power-up time. When V_DDis first

connected, the AD7810 is in a low current mode of operation.

In order to carry out a conversion, the AD7810 must first be

powered up. The ADC is powered up by a rising edge on the

CONVST pin. A conversion is initiated on the falling edge of

CONVST. Figure 12 shows how to power up the AD7810 when

V_DDis first connected or after the AD7810 is powered down

using the CONVST pin.

Mode 1 Operation (High Speed Sampling)

When the AD7810 is used in this mode of operation, the part is

not powered down between conversions. This mode of opera-

tion allows high throughput rates to be achieved. The timing

diagram in Figure 14 shows how this optimum throughput rate

is achieved by bringing the CONVST signal high before the end

of the conversion. The AD7810 leaves its tracking mode and

goes into hold on the falling edge of CONVST. A conversion is

also initiated at this time. The conversion takes 2.3 µs to complete.

At this point, the result of the current conversion is latched into the

serial shift register, and the state of the CONVST signal checked.

The CONVST signal should be high at the end of the conversion

to prevent the part from powering down.

Care must be taken to ensure that the CONVST pin of the

AD7810 is logic low when V_DDis first applied.

MODE 1 (CONVST IDLES HIGH)

V

DD

t_POWER-UP

1.5␮s

< 1␮s

t₁

CONVST

MODE 2 (CONVST IDLES LOW)

A

B

t₂

V

DD

t_POWER-UP

SCLK

1.5␮s

CONVST

D

CURRENT CONVERSION RESULT

OUT

Figure 12. Power-Up Times

Figure 14. Mode 1 Operation Timing

POWER VS. THROUGHPUT RATE

The serial port on the AD7810 is enabled on the rising edge of

the CONVST signal (see Serial Interface section). As explained

earlier, this rising edge should occur before the end of the con-

version process if the part is not to be powered down. A serial

read can take place at any stage after the rising edge of CONVST.

If a serial read is initiated before the end of the current con-

version process (i.e., at time “A”), the result of the previous

conversion is shifted out on the D_OUTpin. It is possible to allow

the serial read to extend beyond the end of a conversion. In this

case the new data will not be latched into the output shift regis-

ter until the read has finished. The dynamic performance of the

AD7810 typically degrades by up to 3 dBs while reading during

a conversion. If the user waits until the end of the conversion

process, i.e., 2.3 µs after falling edge of CONVST (Point “B”),

before initiating a read, the current conversion result is shifted out.

By operating the AD7810 in Mode 2, the average power con-

sumption of the AD7810 decreases at lower throughput rates.

Figure 13 shows how the automatic power-down is implemented

using the CONVST signal to achieve the optimum power per-

formance for the AD7810. As the throughput rate is reduced, the

device remains in its power-down state longer and the average

power consumption over time drops accordingly.

t_CONVERT

2.3␮s

t_POWER-UP

POWER-DOWN

1.5␮s

CONVST

t_CYCLE

100␮s @ 10kSPS

Figure 13. Automatic Power-Down

For example, if the AD7810 is operated in a continuous sampling

mode with a throughput rate of 10 kSPS, the power consump-

tion is calculated as follows. The power dissipation during normal

operation is 9 mW, V_DD= 3 V. If the power-up time is 1.5 µs

and the conversion time is 2.3 µs, the AD7810 can be said to

dissipate 9 mW for 3.8 µs (worst case) during each conversion

cycle. If the throughput rate is 10 kSPS, the cycle time is

100 µs and the average power dissipated during each cycle is

(3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of

Power vs. Throughput.

REV. B

–8–

AD7810

Mode 2 Operation (Automatic Power-Down)

before initiating a serial read. The serial port of the AD7810 is

still functional even though the AD7810 has been powered down.

NOTE: Serial read should not cross the next rising edge of

CONVST.

When used in this mode of operation, the part automatically

powers down at the end of a conversion. This is achieved by

leaving the CONVST signal low until the end of the conversion.

Because it takes approximately 1.5 µs for the part to power up

after it has been powered down, this mode of operation is in-

tended to be used in applications where slower throughput rates

are required, i.e., in the order of 100 kSPS. The timing diagram

in Figure 15 shows how to operate the part in this mode. If the

AD7810 is powered down, the rising edge of the CONVST

pulse causes the part to power up. When the part has powered

up (≈ 1.5 µs after the rising edge of CONVST), the CONVST

signal is brought low, and a conversion is initiated on this falling

edge of the CONVST signal. The conversion takes 2.3 µs and

after this time, the conversion result is latched into the serial

shift register and the part powers down. Therefore, when the

part is operated in Mode 2, the effective conversion time is

equal to the power-up time (1.5 µs) and the SAR conversion

time (2.3 µs).

Because it is possible to do a serial read from the part while it

is powered down, the AD7810 is powered up only to do the

conversion and is immediately powered down at the end of a

conversion. This significantly improves the power consumption

of the part at slower throughput rates—see Power vs. Through-

put Rate section.

SERIAL INTERFACE

The serial interface of the AD7810 consists of three wires, a

serial clock input SCLK, serial port enable CONVST and a

serial data output D_OUT(see Figure 16). The serial interface

is designed to allow easy interfacing to most microcontrollers,

e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any

gluing logic. When interfacing to the 8051, the SCLK must be

inverted. The Microprocessor Interface section explains how to

interface to some popular microcontrollers.

NOTE: Although the AD7810 takes 1.5 µs to power up after the

rising edge of CONVST, it is not necessary to leave CONVST

high for 1.5 µs after the rising edge before bringing it low to

initiate a conversion. If the CONVST signal goes low before 1.5 µs

in time has elapsed, then the power-up time is timed out inter-

nally and a conversion is then initiated. Hence the AD7810 is

guaranteed to have always powered up before a conversion is

initiated—even if the CONVST pulsewidth is < 1.5 µs. If the

CONVST width is > 1.5 µs, then a conversion is initiated on

the falling edge.

Figure 16 shows the timing diagram for a serial read from the

AD7810. The serial interface works with both a continuous and

a noncontinuous serial clock. The rising edge of the CONVST

signal resets a counter, which counts the number of serial clocks

to ensure the correct number of bits are shifted out of the serial

shift registers. The SCLK is ignored once the correct number of

bits have been shifted out. In order for another serial transfer to

take place, the counter must be reset by the falling edge of the

10th SCLK. Data is clocked out from the D_OUTline on the first

rising SCLK edge after the rising edge of the CONVST signal

and on subsequent SCLK rising edges. D_OUTenters its high

impedance state again on the falling edge of the 10th SCLK.

In multipackage applications, the CONVST signal can be used

as a chip select signal. The serial interface will not shift data out

until it receives a rising edge on the CONVST pin.

As in the case of Mode 1 operation, the rising edge of the

CONVST pulse enables the serial port of the AD7810 (see

Serial Interface section). If a serial read is initiated soon after

this rising edge (Point “A”), i.e., before the end of the conver-

sion, the result of the previous conversion is shifted out on pin

D_OUT. In order to read the result of the current conversion, the

user must wait at least 2.3 µs after the falling edge of CONVST

t_POWER-UP

1.5␮s

t₁

CONVST

SCLK

B

A

D

OUT

CURRENT CONVERSION RESULT

Figure 15. Mode 2 Operation Timing

t₃

2

SCLK

1

3

4

5

6

7

8

9

10

t₄

t₅

CONVST

t₇

DB8

t₈

DB0

t₆

D

OUT

DB9

DB7

DB6

DB5

DB4

DB3

DB2

DB1

Figure 16. AD7810 Serial Interface Timing

REV. B

–9–

AD7810

MICROPROCESSOR INTERFACING

AD7810 to 8051

The serial interface on the AD7810 allows the parts to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7810 with some of the

more common microcontroller serial interface protocols.

The AD7810 requires a clock synchronized to the serial data;

therefore, the 8051 serial interface must be operated in Mode

0. In this mode serial data enters and exits through RXD, and a

serial clock is output on TXD (half duplex). Figure 19 shows

how the 8051 is connected to the AD7810. However, because

the AD7810 shifts data out on the rising edge of the serial

clock, the serial clock must be inverted.

AD7810 to PIC16C6x/7x

The PIC16C6x Synchronous Serial Port (SSP) is configured

as an SPI Master with the Clock Polarity Bit = 0. This is done

by writing to the Synchronous Serial Port Control Register

(SSPCON). See PIC16/17 Microcontroller User Manual. Figure

17 shows the hardware connections needed to interface to the

PIC16/PIC17. In this example I/O port RA1 is being used to

pulse CONVST and enable the serial port of the AD7810. This

microcontroller transfers only eight bits of data during each

serial transfer operation, therefore, two consecutive read opera-

tions are needed.

AD7810*

8051*

SCLK

TXD

RXD

P1.1

D

OUT

CONVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 19. Interfacing to the 8051 Serial Port

It is possible to implement a serial interface using the data ports

on the 8051 (or any microcontroller). This would allow direct

interfacing between the AD7810 and 8051 to be implemented.

The technique involves “bit banging” an I/O port (e.g., P1.0)

to generate a serial clock and using another I/O port (e.g., P1.1)

to read in data, see Figure 20.

PIC16C6x/7x*

AD7810*

SCK/RC3

SCLK

SDO/RC5

RA1

D

OUT

CONVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. Interfacing to the PIC16/PIC17

AD7810 to MC68HC11

AD7810*

SCLK

8051*

P1.0

P1.1

P1.2

The Serial Peripheral Interface (SPI) on the MC68HC11 is

configured for Master Mode (MSTR = 0), Clock Polarity Bit

(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is

configured by writing to the SPI Control Register (SPCR)—see

68HC11 User Manual. A connection diagram is shown in

Figure 18.

D

OUT

CONVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 20. Interfacing to the 8051 Using I/O Ports

AD7810*

MC68HC11*

SCLK/PD4

SCLK

MISO/PD2

PA0

D

OUT

CONVST

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 18. Interfacing to the MC68HC11

REV. B

–10–

AD7810

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

0.430 (10.92)

0.348 (8.84)

8

5

0.280 (7.11)

0.240 (6.10)

1

4

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.195 (4.95)

0.115 (2.93)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

SEATING

PLANE

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

8-Lead Small Outline

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

1

5

4

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0196 (0.50)

0.0099 (0.25)

x 45°

0.0098 (0.25)

0.0040 (0.10)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8-Lead microSOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

5

4

8

1

0.199 (5.05)

0.187 (4.75)

0.122 (3.10)

0.114 (2.90)

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33°

27°

0.018 (0.46)

0.008 (0.20)

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

REV. B

–11–


型号：	AD7810YRZ-REEL7
厂家：	ADI
描述：	2.7 V to 5.5 V, 2.3 s, 10-Bit ADC in 8-Lead microSOIC/DIP 2.7 V至5.5 V ， 2.3秒，10位ADC，采用8引脚MicroSOIC / DIP
文件：	总11页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7810YRZ-REEL7 [ADI]

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