AD781 [ADI]
Complete 700 ns Sample-and-Hold Amplifier; 完整的700 ns的采样和保持放大器
| 型号： | AD781 |
| 厂家： | 
ADI |
| 描述： | Complete 700 ns Sample-and-Hold Amplifier |
| 文件： | 总8页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 700 ns
Sample-and-Hold Amplifier
a
AD781*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Acquisition Tim e to 0.01%: 700 ns Maxim um
Low Pow er Dissipation: 95 m W
Low Droop Rate: 0.01 V/ s
Fully Specified and Tested Hold Mode Distortion
Total Harm onic Distortion: –80 dB Maxim um
Aperture J itter: 75 ps Maxim um
Internal Hold Capacitor
1
2
3
4
8
7
6
5
OUT
V
CC
IN
COMMON
NC
S/H
NC
X1
V
Self-Correcting Architecture
AD781
EE
8-Pin Mini Cerdip and Plastic Package
MIL-STD-883 Com pliant Versions Available
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD781 is a high speed monolithic sample-and-hold
amplifier (SHA). T he AD781 guarantees a maximum
acquisition time of 700 ns to 0.01% over temperature. T he
AD781 is specified and tested for hold mode total harmonic
distortion and hold mode signal-to-noise and distortion. T he
AD781 is configured as a unity gain amplifier and uses a
self-correcting architecture that minimizes hold mode errors and
insures accuracy over temperature. T he AD781 is self-contained
and requires no external components or adjustments.
1. Fast acquisition time (700 ns), low aperture jitter (75 ps) and
fully specified hold mode distortion make the AD781 an
ideal SHA for sampling systems.
2. Low droop (0.01 µV/µs) and internally compensated hold
mode error results in superior system accuracy.
3. Low power (95 mW typical), complete functionality and
small size make the AD781 an ideal choice for a variety of
high performance, low power applications.
4. T he AD781 requires no external components or adjustments.
T he low power dissipation, 8-pin mini-DIP package and
completeness make the AD781 ideal for highly compact board
layouts. T he AD781 will acquire a full-scale input in less than
700 ns and retain the held value with a droop rate of 0.01 µV/µs.
Excellent linearity and hold mode dc and dynamic performance
make the AD781 ideal for 12- and 14-bit high speed analog-
to-digital converters.
5. Excellent choice as a front-end SHA for high speed analog-
to-digital converters such as the AD671, AD7586, AD674B,
AD774B, AD7572 and AD7672.
6. Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
7. T he AD781 is available in versions compliant with MIL-
ST D-883. Refer to the Analog Devices Military Products
Databook or current AD781/883B data sheet for detailed
specifications.
T he AD781 is manufactured on Analog Devices’ BiMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
T he AD781 is specified for three temperature ranges. T he J
grade device is specified for operation from 0°C to +70°C, the A
grade from –40°C to +85°C and the S grade from –55°C to
+125°C. T he J and A grades are available in 8-pin plastic DIP
packages. T he S grade is available in an 8-pin cerdip package.
*P r otected by U.S. P atent No. 4,962,325.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD781–SPECIFICATIONS
(TMIN to T , V = +12 V ؎ 10%, V = –12 V ؎ 10%, C = 20 pF, unless otherwise noted)
DC SPECIFICATIONS
MAX CC
EE
L
AD 781J
Typ
AD 781A
Typ
AD 781S
Typ
P aram eter
Min
Max
Min
Max
Min
Max
Units
SAMPLING CHARACT ERIST ICS
Acquisition T ime
10 V Step to 0.01%
10 V Step to 0.1%
Small Signal Bandwidth
Full Power Bandwidth
600
500
4
700
600
600
500
4
700
600
600
500
4
700
600
ns
ns
MHz
MHz
1
1
1
HOLD CHARACT ERIST ICS
Effective Aperture Delay (25°C)
Aperture Jitter (25°C)
Hold Settling (to 1 mV, 25°C)
Droop Rate
–35
–25
50
250
0.01
–15
75
500
1
–35
–25
50
250
0.01
–15
75
500
1
–35
–25
50
250
0.01
–15
75
500
1
ns
ps
ns
µV/µs
Feedthrough (25°C)
(VIN = ±5 V, 100 kHz)
–86
–86
–86
dB
ACCURACY CHARACT ERIST ICS1
Hold Mode Offset
Hold Mode Offset Drift
Sample Mode Offset
Nonlinearity
–4
–5
–1
10
50
+3
–4
–5
–1
10
50
+3
–4
–5
–1
10
50
+3
mV
µV/°C
mV
% FS
% FS
200
200
200
±0.002 ±0.003
±0.01
±0.002 ±0.003
±0.01
±0.003 ±0.005
±0.01
Gain Error
±
0.025
±
0.025
±0.025
OUT PUT CHARACT ERIST ICS
Output Drive Current
Output Resistance, DC
T otal Output Noise (DC to 5 MHz)
Sampled DC Uncertainty
Hold Mode Noise (DC to 5 MHz)
Short Circuit Current
Source
+5
0.5
+5
0.5
+5
0.5
mA
Ω
µV rms
µV rms
µV rms
0.3
150
85
0.3
150
85
0.3
150
85
125
125
125
20
10
20
10
20
10
mA
mA
Sink
INPUT CHARACT ERIST ICS
Input Voltage Range
Bias Current
Input Impedance
Input Capacitance
–5
+5
250
–5
+5
250
–5
+5
250
V
50
50
2
50
50
2
50
50
2
nA
MΩ
pF
DIGIT AL CHARACT ERIST ICS
Input Voltage Low
Input Voltage High
0.8
10
0.8
10
0.8
10
V
V
µA
2.0
2.0
2.0
Input Current High (VIN = 5 V)
2
2
2
POWER SUPPLY CHARACT ERIST ICS
Operating Voltage Range
Supply Current
+PSRR (+12 V ± 10%)
–PSRR (–12 V ± 10%)
Power Consumption
±10.8 ±12
±13.2
6.5
±10.8 ±12
±13.2
6.5
±10.8 ±12
±13.2
7
V
4
4
4
mA
dB
dB
mW
70
65
80
75
95
70
65
80
75
95
70
65
80
75
95
175
+70
175
+85
185
T EMPERAT URE RANGE
Specified Performance
0
–40
–55
+125
°C
NOT E
1Specified and tested over an input range of ±5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.
–2–
REV. A
AD781
(TMIN to T , V = +12 V ؎ 10%, V = –12 V ؎ 10%, C = 20 pF,
MAX CC
EE
L
unless otherwise noted)1
HOLD MODE AC SPECIFICATIONS
AD 781J
AD 781A
Typ
AD 781S
Typ
P aram eter
Min
Typ
Max
–80
Min
Max
–80
Min
Max
–80
Units
T OT AL HARMONIC DIST ORT ION
FIN = 10 kHz
FIN = 50 kHz
–90
–73
–68
–90
–73
–68
–90
–73
–68
dB
dB
dB
FIN = 100 kHz
SIGNAL-T O-NOISE AND DIST ORT ION
FIN = 10 kHz
FIN = 50 kHz
FIN = 100 kHz
72
78
73
67
72
78
73
67
72
78
73
67
dB
dB
dB
INT ERMODULAT ION DIST ORT ION
FIN1 = 49 kHz, FIN2 = 50 kHz
2nd Order Products
–77
–78
–77
–78
–77
–78
dB
dB
3rd Order Products
NOT E
1FIN amplitude = 0 dB and FSAMPLE = 500 kHz unless otherwise indicated.
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed although only those shown in boldface are tested.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
With
P IN CO NFIGURATIO N
Spec
Respect to
Min
Max
Unit
1
8
7
6
5
OUT
V
CC
AD781
TOP VIEW
(Not to Scale)
VCC
VEE
Common
Common
Common
Common
–0.3
–15
–0.5
–12
+15
+0.3
+7
V
V
V
V
IN
2
3
4
S/H
NC
COMMON
NC
Control Input
Analog Input
Output Short Circuit to
Ground, VCC, or VEE
Maximum Junction
T emperature
Storage
Lead T emperature
(10 sec max)
Power Dissipation
+12
V
EE
Indefinite
O RD ERING GUID E
+175 °C
+150 °C
–65
Tem perature
Range
P ackage
O ptions2
Model1
D escription
+300 °C
195 mW
AD781JN 0°C to +70°C
AD781AN –40°C to +85°C
AD781SQ –55°C to +125°C 8-Pin Cerdip
8-Pin Plastic DIP N-8
8-Pin Plastic DIP N-8
*Stresses above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. T his is a stress rating only and functional opera-
tion of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
Q-8
NOT ES
1For details on grade and package offerings screened in accordance with
MIL-ST D-883, refer to the Analog Devices Military Products Databook or
current AD781/883B data sheet.
2N = Plastic DIP; Q = Cerdip.
CAUTIO N
ESD (electrostatic discharge) sensitive device. T he digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD781
80
70
60
50
40
30
20
10
–10
–15
–20
–25
–30
10.0
1.0
V+
V–
0.1
0.01
0.001
0
1
10
100
1k
10k
100k
1M
0
100
25
50
75
100
125
150
1k
10k
100k
1M
FREQUENCY – Hz
TEMPERATURE – °C
FREQUENCY – Hz
Power Supply Rejection Ratio vs.
Frequency
Droop Rate vs. Tem perature,
VIN = 0 V
Effective Aperture Delay vs.
Frequency
5
4
3
5
200
150
100
50
4
3
2
1
0
–50
–100
–150
–200
2
1
–75 –50 –25
0
25 50 75 100 125 150
±10
±11
±12
±13
±14
±15
–10
–5
0
5
10
TEMPERATURE – °C
SUPPLY VOLTAGE – V
INPUT VOLTAGE – V
Bias Current vs. Input Voltage
Supply Current vs. Tem perature
Supply Current vs. Supply Voltage
1000
750
500
250
0
0
2
4
6
8
10
INPUT STEP – V
Acquisition Tim e (to 0.01%) vs.
Input Step Size
–4–
REV. A
AD781
D EFINITIO NS O F SP ECIFICATIO NS
Signal-To-Noise and D istor tion (S/N+D ) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. T he value for
S/N+D is expressed in decibels.
Acquisition Tim e—T he length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Sm all Signal Bandwidth—T he frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Total H ar m onic D istor tion (TH D )—T HD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed as a percentage or
in decibels.
Full P ower Bandwidth—T he frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Inter m odulation D istor tion (IMD )—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa±nfb, where m, n = 0, 1, 2,
3.... Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). T he IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. T he two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. T he IMD products are normalized to a 0 dB input signal.
Effective Aper tur e D elay—T he difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. T his effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aper tur e Jitter—T he variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
H old Settling Tim e—T he time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
FUNCTIO NAL D ESCRIP TIO N
T he AD781 is a complete sample-and hold amplifier that
provides high speed sampling to 12-bit accuracy in less than
700 ns.
D r oop Rate—T he drift in output voltage while in the hold
mode.
Feedthr ough—T he attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
T he AD781 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or
adjustments to perform the sampling function. Both input and
output are treated as a single-ended signal, referred to common.
H old Mode O ffset—T he difference between the input signal
and the held output. T his offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
T he AD781 utilizes a proprietary circuit design which includes a
self-correcting architecture. T his sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD781.
Tr acking Mode O ffset—T he difference between the input and
output signals when the SHA is in the track mode.
Nonlinear ity--T he deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Gain Er r or—Deviation from a gain of +1 on the transfer
function of input vs. held output.
P ower Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
1
2
3
4
8
7
6
5
OUT
V
CC
IN
COMMON
NC
S/H
NC
Sam pled D C Uncer tainty—T he internal rms SHA noise that
is sampled onto the hold capacitor.
X1
H old Mode Noise—T he rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
V
AD781
EE
Total O utput Noise—T he total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Functional Block Diagram
O utput D r ive Cur r ent—T he maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
REV. A
–5–
AD781
D YNAMIC P ERFO RMANCE
(V
OUT
HOLD – V ), mV
IN
T he AD781 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. T he fast acquisition time, fast
hold settling time and good output drive capability allow the
AD781 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. T he AD781’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. T ypically, the sample and hold can
acquire a 10 V step in less than 600 ns. Figure 1 shows the
settling accuracy as a function of acquisition time.
+1
V
, VOLTS
+5
IN
–4
–3
–2
3
–5
–1
2
1
4
HOLD MODE OFFSET
0.08
0.06
0.04
–1
GAIN ERROR
NONLINEARITY
Figure 3. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). T he offset will
change less than 0.5 mV over the specified temperature range.
0.02
0
500
750
1000
250
0
ACQUISITION TIME – ns
Figure 1. VOUT Settling vs. Acquisition Tim e
SUP P LY D ECO UP LING AND GRO UND ING
CO NSID ERATIO NS
T he hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. T he typical settling behavior of the AD781 is shown
in Figure 2. T he settling time of the AD781 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from exces-
sive high frequency noise (ripple). T he supply connection to the
AD781 should also be capable of delivering transient currents to
the device. T o achieve the specified accuracy and dynamic per-
formance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
0.1 µF capacitors should be connected from VCC and VEE to
common.
ANALOG
P.S.
DIGITAL
P.S.
–12V
+5V
C
C
+12V
0.1µF 0.1µF
1µF
1µF
1µF
+
INPUTS
7
9
11 15
1
DIGITAL
DATA
AD781
Figure 2. Typical AD781 Hold Mode
AD674
OUTPUT
H O LD MO D E O FFSET
SIGNAL GROUND
T he dc accuracy of the AD781 is determined primarily by the
hold mode offset. T he hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. T he hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. T he nominal hold
mode offset is specified for a 0 V input condition. Over the
input range of –5 V to +5 V, the AD781 is also characterized for
an effective gain error and nonlinearity of the held value, as
shown in Figure 3. As indicated by the AD781 specifications,
the hold mode offset is very stable over temperature.
Figure 4. Basic Grounding and Decoupling Diagram
T he AD781 does not provide separate analog and digital ground
leads as is the case with most A-to-D converters. T he common
pin is the single ground terminal for the device. It is the refer-
ence point for the sampled input voltage and the held output
voltage and also the digital ground return path. T he common
pin should be connected to the reference (analog) ground of the
A-to-D converter with a separate ground lead. Since the analog
and digital grounds in the AD781 are connected internally, the
–6–
REV. A
AD781
common pin should also be connected to the digital ground,
which is usually tied to analog common at the A-to-D converter.
Figure 4 illustrates the recommended decoupling and grounding
practice.
Measurements of Figures 7 and 8 were made using a 14-bit A/D
converter with VIN = 10 V p-p and a sample frequency of
100 kSPS.
1%
NO ISE CH ARACTERISTICS
1/2 BIT @
8 BITS
Designers of data conversion circuits must also consider the
effect of noise sources on the accuracy of the data acquisition
system. A sample-and-hold amplifier that precedes the A-to-D
converter introduces some noise and represents another source
of uncertainty in the conversion process. T he noise from the
AD781 is specified as the total output noise, which includes
both the sampled wideband noise of the SHA in addition to the
band limited output noise. T he total output noise is the rms
sum of the sampled dc uncertainty and the hold mode noise. A
plot of the total output noise vs. the equivalent input bandwidth
of the converter being used is given in Figure 5.
0.1%
1/2 BIT @
10 BITS
1/2 BIT @
12 BITS
0.01%
1/2 BIT @
14 BITS
APERTURE JITTER TYPICAL AT 50ps
1k
10k
100k
1M
300
200
100
0
FREQUENCY – Hz
Figure 6. Error Magnitude vs. Frequency
–65
–70
–75
–80
–85
–90
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 5. RMS Noise vs. Input Bandwidth of ADC
–95
100
1k
100k
1M
10k
D RIVING TH E ANALO G INP UTS
FREQUENCY – Hz
For best performance, it is important to drive the AD781 analog
input from a low impedance signal source. T his enhances the
sampling accuracy by minimizing the analog and digital
crosstalk. Signals which come from higher impedance sources
(e.g., over 5 kΩ) will have a relatively higher level of crosstalk.
For applications where signals have high source impedance, an
operational amplifier buffer in front of the AD781 is required.
T he AD711 (precision BiFET op amp) is recommended for
these applications.
Figure 7. Total Harm onic Distortion vs. Frequency
90
80
70
60
50
40
30
20
10
0
H IGH FREQ UENCY SAMP LING
Aperture jitter and distortion are the primary factors which limit
frequency domain performance of a sample-and-hold amplifier.
Aperture jitter modulates the phase of the hold command and
produces an effective noise on the sampled analog input. T he
magnitude of the jitter induced noise is directly related to the
frequency of the input signal.
100
1k
10k
100k
A graph showing the magnitude of the jitter induced error vs.
frequency of the input signal is given in Figure 6.
FREQUENCY – Hz
Figure 8. Signal/(Noise and Distortion) vs. Frequency
T he accuracy in sampling high frequency signals is also con-
strained by the distortion and noise created by the sample-and
hold. T he level of distortion increases with frequency and re-
duces the “effective number of bits” of the conversion.
REV. A
–7–
AD781
20
AD 781 TO AD 674 INTERFACE
Figure 9 shows a typical data acquisition circuit using the
AD781, a high linearity, low aperture jitter SHA and the AD674
a 12-bit high speed ADC. T he time between the AD674 status
line going high and the actual start of conversion allows the
AD781 to settle to 0.01%. As a result, the AD674 status line
can be used to control the AD781; only an inverter is needed to
interface the two devices.
0
–20
–40
–60
–80
STATUS
–100
–120
+5V
0.1µF
7404
OR EQUIV.
+12V
1
2
6
CE 12/8
STS
V
–140
L
30
33
0
3
7
10
13
16
20
26
23
28
0.1µF
FREQUENCY BINS – kHz
15 DGND
7
1
3
Figure 10. FFT Plot of AD781 to AD674 Interface,
FIN = 1 kHz
CS
V
CC
4
6
S/H
NC
NC
A
4
AD674
0
IN
V
2
3
OUT
IN
8
13
14
10 V
20 V
IN
16
27
12-BIT
THREE-STATE
DATA
AD781
EE
GND
NC
D0–11
IN
V
5
GAIN
10
REF IN
0.1µF
100Ω
100Ω
–12V
8
REF OUT
BIP OFFSET
12
OFFSET
5
9
CONVERT
R/C
AGND
11
7
+12V
4.7µF
–12V
0.1µF
0.1µF
4.7µF
Figure 9. AD781 to AD674 Interface
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Cerdip (Q) P ackage
Mini-D IP (N) P ackage
–8–
REV. A
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