AD7846JP [ADI]
LC2MOS 16-Bit Voltage Output DAC; LC2MOS 16位电压输出DAC
| 型号： | AD7846JP |
| 厂家： | 
ADI |
| 描述： | LC2MOS 16-Bit Voltage Output DAC |
| 文件： | 总16页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
16-Bit Voltage Output DAC
a
AD7846
FEATURES
FUNCTIONAL BLOCK DIAGRAM
16-Bit Monotonicity over Temperature
؎2 LSBs Integral Linearity Error
Microprocessor Compatible with Readback Capability
Unipolar or Bipolar Output
Multiplying Capability
Low Power (100 mW Typical)
V
V
DD
CC
V
REF +
AD7846
R
R
R
R
R
R
V
A2
A1
IN
16
SEGMENT
SWITCH
MATRIX
A3
OUT
12-BIT DAC
12
CS
V
REF –
DAC LATCH
12
4
R/ W
LDAC
CLR
CONTROL
LOGIC
I/O LATCH
V
DB15 DB0
DGND
SS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7846 is a 16-bit DAC constructed with Analog Devices’
LC2MOS process. It has VREF+ and VREF– reference inputs and
an on-chip output amplifier. These can be configured to give a
unipolar output range (0 V to +5 V, 0 V to +10 V) or bipolar
output ranges ( 5 V, 10 V).
1. 16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature makes
the AD7846 ideal for closed-loop applications.
2. Readback
The ability to read back the DAC register contents minimizes
software routines when the AD7846 is used in ATE systems.
The DAC uses a segmented architecture. The 4 MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral
linearity results from tight matching between the input offset
voltages of the two buffer amplifiers.
3. Power Dissipation
Power dissipation of 100 mW makes the AD7846 the lowest
power, high accuracy DAC on the market.
In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor interface. There are
16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR).
R/W and CS allow writing to and reading from the I/O latch.
This is the readback function which is useful in ATE applica-
tions. LDAC allows simultaneous updating of DACs in a multi-
DAC system and the CLR line will reset the contents of the
DAC latch to 00 . . . 000 or 10 . . . 000 depending on the state
of R/W. This means that the DAC output can be reset to 0 V in
both the unipolar and bipolar configurations.
The AD7846 is available in 28-lead plastic, ceramic, and PLCC
packages.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V.
OUT loaded with 2 k⍀, 1000 pF to 0 V; VREF+ = +5 V; RIN connected to 0 V. All
specifications TMIN to TMAX, unless otherwise noted.)
V
AD7846–SPECIFICATIONS1
Parameter
J, A Versions
K, B Versions
Unit
Test Conditions/Comments
RESOLUTION
16
16
Bits
UNIPOLAR OUTPUT
Relative Accuracy @ +25°C
TMIN to TMAX
VREF– = 0 V, VOUT = 0 V to +10 V
1 LSB = 153 µV
12
16
1
4
8
0.5
LSB typ
LSB max
LSB max
Differential Nonlinearity Error
All Grades Guaranteed Monotonic
Gain Error @ +25°C
12
16
12
16
1
6
16
6
16
1
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/°C typ
ppm FSR/°C typ
VOUT Load = 10 MΩ
T
MIN to TMAX
Offset Error @ +25°C
TMIN to TMAX
Gain TC2
Offset TC2
1
1
BIPOLAR OUTPUT
VREF– = –5 V, VOUT = –10 V to +10 V
1 LSB = 305 µV
Relative Accuracy @ +25°C
6
8
2
4
LSB typ
LSB max
T
MIN to TMAX
Differential Nonlinearity Error
Gain Error @ +25°C
TMIN to TMAX
Offset Error @ +25°C
TMIN to TMAX
1
6
16
6
16
6
12
1
1
0.5
4
16
4
12
4
8
1
1
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/°C typ
ppm FSR/°C typ
ppm FSR/°C typ
All Grades Guaranteed Monotonic
V
OUT Load = 10 MΩ
V
OUT Load = 10 MΩ
Bipolar Zero Error @ +25°C
T
MIN to TMAX
Gain TC2
Offset TC2
Bipolar Zero TC2
1
1
REFERENCE INPUT
Input Resistance
20
40
20
40
kΩ min
kΩ max
Volts
Resistance from VREF+ to VREF–
Typically 30 kΩ
V
V
REF+ Range
REF– Range
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
Volts
OUTPUT CHARACTERISTICS
Output Voltage Swing
VSS + 4 to
VSS + 4 to
VDD – 3
2
1000
0.3
V max
V
DD – 3
Resistive Load
2
kΩ min
pF max
Ω typ
To 0 V
To 0 V
Capacitive Load
Output Resistance
Short Circuit Current
1000
0.3
25
25
mA typ
To 0 V or Any Power Supply
DIGITAL INPUTS
V
IH (Input High Voltage)
2.4
0.8
10
2.4
0.8
10
V min
VIL (Input Low Voltage)
IIN (Input Current)
V max
µA max
pF max
CIN (Input Capacitance)2
10
10
DIGITAL OUTPUTS
VOL (Output Low Voltage)
VOH (Output High Voltage)
Floating State Leakage Current
Floating State Output Capacitance2
0.4
4.0
10
0.4
4.0
10
Volts max
Volts min
µA max
ISINK = 1.6 mA
ISOURCE = 400 µA
DB0–DB15 = 0 to VCC
10
10
pF max
POWER REQUIREMENTS3
VDD
VSS
VCC
IDD
+11.4/+15.75
–11.4/–15.75
+4.75/+5.25
5
+11.4/+15.75
–11.4/–15.75
+4.75/+5.25
5
V min/V max
V min/V max
V min/V max
mA max
VOUT Unloaded
VOUT Unloaded
ISS
ICC
5
1
1.5
100
5
1
1.5
100
mA max
mA max
LSB/V max
mW typ
Power Supply Sensitivity4
Power Dissipation
VOUT Unloaded
NOTES
1Temperature ranges as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°C
2Guaranteed by design and characterization, not production tested.
3The AD7846 is functional with power supplies of 12 V. See Typical Performance Curves.
4Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD, VSS variations.
Specifications subject to change without notice.
–2–
REV. E
AD7846
These characteristics are included for design guidance and are not
subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V
to –15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V.)
AC PERFORMANCE CHARACTERISTICS
Limit at
TMIN to TMAX
(All Versions)
Parameter
Unit
Test Conditions/Comments
Output Settling Time1
6
9
7
µs max
µs max
V/µs typ
To 0.006% FSR. VOUT loaded. VREF– = 0 V. Typically 3.5 µs.
To 0.003% FSR. VOUT loaded. VREF– = –5 V. Typically 6.5 µs.
Slew Rate
Digital-to-Analog Glitch
Impulse
70
0.5
10
50
nV-secs typ
mV pk-pk typ
nV-secs typ
nV/√Hz typ
DAC alternately loaded with 10 . . . 0000 and
01 . . . 1111. VOUT unloaded.
VREF– = 0 V, VREF+ = 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s.
AC Feedthrough
Digital Feedthrough
Output Noise Voltage
Density 1 kHz–100 kHz
DAC alternately loaded with all 1s and all 0s. CS High.
Measured at VOUT. DAC loaded with 0111011 . . . 11.
VREF+ = VREF– = 0 V.
NOTES
1LDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ).
Specifications subject to change without notice.
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)
TIMING CHARACTERISTICS
Parameter
Limit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
0
60
0
60
0
120
10
60
0
70
0
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
R/W to CS Setup Time
CS Pulsewidth (Write Cycle)
R/W to CS Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Bus Relinquish Time
t8
t9
t10
t11
t12
CLR Setup Time
CLR Pulsewidth
CLR Hold Time
LDAC Pulsewidth
CS Pulsewidth (Read Cycle)
70
130
NOTES
1Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.
2t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
5V
3k⍀
DBN
DBN
100pF
DGND
100pF
3k⍀
DGND
t1
t3
t1
t3
5V
0V
R/ W
a. High Z to VOH
b. High Z to VOL
t12
t2
t4
5V
0V
CS
Figure 1. Load Circuits for Access Time (t6)
t5
t6
t7
5V
5V
0V
5V
DATA
DATA VALID
DATA VALID
3k⍀
t8
t9
t8
tt
9
t10
t10
DBN
DBN
10pF
10pF
3k⍀
DGND
CLR
0V
DGND
t11
5V
0V
LDAC
a. VOH to High Z
Figure 2. Load Circuits for Bus Relinquish Time (t7)
b. VOL to High Z
Figure 3. Timing Diagram
REV. E
–3–
AD7846
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +17 V
V
CC to DGND . . . . . . . . . . . . . . . –0.4 V, VDD + 0.4 V or +7 V
(Whichever Is Lower)
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –17 V
REF+ to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
V
2VOUT may be shorted to DGND, VDD, VSS, VCC provided that the power dissipation
of the package is not exceeded.
VREF– to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
V
OUT to DGND2 . . . . . . . . VDD + 0.4 V, VSS – 0.4 V or 10 V
(Whichever Is Lower)
RIN to DGND . . . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
Digital Input Voltage to DGND . . . . . . –0.4 V to VCC + 0.4 V
Digital Output Voltage to DGND . . . . . –0.4 V to VCC + 0.4 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Operating Temperature Range
J, K Versions . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . +300°C
ORDERING GUIDE
Model
Temperature Range
Relative Accuracy
Package Description
Package Options
AD7846JN
AD7846KN
AD7846JP
AD7846KP
AD7846AP
AD7846AQ
AD7846BP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16 LSB
8 LSB
16 LSB
8 LSB
16 LSB
16 LSB
8 LSB
Plastic DIP
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Plastic Leaded Chip Carrier (PLCC)
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP
N-28A
N-28A
P-28A
P-28A
P-28A
Q-28
Plastic Leaded Chip Carrier (PLCC)
P-28A
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
Offset Error
TERMINOLOGY
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
LEAST SIGNIFICANT BIT
This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7846, 1 LSB = (VREF+ – VREF–)/216.
Bipolar Zero Error
Relative Accuracy
When the AD7846 is connected for bipolar output and 10 . . . 000
is loaded to the DAC, the deviation of the analog output from the
ideal midscale of 0 V is called the bipolar zero error.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after adjust-
ing for both endpoints (i.e., offset and gain errors are adjusted
out) and is normally expressed in least significant bits or as a
percentage of full-scale range.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or a
voltage.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of 1 LSB over the operating
temperature range ensures monotonicity.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
Gain Error
Digital Feedthrough
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
When the DAC is not selected (i.e., CS is held high), high fre-
quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
–4–
REV. E
AD7846
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
DIP
Pin
Mnemonic
Description
1–3
4
DB2–DB0
VDD
Data I/O pins. DB0 is LSB.
Positive supply for analog circuitry. This is
+15 V nominal.
DB2
DB1
DB0
DB3
DB4
DB5
1
2
28
27
26
25
24
23
22
21
5
6
VOUT
RIN
DAC output voltage pin.
3
Input to summing resistor of DAC output
amplifier. This is used to select output
voltage ranges. See Table I.
V
4
LDAC
CLR
CS
DD
V
5
OUT
R
6
IN
AD7846
TOP VIEW
(Not to Scale)
7
8
VREF+
VREF–
VREF+ Input. The DAC is specified for VREF+
= +5 V.
V
V
7
R/W
REF+
8
V
REF–
CC
9
V
20 DGND
VREF– Input. For unipolar operation con-
nect VREF– to 0 V and for bipolar operation
connect it to –5 V. The device is specified
for both conditions.
SS
10
11
12
13
14
19
DB15
DB14
DB13
DB12
DB11
DB6
18
DB7
17
DB8
16
DB9
9
VSS
Negative supply for the analog circuitry.
This is –15 V nominal.
15
DB10
10–19 DB15–DB6
Data I/O pins. DB15 is MSB.
Ground pin for digital circuitry.
20
21
DGND
VCC
Positive supply for digital circuitry. This is
+5 V nominal.
PLCC
22
R/W
R/W input. This can be used to load data to
the DAC or to read back the DAC latch
contents.
4
3
2
1
28 27 26
23
24
CS
Chip select input. This selects the device.
CLR
Clear input. The DAC can be cleared to
000 . . . 000 or 100 . . . 000. See Table II.
PIN 1
IDENTIFIER
V
5
6
7
8
9
25
24
23
22
21
LDAC
CLR
CS
OUT
R
IN
V
V
REF+
25
LDAC
Asynchronous load input to DAC.
Data I/O pins.
AD7846
TOP VIEW
(Not to Scale)
R/W
REF–
26–28 DB5–DB3
V
V
SS
CC
DB15 10
DB14 11
20 DGND
19 DB6
Table I. Output Voltage Ranges
12 13 14 15 16 17 18
Output Range
VREF+
VREF–
RIN
0 V to +5 V
+5 V
+5 V
+5 V
+5 V
+5 V
0 V
0 V
–5 V
0 V
–5 V
VOUT
0 V
VOUT
+5 V
0 V
0 V to +10 V
+5 V to –5 V
+5 V to –5 V
+10 V to –10 V
REV. E
–5–
AD7846–Typical Performance Curves
8
30
V
V
V
V
= +15V
= –15V
DD
SS
V
V
V
V
= +15V
= –15V
DD
SS
= ؎5V SINE WAVE
REF+
= +1Vrms
= 0V
REF+
= 0V
6
4
2
0
REF–
REF–
GAIN = +2
20
10
0
1
2
3
4
5
6
7
2
3
4
5
6
10
10
10
10
10
10
10
10
10
10
10
10
FREQUENCY – Hz
FREQUENCY – Hz
Figure 6. Large Signal Frequency
Response
Figure 5. AC Feedthrough vs.
Frequency
Figure 4. AC Feedthrough. VREF+
1 V rms, 10 kHz Sine Wave
=
500
V
= V = 0V
REF–
REF+
GAIN = +1
DAC LOADED WITH ALL 1s
400
50mV/DIV
V
50mV/DIV
OUT
V
OUT
300
200
LDAC
5V/DIV
5V/DIV
100
0
DATA
DATA
5V/DIV
2
3
4
5
6
10
10
10
10
10
1s/DIV
0.5s/DIV
FREQUENCY – Hz
Figure 9. Digital-to-Analog Glitch
Impulse With Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)
Figure 7. Noise Spectral Density
Figure 8. Digital-to-Analog Glitch
Impulse Without Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)
Figure 12. Spectral Response of
Digitally Constructed Sine Wave
Figure 11. Pulse Response
(Small Signal)
Figure 10. Pulse Response
(Large Signal)
–6–
REV. E
AD7846
1.0
0.8
4.0
3.5
3.0
T = +25؇C
A
T
V
V
= +25؇C
A
V
V
= +5V
= 0V
= +5V
= 0V
REF+
REF+
REF–
REF–
GAIN = +1
GAIN = +1
0.6
0.4
2.5
2.0
1.5
0.2
0
1.0
0.5
11
12
13
14
15
16
11
12
13
14
15
16
V
/V – Volts
V
/V – Volts
DD SS
DD SS
Figure 14. Typical Monotonicity vs.
DD/VSS
Figure 13. Typical Linearity vs. VDD/VSS
V
CIRCUIT DESCRIPTION
Digital Section
Table II. Control Logic Truth Table
R/W LDAC CLR Function
CS
Figure 15 shows the digital control logic and on-chip data
latches in the AD7846. Table II is the associated truth table.
The D/A converter has two latches that are controlled by four
signals: CS, R/W, LDAC and CLR. The input latch is con-
nected to the data bus (DB15–DB0). A word is written to the
input latch by bringing CS low and R/W low. The contents of
the input latch may be read back by bringing CS low and R/W
high. This feature is called “readback” and is used in system
diagnostic and calibration routines.
1
X
X
X
X
0
X
X
X
1
3-State DAC I/O Latch in High-
Z State
DAC I/O Latch Loaded with
DB15–DB0
Contents of DAC I/O Latch
Available on DB15–DB0
Contents of DAC I/O Latch
Transferred to DAC Latch
DAC Latch Loaded with
000 . . . 000
DAC Latch Loaded with
100 . . . 000
0
0
0
1
X
X
X
X
0
X
X
0
Data is transferred from the input latch to the DAC latch with
the LDAC strobe. The equivalent analog value of the DAC
latch contents appears at the DAC output. The CLR pin resets
the DAC latch contents to 000 . . . 000 or 100 . . . 000, depend-
ing on the state of R/W. Writing a CLR loads 000 . . . 000 and
reading a CLR loads 100 . . . 000. To reset a DAC to 0 V in a
unipolar system the user should exercise CLR while R/W is low;
to reset to 0 V in a bipolar system exercise the CLR while R/W
is high.
1
0
D/A Conversion
Figure 16 shows the D/A section of the AD7846. There are
three DACs, each of which have their own buffer amplifiers.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage refer-
ence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
R/W
CLR
The 4 MSBs of the 16-bit digital code drive DAC1 and DAC2
while the 12 LSBs control DAC3. Using DAC1 and DAC2, the
MSBs select a pair of adjacent nodes on the resistor string and
present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
DAC
16
DB15 RST
LDAC
DB15–DB0
LATCHES
DB15 SET
DB14–DB0
RST
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
For example, when switching from Segment 1 to Segment 2,
DAC1 switches from the bottom of Segment 1 to the top of
Segment 2 while DAC2 stays connected to the top of Segment
1. The code driving DAC3 is automatically complemented to
compensate for the inversion of its inputs. This means that any
linearity effects due to amplifier offset voltages remain un-
changed when switching from one segment to the next and
16-bit monotonicity is ensured if DAC3 is monotonic. So,
12-bit resistor matching in DAC3 guarantees overall 16-bit
monotonicity. This is much more achievable than the 16-bit
matching which a conventional R-2R structure would have
needed.
16
3-STATE I/O
LATCH
CS
16
DB15
DB0
Figure 15. Input Control Logic
REV. E
–7–
AD7846
V
REF+
SEGMENT 16
R
R
DAC1
DAC2
R
V
IN
S1
S3
S2
S4
DAC3
A1
A2
A3
OUT
12 BIT DAC
S15
S17
S14
S16
DB11–DB0
DB15–DB12
DB15–DB12
SEGMENT 1
V
REF–
Figure 16. D/A Conversion
+15V
+5V
Output Stage
The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 kΩ/1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
4
V
V
DD
CC
V
V
OUT
(0V TO +10V)
V
REF+
OUT
AD586
R1
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 µs
after the leading edge of LDAC. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.
10k⍀
AD7846*
C1
1F
R
IN
V
REF–
DGND
V
SS
SIGNAL
GROUND
*ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
Figure 18. Unipolar Binary Operation
Table III. Code Table for Figure 18
R
IN
10k⍀
10k⍀
Binary Number
in DAC Latch
Analog Output
(VOUT
)
C1
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0
V
OUT
DAC3
ONE
SHOT
NOTE
1 LSB = 10 V/216 = 10 V/65536 = 152 µV.
LDAC
Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the VREF– input from 0 V, load the
DAC with all 0s and adjust the VREF– voltage until VOUT = 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until VOUT = 10 (65535)/(65536) = 9.999847 V.
If a simple resistor divider is used to vary the VREF– voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (–300 ppm/°C). Other-
wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 8 (VREF– ) of the AD7846 tied to 0 V.
Figure 17. Output Stage
UNIPOLAR BINARY OPERATION
Figure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer-
ence. Since RIN is tied to 0 V, the output amplifier has a gain of
2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, RIN should be tied to VOUT, configuring the output
stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.
–8–
REV. E
AD7846
BIPOLAR OPERATION
Other Output Voltage Ranges
Figure 19 shows the AD7846 set up for 10 V bipolar opera-
tion. The AD588 provides precision 5 V tracking outputs
which are fed to the VREF+ and VREF– inputs of the AD7846.
The code table for Figure 19 is shown in Table IV.
In some cases, users may require output voltage ranges other
than those already mentioned. One example is systems which
need the output voltage to be a whole number of millivolts (i.e.,
1 mV, 2 mV, etc.). If the AD689 (8.192 V reference) is used
with the AD7846 as in Figure 20, then the LSB size is 125 µV.
This makes it possible to program whole millivolt values at the
Output. Table V shows the code table for Figure 20.
+15V
R1
+15V
+5V
39k⍀
4
+15V
+5V
V
V
DD
CC
+15V
V
C1
1F
OUT
V
V
OUT
REF+
(–10V TO +10V)
V
V
DD
CC
V
AD588
OUT
(0V TO 8.192V)
V
AD7846*
R2
10k⍀
OUT
V
REF+
R
IN
AD689
AD7846*
R
IN
V
REF–
DGND
SIGNAL
GROUND
–15V
V
V
DGND
REF–
SS
V
SS
SIGNAL GROUND
R3
100k⍀
*ADDITIONAL PINS
OMITTED FOR CLARITY
*ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
–15V
Figure 19. Bipolar 10 V Operation
Table IV. Offset Binary Code Table for Figure 19
Figure 20. Unipolar Output with AD689
Table V. Code Table for Figure 20
Binary Number
in DAC Latch
Analog Output
(VOUT
Binary Number
in DAC Latch
Analog Output
(VOUT
)
)
MSB
LSB
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+10 (32767/32768) V
+10 (1/32768) V
0 V
–10 (1/32768) V
–10 (32768/32768) V
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 1000
0000 0000 0000 0100
0000 0000 0000 0010
0000 0000 0000 0001
8.192 V (65535/65536) = 8.1919 V
8.192 V (32768/65536) = 4.096 V
8.192 V (8/65536) = 0.001 V
8.192 V (4/65536) = 0.0005 V
8.192 V (2/65536) = 0.00025 V
8.192 V (1/65536) = 0.000125 V
NOTE
1 LSB = 10 V/215 = 10 V/32768 = 305 µV.
NOTE
1 LSB = 8.192 V/2l6 = 125 µV.
Full scale and bipolar zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and –5 V outputs together
with respect to ground.
Multiplying Operation
The AD7846 is a full multiplying DAC. To get four-quadrant
multiplication, tie VREF– to 0 V, apply the ac input to VREF+ and
tie RIN to VREF+. Figure 6 shows the Large Signal Frequency
Response when the DAC is used in this fashion.
For bipolar zero adjustment on the AD7846, load the DAC with
100 . . . 000 and adjust R3 until VOUT = 0 V. Full scale is ad-
justed by loading the DAC with all 1s and adjusting R2 until
VOUT = 9.999694 V.
When bipolar zero and full scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating. If a user
wants a +5 V output range, there are two choices. By tying Pin
6 (RIN) of the AD7846 to VOUT (Pin 5), the output stage gain is
reduced to unity and the output range is 5 V. If only a positive
+5 V reference is available, bipolar 5 V operation is still pos-
sible. Tie VREF– to 0 V and connect RIN to VREF+. This will also
give a 5 V output range. However, the linearity, gain, and
offset error specifications will be the same as the unipolar 0 V to
+5 V range.
REV. E
–9–
AD7846
TEST APPLICATION
input or output. The AD345 is the pin driver for the digital
inputs, and the AD9687 is the receiver for the digital outputs.
The digital control circuitry determines the signal timing and
format.
Figure 21 shows the AD7846 in an Automatic Test Equipment
application. The readback feature of the AD7846 is very useful
in these systems. It allows the designer to eliminate phantom
memory used for storing DAC contents and increases system
reliability since the phantom memory is now effectively on chip
with the DAC. The readback feature is used in the following
manner to control a data transfer. First, write the desired 16-bit
word to the DAC input latch using the CS and R/W inputs.
Verify that correct data has been received by reading back the
latch contents. Now, the data transfer can be completed by
bringing the asynchronous LDAC control line low. The analog
equivalent of the digital word now appears at the DAC output.
In Figure 21, each pin on the Device Under Test can be an
DACs 1 and 2 set the pin driver voltage levels (VH and VL), and
DACs 3 and 4 set the receiver voltage levels. The pin drivers
used in ATE systems normally have a nonlinearity between
input and output. The 16-bit resolution of the AD7846 allows
compensation for these input/output nonlinearities. The dc
parametrics shown in Figure 21 measure the voltage at the
device pin and feed this back to the system processor. The pin
voltage can thus be fine-tuned by incrementing or decrementing
DACs 1 and 2 under system processor control.
DC PARAMETRICS
V
H
D
D
INH
STORED DATA
AND INHIBIT
PATTERN
DUT
FORMATTER
AD345
INH
V
L
PERIOD
GENERATION
AND DELAY
COMPARE
REGISTER
COMPARE DATA
AND DON'T
CARE DATA
AD9687
+15V
R1
39k⍀
DAC1
DAC2
DAC3
DAC4
AD7846
AD7846
AD7846
AD7846
V
V
V
V
OUT
OUT
OUT
OUT
V
V
V
V
REF+
REF+
REF+
REF+
AD588
R
R
R
R
IN
IN
IN
IN
V
V
V
V
REF–
REF–
REF–
REF–
DGND
DGND
DB15 DB0
DGND
DB15 DB0
DGND
DB15 DB0
DB15 DB0
–15V
Figure 21. Digital Test System with 16-Bit Performance
–10–
REV. E
AD7846
POSITION MEASUREMENT APPLICATION
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure
24, a 16-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought low, updating all the
DACs simultaneously.
Figure 22 shows the AD7846 in a position measurement appli-
cation using an LVDT (Linear Variable Displacement Trans-
ducer), an AD630 synchronous demodulator and a comparator
to make a 16-bit LVDT-to-Digital Converter. The LVDT is
excited with a fixed frequency and fixed amplitude sine wave
(usually 2.5 kHz, 2 V pk-pk). The outputs of the secondary coil
are in antiphase and their relative amplitudes depend on the
position of the core in the LVDT. The AD7846 output interpo-
lates between these two inputs in response to the DAC input
code. The AD630 is set up so that it rectifies the DAC output
signal. Thus, if the output of the DAC is in phase with the
VREF+ input, the inverting input to the comparator will be posi-
tive, and if it is in phase with VREF–, the output will be negative.
By turning on each bit of the DAC in succession starting with
the MSB, and deciding to leave it on or turn it off based on the
comparator output, a 16-bit measurement of the core position is
obtained.
ADDRESS BUS
ADDRESS
DECODE
CS
16-BIT
AD7846*
ALE
LATCH
8086
LDAC
DEN
RD
R/W
WR
+5V
CLR
DATA BUS
DB0–DB15
AD0–AD15
ASIN t
LVDT
x ASIN t
CS
V
V
OUT
REF+
AD7846*
R
IN
LDAC
AD7846*
R/W
+5V
V
CLR
REF–
–(1–x)ASIN t
DGND
DB0–DB15
DB15 DB0
SIGNAL
GROUND
CS
*ADDITIONAL PINS
OMITTED FOR CLARITY
PROCESSOR DATA BUS
AD7846*
LDAC
R/W
R1
AD630*
+5V
CLR
100k⍀
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
DB0–DB15
C1
1F
Figure 24. AD7846-to-8086 Interface: Multiple DAC System
TO
PROCESSOR PORT
AD7846-to-MC68000 Interface
Figure 22. AD7846 in Position Measurement Application
Interfacing between the AD7846 and MC68000 is accom-
plished using the circuit of Figure 25. The following routine
writes data to the DAC latches and then outputs the data via the
DAC latch.
MICROPROCESSOR INTERFACING
AD7846-to-8086 Interface
Figure 23 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used
in this circuit since LDAC is permanently tied to 0 V. AD0–
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0–DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is D000H.
1000
MOVE.W #W, D0
The desired DAC data, W,
is loaded into Data Regis-
ter 0. W may be any value
between 0 and 65535
(decimal) or 0 and FFFF
(hexadecimal).
MOVE.W D0, $E000 The data, W, is transferred
between D0 and the DAC
ADDRESS BUS
register.
ADDRESS
MOVE.W #228, D7
TRAP #14
Control is returned to the
System Monitor using
these two instructions.
CS
DECODE
16-BIT
LATCH
LDAC
ALE
8086
+5V
CLR
DEN
RD
AD7846*
R/W
WR
DATA BUS
AD0–AD15
DB0–DB15
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 23. AD7846-to-8086 Interface Circuit
REV. E
–11–
AD7846
A1–A23
ADDRESS BUS
ANALOG SUPPLY
DIGITAL SUPPLY
+5V DGND
+15V 0V –15V
MC68000
ADDRESS
DECODE
CS
DS
+5V
CLR
DTACK
LDAC
AD7846*
R/W
R1
R/W
SIGNAL
GROUND
DATA BUS
D0–D15
DB0–DB15
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
R2
R3
Figure 25. AD7846-to-MC68000 Interface
AD588*
AD7846*
R4
R
V
OUT
(+5V TO –5V)
DIGITAL FEEDTHROUGH
L
In the preceding interface configurations, most digital inputs to
the AD7846 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be con-
stantly changing. The high frequency logic activity on the bus
can feed through the DAC package capacitance to show up as
noise on the analog output. To minimize this Digital Feed-
through isolate the DAC from the noise source. Figure 26 shows
an interface circuit which isolates the DAC from the bus.
R5
*ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 27. AD7846 Grounding
R1 to R5 represent lead and track resistances on the printed
circuit board. R1 is the resistance between the Analog Power
Supply ground and the Signal Ground. Since current flowing in
R1 is very low (bias current of AD588 sense amplifier), the
effect of R1 is negligible. R2 and R3 represent track resistance
between the AD588 outputs and the AD7846 reference inputs.
Because of the Force and Sense outputs on the AD588, these
resistances will also have a negligible effect on accuracy.
A1–A15
ADDRESS BUS
ADDRESS
DECODE
CS
MICRO-
PROCESSOR
+5V
CLR
R4 is the resistance between the DAC output and the load. If
RL is constant, then R4 will introduce a gain error only which
can be trimmed out in the calibration cycle. R5 is the resistance
between the load and the analog common. If the output voltage
is sensed across the load, R5 will introduce a further gain error
which can be trimmed out. If, on the other hand, the output
voltage is sensed at the analog supply common, R5 appears as
part of the load and therefore introduces no errors.
LDAC
R/W
R/W
DIR
G
AD7846*
DATA BUS
B BUS A BUS
DB0–DB15
D0–D15
2
؋
74LS245
Printed Circuit Board Layout
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 28 shows the AD7846 in a typical application with the
AD588 reference, producing an output analog voltage in the
10 volts range. Full scale and bipolar zero adjustment are
provided by potentiometers R2 and R3. Latches (2 × 74LS245)
isolate the DAC digital inputs from the active microprocessor
bus and minimize digital feedthrough.
Figure 26. AD7846 Interface Circuit Using Latches to Mini-
mize Digital Feedthrough
Note that to make use of the AD7846 readback feature using
the isolation technique of Figure 26, the latch needs to be
bidirectional.
The printed circuit board layout for Figure 28 is shown in Fig-
ures 29 and 30. Figure 29 is the component side layout while
Figure 30 is the solder side layout. The component overlay is
shown in Figure 31.
APPLICATION HINTS
Noise
In high resolution systems, noise is often the limiting factor.
With a 10 volt span, a 16-bit LSB is 152 µV (–96 dB). Thus, the
noise floor must stay below –96 dB in the frequency range of
interest. Figure 7 shows the noise spectral density for the AD7846.
In the layout, the general grounding guidelines given in Figure
27 are followed. The AD588 and AD7846 are as close as pos-
sible, and the decoupling capacitors for these are also kept as
close to the device pins as possible.
Grounding
As well as noise, the other prime consideration in high resolu-
tion DAC systems is grounding. With an LSB size of 152 µV
and a load current of 5 mA, 1 LSB of error can be introduced
by series resistance of only 0.03 Ω.
Figure 27 below shows recommended grounding for the AD7846
in a typical application.
–12–
REV. E
AD7846
+15V
J1
C5
10F
C6
0.1F
+5V
C1
10F
C31/A31
C7
0.1F
R1
39k⍀
DB15
20
C2
0.1F
2
18
17
16
C4/A4
C5/A5
C6/A6
DB14
DB13
3
4
5
6
7
8
9
15
14
13
12
11
C12
1F
74LS245
DB12
DB11
DB10
DB9
C7/A7
C8/A8
C9/A9
V
REF+
C10/A10
C11/A11
AD7846
1
19
20
10
AD588
DB8
R2
100k⍀
+5V
DB7 18
V
REF–
2
3
4
18
17
16
–15V
C12/A12
C13/A13
C14/A14
19
DB6
DB5 26
27
V
SS
C4
0.1F
C3
10F
5
6
7
8
9
15
14
13
12
11
74LS245
DB4
DB3 28
C15/A15
C16/A16
C17/A17
C18/A18
C19/A19
C20/A20
1
2
3
DB2
DB1
DB0
10
DGND
1
19
R3
100k⍀
C21/A21
C22/A22
C23/A23
C32/A32
R
IN
R/W
CS
V
OUT
V
CLR
LDAC
OUT
(+10V TO –10V)
Figure 28. Schematic for AD7846 Board
REV. E
–13–
AD7846
Figure 29. PCB Component Side Layout for Figure 28
Figure 30. PCB Solder Side Layout for Figure 30
–14–
REV. E
AD7846
Figure 31. Component Overlay for Circuit of Figure 28
REV. E
–15–
AD7846
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic DIP (Q-28)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
0.610 (15.49)
0.500 (12.70)
1
14
0.620 (15.75)
0.590 (14.99)
PIN 1
0.015
(0.38)
MIN
0.150
(3.81)
MIN
1.490 (37.85) MAX
0.225
(5.72)
MAX
0.018 (0.46)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15°
0°
SEATING
PLANE
0.026 (0.66) 0.110 (2.79)
0.014 (0.36) 0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
28-Lead Plastic DIP (N-28A)
1.450 (36.83)
1.440 (35.576)
28
15
0.550 (13.97)
0.530 (13.462)
14
1
0.160 (4.06)
0.140 (3.56)
0.606 (15.39)
0.594 (15.09)
PIN 1
0.200
(5.080)
MAX
15°
0°
SEATING
PLANE
0.012 (0.306)
0.008 (0.203)
0.020 (0.508)
0.015 (0.381)
0.100
(2.54)
BSC
0.065 (1.65)
0.045 (1.14)
28-Lead Plastic Leaded Chip Carrier (PLCC)
(P-28A)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.056 (1.42)
0.042 (1.07)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
4
26
25
5
PIN 1
IDENTIFIER
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
19
12
18
SQ
SQ
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
0.110 (2.79)
0.085 (2.16)
–16–
REV. E
相关型号：
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