AD7847ARZ [ADI]
LC2MOS Complete, Dual 12-Bit MDACs; LC2MOS完成,双12位MDACs型号: | AD7847ARZ |
厂家: | ADI |
描述: | LC2MOS Complete, Dual 12-Bit MDACs |
文件: | 总12页 (文件大小:494K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AD7837/AD7847–SPECIFICATIONS1
(VDD = +15 V ꢀ 5%, VSS = –15 V ꢀ 5%, AGNDA = AGNDB = DGND
= O V. VREFA = VREFB = +10 V, RL = 2 kꢁ, CL = 100 pF [VOUT connected to RFB AD7837]. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version
B Version
S Version
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
12
1
1
12
1/2
1
12
1
1
Bits
LSB max
LSB max
Relative Accuracy2
Differential Nonlinearity2
Zero Code Offset Error2
@ +25°C
Guaranteed Monotonic
2
4
2
3
2
4
mV max
mV max
DAC Latch Loaded with All 0s
Temperature Coefficient = 5 µV/°C typ
TMIN to TMAX
Gain Error2
@ +25°C
TMIN to TMAX
4
5
2
3
4
5
LSB max
LSB max
DAC Latch Loaded with All 1s
Temperature Coefficient = 2 ppm of
FSR/°C typ
REFERENCE INPUTS
VREF Input Resistance
VREFA, VREFB Resistance Matching
8/13
2
8/13
2
8/13
2
kΩ min/max
% max
Typical Input Resistance = 10 kΩ
Typically 0.25%
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
1
2.4
0.8
1
2.4
0.8
1
V min
V max
µA max
pF max
Digital Inputs at 0 V and VDD
VOUT Connected to AGND
Input Capacitance3
8
8
8
ANALOG OUTPUTS
DC Output Impedance
Short Circuit Current
0.2
11
0.2
11
0.2
11
Ω typ
mA typ
POWER REQUIREMENTS4
VDD Range
14.25/15.75
14.25/15.75
14.25/15.75
V min/max
V
SS Range
–14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max
Power Supply Rejection
∆Gain/∆VDD
∆Gain/∆VSS
IDD
0.01
0.01
0.01
0.01
0.01
0.01
% per % max
% per % max
mA max
VDD = 15 V 5%, VREF = –10 V
VSS = –15 V 5%, VREF = +10 V
Outputs Unloaded. Inputs at Thresholds.
Typically 5 mA
Outputs Unloaded. Inputs at Thresholds.
Typically 3 mA
8
6
8
6
8
6
ISS
mA max
AC CHARACTERISTICS2, 3
Voltage Output Settling Time
3
5
3
5
3
5
µs typ
µs max
Settling Time to Within 1/2 LSB of Final
Value. DAC Latch Alternately Loaded
with All 0s and All 1s
Slew Rate
Digital-to-Analog Glitch Impulse
Channel-to-Channel Isolation
11
10
11
10
11
10
V/µs typ
nV secs typ
1 LSB Change Around Major Carry
V
REFA to VOUTB
–95
–95
–90
750
175
–88
1
–95
–95
–90
750
175
–88
1
–95
–95
–90
750
175
–88
1
dB typ
VREFA = 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
VREFB = 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
VREF = 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
VREF = 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
VREF = 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
VREF = 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
VREFB to VOUTA
dB typ
Multiplying Feedthrough Error
Unity Gain Small Signal BW
Full Power BW
dB typ
kHz typ
kHz typ
dB typ
Total Harmonic Distortion
Digital Crosstalk
nV secs typ
Code Transition from All 0s to All 1s and
Vice Versa
Output Noise Voltage @ +25°C
(0.1 Hz to 10 Hz)
Digital Feedthrough
See Typical Performance Graphs
Amplifier Noise and Johnson Noise of RFB
2
1
2
1
2
1
µV rms typ
nV secs typ
NOTES
1Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4The Devices are functional with VDD/VSS
=
12 V (See typical performance graphs.).
Specifications subject to change without notice.
–2–
REV. C
AD7837/AD7847
TIMING CHARACTERISTICS1, 2, 3 (VDD = +15 V ꢀ 5%, VSS = –15 V ꢀ 5%, AGNDA = AGNDB = DGND = O V)
Limit at TMIN, TMAX
(All Versions)
Parameter
Unit
Conditions/Comments
t1
t2
t3
t4
t54
t64
t74
t8
0
0
30
80
0
0
0
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Address to WR Setup Time
Address to WR Hold Time
LDAC Pulsewidth
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 3 and 5.
3Guaranteed by design and characterization, not production tested.
4AD7837 only.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
ORDERING GUIDE
Temperature Relative
Package
Option2
VDD to DGND, AGNDA, AGNDB . . . . . . . –0.3 V to +17 V
VSS1 to DGND, AGNDA, AGNDB . . . . . . . +0.3 V to –17 V
Model1
Range
Accuracy
V
REFA, VREFB to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
AD7837AN
AD7837BN
AD7837AR
AD7837BR
AD7837AQ
AD7837BQ
AD7837SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
AGNDA, AGNDB to DGND . . . . . . . –0.3 V to VDD + 0.3 V
VOUTA2, VOUTB2 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
RFBA3, RFBB3 to AGNDA, AGNDB
. . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial/Industrial (A, B Versions) . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
AD7847AN
AD7847BN
AD7847AR
AD7847BR
AD7847AQ
AD7847BQ
AD7847SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
NOTES
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
2N = Plastic DIP; Q = Cerdip; R = SOIC.
1If VSS is open circuited with VDD and either AGND applied, the VSS pin will float
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode connected between VSS and AGND (cathode to AGND) ensures
the Maximum Ratings will be observed.
2The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded.
3AD7837 only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD7837/AD7847
Channel-to-Channel Isolation
TERMINOLOGY
This is an ac error due to capacitive feedthrough from the VREF
input on one DAC to VOUT on the other DAC. It is measured
with the DAC latches loaded with all 0s.
Relative Accuracy (Linearity)
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints. It is measured after
allowing for zero and full-scale errors and is expressed in LSBs
or as a percentage of full-scale reading.
Digital Feedthrough
Digital feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the data inputs change state,
but the data in the DAC latches is not changed.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB or less
over the operating temperature range ensures monotonicity.
For the AD7837, it is measured with LDAC held high. For the
AD7847, it is measured with CSA and CSB held high.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in digital code on the DAC
latch of the other converter. It is specified in nV secs.
Zero Code Offset Error
Zero code offset error is the error in output voltage from VOUTA
or VOUTB with all 0s loaded into the DAC latches. It is due to a
combination of the DAC leakage current and offset errors in the
output amplifier.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at the output of the DAC
when the digital code changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs and is
measured for a 1 LSB change around the major carry transition
(0111 1111 1111 to 1000 0000 0000 and vice versa).
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded. It does
not include offset error.
Unity Gain Small Signal Bandwidth
Total Harmonic Distortion
This is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.
This is the frequency at which the small signal voltage output
from the output amplifier is 3 dB below its dc level. It is mea-
sured with the DAC latch loaded with all 1s.
Multiplying Feedthrough Error
Full Power Bandwidth
This is an ac error due to capacitive feedthrough from the VREF
input to VOUT of the same DAC when the DAC latch is loaded
with all 0s.
This is the maximum frequency for which a sinusoidal input
signal will produce full output at rated load with a distortion
less than 3%. It is measured with the DAC latch loaded with
all 1s.
AD7837 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
Description
Pin
Mnemonic
1
2
3
4
5
6
CS
Chip Select. Active low logic input. The device is selected when this input is active.
Amplifier Feedback Resistor for DAC A.
Reference Input Voltage for DAC A. This may be an ac or dc signal.
Analog Output Voltage from DAC A.
Analog Ground for DAC A.
Positive Power Supply.
RFBA
VREFA
VOUTA
AGNDA
VDD
7
VSS
Negative Power Supply.
8
9
10
11
12
13
AGNDB
VOUTB
VREFB
DGND
RFBB
Analog Ground for DAC B.
Analog Output Voltage from DAC B.
Reference Input Voltage for DAC B. This may be an ac or dc signal.
Digital Ground. Ground reference for digital circuitry.
Amplifier Feedback Resistor for DAC B.
WR
Write Input. WR is an active low logic input which is used in conjunction with CS, A0 and A1 to
write data to the input latches.
14
LDAC
DAC Update Logic Input. Data is transferred from the input latches to the DAC latches when LDAC
is taken low.
15
16
17–20
21–24
A1
A0
DB7–DB4
DB3–DB0
Address Input. Most significant address input for input latches (see Table II).
Address Input. Least significant address input for input latches (see Table II).
Data Bit 7 to Data Bit 4.
Data Bit 3 to Data Bit 0 (LSB) or Data Bit 11 (MSB) to Data Bit 8.
–4–
REV. C
AD7837/AD7847
AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS)
Pin
Mnemonic
Description
11
12
13
14
15
16
17
18
19
10
CSA
Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low.
Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low.
Reference Input Voltage for DAC A. This may be an ac or dc signal.
Analog Output Voltage from DAC A.
Analog Ground for DAC A.
Positive Power Supply.
Negative Power Supply.
Analog Ground for DAC B.
Analog Output Voltage from DAC B.
Reference Input Voltage for DAC B. This may be an ac or dc signal.
Digital Ground.
CSB
VREFA
VOUTA
AGNDA
VDD
VSS
AGNDB
VOUTB
VREFB
DGND
DB11
WR
11
12
13
Data Bit 11 (MSB).
Write Input. WR is a positive edge triggered input which is used in conjunction with CSA and CSB
to write data to the DAC latches.
14–24
DB10–DB0
Data Bit 10 to Data Bit 0 (LSB).
AD7837 PIN CONFIGURATION
DIP AND SOIC
AD7847 PIN CONFIGURATION
DIP AND SOIC
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
24
23
22
21
20
19
18
17
16
15
14
13
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
A0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
CS
CSA
CSB
REFA
R
FBA
3
3
V
V
V
V
REFA
4
4
OUTA
OUTA
5
5
AGNDA
AGNDA
AD7837
AD7847
6
6
V
V
DD
DD
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
7
7
V
V
SS
SS
8
8
AGNDB
AGNDB
9
9
V
V
OUTB
OUTB
10
11
12
10
11
12
V
V
A1
DB9
REFB
REFB
DB10
LDAC
WR
DGND
DGND
DB11
R
WR
FBB
REV. C
–5–
AD7837/AD7847–Typical Performance Graphs
25
0.6
0.4
10
V
V
= +15V
DD
DAC A
= –15V
SS
0.2
20
15
0
0
–0.2
–0.4
–0.6
0.6
–10
–20
–30
V
V
V
= +15V
DD
10
0.4
0.2
DAC B
= –15V
SS
V
V
V
= +15V
DD
= +20Vp–p
REF
= –15V
0
SS
DAC CODE = 111...111
5
0
= +20Vp–p @ 1kHz
REF
–0.2
–0.4
–0.6
DAC CODE = 111...111
4
5
6
7
10
100
1k
10k
0
2048
4095
10
10
10
10
CODE
LOAD RESISTANCE – ꢁ
FREQUENCY – Hz
Figure 2. Output Voltage Swing vs.
Resistive Load
Figure 1. Frequency Response
Figure 3. DAC-to-DAC Linearity
Matching
–40
–50
0.5
400
300
0.4
0.3
0.2
0.1
0.0
V
= 7.5V
REF
V
V
V
= +15V
= –15V
DD
V
V
V
= +15V
= –15V
= 0V
–60
–70
DD
SS
= 6V rms
SS
REF
DAC CODE = 111...111
REF
200
100
0
DAC CODE = 111...111
INL
–80
–90
DNL
–100
100
0.1
1
10
0
11
13
/V – Volts
15
17
0.01
0.1
1
10
100
V
FREQUENCY – kHz
DD SS
FREQUENCY – Hz
Figure 4. Linearity vs. Power Supply
Figure 5. Noise Spectral Density vs.
Frequency
Figure 6. THD vs. Frequency
–50
A1 –0.01V
–60
–70
V
V
V
= +15V
DD
= –15V
SS
= 20V p-p
REF
DAC CODE = 000...000
FULL SCALE
–80
V
OUT
–90
ZERO SCALE
B
2ꢂs
200mV 50mV
w
L
–100
0.1
1
10
100
1000
VERT 2V/DIV
HORIZ 2ꢂs/DIV
FREQUENCY – kHz
Figure 7. Multiplying Feedthrough
Error vs. Frequency
Figure 9. Small Signal Pulse
Response
Figure 8. Large Signal Pulse
Response
–6–
REV. C
AD7837/AD7847
CIRCUIT INFORMATION
D/A SECTION
A simplified circuit diagram for one of the D/A converters and
output amplifier is shown in Figure 10.
Table I. AD7847 Truth Table
CSA
CSB
WR
Function
X
1
0
1
0
g
1
g
X
1
1
0
0
1
g
g
1
X
g
g
g
0
0
0
No Data Transfer
No Data Transfer
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
The output amplifier and feedback resistor perform the current
to voltage conversion giving
X = Don’t Care. g = Rising Edge Triggered.
V
OUT = – D × VREF
CSA, CSB
where D is the fractional representation of the digital word. (D
t1
t2
can be set from 0 to 4095/4096.)
t3
WR
The output amplifier can maintain 10 V across a 2 kΩ load. It
is internally compensated and settles to 0.01% FSR (1/2 LSB)
in less than 5 µs. Note that on the AD7837, VOUT must be con-
t5
t4
VALID
DATA
nected externally to RFB
.
DATA
Figure 12. AD7847 Write Cycle Timing Diagram
R
R
R
V
REF
2R
C
2R
B
2R
A
2R
S9
2R
S8
2R
S0
2R
INTERFACE LOGIC INFORMATION—AD7837
R/2
The input loading structure on the AD7837 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches per DAC—an input latch and
a DAC latch. Each input latch is further subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch. Only the
data held in the DAC latches determines the outputs from the part.
The input control logic for the AD7837 is shown in Figure 13,
while the write cycle timing diagram is shown in Figure 14.
V
OUT
SHOWN FOR ALL 1s ON DAC
AGND
Figure 10. D/A Simplified Circuit Diagram
INTERFACE LOGIC INFORMATION—AD7847
The input control logic for the AD7847 is shown in Figure 11.
The part contains a 12-bit latch for each DAC. It can be treated
as two independent DACs, each with its own CS input and a com-
mon WR input. CSA and WR control the loading of data to the
DAC A latch, while CSB and WR control the loading of the
DAC B latch. The latches are edge triggered so that input data
is latched to the respective latch on the rising edge of WR. If CSA
and CSB are both low and WR is taken high, the same data will
be latched to both DAC latches. The control logic truth table is
shown in Table I, while the write cycle timing diagram for the
part is shown in Figure 12.
DAC A
LATCH
DAC B
LATCH
LDAC
CS
12
12
WR
4
DAC A MS
INPUT
LATCH
8
A0
A1
DAC A LS
INPUT
LATCH
4
DAC B LS
INPUT
LATCH
CSA
WR
8
DAC A LATCH
DAC B LS
INPUT
LATCH
DAC B LATCH
CSB
8
DB7 DB0
Figure 11. AD7847 Input Control Logic
Figure 13. AD7837 Input Control Logic
REV. C
–7–
AD7837/AD7847
UNIPOLAR BINARY OPERATION
A0/A1
ADDRESS DATA
Figure 15 shows DAC A on the AD7837/AD7847 connected
for unipolar binary operation. Similar connections apply for
DAC B. When VIN is an ac signal, the circuit performs 2-quad-
rant multiplication. The code table for this circuit is shown in
Table III. Note that on the AD7847 the feedback resistor RFB is
t6 t7
CS
t1
t2
t3
internally connected to VOUT
.
WR
V
DD
t5
t4
VALID
V
AD7837
AD7847
DD
R
FBA
*
DATA
DATA
V
V
OUTA
REFA
DAC A
DGND AGNDA
V
OUT
t8
V
IN
LDAC
V
*INTERNALLY
CONNECTED
ON AD7847
SS
Figure 14. AD7837 Write Cycle Timing Diagram
V
SS
Figure 15. Unipolar Binary Operation
CS, WR, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided that
LDAC is held high, there is no analog output change as a result
of loading data to the input latches. Address lines A0 and A1
determine which latch data is loaded to when CS and WR are low.
The control logic truth table for the part is shown in Table II.
Table III. Unipolar Code Table
DAC Latch Contents
MSB LSB
Analog Output, VOUT
4095
–VIN
–VIN
×
×
×
1111 1111 1111
4096
Table II. AD7837 Truth Table
2048
CS WR A1 A0 LDAC Function
= –1/2 VIN
1000 0000 0000
4096
1
X
0
0
0
0
1
X
1
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
1
1
1
1
1
1
0
No Data Transfer
No Data Transfer
1
–VIN
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
0000 0000 0001
0000 0000 0000
4096
0 V
VIN
Note 1 LSB =
4096
.
X = Don’t Care.
The LDAC input controls the transfer of 12-bit data from the
input latches to the DAC latches. When LDAC is taken low, both
DAC latches, and hence both analog outputs, are updated at
the same time. The data in the DAC latches is held on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in the
simultaneous updating of multiple AD7837s. However, care must
be taken while exercising LDAC during a write cycle. If an LDAC
operation overlaps a CS and WR operation, there is a possibility
of invalid data being latched to the output. To avoid this, LDAC
must remain low after CS or WR return high for a period equal
to or greater than t8, the minimum LDAC pulsewidth.
–8–
REV. C
AD7837/AD7847
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
APPLICATIONS
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Figure 16 shows the AD7837/AD7847 connected for bipolar
operation. The coding is offset binary as shown in Table IV.
When VIN is an ac signal, the circuit performs 4-quadrant multi-
plication. To maintain the gain error specifications, resistors R1,
R2 and R3 should be ratio matched to 0.01%. Note that on the
AD7847 the feedback resistor RFB is internally connected to
The dual DAC/amplifier combination along with access to RFB
make the AD7837 ideal as a programmable gain amplifier. In this
application, the DAC functions as a programmable resistor in the
amplifier feedback loop. This type of configuration is shown
in Figure 17 and is suitable for ac gain control. The circuit con-
sists of two PGAs in series. Use of a dual configuration provides
greater accuracy over a wider dynamic range than a single PGA
solution. The overall system gain is the product of the individual
gain stages. The effective gains for each stage are controlled by
the DAC codes. As the code decreases, the effective DAC
resistance increases, and so the gain also increases.
VOUT
.
R2
20kꢁ
R1
20kꢁ
V
AD711
DD
V
OUT
V
AD7837
AD7847
DD
R
V
FBA
V
*
REFA
R3
10kꢁ
DAC A
V
R
OUTA
REFA
FBA
DAC A
V
V
V
IN
IN
OUTA
*INTERNALLY
CONNECTED
ON AD7847
AGNDA
V
DGND AGNDA
SS
AD7837
R
V
REFB
DAC B
V
SS
FBB
V
OUTB
Figure 16. Bipolar Offset Binary Operation
V
OUT
AGNDB
Table IV. Bipolar Code Table
Figure 17. Dual PGA Circuit
The transfer function is given by
DAC Latch Contents
MSB LSB
Analog Output, VOUT
REQA REQB
×
VOUT
VIN
2047
=
(1)
+VIN
×
×
1111 1111 1111
RFBA RFBB
2048
where REQA, REQB are the effective DAC resistances controlled
by the digital input code:
1
2048
+VIN
0 V
1000 0000 0001
1000 0000 0000
212 RIN
REQ
=
(2)
N
1
2048
where RIN is the DAC input resistance and is equal to RFB and
N = DAC input code in decimal.
–VIN
×
×
0111 1111 1111
0000 0000 0000
The transfer function in (1) thus simplifies to
2048
–VIN
= –VIN
2048
VOUT
VIN
212 212
×
=
(3)
NA NB
VIN
Note 1 LSB =
2048
.
where NA = DAC A input code in decimal and NB = DAC B
input code in decimal.
NA, NB may be programmed between 1 and (212–1). The zero
code is not allowed as it results in an open loop amplifier
response. To minimize errors, the digital codes NA and NB
should be chosen to be equal to or as close as possible to each
other to achieve the required gain.
REV. C
–9–
AD7837/AD7847
ANALOG PANNING CIRCUIT
0.6
0.5
0.4
0.3
0.2
0.1
0.0
In audio applications it is often necessary to digitally “pan” or
split a single signal source into a two-channel signal while main-
taining the total power delivered to both channels constant. This
may be done very simply by feeding the signal into the VREF
input of both DACs. The digital codes are chosen such that the
code applied to DAC B is the two's complement of that applied
to DAC A. In this way the signal may be panned between both
channels as the digital code is changed. The total power varia-
tion with this arrangement is 3 dB.
For applications which require more precise power control the
circuit shown in Figure 18 may be used. This circuit requires
the AD7837/AD7847, an AD712 dual op amp and eight equal
value resistors.
1
512
1024
1536
2048
2560
3072
3584
4095
DIGITAL INPUT CODE N
A
Again both channels are driven with two's complementary data.
The maximum power variation using this circuit is only 0.5 dBs.
Figure 19. Power Variation for Circuit in Figure 9
R
R
APPLYING THE AD7837/AD7847
General Ground Management
1/2
AC or transient voltages between the analog and digital grounds
i.e., between AGNDA/AGNDB and DGND can cause noise
injection into the analog output. The best method of ensuring
that both AGNDs and DGND are equal is to connect them
together at the AD7837/AD7847 on the circuit board. In more
complex systems where the AGND and DGND intertie is on the
backplane, it is recommended that two diodes be connected in
inverse parallel between the AGND and DGND pins (1N914 or
equivalent).
V
V
REFA
AD712
AD7837/
AD7847
R
R
R
R
OUTA
V
V
OUTB
IN
1/2
AD712
V
REFB
R
R
Power Supply Decoupling
V
V
OUTA
OUTB
In order to minimize noise it is recommended that the VDD and
the VSS lines on the AD7837/AD7847 be decoupled to DGND
using a 10 µF in parallel with a 0.1 µF ceramic capacitor.
RL
RL
B
A
Figure 18. Analog Panning Circuit
Operation with Reduced Power Supply Voltages
The AD7837/AD7847 is specified for operation with VDD/VSS
15 V 5%. The part may be operated down to VDD/VSS
10 V without significant linearity degradation. See typical
performance graphs. The output amplifier however requires
approximately 3 V of headroom so the VREF input should not
approach within 3 V of either power supply voltages in order to
maintain accuracy.
=
The voltage output expressions for the two channels are as
follows:
=
NA
212 + N
VOUTA = –VIN
VOUT B = –VIN
A
NB
212 + N
B
MICROPROCESSOR INTERFACING–AD7847
Figures 20 to 22 show interfaces between the AD7847 and three
popular 16-bit microprocessor systems, the 8086, MC68000 and
the TMS320C10. In all interfaces, the AD7847 is memory-
mapped with a separate memory address for each DAC latch.
where NA = DAC A input code in decimal (1 ≤ NA ≤ 4095)
and NB = DAC B input code in decimal (1 ≤ NB ≤ 4095)
with NB = 2s complement of NA.
The two's complement relationship between NA and NB causes
NB to increase as NA decreases and vice versa.
AD7847–8086 Interface
Figure 20 shows an interface between the AD7847 and the 8086
microprocessor. A single MOV instruction loads the 12-bit word
into the selected DAC latch and the output responds on the ris-
ing edge of WR.
Hence NA + NB = 4096.
With NA = 2048, then NB = 2048 also; this gives the balanced
condition where the power is split equally between both chan-
nels. The total power variation as the signal is fully panned from
Channel B to Channel A is shown in Figure 19.
–10–
REV. C
AD7837/AD7847
MICROPROCESSOR INTERFACING–AD7837
ADDRESS BUS
Figures 23 to 25 show the AD7837 configured for interfacing to
microprocessors with 8-bit data bus systems. In all cases, data is
right-justified and the AD7837 is memory-mapped with the two
lowest address lines of the microprocessor address bus driving
the A0 and A1 inputs of the AD7837. Five separate memory
addresses are required, one for the each MS latch and one for
each LS latch and one for the common LDAC input. Data is
written to the respective input latch in two write operations.
Either high byte or low byte data can be written first to the
input latch. A write to the AD7837 LDAC address transfers the
data from the input latches to the respective DAC latches and
updates both analog outputs. Alternatively, the LDAC input
can be asynchronous and can be common to several AD7837s
for simultaneous updating of a number of voltage channels.
8086
CSA
CSB
ADDRESS
DECODE
16 BIT
LATCH
ALE
AD7847
*
WR
WR
DB11
DB0
AD15
AD0
ADDRESS/DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD7847 to 8086 Interface
AD7847–MC68000 Interface
Figure 21 shows an interface between the AD7847 and the
MC68000. Once again a single MOVE instruction loads the
12-bit word into the selected DAC latch. CSA and CSB are
AND-gated to provide a DTACK signal when either DAC
latch is selected.
AD7837–8051/8088 Interface
Figure 23 shows the connection diagram for interfacing the
AD7837 to both the 8051 and the 8088. On the 8051, the
signal PSEN is used to enable the address decoder while DEN
is used on the 8088.
A23
ADDRESS BUS
A1
A15
MC68000
AS
ADDRESS
DECODE
ADDRESS BUS
A8
CSA
CSB
EN
A0 A1
8051/8088
ADDRESS
DECODE
AD7847
*
CS
DTACK
LDAC
PSEN OR DEN
EN
LDS
WR
R/W
OCTAL
LATCH
AD7837
*
DB11
ALE
DB0
WR
WR
D15
D0
DB7
DB0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7
AD0
ADDRESS/DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7847 to MC68000 Interface
AD7847–TMS320C10 Interface
Figure 22 shows an interface between the AD7847 and the
TMS320C10 DSP processor. A single OUT instruction loads
the 12-bit word into the selected DAC latch.
Figure 23. AD7837 to 8051/8088 Interface
AD7837–MC68008 Interface
An interface between the AD7837 and the MC68008 is shown
in Figure 24. In the diagram shown, the LDAC signal is derived
from an asynchronous timer but this can be derived from the
address decoder as in the previous interface diagram.
A11
ADDRESS BUS
A0
TMS320C10
ADDRESS
CSA
TIMER
DECODE
CSB
EN
MEN
WE
A19
AD7847
*
ADDRESS BUS
A0
WR
DB11
DB0
A0 A1
MC68008
ADDRESS
DECODE
CS
LDAC
AS
EN
D15
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
DTACK
AD7837
*
DS
WR
R/W
DB7
Figure 22. AD7847 to TMS320C10 Interface
DB0
D7
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. AD7837 to 68008 Interface
REV. C
–11–
AD7837/AD7847
AD7837–6502/6809 Interface
Figure 25 shows an interface between the AD7837 and the 6502
or 6809 microprocessor. For the 6502 microprocessor, the φ2
clock is used to generate the WR, while for the 6809 the E sig-
nal is used.
A15
ADDRESS BUS
A0
A0 A1
ADDRESS
DECODE
6502/6809
R/W
CS
LDAC
EN
AD7837
*
ꢃ2 OR E
WR
DB7
DB0
D7
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD7837 to 6502/6809 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24)
24-Lead Cerdip (Q-24)
1.228 (31.19)
1.226 (31.14)
24
13
0.295
(7.493)
MAX
PIN 1
24
13
12
0.261 ꢀ 0.001
(6.61 ꢀ 0.03)
0.320 (8.128)
0.290 (7.366)
1
12
0.32 (8.128)
0.30 (7.62)
1
0.070 (1.778)
0.020 (0.508)
1.290 (32.77) MAX
PIN 1
0.180
(4.572)
MAX
0.225 (5.715)
0.130 (3.30)
0.128 (3.25)
MAX
0.125 (3.175)
MIN
SEATING
PLANE
SEATING
PLANE
0.012 (0.305)
0.008 (0.203)
TYP
0.011 (0.28)
0.009 (0.23)
0.021 (0.533) 0.110 (2.794)
0.015 (0.381) 0.090 (2.286)
0.065 (1.651)
0.055 (1.397)
15°
0°
0.02 (0.5)
0.016 (0.41)
0.11 (2.79)
0.09 (2.28)
0.07 (1.78)
0.05 (1.27)
15°
0°
TYP
TYP
1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.
1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.
2. PLASTIC LEADS WILL EITHER BE SOLDER DIPPED OR TIN LEAD PLATED.
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
2. CERDIP LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED.
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
24-Lead SOIC (R-24)
0.608 (15.45)
0.596 (15.13)
24
1
13
12
0.299 (7.6)
0.291 (7.39)
0.414 (10.52)
0.398 (10.10)
PIN 1
0.096 (2.44)
0.089 (2.26)
0.03 (0.76)
0.02 (0.51)
6ꢄ
0ꢄ
0.05
(1.27)
SEATING
PLANE
0.019 (0.49)
0.014 (0.35)
0.01 (0.254)
0.006 (0.15)
0.042 (1.067)
0.018 (0.457)
0.013 (0.32)
0.009 (0.23)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. SOIC LEADS WILL EITHER BE TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
–12–
REV. C
相关型号:
AD7847BN
DUAL, PARALLEL, WORD INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDIP24, 0.300 INCH, PLASTIC, DIP-24
ROCHESTER
AD7847BNZ
DUAL, PARALLEL, WORD INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDIP24, 0.300 INCH, PLASTIC, DIP-24
ROCHESTER
AD7847BQ
DUAL, PARALLEL, WORD INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, CDIP24, 0.300 INCH, GLASS SEALED, CERDIP-24
ROCHESTER
©2020 ICPDF网 联系我们和版权申明