AD7849CR [ADI]
Serial Input, 14-Bit/16-Bit DAC; 串行输入， 14位/ 16位DAC
| 型号： | AD7849CR |
| 厂家： | 
ADI |
| 描述： | Serial Input, 14-Bit/16-Bit DAC |
| 文件： | 总15页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Serial Input,
14-Bit/16-Bit DAC
a
AD7849*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
14-Bit/16-Bit Multiplying DAC
Guaranteed Monotonicity
Output Control on Power-Up and Power-Down
Internal or External Control
Versatile Serial Interface
V
V
CC
DD
R
V
REF+
R
OFS
R
A1
A2
R
RST IN
16-
DAC Clears to 0 V in Both Unipolar and Bipolar Output
Ranges
G1
SEG-
V
A3
OUT
MENT
SWITCH
MATRIX
10-BIT/
12-BIT
DAC
R
R
APPLICATIONS
G2
Industrial Process Control
PC Analog I/O Boards
Instrumentation
10/
12
LOGIC
CIRCUITRY
DAC
LATCH
V
REF–
VOLTAGE
MONITOR
10/
12
AGND
4
RST OUT
INPUT
LATCH
AD7849
INPUT SHIFT REGISTER/
CONTROL LOGIC
GENERAL DESCRIPTION
The AD7849 is a 14-bit/16-bit serial input multiplying DAC.
The DAC architecture ensures excellent differential linearity
performance, and monotonicity is guaranteed to 14 bits for the
A grade and to 16 bits for all other grades over the specified
temperature ranges.
DGND SDIN SCLK SYNC CLR BIN/ DCEN SDOUT LDAC V
SS
COMP
The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
During power-up and power-down sequences (when the supply
voltages are changing), the VOUT pin is clamped to 0 V via a low
impedance path. To prevent the output of A3 being shorted to
0 V during this time, transmission gate G1 is also opened.
These conditions are maintained until the power supplies
stabilize and a valid word is written to the DAC register. At this
time, G2 opens and G1 closes. Both transmission gates are also
externally controllable via the Reset In (RST IN) control input.
For instance, if the RST IN input is driven from a battery super-
visor chip, then on power-off or during a brown out, the RST
IN input will be driven low to open G1 and close G2. The DAC
must be reloaded, with RST IN high, to re-enable the output.
Conversely, the on-chip voltage detector output (RST OUT) is
also available to the user to control other parts of the system.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multi-
channel system. The DCEN (Daisy Chain Enable) input con-
trols this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP
set to 0, the coding is straight binary; and with it set to 1, the
coding is 2s complement. This allows the user to reset the DAC
to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead DIP and 20-lead SOIC package.
*Protected by U.S. Patent No. 5,319,371.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD7849–SPECIFICATIONS1
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V; VOUT loaded with 2 kΩ,2 200 pF to 0 V; VREF+ = +5 V;
ROFS connected to 0 V; TA = TMIN to TMAX, unless otherwise noted)
A
B, T
Versions
C
Parameter
Versions
Versions
Units
Test Conditions/Comments
RESOLUTION
14
16
16
Bits
A Versions: 1 LSB = 2 (VREF+–VREF–)/214
B, C, T Versions: 1 LSB = 2 (VREF+–VREF–)/216
UNIPOLAR OUTPUT
Relative Accuracy @ +25°C
TMIN to TMAX
Differential Nonlinearity
Gain Error @ +25°C
TMIN to TMAX
VREF– = 0 V, VOUT = 0 V to +10 V
4
5
0.25
1
4
1
6
2
6
4
8
0.5
4
16
4
16
2
2
LSBs typ
LSBs max
LSBs max
LSBs typ
LSBs max
LSBs typ
LSBs max
16
0.9
4
16
4
24
2
2
All Grades Guaranteed Monotonic Over Temperature
VOUT Load = 10 MΩ
Offset Error @ +25°C
T
MIN to TMAX
Gain TC3
ppm FSR/°C typ
ppm FSR/°C typ
Offset TC3
2
BIPOLAR OUTPUT
Relative Accuracy @ +25°C
TMIN to TMAX
Differential Nonlinearity
Gain Error @ +25°C
TMIN to TMAX
V
REF– = –5 V, VOUT = –10 V to +10 V
2
3
0.25
1
4
0.5
3
3
8
0.9
4
16
2
12
2
4
0.5
4
16
2
8
LSBs typ
LSBs max
LSBs max
LSBs typ
LSBs max
LSBs typ
LSBs max
All Grades Guaranteed Monotonic Over Temperature
OUT Load = 10 MΩ
V
Offset Error @ +25°C
TMIN to TMAX
Bipolar Zero Error @ +25°C
0.5
4
2
2
2
2
12
2
2
2
2
8
2
2
LSBs typ
LSBs max
ppm FSR/°C typ
ppm FSR/°C typ
ppm FSR/°C typ
T
MIN to TMAX
Gain TC3
Offset TC3
Bipolar Zero TC3
2
REFERENCE INPUT
Input Resistance
25
43
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
25
43
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
25
43
VSS + 6 to
VDD – 6
VSS + 6 to
VDD – 6
kΩ min
kΩ max
Volts
Resistance from VREF+ to VREF–
Typically 34 kΩ
V
REF+ Range
REF– Range
V
Volts
OUTPUT CHARACTERISTICS
Output Voltage Swing
VSS + 4 to
VSS + 4 to
VSS + 4 to
V max
VDD – 4
2
200
0.3
VDD – 4
2
200
0.3
VDD – 4
2
200
0.3
Resistive Load
kΩ min
pF max
Ω typ
To 0 V
To 0 V
Capacitive Load
Output Resistance
Short Circuit Current
25
25
25
mA typ
Voltage Range: –10 V to +10 V
DIGITAL INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
2.4
0.8
10
2.4
0.8
10
2.4
0.8
10
V min
V max
µA max
pF max
CIN, Input Capacitance
10
10
10
DIGITAL OUTPUTS
VOL (Output Low Voltage)
VOH (Output High Voltage)
Floating State Leakage Current
Floating State Output
Capacitance
0.4
4.0
10
0.4
4.0
10
0.4
4.0
10
Volts max
Volts min
µA max
ISINK = 1.6 mA
ISOURCE = 400 µA
10
10
10
pF max
POWER REQUIREMENTS4
VDD
VSS
+14.25/+15.75 +14.25/+15.75 +14.25/+15.75 V min/V max
–14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/V max
VCC
IDD
ISS
ICC
+4.75/+5.25
5
5
2.5
0.4
100
+4.75/+5.25
5
5
2.5
1.5
100
+4.75/+5.25
5
5
2.5
1.5
100
V min/V max
mA max
mA max
mA max
LSB/V max
VOUT Unloaded, VINH = VDD – 0.1 V, VINL = 0.1 V
VOUT Unloaded, VINH = VDD – 0.1 V, VINL = 0.1 V
VINH = VDD – 0.1 V, VINL = 0.1 V
Power Supply Sensitivity5
Power Dissipation
mW typ
VOUT Unloaded
NOTES
1Temperature ranges: A, B, C Versions: –40°C to +85°C; T Version: –55°C to +125°C.
2Minimum load for T Version is 3 kΩ.
3Guaranteed by design and characterization, not production tested.
4The AD7849 is functional with power supplies of 12 V. See Typical Performance Curves.
5Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD, VSS variations.
Specifications subject to change without notice.
–2–
REV. B
AD7849
(These specifications apply when the device goes into the Reset mode during a power-up or
RESET SPECIFICATIONS
power-down sequence.) VOUT unloaded.
Parameter
All Versions Units
Test Conditions/Comments
VA1, Low Threshold Voltage for VDD, VSS 1.2
0
VB, High Threshold Voltage for VDD, VSS 9.5
6.4
Volt max This is the lower VDD/VSS threshold voltage for the reset
Volts typ function. Above this, the reset is activated.
Volts max This is the higher VDD/VSS threshold voltage for the reset
Volts min function. Below this, the reset is activated. Typically 8 volts.
Volt max This is the lower threshold voltage for the reset function.
Volts typ Above this, the reset is activated.
VC, Low Threshold Voltage for VCC
1
0
VD, High Threshold Voltage for VCC
4
2.5
1
Volts max This is the higher VCC threshold voltage for the reset function.
Volts min Below this, the reset is activated. Typically 3 volts.
G2 RON
kΩ typ
On Resistance of G2; VDD = 2 V; VSS = –2 V; IG2 = 1 mA.
NOTES
1A pull-down resistor (65 kΩ) on VOUT maintains 0 V output when VDD/VSS is below VA.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not
subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V; ROFS connected to 0 V.)
T
A, B, C
Versions
Parameter
Version
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Settling Time1
7
10
4
7
10
4
µs typ
To 0.006% FSR. VOUT Loaded. VREF– = 0 V.
To 0.003% FSR. VOUT Loaded. VREF– = –5 V.
µs typ
Slew Rate
Digital-to-Analog Glitch Impulse
V/µs typ
nV-s typ
250
250
DAC Alternately Loaded with 00 . . . 00 and
111 . . . 11. VOUT Unloaded. LDAC Perma-
nently Low. BIN/COMP Set to 1. VREF– = –5 V.
LDAC Frequency = 100 kHz
150
1
150
1
nV-s typ
AC Feedthrough
mV pk-pk typ VREF– = 0 V, VREF+ = 1 V rms, 10 kHz Sine Wave.
DAC Loaded with All 0s. BIN/COMP Set to 0.
DAC Alternately Loaded with All 1s and All 0s.
Digital Feedthrough
5
5
nV-s typ
SYNC High.
Output Noise Voltage Density
1 kHz–100 kHz
80
80
nV/√Hz typ
Measured at VOUT. VREF+ = VREF– = 0 V.
BIN/COMP Set to 0.
NOTES
1LDAC = 0. Settling time does not include deglitching time of 5 µs (typ).
Specification subject to change without notice.
TIMING CHARACTERISTICS1, 2
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V;
RL = 2 kΩ, CL = 200 pF. All Specifications TMIN to TMAX unless otherwise noted.)
Limit at +25؇C
(All Versions)
Limit at TMIN, TMAX
(All Versions)
Parameter
Units
Conditions/Comments
3
t1
200
50
70
10
40
80
80
30
30
200
50
70
10
40
80
80
30
30
ns min
ns min
ns min
ns min
ns min
ns max
ns min
µs max
µs max
SCLK Cycle Time
t2
t3
t4
t54
t6
t7
tr
SYNC to SCLK Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SDO Valid
LDAC, CLR Pulsewidth
Digital Input Rise Time
Digital Input Fall Time
tf
NOTES
1Guaranteed by characterization.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3SCLK mark/space ratio range is 40/60 to 60/40.
4SDO load capacitance is 50 pF.
Specification subject to change without notice.
REV. B
–3–
AD7849
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +17 V
VCC to DGND2 . . . . . . . . . . . . . . . . . . –0.4 V, VDD + 0.4 V or
+7 V (Whichever Is Lower)
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2VCC must not exceed VDD by more than 0.4 V. If it is possible for this to happen
during power-up or power-down (for example, if VCC is greater than +0.4 V while
VDD is still 0 V), the following diode protection scheme will ensure protection.
V
SS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to –17 V
VREF+ to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
V
V
REF– to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
OUT to DGND3 . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V or
10 V (Whichever Is Lower)
V
V
CC
DD
SD103C
1N5711
1N5712
ROFS to DGND . . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V
Digital Input Voltage to DGND . . . . . . –0.4 V to VCC + 0.4 V
Input Current to any Pin Except Supplies4 . . . . . . . . . 10 mA
Operating Temperature Range
1N4148
V
V
CC
DD
Commercial/Industrial (A, B, C Versions). . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . . 875 mW
AD7849
3VOUT may be shorted to DGND, +10 V, –10 V, provided that the power dissipation
of the package is not exceeded.
4Transient currents of up to 100 mA will not cause SCR latch-up.
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 102°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +260°C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . . 875 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 875 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 71°C/W
Lead Temperature, Soldering (Soldering 10 secs) . . . 260°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7849 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
ORDERING GUIDE
Temperature
Range
Resolution
(Bits)
Bipolar
INL (LSBs)
Package
Option*
V
V
20
19
18
17
1
2
R
V
REF+
OFS
Model
REF–
OUT
AD7849AN
AD7849BN
AD7849CN
AD7849AR
AD7849BR
AD7849CR
AD7849TQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
14
16
16
14
16
16
16
3
8
4
3
8
4
8
N-20
N-20
N-20
R-20
R-20
R-20
Q-20
V
SS
3
NC
SYNC
4
V
DD
16 AGND
SCLK
5
AD7849
TOP VIEW
(Not to Scale)
RSTOUT
V
CC
15
14
13
12
11
6
RSTIN
CLR
7
SDOUT
8
DCEN
BIN/COMP
SDIN
9
*N = Plastic DIP; R = SOP (Small Outline Package); Q = Cerdip.
LDAC
10
DGND
NC = NO CONNECT
–4–
REV. B
AD7849
TERMINOLOGY
Offset Error
Least Significant Bit
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7849, B, C and T versions, 1 LSB = (VREF+ – VREF–)/
216. For the AD7849, A version, 1 LSB = (VREF+ – VREF–)/214.
Bipolar Zero Error
Relative Accuracy
When the AD7849 is connected for bipolar output and
(100 . . . 000) is loaded to the DAC, the deviation of the analog
output from the ideal midscale of 0 V, is called the bipolar zero
error.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain errors are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in nV-secs.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of less than 1 LSB over the
operating temperature range ensures monotonicity.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
Digital Feedthrough
Gain Error
When the DAC is not selected (SYNC is held high), high fre-
quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
2
3
4
5
6
7
VREF+
VREF–
VSS
VREF+ Input. The DAC is specified for VREF+ of +5 V. The DAC is fully multiplying so that the VREF+ range is +5 V to –5 V.
VREF– Input. The DAC is specified for VREF– of –5 V. Since the DAC is fully multiplying the VREF– range is –5 V to +5 V.
Negative supply for the analog circuitry. This is nominally –15 V.
SYNC
SCLK
VCC
Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data word.
Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge.
Positive supply for the digital circuitry. This is nominally +5 V.
SDOUT
Serial Data Output. With DCEN at Logic “1,” this output is enabled and the serial data in the input shift register is
clocked out on each rising edge of SCLK.
8
9
DCEN
Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise this pin must be
connect low.
BIN/COMP
Logic Input. This input selects the data format to be either binary or 2s complement. In the unipolar output range,
natural binary format is selected by connecting the input to a Logic “0.” In the bipolar output range, offset binary is
selected by connecting this input to a Logic “0” and 2s complement is selected by connecting it to a Logic “1.”
10
11
DGND
Digital Ground. Ground reference point for the on-chip digital circuitry.
LDAC
Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively, if this input is permanently low, an automatic update mode is selected whereby the DAC is updated
on the 16th falling SCLK edge.
12
13
SDIN
Serial Data Input. The 16-bit serial data word is applied to this input.
CLR
Clear Logic Input. Taking this input low sets VOUT to 0 V in both the unipolar output range and the bipolar 2s comple-
ment output range. It sets VOUT to VREF– in the offset binary bipolar output range.
14
15
RSTIN
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic “0” to this input, resets
the DAC output to 0 V. In normal operation it should be tied to Logic “1.”
RSTOUT
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It may used to control
other system components if desired.
16
17
18
19
20
AGND
VDD
This is the analog ground for the device. It is the point to which the output gets shorted in the reset mode.
Positive supply for the analog circuitry. This is +15 V nominal.
No Connect. Leave unconnected.
NC
VOUT
ROFS
DAC Output Voltage Pin.
Input to summing resistor of DAC output amplifier. This is used to select output voltage ranges. See Figures 16 to 19
in “APPLYING THE AD7849.”
REV. B
–5–
AD7849
Typical Performance Curves
7
6
5
4
3
2
1
V
V
V
V
= +15V
= –15V
DD
SS
C1 FREQ
9.9942kHz
= 1V rms
= 0V
REF+
V
REF+
1
REF–
C1 RMS
728mV
C4 RMS
556µV
V
OUT
4
0
10
2
3
4
5
6
M 20.0µs CH1
–300mV
CH1 1.00V
CH4 1.00mV
10
10
FREQUENCY – Hz
10
10
Figure 1a. AC Feedthrough
Figure 1b. AC Feedthrough vs. Frequency
LDAC
SYNC
1
1
2
SDIN
SDIN
2
C4 AREA
247.964nV
S
V
OUT
4
V
OUT
4
CH2 5.00V
CH4 200mV
M
1.00µs
CH1
3.7V
CH2 5.00V
CH4 50.0mV
M
5.00µs
CH1
2.3V
CH1 5.00V
CH1 5.00V
Figure 2a. Digital-to-Analog Glitch Impulse Without
Internal Deglitcher
Figure 2b. Digital-to-Analog Glitch Impulse with
Internal Deglitcher
22
20
18
C1 Pk-Pk
10.4V
1
V
REF+
V
V
V
V
= +15V
= –15V
DD
16
14
12
10
8
SS
=
5V SINE WAVE
REF+
= 0V
REF–
GAIN = +2
C2 Pk-Pk
20.8V
C2 RISE
2.79230µs
2
V
OUT
6
C2 FALL
3.20385µs
4
2
10
2
3
4
5
6
10
10
FREQUENCY – Hz
10
10
CH2 20.0V
M
2.5µs CH1
–400mV
CH1 10.0V
Figure 3. Large Signal Frequency Response
Figure 4. Pulse Response (Large Signal)
–6–
REV. B
AD7849
C1 Pk-Pk
104mV
1
2
V
V
REF+
C2 Pk-Pk
216mV
OUT
C2 RISE
458ns
C2 FALL
452.4ns
CH2 200mV
M
2.00µs CH1
–10mV
CH1 100mV
Figure 5. Pulse Response (Small Signal)
2
1.5
1
T
V
V
= +25°C
A
= +5V
REF+
C1 RISE
3.808 ms
V
DD
= 0V
REF–
GAIN = 1
1
C2 RISE
8µs
V
OUT
2
0.5
0
LDAC
3
11
12.25
13.5
/V – Volts
14.75
16
V
DD SS
CH 2 10.0V
M
10.0ms CH1
7.8V
CH1 10.0V
CH3 5.00V
Figure 8. Turn-On Characteristics
Figure 6. Typical Integral Nonlinearity vs. Supplies
0.5
T
A
= +25°C
V
V
= +5V
= 0V
REF+
7.8V
REF–
0.375
0.25
0.125
0
V
DD
C1 FALL
4.7621ms
GAIN = 1
1
V
OUT
2
11
12
13
14
/V – Volts
15
16
V
DD SS
CH 2 10.0V
M
1.00ms
CH1
7.8V
CH1 10.0V
Figure 7. Typical Differential Nonlinearity vs. Supplies
Figure 9. Turn-Off Characteristics
REV. B
–7–
AD7849
CIRCUIT DESCRIPTION
R
RSTIN
OFS
D/A CONVERSION
R
10kΩ
R
Figure 10 shows the D/A section of the AD7849. There are
three on-chip DACs each of which has its own buffer amplifier.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage ref-
erence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
10kΩ
C1
G3
G1
V
OUT
DAC 3
G2
LOGIC
CIRCUITRY
ONE-SHOT
The 4 MSBs of the 16-bit digital input code drive DAC1 and
DAC2 while the 12 LSBs control DAC3. Using DAC1 and
DAC2, the MSBs select a pair of adjacent nodes on the resistor
string and present that voltage to the positive and negative
inputs of DAC3. This DAC interpolates between these two
voltages to produce the analog output voltage.
AGND
VOLTAGE
MONITOR
LDAC
RSTOUT
Figure 11. AD7849 Output Stage
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
For example, when switching from Segment 1 to Segment 2,
DAC1 switches from the bottom of Segment 1 to the top of
Segment 2 while DAC 2 remains connected to the top of Seg-
ment 1. The code driving DAC3 is automatically comple-
mented to compensate for the inversion of its inputs. This
means that any linearity effects due to amplifier offset voltages
remain unchanged when switching from one segment to the
next and 16-bit monotonicity is ensured if DAC3 is monotonic.
So, 12-bit resistor matching in DAC3 guarantees overall 16-bit
monotonicity. This is much more achievable than the 16-bit
matching which a conventional R-2R structure would have
needed.
When the supply voltages are changing, the VOUT pin is clamped
to 0 V via a low impedance path . To prevent the output of A3
being shorted to 0 V during this time, transmission gate G1 is
also opened. These conditions are maintained until the power
supplies stabilize and a valid word is written to the DAC regis-
ter. At this time, G2 opens and G1 closes. Both transmission
gates are also externally controllable via the Reset In (RST IN)
control input. For instance, if the RST IN input is driven from a
battery supervisor chip, then on power-off or during a brown-
out, the RST IN input will be driven low to open G1 and close
G2. The DAC has to be reloaded, with RST IN high, to re-en-
able the output. Conversely, the on-chip voltage detector out-
put (RST OUT) is also available to the user to control other
parts of the system.
Output Stage
The output stage of the AD7849 is shown in Figure 11. It is ca-
pable of driving a load of 2 kΩ in parallel with 200 pF. The
feedback and offset resistors allow the output stage to be config-
ured for gains of 1 or 2. Additionally, the offset resistor may be
used to shift the output range.
The AD7849 output buffer is configured as a track-and-hold
amplifier. Although normally tracking its input, this amplifier is
placed in a hold mode for approximately 5 µs after the leading
edge of LDAC. This short state keeps the DAC output at its
previous voltage while the AD7849 is internally changing to its
new value. So, any glitches that occur in the transition are not
seen at the output. In systems where the LDAC is permanently
low, the deglitching will not be in operation.
The AD7849 has a special feature to ensure output stability
during power-up and power-down sequences. This is specifi-
cally available for control applications where actuators must not
be allowed to move in an uncontrolled fashion.
V
REF
+
R
R
R
DAC 1
S1
DAC 2
S2
DAC 3
S4
S3
OUTPUT
STAGE
A1
10-BIT/12-BIT
DAC
S15
S17
S14
S16
R
R
R
10/12
DB15–DB12
DB15–DB12
V
REF
–
A2
Figure 10. AD7849 D/A Conversion
–8–
REV. B
AD7849
t1
SCLK
t3
t2
SYNC
BIN/COMP
t4
t5
SDIN
DB15
DB13
DB0
(AD7849B/C/T)
t4
t5
SDIN
(AD7849A)
DB0
t7
LDAC, CLR
DCEN IS TIED PERMANENTLY LOW
Figure 12. Timing Diagram (Stand-Alone Mode)
DIGITAL INTERFACE
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status,
one of two update modes is selected.
The AD7849 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading
circuitry is shown in Figure 12. Serial data on the SDIN input
is loaded to the input register under control of DCEN, SYNC
and SCLK. When a complete word is held in the shift register it
may then be loaded into the DAC latch under control of
LDAC. Only the data in the DAC latch determines the analog
output on the AD7849.
If LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked
in. The update thus takes place on the sixteenth falling SCLK
edge.
The DCEN (daisy-chain enable) input is used to select either a
stand-alone mode or a daisy-chain mode. The loading format is
slightly different depending on which mode is selected.
If LDAC = 1 then the automatic update is disabled. The DAC
latch update and output update are now separate. The DAC
latch is updated on the falling edge of LDAC. However, the
output update is delayed for a further 5 µs by means of an inter-
nal track-and-hold amplifier in the output stage. This function
results in lower digital-to-analog glitch impulse at the DAC
output. Note that the LDAC input must be taken back high
again before the next data transfer is initiated.
Serial Data Loading Format (Stand-Alone Mode)
With DCEN at Logic 0 the stand-alone mode is selected. In this
mode a low SYNC input provides the frame synchronization
signal which tells the AD7849 that valid serial data on the SDIN
input will be available for the next 16 falling edges of SCLK. An
internal counter/decoder circuit provides a low gating signal so
that only 16 data bits are clocked into the input shift register.
After 16 SCLK pulses the internal gating signal goes inactive
(high) thus locking out any further clock pulses. Therefore ei-
ther a continuous clock or a burst clock source may be used to
clock in the data.
DCEN
SYNC
GATED
SIGNAL
EN
RESET
16
INPUT
SHIFT REGISTER
(16 BITS)
÷
SCLK
SDIN
COUNTER/
DECODER
GATED
SCLK
The SYNC input is taken high after the complete 16-bit word is
loaded in.
SDOUT
AUTO-UPDATE
CIRCUITRY
The AD7849B, AD7849C and AD7849T versions are 16-bit
resolution DACS and have a straight 16-bit load format, with
the MSB (DB15) being loaded first. The AD7849A is a 14-bit
DAC but the loading structure is still 16-bit. The MSB (DB13)
is loaded first and the final two bits of the 16-bit stream must
be 0s.
LDAC
CLR
DAC LATCH
(14/16 BITS)
Figure 13. Simplified Loading Structure
REV. B
–9–
AD7849
t1
SCLK
t2
t3
SYNC
BIN/COMP
t4
t5
SDIN
(AD7849B/C/T)
DB15
(N+1)
DB0
(N+1)
DB15 (N)
DB0 (N)
t6
SDOUT
(AD7849B/C/T)
DB0 (N)
DB15 (N)
t4
t5
DB13
(N+1)
DB0
(N+1)
SDIN
(AD7849A)
DB13 (N)
DB0 (N)
t6
SDOUT
(AD7849A)
DB13 (N)
DB0 (N)
t7
LDAC, CLR
DCEN IS TIED PERMANENTLY HIGH
Figure 14. Timing Diagram (Daisy-Chain Mode)
Serial Data Loading Format (Daisy Chain Mode)
Clear Function (CLR)
By connecting DCEN high, the daisy-chain mode is enabled.
This mode of operation is designed for multi-DAC systems
where several AD7849s may be connected in cascade. In this
mode, the internal gating circuitry on SCLK is disabled and a
serial data output facility is enabled. The internal gating signal
is permanently active (low) so that the SCLK signal is continu-
ously applied to the input shift register when SYNC is low. The
data is clocked into the register on each falling SCLK edge after
SYNC going low. If more than 16 clock pulses are applied, the
data ripples out of the shift register and appears on the
SDOUT line. By connecting this line to the SDIN input on the
next AD7849 in the chain, a multi-DAC interface may be con-
structed. Sixteen SCLK pulses are required for each DAC in the
system. Therefore the total number of clock cycles must equal
16 × N where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data being clocked into
the input register.
The clear function bypasses the input shift register and loads the
DAC Latch with all 0s. It is activated by taking CLR low. In all
ranges except the Offset Binary bipolar range (–5 V to +5 V) the
output voltage is reset to 0 V. In the offset binary bipolar range
the output is set to VREF–
. This clear function is distinct and
separate from the automatic power-on reset feature of the device.
APPLYING THE AD7849
Power Supply Sequencing and Decoupling
In the AD7849, VCC should not exceed VDD by more than
0.4 V. If this does happen then an internal diode can be turned
on and produce latch-up in the device. Care should be taken to
employ the following power supply sequence: VDD; VSS; VCC
In systems where it is possible to have an incorrect power
.
sequence (for example, if VCC is greater than 0.4 V while VDD is
still 0 V), the circuit of Figure 15 may be used to ensure that
the Absolute Maximum Ratings are not exceeded.
V
V
CC
DD
A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock
cycles may be used and SYNC taken high some time later.
SD103C
1N5711
1N5712
1N4148
V
V
CC
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC latches with the data in each in-
put register. All analog outputs are therefore updated simulta-
neously, 5 µs after the falling edge of LDAC.
DD
AD7849
Figure 15. Power Supply Protection
–10–
REV. B
AD7849
Unipolar Configuration
Bipolar Configuration
Figure 16 shows the AD7849 in the unipolar binary circuit con-
figuration. The DAC is driven by the AD586, +5 V reference.
Since ROFS is tied to 0 V, the output amplifier has a gain of ×2
and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, ROFS should be tied to VOUT, configuring the output
stage for a gain of ×1. Table I gives the code table for the circuit
of Figure 16.
Figure 17 shows the AD7849 set up for 10 V bipolar opera-
tion. The AD588 provides precision 5 V tracking outputs
which are fed to the VREF+ and VREF– inputs of the AD7849.
The code table for Figure 17 is shown in Table II.
Full-scale and bipolar-zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and –5 V outputs together
with respect to ground.
+15V
+5V
+5V
+15V
V
V
CC
DD
2
V
R1
39kΩ
OUT
(0 TO +10V)
V
OUT
8
6
5
V
V
V
V
REF+
DD
CC
R
AD586
4
OFS
6
4
V
V
OUT
OUT
R1
10kΩ
2
3
1
AD7849*
(–10V TO +10V)
7
9
5
C1
C1
1µF
AGND
R
V
OFS
1nF
REF+
DGND
REF–
AD7849*
AGND
V DGND
REF–
AD588
V
R2
100kΩ
SS
14
15
16
SIGNAL GND
10
11
*
ADDITIONAL PINS
OMITTED FOR CLARITY
SIGNAL
GND
V
–15V
SS
12
8
13
R3
100kΩ
Figure 16. Unipolar Binary Operation
–15V
*
ADDITIONAL PINS
OMITTED FOR CLARITY
Table I. Code Table for Figure 16
Figure 17. Bipolar 10 V Operation
Table II. Offset Binary Code Table for Figure 17
Binary Number in DAC Latch
MSB LSB
Analog Output
(VOUT
)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0 V
Binary Number in DAC Latch
MSB LSB
Analog Output
(VOUT
)
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+10 (32767/32768) V
+10 (1/32768) V
0 V
–10 (1/32768) V
–10 (32768/32768) V
NOTE: Assumes 16-bit resolution; 1 LSB = 10 V/216 = 10 V/65536 = 152 µV.
Offset and gain may be adjusted in Figure 16 as follows: To ad-
just offset, disconnect the VREF– input from 0 V, load the DAC
with all 0s and adjust the VREF– voltage until VOUT = 0 V. For
gain adjustment, the AD7849 should be loaded with all 1s and
R1 adjusted until VOUT = 10 (65535)/65536 = 9.9998474 V,
(B, T and C, 16-bit versions). For the 14-bit A version, VOUT
should be 10 (16383/16384) = 9.9993896 V.
NOTE: Assumes 16-bit resolution; 1 LSB = 20 V/216 = 305 µV.
For bipolar-zero adjustment on the AD7849, load the DAC
with 100 . . . 000 and adjust R3 until VOUT = 0 V. Full scale is
adjusted by loading the DAC with all 1s and adjusting R2 until
VOUT = 9.999694 V.
If a simple resistor divider is used to vary the VREF– voltage, it is
important that the temperature coefficients of these resistors match
that of the DAC input resistance (–300 ppm/°C). Otherwise, extra
offset errors will be introduced over temperature. Many circuits
will not require these offset and gain adjustments. In these cir-
cuits, R1, can be omitted. Pin 5 of the AD586 may be left open
circuit and Pin 2 (VREF– ) of the AD7849 tied to 0 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
If a user wants a 5 V output range with the circuit of Figure
17, simply tie Pin 20 (ROFS) to Pin 19 (VOUT), thus reducing the
output gain stage to unity and giving an output range of 5 V.
REV. B
–11–
AD7849
Other Output Voltage Ranges
MICROPROCESSOR INTERFACING
In some cases, users may require output voltage ranges other
than those already mentioned. One example is systems which
need the output voltage to be a whole number of millivolts (i.e.,
1 mV, 2 mV, etc.,). If Figure 18 is used, then the LSB size is
125 µV. This makes it possible to program whole millivolt val-
ues at the output. Table III shows the code table for Figure 18.
Microprocessor interfacing to the AD7849 is via a serial bus
which uses standard protocol compatible with DSP processors
and microcontrollers. The communications channel requires a
three-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7849 requires a 16-bit
data word with data valid on the falling edge of SCLK. For all
the interfaces, the DAC update may be done automatically
when all the data is clocked in or it may be done under control
of LDAC.
+15V
+5V
V
V
DD
CC
Figures 20 to 24 show the AD7849 configured for interfacing to
a number of popular DSP processors and microcontrollers.
8
R
OFS
V
R1
REF+
8.192V
R2
V
OUT
(0V TO +8.192V)
V
1
OUT
AD7849-ADSP-2101/ADSP-2102 Interface
AD584
AD7849*
Figure 20 shows a serial interface between the AD7849 and the
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/
ADSP-2102 contains two serial ports and either port may be
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ ADSP-2102 is clocked into the
AD7849 on the falling edge of SCLK. The DAC can be up-
dated by holding LDAC high while performing the write cycle.
TFS must be taken high after the 16-bit write cycle. LDAC is
brought low at the end of the cycle and the DAC output is up-
dated. In the interface shown the DAC is updated using an ex-
ternal timer which generates an LDAC pulse. This could also be
done using a control or decoded address line from the proces-
sor. Alternatively, if the LDAC input is hardwired low the out-
put update takes place automatically on the 16th falling edge of
SCLK.
DGND
AGND
4
V
REF–
SIGNAL
GND
*
ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 18. 0 V to 8.192 V Output Range
Table III. Code Table for Figure 18
Binary Number
in DAC Latch
MSB
Analog Output
(VOUT
)
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 1000
0000 0000 0000 0100
0000 0000 0000 0010
0000 0000 0000 0001
8.192 V (65535/65536) = 8.1919 V
8.192 V (32768/65536) = 4.096 V
8.192 V (8/65536) = 0.001 V
8.192 V (4/65536) = 0.0005 V
8.192 V (2/65536) = 0.00025 V
8.192 V (1/65536) = 0.000125 V
TIMER
ADSP-2101
LDAC
ADSP-2102*
SCLK
SCLK
AD7849*
SDIN
DT
NOTE: Assumes 16-bit resolution; 1 LSB = 8.192 V/216 = 125 µV.
SYNC
TFS
Generating ؎5 V Output Range From Single +5 V Reference
The diagram below shows how to generate a 5 V output range
when using a single +5 V reference. VREF– is connected to 0 V
and ROFS is connected to VREF+. The +5 V reference input is
applied to these pins. With all 0s loaded to the DAC, the non-
inverting terminal of the output stage amplifier is at 0 V and
VOUT is simply the inverse of VREF+. With all 1s loaded to the
DAC, the noninverting terminal of the output stage amplifier is
at 5 V and so VOUT is also at 5 V.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD7849 to ADSP-2101/ADSP-2102 Interface
AD7849-DSP56000 Interface
A serial interface between the AD7849 and the DSP56000 is
shown in Figure 21. The DSP56000 is configured for Normal
Mode Asynchronous operation with Gated Clock. It is also set
up for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a “0”. SCK is internally generated on the
DSP56000 and applied to the AD7849 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK. The SC2
output provides the framing pulse for valid data. This line must
be inverted before being applied to the SYNC input of the
AD7849.
+15V
+5V
V
V
CC
DD
2
R
OFS
8
V
6
5
V
V
OUT
REF+
OUT
(–5V TO +5V)
AD586
4
R1
10kΩ
AD7849*
In this interface an LDAC pulse generated from an external
timer is used to update the outputs of the DACs. This update
can also be produced using a bit programmable control line
from the DSP56000.
C1
1nF
DGND
AGND
V
REF–
V
SS
SIGNAL GND
*
ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
Figure 19. Generating 5 V Output Range From Single +5 V
–12–
REV. B
AD7849
Figure 23 shows the LDAC input of the AD7849 being driven
from another bit programmable port line (PC1). As a result, the
DAC can be updated by taking LDAC low after the DAC input
register has been loaded.
TIMER
LDAC
DSP56000
SCLK
SCK
AD7849*
SDIN
STD
SC2
SYNC
LDAC
SYNC
SCLK
SDIN
PC1
PC0
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7849*
68HC11*
SCK
MOSI
Figure 21. AD7849 to DSP56000 Interface
AD7849-TMS320C2x Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22 shows a serial interface between the AD7849 and the
TMS320C2x DSP processor. In this interface, the CLKX and
FSX signals for the TMS320C2x should be generated using
external clock/timer circuitry. The FSX pin of the TMS320C2x
must be configured as an input. Data from the TMS320C2x is
valid on the falling edge of CLKX.
Figure 23. AD7849 to 68HC11 Interface
AD7849-87C51 Interface
A serial interface between the AD7849 and the 87C51 micro-
controller is shown in Figure 24. TXD of the 87C51 drives
SCLK of the AD7849 while RXD drives the serial data line of
the part. The SYNC signal is derived from the port line P3.3
and the LDAC line is driven port line P3.2.
CLOCK/TIMER
TMS320C2x
LDAC
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the most significant bits are the first to be transmitted to the
AD7849 and the last bit to be sent is the LSB of the word to be
loaded to the AD7849. When data is to be transmitted to the
part, P3.3 is taken low. Data on RXD is valid on the falling
edge of TXD. The 87C51 transmits its serial data in 8-bit bytes
with only eight falling clock edges occurring in the transmit
cycle. To load data to the AD7849, P3.3 is left low after the
first eight bits are transferred and a second byte of data is then
transferred serially to the AD7849. When the second serial
transfer is complete, the P3.3 line is taken high.
SYNC
FSX
AD7849*
CLKX
DX
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7849 to TMS320C2x Interface
The clock/timer circuitry generates the LDAC signal for the
AD7849 to synchronize the update of the output with the serial
transmission. Alternatively, the automatic update mode may be
selected by connecting LDAC to DGND.
AD7849-68HC11 Interface
Figure 24 shows the LDAC input of the AD7849 driven from
the bit programmable port line P3.2. As a result, the DAC out-
put can be updated by taking the LDAC line low following the
completion of the write cycle. Alternatively LDAC could be
hardwired low and the analog output will be updated on the
sixteenth falling edge of TXD after the SYNC signal for the
DAC has gone low.
Figure 23 shows a serial interface between the AD7849 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7849 while the MOSI output drives the serial data line
of the AD7849. The SYNC signal is derived from a port line
(PC0 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC0 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. To load data to the AD7849, PC0 is left
low after the first eight bits are transferred and a second byte of
data is then transferred serially to the AD7849. When the sec-
ond serial transfer is complete, the PC0 line is taken high.
P3.2
LDAC
SYNC
P3.3
TXD
RXD
87C51*
AD7849*
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. AD7849 to 87C51 Interface
REV. B
–13–
AD7849
APPLICATIONS
Opto-Isolated Interface
31. This leaves 800 ns for the LDAC pulse. Of course, as the
update rate requirement decreases, the number of possible
channels increases.
In many process control type applications it is necessary to
provide an isolation barrier between the controller and the unit
being controlled. Opto isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7849
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum.
The sequence of events to program the output channels in Fig-
ure 25 is as follows.
1. Take the SYNC line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
Figure 25 shows a 4-channel isolated interface using the
AD7849. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 14-bit or 16-bit resolu-
tion are provided in the circuit shown, but this may be expanded
to accommodate any number of DAC channels without any
extra isolation circuitry. The only limitation is the output up-
date rate. For example, if an output update rate of 10 kHz is
required, then all the DACs must be loaded and updated in a
time period of 100 µs. Operating at the maximum clock rate of
5 MHz means that it takes 3.2 µs to load a DAC. This means
that the total number of channels for this update rate would be
3. Take the SYNC line high.
4. Pulse the LDAC line low. This updates all output channels
simultaneously on the falling edge of LDAC.
To reduce the number of opto-couplers, the LDAC line could
be driven from a one-shot which is triggered by the rising edge
on the SYNC line. A low level pulse of 100 ns duration or
greater is all that is required to update the outputs.
V
V
V
V
DD
DD
DD
DD
DATA OUT
CONTROLLER
SDIN
CLOCK OUT
SCLK
V
OUT
V
OUT
A
SYNC
AD7849*
LDAC
SYNC OUT
+5V
+5V
+5V
+5V
DCEN
SDOUT
CONTROL OUT
SDIN
SCLK
SYNC
AD7849*
LDAC
V
V
OUT
B
C
D
OUT
QUAD OPTO-COUPLER
DCEN
SDOUT
SDIN
SCLK
SYNC
AD7849*
LDAC
V
V
OUT
OUT
DCEN
SDOUT
SDIN
SCLK
SYNC
AD7849*
LDAC
SDOUT
V
V
OUT
OUT
*ADDITIONAL PINS OMITTED FOR CLARITY
DCEN
Figure 25. Four-Channel Opto-Isolated Interface
–14–
REV. B
AD7849
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-20)
20
11
0.280 (7.11)
0.240 (6.10)
10
PIN 1
1
0.325 (8.25)
0.300 (7.62)
1.060 (26.90)
0.925 (23.50)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
0.150
(3.81)
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.78)
0.045 (1.15)
Cerdip (Q-20)
20
11
10
0.28 (7.11)
0.24 (6.1)
PIN 1
1
0.97 (24.64)
0.935 (23.75)
0.32 (8.128)
0.29 (7.366)
0.18 (4.57)
0.125 (3.18)
0.20 (5.0)
0.14 (3.56)
0.011 (0.28)
0.009 (0.23)
0.15 (3.8)
0.125 (3.18)
15
°
SEATING
PLANE
0
°
0.07 (1.78)
0.05 (1.27)
0.02 (0.5)
0.016 (0.41)
0.11 (2.79)
0.09 (2.28)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
SOIC (R-20)
20
11
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
10
1
PIN 1
0.1043 (2.65)
0.5118 (13.00)
0.4961 (12.60)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
REV. B
–15–
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