AD7851KRZ3_技术文档

14-Bit 333 kSPS

Serial A/D Converter

a

AD7851

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AV

AGND

Single 5 V Supply

AGND

DD

333 kSPS Throughput Rate/؎2 LSB DNL—A Grade

285 kSPS Throughput Rate/؎1 LSB DNL—K Grade

A and K Grades Guaranteed to 125؇C/238 kSPS

Throughput Rate

Pseudo-Differential Input with Two Input Ranges

System and Self-Calibration with Autocalibration on

Power-Up

AIN (+)

AIN (–)

DV

DD

T/H

AD7851

DGND

4.096V

REFERENCE

REF

IN

/

COMP

BUF

REF

OUT

Read/Write Capability of Calibration Data

Low Power: 60 mW Typ

AMODE

Power-Down Mode: 5 ␮W Typ Power Consumption

Flexible Serial Interface: 8051/SPI^®/QSPI™/␮P Compatible

24-Lead PDIP, SOIC, and SSOP Packages

CLKIN

C

CHARGE

REDISTRIBUTION

DAC

REF1

REF2

CAL

CONVST

SAR + ADC

CONTROL

C

BUSY

APPLICATIONS

SLEEP

Digital Signal Processing

Speech Recognition and Synthesis

Spectrum Analysis

CALIBRATION

MEMORY

AND CONTROLLER

DSP Servo Control

Instrumentation and Control Systems

High Speed Modems

Automotive

SERIAL INTERFACE/CONTROL REGISTER

SM1 SM2 SYNC DIN DOUT SCLK POLARITY

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7851 is a high speed, 14-bit ADC that operates from a

single 5 V power supply. The ADC powers up with a set of default

conditions at which time it can be operated as a read-only ADC.

The ADC contains self-calibration and system calibration options

to ensure accurate operation over time and temperature and has a

number of power-down options for low power applications.

1. Single 5 V supply.

2. Operates with reference voltages from 4 V to V_DD

3. Analog input ranges from 0 V to V_DD

4. System and self-calibration including power-down mode.

5. Versatile serial I/O port.

.

The AD7851 is capable of a 333 kHz throughput rate. The

input track-and-hold acquires a signal in 0.33 µs and features

a pseudo-differential sampling scheme. The AD7851 has the

added advantage of two input voltage ranges (0 V to V_REFand

–V_REF/2 to +V_REF/2 centered about V_REF/2). Input signal

range is to V_DDand the part is capable of converting full

power signals to 20 MHz.

CMOS construction ensures low power dissipation (60 mW typ)

with power-down mode (5 µW typ). The part is available in a

24-lead, 0.3 inch-wide PDIP, a 24-lead SOIC, and a 24-lead

SSOP package.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD7851

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5

TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 7

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9

AD7851 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . 10

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . 10

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 13

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 13

Writing to/Reading from the Calibration Registers . . . . . . 13

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 14

Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 14

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 15

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 18

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 19

POWER-UP TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 20

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 20

POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20

CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . 21

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 21

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 22

System Calibration Description . . . . . . . . . . . . . . . . . . . . 22

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 23

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 23

SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 24

Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 24

DETAILED TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 25

Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 26

Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 26

Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 27

CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 28

AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 28

Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 29

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 30

Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 30

MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 31

AD7851 to 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . 31

AD7851 to 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 31

AD7851 to ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . 32

AD7851 to DSP56000/1/2/L002 Interface . . . . . . . . . . . . . 32

AD7851 to TMS320C20/25/5x/LC5x Interface . . . . . . . . . 32

APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 33

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

REV. B

–2–

AD7851

SPECIFICATIONS^{1, 2}

A Grade: f_CLKIN= 7 MHz (–40؇C to +85؇C), f_SAMPLE= 333 kHz; K Grade: f_CLKIN= 6 MHz (0؇C to 85؇C), f_SAMPLE= 285 kHz; A and K Grade: f_CLKIN= 5 MHz

(to 125؇C), f_SAMPLE= 238 kHz; (AV_DD= DV_DD= 5.0 V ؎ 5%, REF_IN/REF_OUT= 4.096 V External Reference; SLEEP = Logic High; T_A= T_MINto T_MAX

,

unless otherwise noted.)

Parameter

Version A¹Version K¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio³(SNR) 77

78

dB min

dB max

Typically SNR Is 79.5 dB.

V_IN= 10 kHz, Sine Wave, f_SAMPLE= 333 kHz.

V_IN= 10 kHz, Sine Wave, f_SAMPLE= 333 kHz,

typically –96 dB.

V_IN= 10 kHz, f_SAMPLE= 333 kHz.

Total Harmonic Distortion (THD)

–86

–87

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

Second-Order Terms

Third-Order Terms

Full Power Bandwidth

–87

–86

20

–90

20

dB typ

MHz typ

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 333 kHz.

@ 3 dB.

DC ACCURACY

Resolution

14

2

10

1

14

1

10

1

Bits

Integral Nonlinearity

Differential Nonlinearity

Unipolar Offset Error

Positive Full-Scale Error

Negative Full-Scale Error

Bipolar Zero Error

LSB max

LSB typ

Guaranteed No Missed Codes to 14 Bits

Review: Adjusting the Offset Calibration

Register in the Calibration Registers section.

ANALOG INPUT

Input Voltage Ranges

0 V to V_REF0 V to V_REF

V_REF/2 V_REF/2

V

AIN(+) – AIN(–) = 0 V to V_REF, AIN(–) can be

biased up but AIN(+) cannot go below AIN(–).

AIN(+) – AIN(–) = –V_REF/2 to +V_REF/2, AIN(–)

should be biased up and AIN(+) can go below

AIN(–) but cannot go below 0 V.

Leakage Current

Input Capacitance

1

20

1

20

µA max

pF typ

REFERENCE INPUT/OUTPUT

REF_INInput Voltage Range

Input Impedance

REF_OUTOutput Voltage

REF_OUTTemperature Coefficient

4/V_DD

150

4/V_DD

150

V min/max Functional from 1.2 V.

kΩ typ

Resistor Connected to Internal Reference Node.

3.696/4.496 3.696/4.496

50

V min/max

ppm/°C typ

50

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

V_DD– 1.0

V min

0.4

10

0.4

10

V max

µA max

pF max

V_IN= 0 V or V_DD

.

4

Input Capacitance, C_IN

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating State Leakage Current

Floating State Output Capacitance⁴

Output Coding

V_DD– 0.4

V min

I_SOURCE= 200 µA.

0.4

10

0.4

10

V max

µA max

pF max

I_SINK= 0.8 mA.

Straight (Natural) Binary

Twos Complement

Unipolar Input Range.

Bipolar Input Range.

CONVERSION RATE

Conversion Time

Conversion + Track-and-Hold

Acquisition Time

2.78

3.0

3.25

3.5

µs max

19.5 CLKIN Cycles.

21 CLKIN Cycles Throughput Rate.

–3–

REV. B

AD7851

Parameter

Version A¹

Version K¹

Unit

Test Conditions/Comments

POWER PERFORMANCE

AV_DD,DV_DD

4.75/5.25

17

4.75/5.25

17

V min/max

mA max

I_DD

Normal Mode⁴

AV_DD= DV_DD= 4.75 V to 5.25 V. Typically

12 mA.

Sleep Mode⁵

With External Clock On

20

µA typ

µA max

Full Power-Down. Power management bits

in control register set as PMGT1 = 1, PMGT0 = 0.

Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Typically 1 µA. Full Power-Down. Power

management bits in control register set as

PMGT1 = 1, PMGT0 = 0.

600

10

600

10

With External Clock Off

300

µA typ

Partial Power-Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Normal Mode Power Dissipation

Sleep Mode Power Dissipation

With External Clock On

89.25

mW max

V_DD= 5.25 V: Typically 63 mW; SLEEP = V_DD

.

105

52.5

105

52.5

µW typ

µW max

V_DD= 5.25 V; SLEEP = 0 V.

V_DD= 5.25 V; Typically 5.25 µW; SLEEP = 0 V.

With External Clock Off

SYSTEM CALIBRATION

Offset Calibration Span⁶

Gain Calibration Span⁶

+0.05 × V_REF/–0.05 × V_REF

V max/min Allowable Offset Voltage Span for Calibration.

+1.025 × V_REF/–0.975 × V_REFV max/min Allowable Full-Scale Voltage Span for Calibration.

NOTES

¹Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C.

²Specifications apply after calibration.

³SNR calculation includes distortion and noise components.

⁴All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV_DD. No load on the digital outputs. Analog inputs at AGND.

⁵CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV_DD. No load on the digital outputs.

Analog inputs at AGND.

⁶The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are

not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) 0.05 × V_REF, and the

allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V_REF0.025 × V_REF). This is

explained in more detail in the Calibration section of the data sheet.

Specifications subject to change without notice.

REV. B

–4–

AD7851

TIMING SPECIFICATIONS¹

(AV_DD= DV_DD= 5.0 V ؎ 5%; f_CLKIN= 6 MHz, T_A= T_MINto T_MAX, unless otherwise noted.)

Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin

LOW, then the opposite edge of SCLK will apply.

Limit at T_MIN, T_MAX

(A, K Versions)

Parameter

Unit

Description

2

f_CLKIN

500

7

10

f_{CLK IN}

100

kHz min

MHz max

ns min

Master Clock Frequency

3

f_SCLK

Interface Modes 1, 2, 3 (External Serial Clock)

Interface Modes 4, 5 (Internal Serial Clock)

CONVST Pulse Width

4

t₁

t₂

50

3.25

–0.4 t_SCLK

0.4 t_SCLK

0.6 t_SCLK

30

45

30

20

0.4 t_SCLK

30

30/0.4 t_SCLK

50

90

50

ns max

µs max

CONVST↓ to BUSY↑ Propagation Delay

t_CONVERT

t₃

Conversion Time = 20 t_CLKIN

ns min

SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)

SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only

Delay from SYNC↓ until DOUT Three-State Disabled

Delay from SYNC↓ until DIN Three-State Disabled

Data Access Time after SCLK↓

ns min/max

ns min

ns max

ns min

ns min/max

ns max

ms typ

t₄₅

t₅

5

t₅₅_A

t₆

t₇

Data Setup Time prior to SCLK↑

Data Valid to SCLK Hold Time

t₈₆

t₉

SCLK High Pulse Width (Interface Modes 4 and 5)

SCLK Low Pulse Width (Interface Modes 4 and 5)

SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)

(Continuous SCLK) Does Not Apply to Interface Mode 3

SCLK↑ to SYNC↑ Hold Time

Delay from SYNC↑ until DOUT Three-State Enabled

Delay from SCLK↑ to DIN Being Configured as Output

Delay from SCLK↑ to DIN Being Configured as Input

CAL↑ to BUSY↑ Delay

CONVST↓ to BUSY↑ Delay in Calibration Sequence

Full Self-Calibration Time, Master Clock Dependent

6

t₁₀

t₁₁

t_11A

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t_CAL

7

8

2.5 t_CLKIN

41.7

9

(250026 t_CLKIN

Internal DAC Plus System Full-Scale Calibration Time, Master Clock

Dependent (222228 t_CLKIN

System Offset Calibration Time, Master Clock Dependent

(27798 t_CLKIN

Delay from CLK to SCLK

)

9

t_CAL1

37.04

4.63

65

ms typ

ns max

)

9

t_CAL2

)

t_DELAY

NOTES

¹Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V. See

Table X and timing diagrams for different interface modes and calibration.

²Mark/space ratio for the master clock input is 40/60 to 60/40.

³For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f _CLKIN

⁴The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-

Down section).

.

⁵Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁶For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t_SCLK= 0.5 t_CLKIN

.

⁷The time t₁₂is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t₁₂as quoted in the timing characteristics is the true bus

relinquish time of the part and is independent of the bus loading.

⁸The time t₁₄is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true

delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing

that a bus conflict will not occur.

⁹The typical time specified for the calibration times is for a master clock of 6 MHz.

Specifications subject to change without notice.

REV. B

–5–

AD7851

TYPICAL TIMING DIAGRAMS

1.6mA

I

OL

Figures 2 and 3 show typical read and write timing diagrams.

Figure 2 shows the reading and writing after conversion in

Interface Modes 2 and 3. To attain the maximum sample rate of

285 kHz in Interface Modes 2 and 3, reading and writing must

be performed during conversion. Figure 3 shows the timing dia-

gram for Interface Modes 4 and 5 with sample rate of 285 kHz.

At least a 330 ns acquisition time must be allowed (the time

from the falling edge of BUSY to the next rising edge of

CONVST) before the next conversion begins to ensure that the

part is settled to the 14-bit level. If the user does not want to

provide the CONVST signal, the conversion can be initiated in

software by writing to the control register.

TO

OUTPUT

2.1V

C

L

50pF

200µA

I

OH

Figure 1. Load Circuit for Digital Output Timing

Specifications

t_CONVERT= 3.25µs MAX, t₁= 100ns MIN,

t₅= 30ns MAX, t₇= 30ns MIN

POLARITY PIN LOGIC HIGH

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (I/P)

t₃

t₁₁

t₉

1

5

6

16

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t₁₀

t₅

t₆

DB11

t₁₂

t₆

DB15

THREE-STATE

DB0

t₇

t₈

DB15

DB0

DB11

Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

t_CONVERT= 3.25µs MAX, t₁= 100ns MIN,

t₅= 30ns MAX, t₇= 30ns MIN

POLARITY PIN LOGIC HIGH

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (O/P)

t₄

t₁₁

t₉

1

5

6

16

SCLK (O/P)

DOUT (O/P)

DIN (I/P)

t₁₀

t₅

t₁₂

t₆

THREE-STATE

t₇

THREE-STATE

DB15

DB11

DB0

t₈

DB15

DB0

DB11

Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

REV. B

–6–

AD7851

ABSOLUTE MAXIMUM RATINGS¹

Lead Temperature, Soldering

(T_A= 25°C, unless otherwise noted.)

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

REF_IN/REF_OUTto AGND . . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies². . . . . . . . . 10 mA

Operating Temperature Range

Commercial (A, K Versions) . . . . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latch-up.

PINOUT FOR DIP, SOIC, AND SSOP

SYNC

CONVST

24

23

22

21

20

19

18

17

1

2

BUSY

SCLK

CLKIN

DIN

SLEEP

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

3

θ

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . .34.7°C/W

4

REF /REF

IN

OUT

Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . 260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

AV

5

DOUT

DGND

DD

AD7851

TOP VIEW

(Not to Scale)

AGND

6

θ

_JAThermal Impedance . . 75°C/W (SOIC), 122.28°C/W (SSOP)

C

7

DV

DD

1

2

REF

θ

_JCThermal Impedance . . . 25°C/W (SOIC), 31.25°C/W (SSOP)

CAL

C

8

REF

AIN(+)

AIN(–)

NC

16 SM2

9

10

11

15

14

SM1

POLARITY

AGND 12

13 AMODE

NC = NO CONNECT

ORDERING GUIDE¹

Linearity

Error

Temperature

Range

Throughput

Rate (kSPS)

Throughput

at 125؇C (kSPS) Description

Package

Options³

Model

(LSB)²

AD7851AN

AD7851KN

AD7851AR

–40°C to +85°C

0°C to 85°C

2

1

2

1

2

333

285

333

285

333

238

PDIP

SOIC

SSOP

Evaluation Board

Controller Board

N-24

R-24

RS-24

–40°C to +85°C

0°C to 85°C

AD7851AR-REEL

AD7851ARZ³

AD7851ARZ-REEL³

AD7851KR

AD7851KR-REEL

0°C to 85°C

AD7851KRZ³

0°C to 85°C

AD7851KRZ-REEL³

AD7851ARS

0°C to 85°C

–40°C to +85°C

AD7851ARS-REEL

EVAL-AD7851CB⁴

EVAL-CONTROL BRD2⁵

NOTES

¹Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).

²Linearity error refers to the integral linearity error.

³Z = Pb-free part.

⁴This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

⁵This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a

complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, and a 12 V ac trans-

former. See the Evaluation Board application note for more information.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD7851 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. B

–7–

AD7851

TERMINOLOGY

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7851, it is defined as

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

V ²+V₃²+V₄²+V₅²+V₆²

(

)

2

THD(dB) = 20log

V

1

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Peak Harmonic or Spurious Noise

Total Unadjusted Error

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

This is the deviation of the actual code from the ideal code tak-

ing all errors into account (gain, offset, integral nonlinearity, and

other errors) at any point along the transfer function.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)

when operating in unipolar mode.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second-order terms include (fa + fb) and (fa – fb), while the

third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and

(fa – 2fb).

Positive Full-Scale Error

This applies to unipolar and bipolar modes and is the deviation of

the last code transition from the ideal AIN(+) voltage (AIN(–) +

full scale – 1.5 LSB) after the offset error has been adjusted out.

Negative Full-Scale Error

This applies to bipolar mode only and is the deviation of the

first code transition (10 . . . 000 to 10 . . . 001) from the ideal

AIN(+) voltage (AIN(–) – V_REF/2 + 0.5 LSB).

Testing is performed using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second-order terms are usually distanced

in frequency from the original sine waves while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in dBs.

Bipolar Zero Error

This is the deviation of the midscale transition (all 1s to all 0s)

from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode at the end

of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 1/2 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at

the output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitiza-

tion process; the more levels, the smaller the quantization noise.

The theoretical signal-to-(noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in ADC output at fre-

quency f to the power of the full-scale sine wave applied to the

supply voltage (V_DD). The units are in LSB, % of FS per % of

supply voltage, or expressed logarithmically, in dB (PSRR (dB)

= 10 log (Pf/Pfs)).

Full Power Bandwidth (FPBW)

FPBW is that frequency at which the amplitude of the recon-

structed fundamental (using FFTs and neglecting harmonics

and SNR) is reduced by 3 dB for a full-scale input.

Signal-to-(Noise + Distortion) = (6.02 N +1.76) dB

Thus, for a 14-bit converter, this is 86 dB.

REV. B

–8–

AD7851

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1

CONVST

Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold

mode and starts conversion. When this input is not used, it should be tied to DV_DD

.

2

BUSY

Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed

its on-chip calibration sequence.

3

4

SLEEP

Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the

internal voltage reference, provided there is no conversion or calibration being performed. Calibration data

is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

REF_IN/

REF_OUT

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears

at the pin. This pin can be overdriven by an external reference or can be taken as high as AV_DD. When this

pin is tied to AV_DD, or when an externally applied reference approaches V_DD, then the C_REF1pin should also

be tied to AV_DD

.

5

AV_DD

AGND

C_REF1

Analog Positive Supply Voltage, 5.0 V 5%.

6, 12

7

Analog Ground. Ground reference for track and hold, reference, and DAC.

Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is

used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.

8

C_REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip

reference. The capacitor should be tied between the pin and AGND.

9

AIN(+)

AIN(–)

Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time and cannot go below AIN(–) when the unipolar input range is selected.

10

Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time.

11

13

NC

No Connect Pin.

AMODE

Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range

0 to V_REF(i.e., AIN(+) – AIN(–) = 0 to V_REF). In this case, AIN(+) cannot go below AIN(–) and AIN(–)

cannot go below AGND. A Logic 1 selects range –V_REF/2 to +V_REF/2 (i.e., AIN(+) – AIN(–) = –V_REF/2 to

+V_REF/2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V_REF/2 to

allow AIN(+) to go from 0 V to +V_REFV.

14

POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high

and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and

Table IX for the SCLK active edges.

15

16

17

SM1

SM2

CAL

Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table X.

Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table X.

Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all

calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF

capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides

all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high.

18

19

20

21

DV_DD

DGND

DOUT

DIN

Digital Supply Voltage, 5.0 V 5%.

Digital Ground. Ground reference point for digital circuitry.

Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as

an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X).

22

23

CLKIN

SCLK

Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times.

Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

24

SYNC

This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).

REV. B

–9–

AD7851

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will

operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration.

Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC.

Extra features and flexibility, such as performing different power-down options, different types of calibrations, including system cali-

bration, and software conversion starts can be selected by writing to the part.

The AD7851 contains a control register, ADC output data register, status register, test register, and 10 calibration registers.

The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration

registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which regis-

ter is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that

the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall

write register hierarchy.

Table I. Write Register Addressing

ADDR1

ADDR0 Comment

0

1

0

1

0

This combination does not address any register so the subsequent 14 data bits are ignored.

This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.

This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

1

This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0

All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default

setting. There will always be two leading zeros when reading from the ADC output data register.

0

1

0

1

All successive read operations will be from TEST REGISTER.

All successive read operations will be from CALIBRATION REGISTERS.

All successive read operations will be from STATUS REGISTER.

RDSLT1, RDSLT0

ADDR1, ADDR0

DECODE

00

01

TEST

REGISTER

10

11

01

TEST

REGISTER

10

11

ADC OUTPUT

DATA REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

CALIBRATION

REGISTERS

CONTROL

REGISTER

GAIN (1)

OFFSET (1) OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

10

GAIN (1)

11

OFFSET (1)

10

GAIN (1)

11

OFFSET (1)

00

01

00

01

CALSLT1, CALSLT0

DECODE

CALSLT1, CALSLT0

DECODE

Figure 5. Read Register Hierarchy/Address Decoding

Figure 4. Write Register Hierarchy/Address Decoding

REV. B

–10–

AD7851

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The

control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described

below. The power-up status of all bits is 0.

MSB

ZERO

PMGT1

PMGT0

RDSLT1

RDSLT0

CONVST

CALMD

CALSLT1 CALSLT0

STCAL

LSB

2/3 MODE

Control Register Bit Function Descriptions

Bit No.

Mnemonic

Comment

These four bits must be set to 0 when writing to the control register.

13

12

11

10

ZERO

9

8

PMGT1

PMGT0

Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various

power-down modes (see Power-Down section for more details).

7

6

RDSLT1

RDSLT0

Theses two bits determine which register is addressed for the read operations. See Table II.

5

2/3 MODE

Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by

default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every

write cycle.

4

3

CONVST

Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration

(see Calibration section).

CALMD

Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. These bits have two functions:

With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-

formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on Calibration Registers for more details).

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

0

A full internal calibration is initiated where the internal DAC is calibrated followed by the

internal gain error, and finally the internal offset error is calibrated out. This is the default setting.

0

1

Here the internal gain error is calibrated out followed by the internal offset error calibrated

out.

0

1

0

1

0

This calibrates out the internal offset error only.

This calibrates out the internal gain error only.

A full system calibration is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out.

1

0

1

0

1

Here the system gain error is calibrated out followed by the system offset error.

This calibrates out the system offset error only.

This calibrates out the system gain error only.

REV. B

–11–

AD7851

STATUS REGISTER

The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The

status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the

bits in the status register is described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

MSB

ZERO

BUSY

ZERO

X

ZERO

PMGT1

PMGT0

RDSLT1

RDSLT0

CALMD

CALSLT1 CALSLT0

STCAL

LSB

2/3 MODE

Status Register Bit Function Descriptions

Bit No. Mnemonic Comment

15

14

ZERO

BUSY

This bit is always 0.

Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration

in progress. When this bit is 0, there is no conversion or calibration in progress.

13

12

11

10

ZERO

These four bits are always 0.

9

8

PMGT1

PMGT0

Power Management Bits. These bits along with the SLEEP pin will indicate whether the part is in a power-

down mode. (See Table VI in the Power-Down Options section for description.)

7

6

RDSLT1

RDSLT0

Both these bits are always 1 indicating it is the status register that is being read. (See Table II.)

5

2/3 MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in

Interface Mode 1. This bit is reset to 0 after every read cycle.

4

3

X

Don’t care bit.

CALMD

Calibration Mode Bit. A 0 in this bit indicates self-calibration is selected, and 1 in this bit indicates a system

calibration is selected (see Table III).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in

progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate which

of the calibration registers are addressed for reading and writing (see the Calibration Registers section for

more details)

REV. B

–12–

AD7851

CALIBRATION REGISTERS

The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset, and 1 for gain. Data can be written to or read from all

10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs

to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register, CALSLT1 and CALSLT0, determine which of the calibration registers are

addressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user

should not attempt to read from and write to the calibration registers at the same time.

Table IV. Calibration Register Addressing

CALSLT1 CALSLT0

This Combination Addresses the

0

1

0

1

0

1

Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.

Gain (1) and Offset (1) Registers. Two registers in total.

Offset Register. One register in total.

Gain Register. One register in total.

When reading from the calibration registers there will always be

two leading zeros for each of the registers. When operating in

Serial Interface Mode 1, the read operations to the calibration

registers cannot be aborted. The full number of read operations

must be completed (see the Serial Interface Summary section

for more detail).

Writing to/Reading from the Calibration Registers

For writing to the calibration registers, a write to the control reg-

ister is required to set the CALSLT0 and CALSLT1 bits. For

reading from the calibration registers, a write to the control regis-

ter is required to set the CALSLT0 and CALSLT1 bits, but also

to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the

calibration registers for reading). The calibration register pointer

is reset on writing to the control register setting the CALSLT1

and CALSLT0 bits, or upon completion of all the calibration

register write/read operations. When reset, it points to the first

calibration register in the selected write/read sequence. The cali-

bration register pointer will point to the gain calibration register

upon reset in all but one case, this case being where the offset

calibration register is selected on its own (CALSLT1 = 1,

CALSLT0 = 0). Where more than one calibration register is being

accessed, the calibration register pointer will be automatically

incremented after each calibration register write/read operation.

The order in which the 10 calibration registers are arranged is

shown in Figure 7. The user may abort at any time before all

the calibration register write/read operations are completed,

and the next control register write operation will reset the cali-

bration register pointer. The flowchart in Figure 8 shows the

sequence for writing to the calibration registers and Figure 9

shows the sequence for reading.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

REGISTER

CALIBRATION REGISTERS

CAL REGISTER

NO

WRITE

OPERATION

OR

(1)

(2)

GAIN REGISTER

OFFSET REGISTER

ADDRESS POINTER

ABORT

?

(3)

DAC 1st MSB REGISTER

YES

FINISHED

(10)

DAC 8th MSB REGISTER

Figure 8. Flowchart for Writing to the Calibration Registers

CALIBRATION REGISTER ADDRESS POINTER POSITION IS

DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS

ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.

Figure 7. Calibration Register Arrangement

REV. B

–13–

AD7851

This gives a resolution of 0.0006% of V_REFapproximately.

More accurately the resolution is (0.05 × V_REF)/2¹³V =

0.015 mV, with a 2.5 V reference. The maximum offset that

can be compensated for is 5% of the reference voltage, which

equates to 125 mV with a 2.5 V reference and 250 mV with

a 5 V reference.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,

RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

Q. If a +20 mV offset is present in the analog input signal and

the reference voltage is 2.5 V, what code needs to be written

to the offset register to compensate for the offset?

A. The 2.5 V reference implies that the resolution in the off-

set register is 5% × 2.5 V/2¹³= 0.015 mV. 20 mV/

0.015 mV = 1310.72; rounding to the nearest number gives

1311. In binary terms this is 0101 0001 1111, therefore

decrease the offset register by 0101 0001 1111.

READ CAL REGISTER

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

This method of compensating for offset in the analog input signal

allows for fine-tuning the offset compensation. If the offset on the

analog input signal is known, there will be no need to apply the

offset voltage to the analog input pins to do a system calibration.

The offset compensation can take place in software.

LAST

REGISTER

WRITE

OPERATION

OR

ABORT

?

NO

Adjusting the Gain Calibration Register

YES

The gain calibration register contains 16 bits, 2 leading 0s, and

14 data bits. The data bits are binary weighted as in the offset

calibration register. The gain register value is effectively multi-

plied by the analog input to scale the conversion result over the

full range. Increasing the gain register compensates for a

smaller analog input range and decreasing the gain register

compensates for a larger input range. The maximum analog

input range that the gain register can compensate for is 1.025

times the reference voltage, and the minimum input range is

0.975 times the reference voltage.

FINISHED

Figure 9. Flowchart for Reading from the

Calibration Registers

Adjusting the Offset Calibration Register

The offset calibration register contains 16 bits, 2 leading 0s, and

14 data bits. By changing the contents of the offset register, dif-

ferent amounts of offset on the analog input signal can be com-

pensated for. Increasing the number in the offset calibration

register compensates for the negative offset on the analog input

signal, and decreasing the number in the offset calibration regis-

ter compensates for the positive offset on the analog input signal.

The default value of the offset calibration register is approxi-

mately 0010 0000 0000 0000. This is not an exact value, but the

value in the offset register should be close to this value. Each of

the 14 data bits in the offset register is binary weighted; the MSB

has a weighting of 5% of the reference voltage, the MSB-1 has a

weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so

on down to the LSB which has a weighting of 0.0006%.

REV. B

–14–

AD7851

CIRCUIT INFORMATION

mum specified conversion time is 3.25 µs (6 MHz ) and 2.8 µs

(7 MHz) for the A and K Grades, respectively, for the AD7851

(19.5 t_CLKIN,CLKIN = 6 MHz/7 MHz). When a conversion is

completed, the BUSY output goes low, and then the result of

the conversion can be read by accessing the data through the

edge of serial interface. To obtain optimum performance from

the part, the read operation should not occur during the conver-

sion or 500 ns prior to the next CONVST rising edge. How-

ever, the maximum throughput rates are achieved by reading/

writing during conversion, and reading/writing during conver-

sion is likely to degrade the signal-to-(noise + distortion) by

only 0.5 dBs. The AD7851 can operate at throughput rates up

to 333 kHz. For the AD7851, a conversion takes 19.5 CLKIN

periods; 2 CLKIN periods are needed for the acquisition time

giving a full cycle time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz)

for the K grade and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for

the A grade.

The AD7851 is a fast, 14-bit single-supply ADC. The part

requires an external 6/7 MHz master clock (CLKIN), two

C_REFcapacitors, a CONVST signal to start conversion, and

power supply decoupling capacitors. The part provides the user

with track-and-hold, on-chip reference, calibration features,

ADC, and serial interface logic functions on a single chip. The

ADC section of the AD7851 consists of a conventional succes-

sive approximation converter based around a capacitor DAC.

The AD7851 accepts an analog input range of 0 V to +V_DD

where the reference can be tied to V_DD. The reference input to

the part is buffered on-chip.

A major advantage of the AD7851 is that a conversion can be

initiated in software as well as applying a signal to the CONVST

pin. Another innovative feature of the AD7851 is self-calibration

on power-up, which is initiated having a capacitor from the

CAL pin to AGND, to give superior dc accuracy (see the

Automatic Calibration on Power-On section). The part is avail-

able in a 24-lead SSOP package which offers the user consider-

able space-saving advantages over alternative solutions.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7851.

The DIN line is tied to DGND so that no data is written to the

part. The AGND and the DGND pins are connected together

at the device for good noise suppression. The CAL pin has a

0.01 µF capacitor to enable an automatic self-calibration on

power-up. The SCLK and SYNC are configured as outputs by

having SM1 and SM2 at DV_DD. The conversion result is output

in a 16-bit word with 2 leading zeros followed by the MSB of

the 14-bit result. Note that after the AV_DDand DV_DDpower up,

the part will require approximately 150 ms for the internal refer-

ence to settle and for the automatic calibration on power-up to

be completed.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7851 by pulsing the

CONVST input or by writing to the control register and setting

the CONVST bit to 1. On the rising edge of CONVST (or at

the end of the control register write operation), the on-chip

track-and-hold goes from track to hold mode. The falling edge

of the CLKIN signal which follows the rising edge of the

CONVST signal initiates the conversion, provided the rising

edge of CONVST occurs at least 10 ns typically before this

CLKIN edge. The conversion cycle will take 18.5 CLKIN peri-

ods from this CLKIN falling edge. If the 10 ns setup time is not

met, the conversion will take 19.5 CLKIN periods. The maxi-

For applications where power consumption is a major concern, the

SLEEP pin can be connected to DGND. (See the Power-Down

Options section for more detail on low power applications.)

7MHz/6MHz

OSCILLATOR

333kHz/285kHz PULSE

GENERATOR

ANALOG (5V)

SUPPLY

0.01␮F

10␮F

0.1␮F

CONVERSION

START INPUT

0V TO V

MASTER

CLOCK

INPUT

AV

DV

DD

REF

AIN(+)

DD

INPUT

AIN(–)

UNIPOLAR RANGE

OSCILLOSCOPE

CLKIN

SCLK

AMODE

CH1

C

SERIAL CLOCK OUTPUT

REF1

0.1␮F

470nF

CONVST

SYNC

DOUT

DIN

CH2

AD7851

C

REF2

CH3

CH4

0.01␮F

FRAME SYNC OUTPUT

SERIAL DATA OUTPUT

SLEEP

DV

POLARITY

DD

CAL

0.01␮F

SM1

SM2

AGND

DIN AT DGND

=> NO WRITING

TO DEVICE

2 LEADING ZEROS

FOR ADC DATA

DV

DD

DGND

REF /REF

IN

OUT

SERIAL MODE

SELECTION BITS

AUTO CAL ON

POWER-UP

INTERNAL/

0.1␮F EXTERNAL

REFERENCE

OPTIONAL

EXTERNAL AD1584/REF198

REFERENCE

ANALOG (5V)

SUPPLY

0.1␮F

10␮F

Figure 10. Typical Circuit

–15–

REV. B

AD7851

ANALOG INPUT

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance will depend on the amount of total harmonic

distortion (THD) that can be tolerated. The THD will increase

as the source impedance increases, and the performance will

degrade. Figure 12 shows a graph of the total harmonic distor-

tion versus the analog input signal frequency for different source

impedances. With the setup as in Figure 13, the THD is at the

–90 dB level. With a source impedance of 1 kΩ and no capacitor

on the AIN(+) pin, the THD increases with frequency.

The equivalent circuit of the analog input section is shown in

Figure 11. During the acquisition interval, the switches are both

in the track position and the AIN(+) charges the 20 pF capacitor

through the 125 Ω resistance. On the rising edge of CONVST,

Switches SW1 and SW2 go into the hold position retaining

charge on the 20 pF capacitor as a sample of the signal on

AIN(+). The AIN(–) is connected to the 20 pF capacitor, and

this unbalances the voltage at Node A at the input of the com-

parator. The capacitor DAC adjusts during the remainder of the

conversion cycle to restore the voltage at Node A to the correct

value. This action transfers a charge, representing the analog input

signal, to the capacitor DAC which in turn forms a digital repre-

sentation of the analog input signal. The voltage on the AIN(–)

pin directly influences the charge transferred to the capacitor

DAC at the hold instant. If this voltage changes during the con-

version period, the DAC representation of the analog input volt-

age will be altered. Therefore, it is most important that the voltage

on the AIN(–) pin remain constant during the conversion period.

Furthermore, it is recommended that the AIN(–) pin always be

connected to AGND or to a fixed dc voltage.

–50

THD VS. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

–60

–70

R

= 560⍀

IN

–80

–90

R

= 10⍀, 10nF

IN

AS IN FIGURE 13

–100

–110

125⍀

TRACK

AIN(+)

AIN(–)

CAPACITOR

DAC

80

1

10

20

50

100

120

140

166

SW1

NODE A

20pF

INPUT FREQUENCY (kHz)

HOLD

Figure 12. THD vs. Analog Input Frequency

SW2

In a single-supply application (5 V), the V+ and V– of the op amp

can be taken directly from the supplies to the AD7851 which elimi-

nates the need for extra external power supplies. When operating

with rail-to-rail inputs and outputs at frequencies greater than

10 kHz, care must be taken in selecting the particular op amp for

the application. In particular, for single-supply applications the

input amplifiers should be connected in a gain of –1 arrangement

to get the optimum performance. Figure 13 shows the arrangement

for a single-supply application with a 10 Ω and 10 nF low-pass fil-

ter (cutoff frequency 320 kHz) on the AIN(+) pin. Note that the

10 nF is a capacitor with good linearity to ensure good ac

COMPARATOR

HOLD

TRACK

C

REF2

Figure 11. Analog Input Equivalent Circuit

Acquisition Time

The track and hold amplifier enters its tracking mode on the fall-

ing edge of the BUSY signal. The time required for the track and

hold amplifier to acquire an input signal will depend on how

quickly the 20 pF input capacitance is charged. The acquisition

time is calculated using the formula

t

_ACQ= 9 × (R_IN+ 125 Ω) × 20 pF

performance. Recommended single-supply op amp is the AD820.

where R_INis the source impedance of the input signal, and

125 Ω, 20 pF is the input R, C.

5V

0.1␮F

10␮F

10k⍀

DC/AC Applications

For dc applications, high source impedances are acceptable,

provided there is enough acquisition time between conversions

to charge the 20 pF capacitor. The acquisition time can be cal-

culated from the above formula for different source impedances.

For example, with R_IN= 5 kΩ, the required acquisition time will

be 922 ns.

10k⍀

V

V+

IC1

IN

/2

10⍀

–V

/2 TO +V

REF

TO AIN(+) OF

AD7851

V

/2

10nF

(NPO)

REF

AD820

V–

10k⍀

Figure 13. Analog Input Buffering

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC low-pass

filter on the AIN(+) pin, as shown in Figure 13. In applications

where harmonic distortion and signal-to-noise ratio are critical, the

analog input should be driven from a low impedance source. Large

source impedances will significantly affect the ac performance

of the ADC. This may necessitate the use of an input buffer

amplifier. The choice of the op amp will be a function of the

particular application.

REV. B

–16–

AD7851

Input Ranges

Transfer Functions

The analog input range for the AD7851 is 0 V to V_REFin both

the unipolar and bipolar ranges.

For the unipolar range, the designed code transitions occur mid-

way between successive integer LSB values (i.e., 1/2 LSB,

3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is

straight binary for the unipolar range with 1 LSB = FS/16384 =

4.096 V/16384 = 0.25 mV when V_REF= 4.096 V. The ideal

input/output transfer characteristic for the unipolar range is

shown in Figure 16.

The only difference between the unipolar range and the bipolar

range is that in the bipolar range the AIN(–) has to be biased up

to +V_REF/2 and the output coding is twos complement (see

Table V and Figures 14 and 15). The unipolar or bipolar mode

is selected by the AMODE pin (0 for the unipolar range and 1

for the bipolar range).

OUTPUT

CODE

Table V. Analog Input Connections

111...111

111...110

111...101

Analog Input Input Connections Connection

Range

AIN(+)

AIN(–) Diagram

AMODE

111...100

1

0 V to V_REF

V_REF/2²

V_IN

AGND Figure 8

DGND

DV_DD

V_REF/2

Figure 9

NOTES

¹Output code format is straight binary.

FS

16384

000...011

1LSB =

²Range is V_REF/2 biased about V_REF/2. Output code format is twos complement.

000...010

Note that the AIN(–) pin on the AD7851 can be biased up above

AGND in the unipolar mode also, if required. The advantage of

biasing the lower end of the analog input range away from

AGND is that the user does not have to have the analog input

swing all the way down to AGND. This has the advantage in

true single-supply applications that the input amplifier does not

have to swing all the way down to AGND. The upper end of the

analog input range is shifted up by the same amount. Care must

be taken so that the bias applied does not shift the upper end of

the analog input above the AV_DDsupply. In the case where the

reference is the supply, AV_DD, the AIN(–) must be tied to

AGND in unipolar mode.

000...001

000...000

0V 1LSB

+FS – 1LSB

V

= (AIN(+) – AIN(–)), INPUT VOLTAGE

IN

Figure 16. AD7851 Unipolar Transfer Characteristic

Figure 15 shows the AD7851’s V_REF/2 bipolar analog input con-

figuration (where AIN(+) cannot go below 0 V, so for the full bipo-

lar range the AIN(–) pin should be biased to +V_REF/2). Once again

the designed code transitions occur midway between successive

integer LSB values. The output coding is twos complement with

1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. The ideal input/

output transfer characteristic is shown in Figure 17.

TRACK AND HOLD

OUTPUT

CODE

AIN(+)

AIN(–)

AMPLIFIER

V

= 0 TO V

REF

STRAIGHT

BINARY

FORMAT

IN

DOUT

011...111

011...110

AD7851

UNIPOLAR

ANALOG

AMODE

(V

/2) – 1 LSB

REF

INPUT RANGE

SELECTED

000...001

000...000

0V

Figure 14. 0 V to V_REFUnipolar Input Configuration

+ FS – 1 LSB

/2) + 1 LSB

111...111

(V

REF

TRACK AND HOLD

FS = V

V

100...010

REF

AIN(+)

AIN(–)

AMPLIFIER

FS

16384

V

= 0 TO V

V

TWOS

COMPLEMENT

FORMAT

1LSB =

IN

REF

/2

DOUT

100...001

100...000

REF

DV

DD

AD7851

V

/2

REF

UNIPOLAR

ANALOG

V

= (AIN(+) – AIN(–)), INPUT VOLTAGE

AMODE

IN

INPUT RANGE

SELECTED

Figure 17. AD7851 Bipolar Transfer Characteristic

Figure 15. V_REF/2 about V_REF/2 Bipolar Input Configuration

REV. B

–17–

AD7851

REFERENCE SECTION

AD7851 PERFORMANCE CURVES

For specified performance, it is recommended that when using

an external reference this reference should be between 4 V and

the analog supply AV_DD. The connections for the relevant refer-

ence pins are shown in the typical connection diagrams. If the

internal reference is being used, the REF_IN/REF_OUTpin should

have a 100 nF capacitor connected to AGND very close to the

REF_IN/REF_OUTpin. These connections are shown in Figure 18.

Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz

sample rate and 10 kHz input frequency.

0

AV = DV = 5V

DD

–20

–40

f_SAMPLE= 333kHz

f_IN= 10kHz

SNR = 79.5dB

THD = –95.2

If the internal reference is required for use external to the ADC,

it should be buffered at the REF_IN/REF_OUTpin and a 100 nF

capacitor connected from this pin to AGND. The typical noise

performance for the internal reference with 5 V supplies is

150 nV/√Hz @ 1 kHz and dc noise is 100 µV p-p.

–60

–80

10⍀

ANALOG

SUPPLY

5V

–100

–120

0.01␮F

10␮F

0.1␮F

0

20

40

60

80

100

AV

DV

DD

FREQUENCY (kHz)

DD

C

REF1

Figure 20. FFT Plot

0.1␮F

470nF

Figure 21 shows the SNR versus frequency for a 5 V supply and

a 4.096 external reference (5 V reference is typically 1 dB better

performance).

AD7851

C

REF2

0.01␮F

REF /REF

IN

OUT

79

78

77

76

75

0.1␮F

Figure 18. Relevant Connections When Using

Internal Reference

The other option is that the REF_IN/REF_OUTpin be overdriven

by connecting it to an external reference. This is possible due to

the series resistance from the REF_IN/REF_OUTpin to the internal

reference. This external reference can have a range that includes

AV_DD. When using AV_DDas the reference source, the 100 nF

capacitor from the REF_IN/REF_OUTpin to AGND should be as

close as possible to the REF_IN/REF_OUTpin, and also the C_REF1

pin should be connected to AV_DDto keep this pin at the same

level as the reference. The connections for this arrangement are

shown in Figure 19. When using AV_DDit may be necessary to

add a resistor in series with the AV_DDsupply. This will have the

effect of filtering the noise associated with the AV_DDsupply.

0

10

20

50

80

100

120

140

166

INPUT FREQUENCY (kHz)

Figure 21. SNR vs. Frequency

Figure 22 shows the power supply rejection ratio versus fre-

quency for the part. The power supply rejection ratio is defined

as the ratio of the power in ADC output at frequency f to the

power of a full-scale sine wave.

10⍀

ANALOG

SUPPLY

5V

0.1␮F

0.01␮F

10␮F

PSRR (dB) = 10 log (Pf/Pfs)

AV

DV

DD

Pf is the power at frequency f in ADC output, Pfs is the power

of a full-scale sine wave. Here a 100 mV peak-to-peak sine wave

is coupled onto the AV_DDsupply while the digital supply is left

unaltered.

C

REF1

0.01␮F

470nF

AD7851

10⍀

C

REF2

0.01␮F

REF /REF

IN OUT

0.1␮F

Figure 19. Relevant Connections When Using AV_DD

as the Reference

REV. B

–18–

AD7851

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

When using the SLEEP pin, the power management bits

AV = DV = 5.0V

DD

PMGT1 and PMGT0 should be set to 0 (default status on

power-up). Bringing the SLEEP pin logic high ensures normal

operation, and the part does not power down at any stage. This

may be necessary if the part is being used at high throughput

rates when it is not possible to power down between conver-

sions. If the user wishes to power down between conversions at

lower throughput rates (that is, <100 kSPS for the AD7851) to

achieve better power performances, then the SLEEP pin should

be tied logic low.

100mV pk-pk SINEWAVE ON AV

DD

REF = 4.098 EXT REFERENCE

IN

If the power-down options are to be selected in software only,

then the SLEEP pin should be tied logic high. By setting the

power management bits PMGT1 and PMGT0 as shown in

Table VI, a full power-down, full power-up, full power-down

between conversions, and a partial power-down between con-

versions can be selected.

0.91

13.4

25.7

38.3

50.3

63.5

74.8

87.4

100

INPUT FREQUENCY (kHz)

Figure 22. PSRR vs. Frequency

POWER-DOWN OPTIONS

A combination of hardware and software selection can also be

used to achieve the desired effect.

The AD7851 provides flexible power management to allow the

user to achieve the best power performance for a given throughput

rate. The power management options are selected by programming

the power management bits, PMGT1 and PMGT0, in the con-

trol register and by use of the SLEEP pin. Table VI summarizes

the power-down options that are available and how they can be

selected by using either software, hardware, or a combination of

both. The AD7851 can be fully or partially powered down. When

fully powered down, all the on-chip circuitry is powered down

and I_DDis 1 µA typ. If a partial power-down is selected, then all

the on-chip circuitry except the reference is powered down and I_DD

is 400 µA typ. The choice of full or partial power-down does not

give any significant improvement in throughput with a power-down

between conversions. (This is discussed in the Power-Up Times

section which follows.) But a partial power-down does allow the

on-chip reference to be used externally even though the rest of the

AD7851 circuitry is powered down. It also allows the AD7851 to

be powered up faster after a long power-down period when using

the on-chip reference. (See the Using the Internal (On-Chip) Ref-

erence section which follows.)

Table VI. Power Management Options

PMGT1 PMGT0 SLEEP

Bit

Comment

0

Full power-down between

conversions (HW/SW)

0

1

X

Full power-up (HW/SW)

Full power-down between

conversions (SW)

1

0

1

X

Full power-down (SW)

Partial power-down between

conversions (SW)

SW = Software selection, HW = Hardware selection.

CURRENT, I = 12mA TYP

ANALOG

6MHz/7MHz

OSCILLATOR

285kHz/333kHz PULSE

GENERATOR

(5V)

0.01␮F

0.1␮F

10␮F

0V TO V

MASTER

CLOCK

INPUT

REF

AV

DV

DD

AIN(+)

DD

INPUT

AIN(–)

UNIPOLAR RANGE

CLKIN

SCLK

AMODE

SERIAL CLOCK OUTPUT

C

REF1

CONVST

SYNC

0.1␮F

470nF

CONVERSION

START INPUT

LOW POWER

␮C/␮P

C

AD7851

REF2

0.01␮F

DOUT

DIN

SLEEP

SERIAL DATA OUTPUT

AUTO POWER-

DOWN AFTER

CONVERSION

DIN AT DGND

=> NO WRITING

TO DEVICE

DV

POLARITY

DD

CAL

0.01␮F

AGND

SM1

SM2

SERIAL MODE

SELECTION BITS

REF /REF

IN

DGND

OUT

AUTO CAL ON

POWER-UP

3-WIRE MODE

SELECTED

INTERNAL

REFERENCE

OPTIONAL

EXTERNAL

0.1␮F

REF198

REFERENCE

Figure 23. Typical Low Power Circuit

–19–

REV. B

AD7851

POWER-UP TIMES

Using an External Reference

When using the on-chip reference and powering up when AV_DD

and DV_DDare first connected, it is recommended that the

power-up calibration mode be disabled as explained previously.

When using the on-chip reference, the power-up time is effec-

tively the time it takes to charge up the external capacitor on the

REF_IN/REF_OUTpin. This time is given by the equation

When the AD7851 is powered up, the part is powered up

from one of two conditions: first, when the power supplies

are initially powered up and; secondly, when the parts are

powered up from either a hardware or software power-down

(see previous section).

t

_UP= 9 × R × C

When AV_DDand DV_DDare powered up, the AD7851 enters a

mode whereby the CONVST signal initiates a timeout followed

by a self-calibration. The total time taken for this timeout and

calibration is approximately 35 ms (see the Automatic Calibra-

tion on Power-On section). During power-up, the functionality

of the SLEEP pin is disabled, that is, the part will not power

down until the end of the calibration if SLEEP is tied logic low.

The power-up calibration mode can be disabled if the user

writes to the control register before a CONVST signal is applied. If

the timeout and self-calibration are disabled, then the user

must take into account the time required by the AD7851 to

power up before a self-calibration is carried out. This power-up

time is the time taken for the AD7851 to power up when

power is first applied (300 µs typ), or the time it takes the exter-

nal reference to settle to the 14-bit level—whichever is longer.

where R ≈ 150K and C = external capacitor.

The recommended value of the external capacitor is 100 nF;

this gives a power-up time of approximately 135 ms before a

calibration is initiated and normal operation should commence.

When C_REFis fully charged, the power-up time from a hardware or

software power-down reduces to 5 µs. This is because an internal

switch opens to provide a high impedance discharge path for the

reference capacitor during power-down—see Figure 25. An added

advantage of the low charge leakage from the reference capacitor

during power-down is that even though the reference is being pow-

ered down between conversions, the reference capacitor holds the

reference voltage to within 0.5 LSBs with throughput rates of 100

samples/second and over with a full power-down between conver-

sions. A high input impedance op amp, such as the AD707, should

be used to buffer this reference capacitor if it is being used exter-

nally. Note, if the AD7851 is left in its powered-down state for

more than 100 ms, the charge on C_REFwill start to leak away and

the power-up time will increase. If this long power-up time is a

problem, the user can use a partial power-down for the last conver-

sion so the reference remains powered up.

The AD7851 powers up from a full hardware or software

power-down in 5 µs typ. This limits the throughput which the

part is capable of to 120 kSPS for the K Grade and 126 kSPS

for the A Grade when powering down between conversions.

Figure 24 shows how power-down between conversions is

implemented using the CONVST pin. The user first selects

the power-down between conversions option by using the

SLEEP pin and the power management bits, PMGT1 and

PMGT0, in the control register (see previous section). In this

mode, the AD7851 automatically enters a full power-down at

the end of a conversion, that is, when BUSY goes low. The

falling edge of the next CONVST pulse causes the part to

power up. Assuming the external reference is left powered up,

the AD7851 should be ready for normal operation 5 µs after

this falling edge. The rising edge of CONVST initiates a con-

version so the CONVST pulse should be at least 5 µs wide.

The part automatically powers down on completion of the

conversion. Where the software convert start is used, the part

may be powered up in software before a conversion is initiated.

SWITCH OPENS

AD7851

DURING POWER-DOWN

REF /REF

IN

OUT

ON-CHIP

REFERENCE

EXTERNAL

CAPACITOR

TO OTHER

CIRCUITRY

BUF

Figure 25. On-Chip Reference During Power-Down

POWER VS. THROUGHPUT RATE

The main advantage of a full power-down after a conversion is

that it significantly reduces the power consumption of the part

at lower throughput rates. When using this mode of operation,

the AD7851 is only powered up for the duration of the conver-

sion. If the power-up time of the AD7851 is taken to be 5 µs

and it is assumed that the current during power up is 12 mA

typ, then power consumption as a function of throughput can

easily be calculated. The AD7851 has a conversion time of

3.25 µs with a 6 MHz external clock. This means the AD7851

consumes 12 mA typ for 8.25 µs in every conversion cycle if the

parts are powered down at the end of a conversion. The graph

in Figure 26 shows the power consumption of the AD7851 as a

function of throughput. Table VII lists the power consump-

tion for various throughput rates.

START CONVERSION ON RISING EDGE

POWER UP ON FALLING EDGE

5␮s

3.25␮s

CONVST

t

CONVERT

BUSY

POWER-UP NORMAL

FULL

POWER-UP

TIME

TIME OPERATION POWER-DOWN

Figure 24. Using the CONVST Pin to Power Up for

a Conversion

Using the Internal (On-Chip) Reference

As in the case of an external reference, the AD7851 can power

up from one of two conditions: power up after the supplies are

connected or power up from a hardware/software power-down.

REV. B

–20–

AD7851

Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN)

Table VII. Power Consumption vs. Throughput

Type of Self- or System Calibration

Time (ms)

Throughput Rate

Power AD7851

Full

Gain + Offset

Offset

41.7

9.26

4.63

1 kSPS

2 kSPS

9 mW

18 mW

Gain

100

Automatic Calibration on Power-On

The CAL pin has a 0.15 µA pull-up current source connected to it

internally to allow for an automatic full self-calibration on power-

on. A full self-calibration will be initiated on power-on if a 10 nF

capacitor is connected from the CAL pin to DGND. The internal

current source connected to the CAL pin charges up the external

capacitor and the time required to charge the external capacitor

will depend on the size of the capacitor itself. This time should be

large enough to ensure that the internal reference is settled before

the calibration is performed. However, if an external reference is

being used, this reference must have stabilized before the auto-

matic calibration is initiated (a larger capacitor on the CAL pin

should be used if the external reference has not settled when the

autocalibration is initiated). Once the capacitor on the CAL pin

has charged, the calibration will be performed and will take 32 ms

(4 MHz CLKIN). Therefore, the autocalibration should be com-

plete before operating the part. After calibration, the part is accu-

rate to the 12-bit level and the specifications quoted on the data

sheet apply. There will be no need to perform another calibra-

tion unless the operating conditions change or unless a system

calibration is required.

10

1

0.1

0.01

0

200 400 600 800 1000 1200 1400 1600 1800 2000

THROUGHPUT RATE (Hz)

Figure 26. Power vs. Throughput AD7851

NOTE

When setting the power-down mode by writing to the part,

operating in an interface mode other than Interface Modes 4

and 5 is recommended. This way the user has more control to

initiate power-down and power-up commands.

CALIBRATION SECTION

Calibration Overview

Self-Calibration Description

There are a four different calibration options within the self-

calibration mode. There is a full self-calibration where the

DAC, internal offset, and internal gain errors are calibrated

out; there is (Gain + Offset) self-calibration which calibrates

out the internal gain error and then the internal offset errors

(the internal DAC is not calibrated here); and finally, there are

self-offset and self-gain calibrations that calibrate out the inter-

nal offset errors and the internal gain errors, respectively.

The automatic calibration that is performed on power-up ensures

that the calibration options covered in this section will not be

required for a significant number of applications. The user will

not have to initiate a calibration unless the operating conditions

change (CLKIN frequency, analog input mode, reference voltage,

temperature, and supply voltages). The AD7851 has a number of

calibration features that may be required in some applications,

and there are a number of advantages in performing these differ-

ent types of calibration. First, the internal errors in the ADC can

be reduced significantly to give superior dc performance; and

second, system offset and gain errors can be removed. This allows

the user to remove reference errors (whether internal or external

references) and to make use of the full dynamic range of the

AD7851 by adjusting the analog input range of the part for a

specific system.

The internal capacitor DAC is calibrated by trimming each of the

capacitors in the DAC. It is the ratio of these capacitors to each

other that is critical, and so the calibration algorithm ensures

that this ratio is at a specific value by the end of the calibration

routine. For the offset and gain there are two separate capaci-

tors, one of which is trimmed when an offset or gain calibration

is performed. Again, it is the ratio of these capacitors to the

capacitors in the DAC that is critical and the calibration algo-

rithm ensures that this ratio is at a specified value for both

the offset and gain calibrations.

The AD7851 has two main calibration modes: self-calibration

and system calibration. There are various options in both self-

calibration and system calibration as outlined previously in

Table III. All the calibration functions can be initiated by puls-

ing the CAL pin or by writing to the control register and setting

the STCAL bit to 1. The timing diagrams that follow involve

using the CAL pin.

In bipolar mode, the midscale error is adjusted for an offset cali-

bration and the positive full-scale error is adjusted for the gain

calibration; in unipolar mode, the zero-scale error is adjusted for

an offset calibration and the positive full-scale error is adjusted

for a gain calibration.

The duration of each of the different types of calibrations is

given in Table VIII for the AD7851 with a 6 MHz/7 MHz mas-

ter clock. These calibration times are master-clock dependent.

REV. B

–21–

AD7851

Self-Calibration Timing

MAX SYSTEM FULL SCALE

Figure 27 shows the timing for a full self-calibration. Here the

BUSY line stays high for the full length of the self-calibration. A

self-calibration is initiated by bringing the CAL pin low (which

initiates an internal reset) and then high again or by writing to

the control register and setting the STCAL bit to 1 (note that if

the part is in a power-down mode, the CAL pulse width must

take account of the power-up time). The BUSY line is triggered

high from the rising edge of CAL (or the end of the write to the

control register if calibration is initiated in the software), and

BUSY will go low when the full self-calibration is complete after

IS 2.5ꢀ FROM V

REF

V

+ SYS OFFSET

REF

V

– 1LSB

V

– 1LSB

REF

SYSTEM OFFSET

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

CALIBRATION

SYS OFFSET

AGND

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS 5ꢀ OF V

REF

a time t_CAL

.

Figure 28. System Offset Calibration

Figure 29 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for a by a system gain calibration.

t₁= 100ns MIN,

t₁₅= 2.5 t_CLKINMAX,

t_CAL= 250026 t_CLKIN

t₁

CAL (I/P)

t₁₅

BUSY (O/P)

MAX SYSTEM FULL SCALE

IS 2.5ꢀ FROM V

REF

t_CAL

SYS FULL S.

V

– 1LSB

V

– 1LSB

Figure 27. Timing Diagram for Full Self-Calibration

REF

SYSTEM GAIN

CALIBRATION

For the self-(gain + offset), self-offset, and self-gain calibrations,

the BUSY line will be triggered high by the rising edge of the

CAL signal (or the end of the write to the control register if cali-

bration is initiated in the software) and will stay high for the full

duration of the self-calibration. The length of time that the BUSY

is high will depend on the type of self-calibration that is initiated.

Typical figures are given in Table VIII. The timing diagrams for

the other self-calibration options will be similar to Figure 27.

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

AGND

Figure 29. System Gain Calibration

Finally in Figure 30 both the system offset and gain are accounted

for by the system offset followed by a system gain calibration.

First the analog input range is shifted upwards by the positive

system offset and then the analog input range is adjusted at the

top end to account for the system full scale.

System Calibration Description

System calibration allows the user to take out system errors

external to the AD7851 as well as calibrate the errors of the

AD7851 itself. The maximum calibration range for the system

offset errors is 5% of V_REFand for the system gain errors is

2.5% of V_REF. This means that the maximum allowable system

offset voltage applied between the AIN(+) and AIN(–) pins for

the calibration to adjust out this error is 0.05 × V_REF(that is,

the AIN(+) can be 0.05 × V_REFabove AIN(–) or 0.05 × V_REF

below AIN(–)). For the system gain error, the maximum allow-

able system full-scale voltage, in unipolar mode, that can be

applied between AIN(+) and AIN(–) for the calibration to

adjust out this error is V_REF0.025 × V_REF(that is, the AIN(+)

can be V_REF+ 0.025 × V_REFabove AIN(–) or V_REF– 0.025 ×

V_REFabove AIN(–)). If the system offset or system gain errors

are outside the ranges mentioned, the system calibration algo-

rithm will reduce the errors as much as the trim range allows.

MAX SYSTEM FULL SCALE

IS 2.5ꢀ FROM V

REF

V

+ SYS OFFSET

REF

SYS F.S.

– 1LSB

SYS F.S.

– 1LSB

V

REF

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

SYSTEM GAIN

CALIBRATION

SYS OFFSET

AGND

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS 5ꢀ OF V

REF

MAX SYSTEM OFFSET

IS 5ꢀ OF V

REF

Figure 30. System (Gain + Offset) Calibration

Figures 28, 29, and 30 illustrate why a specific type of system

calibration might be used. Figure 28 shows a system offset

calibration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be accounted for by a system offset calibration.

REV. B

–22–

AD7851

System Gain and Offset Interaction

Next, the system offset voltage is applied to the AIN pin for a

minimum setup time (t_SETUP) of 100 ns before the rising edge of

the CONVST and remains until the BUSY signal goes low. The

rising edge of the CONVST starts the system offset calibration

section of the full system calibration and also causes the BUSY

signal to go high. The BUSY signal will go low after a time t_CAL2

when the calibration sequence is complete.

The inherent architecture of the AD7851 leads to an interaction

between the system offset and gain errors when a system calibra-

tion is performed. Therefore, it is recommended to perform the

cycle of a system offset calibration followed by a system gain cali-

bration twice. Separate system offset and system gain calibrations

reduce the offset and gain errors to at least the 14-bit level. By

performing a system offset calibration first and a system gain

calibration second, priority is given to reducing the gain error to

zero before reducing the offset error to zero. If the system errors

are small, a system offset calibration would be performed, fol-

lowed by a system gain calibration. If the systems errors are

large (close to the specified limits of the calibration range), this

cycle would be repeated twice to ensure that the offset and gain

errors were reduced to at least the 14-bit level. The advantage of

doing separate system offset and system gain calibrations is that

the user has more control over when the analog inputs need to

be at the required levels, and the CONVST signal does not have

to be used.

The timing for a system (gain + offset) calibration is very similar

to that of Figure 31, the only difference being that the time

t

_CAL1will be replaced by a shorter time of the order of t_CAL2as

the internal DAC will not be calibrated. The BUSY signal will

signify when the gain calibration is finished and when the part is

ready for the offset calibration.

t₁= 100ns MIN, t₁₄= 50 MAX,

t₁₅= 4 t_CLKINMAX, t_CAL1= 222228 t_CLKINMAX,

t_CAL2= 27798 t_CLKIN

t₁

CAL (I/P)

t₁₅

Alternatively, a system (gain + offset) calibration can be per-

formed. It is recommended to perform three system (gain +

offset) calibrations to reduce the offset and gain errors to the

14-bit level. For the system (gain + offset) calibration priority

is given to reducing the offset error to 0 before reducing the

gain error to 0. Thus, if the system errors are small then two

system (gain + offset) calibrations will be sufficient. If the

system errors are large (close to the specified limits of the

calibration range), three system (gain + offset) calibrations

may be required to reduce the offset and gain errors to at

least the 14-bit level. There will never be any need to perform

more than three system (offset + gain) calibrations.

BUSY (O/P)

t_CAL2

t_CAL1

t₁₆

CONVST (I/P)

t_SETUP

AIN (I/P)

V

OFFSET

V

SYSTEM FULL SCALE

Figure 31. Timing Diagram for Full System Calibration

The timing diagram for a system offset or system gain calibration is

shown in Figure 32. Here again the CAL is pulsed and the rising

edge of the CAL initiates the calibration sequence (or the calibra-

tion can be initiated in software by writing to the control register).

The rising edge of the CAL causes the BUSY line to go high and it

will stay high until the calibration sequence is finished. The analog

input should be set at the correct level for a minimum setup time

(t_SETUP) of 100 ns before the rising edge of CAL and stay at the

correct level until the BUSY signal goes low.

In bipolar mode, the midscale error is adjusted for an offset cali-

bration and the positive full-scale error is adjusted for the gain

calibration; in unipolar mode, the zero-scale error is adjusted for

an offset calibration and the positive full-scale error is adjusted

for a gain calibration.

System Calibration Timing

t₁

The calibration timing diagram in Figure 31 is for a full system

calibration where the falling edge of CAL initiates an internal

reset before starting a calibration (note that if the part is in power-

down mode the CAL pulse width must take account of the power-up

time). If a full system calibration is performed in the software, it

is easier to perform separate gain and offset calibrations so

that the CONVST bit in the control register does not have to be

programmed in the middle of the system calibration sequence.

The rising edge of CAL starts calibration of the internal DAC

and causes the BUSY line to go high. If the control register is

set for a full system calibration, the CONVST must be used

also. The full-scale system voltage should be applied to the ana-

log input pins from the start of calibration. The BUSY line will

go low once the DAC and system gain calibration are complete.

CAL (I/P)

t₁₅

BUSY (O/P)

t_CAL2

t_SETUP

V

OR V

SYSTEM OFFSET

AIN (I/P)

SYSTEM FULL SCALE

Figure 32. Timing Diagram for System Gain or System

Offset Calibration

REV. B

–23–

AD7851

SERIAL INTERFACE SUMMARY

SM1 and SM2. Interface Mode 1 may only be set by program-

ming the control register (see the Control Register section).

External SCLK and SYNC signals (SYNC may be hardwired

low) are required for Interfaces Modes 1, 2, and 3. In Interface

Modes 4 and 5, the AD7851 generates the SCLK and SYNC.

Table IX details the five interface modes and the serial clock

edges from which the data is clocked out by the AD7851

(DOUT edge) and that the data is latched in on (DIN edge).

The logic level of the POLARITY pin is shown and it is clear

that this reverses the edges.

Some of the more popular µProcessors, µControllers, and the

DSP machines that the AD7851 will interface to directly are

mentioned here. This does not cover all µCs, µPs, and DSPs. The

interface mode of the AD7851 that is mentioned here for a

specific µC, µP, or DSP is only a guide and in most cases another

interface mode may work just as well.

In Interface Modes 4 and 5 the SYNC always clocks out the

first data bit and SCLK will clock out the subsequent bits.

In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK

and the POLARITY pin. Thus, the SYNC may clock out the

MSB of data. Subsequent bits will be clocked out by the serial

clock, SCLK. The conditions for the SYNC clocking out the

MSB of data is as follows.

A more detailed timing description on each of the interface

modes follows.

With the POLARITY pin high, the falling edge of SYNC will

clock out the MSB if the serial clock is low when the SYNC

goes low.

Table X. Interface Mode Description

SM1 SM2

␮Processor

␮Controller

Interface

Mode

With the POLARITY pin low, the falling edge of SYNC will

clock out the MSB if the serial clock is high when the SYNC

goes low.

0

8XC51

8XL51

PIC17C42

1 (2-Wire)

DIN Is an Input/

Output Pin

Table IX. SCLK Active Edge for Different Interface Modes

0

1

68HC11

68L11

2 (3-Wire, SPI/QSPI)

Default Mode

Interface

Mode

POLARITY

DOUT

Edge

DIN

Edge

68HC16

3 (QSPI)

External Serial

Clock, SCLK, and

External Frame Sync,

SYNC Are Required

1, 2, 3

0

1

SCLK ↑

SCLK ↓

SCLK ↑

PIC16C64

ADSP-21xx

DSP56000

DSP56001

DSP56002

DSP56L002

TMS320C30

4, 5

0

1

SCLK ↓

SCLK ↑

SCLK ↓

Resetting the Serial Interface

When writing to the part via the DIN line there is the possibility

of writing data into the incorrect registers, such as the test regis-

ter for instance, or writing the incorrect data and corrupting the

serial interface. The SYNC pin acts as a reset. Bringing the

SYNC pin high resets the internal shift register. The first data

bit after the next SYNC falling edge will now be the first bit of

a new 16-bit transfer. It is also possible that the test register

contents were altered when the interface was lost. Therefore,

once the serial interface is reset, it may be necessary to write

the 16-bit word 0100 0000 0000 0010 to restore the test regis-

ter to its default value. Now the part and serial interface are

completely reset. It is always useful to retain the ability to pro-

gram the SYNC line from a port of the µController/DSP to have

the ability to reset the serial interface.

1

0

1

68HC16

4 (DSP Is Slave)

AD7851 Generates a

Noncontinuous

(16 Clocks) Serial

Clock, SCLK, and the

Frame Sync, SYNC

ADSP-21xx

DSP56000

DSP56001

5 (DSP Is Slave)

AD7851 Generates a

Continuous Serial

Clock, SCLK, and the

Frame Sync, SYNC

DSP56002

DSP56L002

TMS320C20

TMS320C25

TMS320C30

TMS320C5X

TMS320LC5X

Table X summarizes the interface modes provided by the

AD7851. It also outlines the various µP/µC to which the par-

ticular interface is suited.

The interface mode is determined by the serial mode selection

Pins SM1 and SM2. Interface Mode 2 is the default mode.

Note that Interface Mode 1 and 2 have the same combination of

REV. B

–24–

AD7851

DETAILED TIMING SECTION

Mode 1 (2-Wire 8051 Interface)

continuous SCLK shown by the dotted waveform in Figure 33

can be used provided the SYNC is low for only 16 clock pulses

in each of the read and write cycles. The POLARITY pin may

be used to change the SCLK edge which the data is sampled on

and clocked out on.

The read and writing takes place on the DIN line and the conver-

sion is initiated by pulsing the CONVST pin (note that in every

write cycle the 2/3 MODE bit must be set to 1). The conversion

may be started by setting the CONVST bit in the control register

to 1 instead of using the CONVST line.

In Figure 34, the SYNC line is tied low permanently, which

results in a different timing arrangement. With SYNC tied low

permanently, the DIN pin will never be three-stated. The 16th

rising edge of SCLK configures the DIN pin as an input or an

output as shown in the diagram. Here no more than 16 SCLK

pulses must occur for each of the read and write operations.

Below in Figure 33 and in Figure 34 are the timing diagrams for

Interface Mode 1 in the 2-wire interface mode. Here the DIN pin

is used for both input and output as shown. The SYNC input is

level-triggered active low and can be pulsed (Figure 33) or can be

constantly low (Figure 34).

If reading from and writing to the calibration registers in this

interface mode, all the selected calibration registers must be

read from or written to. The read and write operations cannot

be aborted. When reading from the calibration registers, the

DIN pin will remain as an output for the full duration of all

the calibration register read operations. When writing to the

calibration registers, the DIN pin will remain as an input for

the full duration of all the calibration register write operations.

In Figure 33, the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK, the DIN is con-

figured as an output. When the SYNC is taken high, the DIN is

three-stated. Taking SYNC low disables the three-state on the

DIN pin and the first SCLK falling edge clocks out the first data

bit. Once the 16 clocks have been provided, the DIN pin will

automatically revert back to an input after a time t₁₄. Note that a

t₃= –0.4 t_SCLKMIN (NONCONTINUOUS SCLK) ؎0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

t₃

t₁₁

t₃

t₁₁

1

16

1

16

SCLK (I/P)

t_5A

t₇

t₁₄

t₁₂

t₆

t₈

DIN (I/O)

DB15

DB0

DB15

DB0

THREE-STATE

DATA READ

DATA WRITE

DIN BECOMES AN OUTPUT

DIN BECOMES AN INPUT

Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (Interface Mode 1, SM1 = SM2 = 0)

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN,

t₁₃= 90 MAX, t₁₄= 50ns MAX

POLARITY PIN

LOGIC HIGH

6

1

16

1

16

SCLK (I/P)

DIN (I/O)

t₇

t₁₄

t₁₃

t₆

t₈

DB15

DB0

DB15

DB0

DATA READ

DATA WRITE

DIN BECOMES AN INPUT

Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low

(Interface Mode 1, SM1 = SM2 = 0)

REV. B

–25–

AD7851

Mode 2 (3-Wire SPI/QSPI Interface Mode)

Mode 3 (QSPI Interface Mode)

Default Interface Mode

Figure 36 shows the timing diagram for Interface Mode 3. In

this mode, the DSP is the master and the part is the slave. Here

the SYNC input is edge triggered from high to low, and the 16

clock pulses are counted from this edge. Because the clock

pulses are counted internally, the SYNC signal does not have to

go high after the 16th SCLK rising edge as shown by the dotted

SYNC line. Thus a frame sync that gives a high pulse of one

SCLK cycle minimum duration at the beginning of the read/

write operation may be used. The rising edge of SYNC enables

the three-state on the DOUT pin. The falling edge of SYNC

disables the three-state on the DOUT pin, and data is clocked

out on the falling edge of SCLK. Once SYNC goes high, the

three-state on the DOUT pin is enabled. The data input is

sampled on the rising edge of SCLK and thus has to be valid a

time t₇before this rising edge. The POLARITY pin may be

used to change the SCLK edge which the data is sampled on

and clocked out on. If resetting the interface is required, the

SYNC must be taken high and then low.

Figure 35 shows the timing diagram for Interface Mode 2 which

is the SPI/QSPI interface mode. Here the SYNC input is active

low and may be pulsed or tied permanently low. If SYNC is

permanently low, 16 clock pulses must be applied to the SCLK

pin for the part to operate correctly, and with a pulsed SYNC

input a continuous SCLK may be applied provided SYNC is

low for only 16 SCLK cycles. In Figure 35, the SYNC going

low disables the three-state on the DOUT pin. The first falling

edge of the SCLK after the SYNC going low clocks out the first

leading zero on the DOUT pin. The DOUT pin is three-stated

again a time t₁₂after the SYNC goes high. With the DIN pin,

the data input has to be set up a time t₇before the SCLK rising

edge as the part samples the input data on the SCLK rising edge

in this case. The POLARITY pin may be used to change the

SCLK edge which the data is sampled on and clocked out on. If

resetting the interface is required, the SYNC must be taken high

and then low.

t₃= –0.4 t_CLKINMIN (NONCONTINUOUS SCLK) 0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

t₆= 45ns MAX, t₇= 30ns MIN, t₈= 20ns MIN, t₁₁= 30ns MIN (NONCONTINUOUS SCLK),

30/0.4 t_SCLK= ns MIN/MAX (CONTINUOUS SCLK)

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t₉

t₁₁

t₃

1

2

3

4

5

6

16

t₅

t₁₀

t₆

t₁₂

t₆

THREE-STATE

DB15

DB14

DB13

DB12

DB11

DB10

t₈

DB0

t₇

t₈

DB15

DB14

DB13

DB12

DB11

DB10

DB0

Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output, and SYNC Input

(SM1 = SM2 = 0)

t₃= –0.4 t_CLKINMIN (NONCONTINUOUS SCLK) 0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

POLARITY PIN

LOGIC HIGH

t₆= 45ns MAX, t₇= 30ns MIN, t₈= 20ns MIN, t₁₁= 30ns MIN

SYNC (I/P)

t₉

t₁₁

t₃

1

2

3

4

5

6

16

SCLK (I/P)

t₅

t₁₀

t₆

t₁₂

t₆

THREE-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB12

DB11

DB10

t₈

DB0

t₇

t₈

DB15

DB14

DB13

DB12

DB11

DB10

DB0

Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)

REV. B

–26–

AD7851

MODE 4 and 5 (Self-Clocking Modes)

this time, the conversion will be complete, the SYNC will go

high, and the BUSY will go low. The next falling edge of the

CONVST must occur at least 330 ns after the falling edge of

BUSY to allow the track-and-hold amplifier adequate acquisi-

tion time as shown in Figure 38. This gives a throughput time of

3.68 µs. The maximum throughput rate in this case is 272 kHz.

The timing diagrams in Figure 38 and Figure 39 are for Inter-

face Modes 4 and 5. Interface Mode 4 has a noncontinuous

SCLK output and Interface Mode 5 has a continuous SCLK

output (SCLK is switched off internally during calibration for

both Modes 4 and 5). These modes of operation are especially

different from all the other modes because the SCLK and

SYNC are outputs. The SYNC is generated by the part as is the

SCLK. The master clock at the CLKIN pin is routed directly to

the SCLK pin for Interface Mode 5 (continuous SCLK) and the

CLKIN signal is gated with the SYNC to give the SCLK (non-

continuous) for Interface Mode 4.

OUTPUT SERIAL SHIFT

REGISTER IS RESET

t₁

CONVST

(I/P)

BUSY

(O/P)

SYNC

(O/P)

The most important point about these two modes of operation

is that the result of the current conversion is clocked out during

the same conversion and a write to the part during this conver-

sion is for the next conversion. The arrangement is shown in

Figure 37. Figure 38 and Figure 39 show more detailed timing

for the arrangement of Figure 37.

SCLK

(O/P)

t_CONVERT= 3.25␮s

400ns MIN

CONVERSION IS INITIATED

AND TRACK-AND-HOLD

GOES INTO HOLD

SERIAL READ

AND WRITE

OPERATIONS

READ OPERATION

SHOULD END 500ns

PRIOR TO NEXT RISING

EDGE OF CONVST

THE CONVERSION RESULT DUE TO

WRITE N+1 IS READ HERE

t₁= 100ns MIN

CONVERSION ENDS

3.25␮s LATER

WRITE N+1

WRITE N+2

WRITE N+3

READ N+2

Figure 38. Mode 4 and 5 Timing Diagram (SM1 = 1,

SM2 = 1 and 0)

READ N+1

READ N

CONVERSION N

CONVERSION N+1

CONVERSION N+2

In these interface modes, the part is now the master and the

DSP is the slave. Figure 39 is an expansion of Figure 38. The

AD7851 will ensure SYNC goes low after the rising edge C of

the continuous SCLK (Interface Mode 5) in Figure 39. Only in

the case of a noncontinuous SCLK (Interface Mode 4) will the

time t₄apply. The first data bit is clocked out from the falling

edge of SYNC. The SCLK rising edge clocks out all subsequent

bits on the DOUT pin. The input data present on the DIN pin

is clocked in on the rising edge of the SCLK. The POLARITY

pin may be used to change the SCLK edge which the data is

sampled on and clocked out on. The SYNC will go high after

the 16th SCLK rising edge and before the falling edge D of the

continuous SCLK in Figure 39. This ensures the part will not

clock in an extra bit from the DIN pin or clock out an extra bit

on the DOUT pin.

3.25␮s

Figure 37.

In Figure 38 the first point to note is that the BUSY, SYNC,

and SCLK are all outputs from the AD7851 with the CONVST

being the only input signal. Conversion is initiated with the

CONVST signal going low. This CONVST falling edge also

triggers the BUSY to go high. The CONVST signal rising edge

triggers the SYNC to go low after a short delay (2.5 t_CLKINto

3.5 t_CLKINtypically) after which the SCLK will clock out the

data on the DOUT pin during conversion. The data on the DIN

pin is also clocked in to the AD7851 by the same SCLK for the

next conversion. The read/write operations must be complete

after 16 clock cycles (which takes 3.25 µs approximately from

the rising edge of CONVST assuming a 6 MHz CLKIN). At

t₄= 0.6 t_SCLK(NONCONTINUOUS SCLK), t₆= 45ns MAX,

t₇= 30ns MIN, t₈= 20ns MIN , t_11A= 50ns MAX

POLARITY PIN

LOGIC HIGH

SYNC (O/P)

t_11A

t₄

C

t₉

D

1

2

3

4

5

6

16

SCLK (O/P)

t₁₀

t₅

t₁₂

t₆

THREE-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB12

DB11

DB10

t₈

DB0

t₇

t₈

DB15

DB14

DB13

DB12

DB11

DB10

DB0

Figure 39. Mode 4 and 5 Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and

Noncontinuous, SM1 = 1, SM2 = 1 and 0)

REV. B

–27–

AD7851

If the user has control of the CONVST pin but does not want to

exercise it for every conversion, the control register may be used

to start a conversion. Setting the CONVST bit in the control

register to 1 starts a conversion. If the user does not have con-

trol of the CONVST pin, a conversion should not be initiated

by writing to the control register. The reason for this is that the

user may get locked out and not be able to perform any further

write/read operations. When a conversion is started by writing to

the control register, the SYNC goes low and read/write opera-

tions take place while the conversion is in progress. However,

once the conversion is complete, there is no way of writing to

the part unless the CONVST pin is exercised. The CONVST

signal triggers the SYNC signal low which allows read/write

operations to take place. SYNC must be low to perform read/

write operations. The SYNC is triggered low by the CONVST

signal rising edge or by setting the CONVST bit in the control

register to 1. Therefore, if there is not full control of the

CONVST pin, the user may become locked out.

CONFIGURING THE AD7851

AD7851 as a Read-Only ADC

The AD7851 contains 14 on-chip registers that can be accessed

via the serial interface. In the majority of applications, it will not

be necessary to access all of these registers. Figure 40 outlines the

sequence used to configure the AD7851 as a read-only ADC. In

this case, there is no writing to the on-chip registers and only the

conversion result data is read from the part. Interface Mode 1

cannot be used in this case as it is necessary to write to the con-

trol register to set Interface Mode 1. Here the CLKIN signal is

applied directly after power-on; the CLKIN signal must be

present to allow the part to perform a calibration. This automatic

calibration will be completed approximately 42 ms after the

AD7851 has powered up (6 MHz CLK).

START

DIN CONNECTED TO DGND

POWER ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL

4, 5

INTERFACE

MODE

?

2, 3

PULSE CONVST PIN

READ

DATA

DURING

CONVERSION

?

YES

SYNC AUTOMATICALLY GOES LOW

AFTER CONVST RISING EDGE

NO

WAIT APPROXIMATELY 200ns

AFTER CONVST RISING EDGE

WAIT FOR BUSY SIGNAL

TO GO LOW

SCLK AUTOMATICALLY ACTIVE, READ

CONVERSION RESULT ON DOUT PIN

APPLY SYNC (IF REQUIRED), SCLK, AND READ

CONVERSION RESULT ON DOUT PIN

Figure 40. Flowchart for Setting Up and Reading from the AD7851

REV. B

–28–

AD7851

Writing to the AD7851

ence is made to the BUSY bit equal to a Logic 0, to indicate the

end of conversion, the user in this case would poll the BUSY bit

in the status register.

For accessing the on-chip registers, it is necessary to write to the

part. To enable Serial Interface Mode 1, the user must also write

to the part. Figures 41, 42, and 43 shows how to configure the

AD7851 for each of the different serial interface modes. The

continuous loops on all diagrams indicate the sequence for more

than one conversion. The options of using a hardware (pulsing

the CONVST pin) or software (setting the CONVST bit to 1)

conversion start, and reading/writing during or after conversion

are shown in Figures 41 and 42. If the CONVST pin is never

used, then it should be tied to DV_DDpermanently. Where refer-

Interface Modes 2 and 3 Configuration

Figure 41 shows the flowchart for configuring the part in Inter-

face Modes 2 and 3. For these interface modes, the read and

write operations take place simultaneously via the serial port.

Writing all 0s ensures that no valid data is written to any of the

registers. When using the software conversion start and transfer-

ring data during conversion, the Figure 41 note must be obeyed.

START

POWER ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

NOTE: WHEN USING THE SOFTWARE CONVERSION START AND

TRANSFERRING DATA DURING CONVERSION, THE USER MUST ENSURE

THE CONTROL REGISTER WRITE OPERATION EXTENDS BEYOND THE

FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE

CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED

TO 1 TO START THE NEXT CONVERSION.

SERIAL

INTERFACE

MODE

?

2, 3

INITIATE

CONVERSION

YES

IN

SOFTWARE

?

NO

TRANSFER

YES

DATA DURING

CONVERSION

PULSE CONVST PIN

NO

TRANSFER

DATA

YES

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS

CONVERSION RESULT ON DOUT PIN (SEE NOTE)

DURING

CONVERSION

?

WAIT APPROXIMATELY 200ns

AFTER CONVST RISING EDGE

NO

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

REGISTER SETTING CONVST BIT TO 1, READ CURRENT

CONVERSION RESULT ON DOUT PIN

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

WAIT FOR BUSY SIGNAL TO GO LOW

OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3

REV. B

–29–

AD7851

Interface Mode 1 Configuration

Interface Modes 4 and 5 Configuration

Figure 42 shows the flowchart for configuring the part in Inter-

face Mode 1. This mode of operation can only be enabled by

writing to the control register and setting the 2/3 MODE bit.

Reading and writing cannot take place simultaneously in this

mode as the DIN pin is used for both reading and writing.

Figure 43 shows the flowchart for configuring the AD7851 in

Interface Modes 4 and 5, the self-clocking modes. In this case, it

is not recommended to use the software conversion start option.

The read and write operations always occur simultaneously and

during conversion.

START

POWER ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

POWER ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

SERIAL

INTERFACE

MODE

?

4, 5

1

PULSE CONVST PIN

INITIATE

CONVERSION

YES

IN

SOFTWARE

?

SYNC AUTOMATICALLY GOES

LOW AFTER CONVST RISING EDGE

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE 2-WIRE MODE

AND CONVST BIT TO 1

NO

SCLK AUTOMATICALLY ACTIVE, READ CURRENT

CONVERSION RESULT ON DOUT PIN, WRITE

TO CONTROL REGISTER ON DIN PIN

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE 2-WIRE MODE

Figure 43. Flowchart for Setting Up, Reading, and Writing

in Interface Modes 4 and 5

PULSE CONVST PIN

READ

DATA

DURING

YES

CONVERSION

?

WAIT APPROXIMATLY 200ns

AFTER CONVST RISING EDGE

OR AFTER END OF CONTROL

REGISTER WRITE

NO

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DIN PIN

Figure 42. Flowchart for Setting Up, Reading, and Writing

in Interface Mode 1

REV. B

–30–

AD7851

MICROPROCESSOR INTERFACING

OPTIONAL

AD7851

In many applications, the user may not require the facility of

writing to the on-chip registers. The user may just want to

hardwire the relevant pins to the appropriate levels and read

the conversion result. In this case, the DIN pin can be tied low

so that the on-chip registers are never used. Now the part will

operate as a nonprogrammable analog-to-digital converter where

the CONVST is applied, a conversion is performed, and the result

may be read using the SCLK to clock out the data from the output

register on to the DOUT pin. Note that the DIN pin cannot be

tied low when using the 2-wire interface mode of operation.

7MHz/6MHz

CONVST

(8XC51/L51)

/PIC17C42

CLKIN

SCLK

DIN

P3.1/CK

P3.0/DT

(INT0/P3.2)/INT

MASTER

OPTIONAL

BUSY

SLAVE

SYNC

SM1

SM2

DGND FOR 8XC51/L51

POLARITY

DV FOR PIC17C42

The SCLK can also be connected to the CLKIN pin if the user

does not want to have to provide separate serial and master

clocks in Interface Modes 1, 2, and 3. With this arrangement,

the SYNC signal must be low for 16 SCLK cycles in Interface

Modes 1 and 2 for the read and write operations. For Interface

Mode 3, the SYNC can be low for more than 16 SCLK cycles

for the read and write operations. Note that in Interface Modes 4

and 5 the CLKIN and SCLK cannot be tied together as the

SCLK is an output and the CLKIN is an input.

DD

Figure 45. 8XC51/PIC17C42 Interface

AD7851 to 68HC11/16/L11/PIC16C42 Interface

Figure 46 shows the AD7851 SPI/QSPI interface to the

68HC11/16/L11/PIC16C42. The SYNC line is not used and is

tied to DGND. The µController is configured as the master by

setting the MSTR bit in the SPCR to 1, and thus provides the

serial clock on the SCK pin. For all the µControllers, the CPOL

bit is set to 1, and for the 68HC11/16/L11, the CPHA bit is set

to 1. The CLKIN and CONVST signals can be supplied from

the µController or from separate sources. The BUSY signal can

be used as an interrupt to tell the µController when the conver-

sion is finished, then the reading and writing can take place. If

required, the reading and writing can take place during conver-

sion and there will be no need for the BUSY signal in this case.

For no writing to the part then the DIN pin can be tied perma-

nently low. For the 68HC16 and the QSPI interface, the SM2

pin should be tied high and the SS line tied to the SYNC pin.

The microsequencer on the 68HC16 QSPI port can be used for

performing a number of read and write operations independent

of the CPU and storing the conversion results in memory with-

out taxing the CPU. The typical sequence of events would be

writing to the control register via the DIN line setting a conversion

start and at the same time reading data from the previous conver-

sion on the DOUT line, wait for the conversion to be finished

(3.25 µs with 6 MHz CLKIN), and then repeat the sequence. The

maximum serial frequency will be determined by the data access

and hold times of the µControllers and the AD7851.

CONVERSION

START

CONVST

7 MHz/6MHz

MASTER

CLOCK

SYNC SIGNAL

CLKIN

SCLK

AD7851

SYNC

TO GATE

THE SCLK

DIN

SERIAL DATA

OUTPUT

DOUT

Figure 44. Simplified Interface Diagram with DIN

Grounded and SCLK Tied to CLKIN

AD7851 to 8XC51/PIC17C42 Interface

Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42,

which only runs at 5 V. The 8XC51 is in Mode 0 operation.

This is a 2-wire interface consisting of the SCLK and the DIN

which acts as a bidirectional line. The SYNC is tied low. The

BUSY line can be used to give an interrupt driven system but

this would not normally be the case with the 8XC51/PIC17C42.

For the 8XC51, 12 MHz version, the serial clock will run at a

maximum of 1 MHz so that the serial interface to the AD7851

will only be running at 1 MHz. The CLKIN signal must be pro-

vided separately to the AD7851 from a port line on the 8XC51

or from a source other than the 8XC51. Here the SCLK cannot

be tied to the CLKIN as the 8XC51 only provides a noncon-

tinuous serial clock. The CONVST signal can be provided from

an external timer or conversion can be started in software if

required. The sequence of events would typically be writing to

the control register via the DIN line setting a conversion start

and the 2-wire interface mode (this would be performed in two

8-bit writes), wait for the conversion to be finished (3.25 µs with

6 MHz CLKIN), read the conversion result data on the DIN line

(this would be performed in two 8-bit reads), and then repeat the

sequence. The maximum serial frequency will be determined by

the data access and hold times of the 8XC51/PIC17C42 and the

AD7851.

OPTIONAL

AD7851

CONVST

7MHz/6MHz

68HC11/16/

L11/PIC16C42

DV

DD

CLKIN

SPI

HC16, QSPI

SYNC

SS

SCLK

DOUT

BUSY

SCK

MISO

IRQ

MASTER

OPTIONAL

DIN

MOSI

SLAVE

SM1

DIN AT DGND FOR

NO WRITING TO PART

DV FOR HC11, SPI

DD

SM2

DGND FOR HC16, QSPI

DV

POLARITY

DD

Figure 46. 68HC11 and 68HC16 Interface

REV. B

–31–

AD7851

AD7851 to ADSP-21xx Interface

OPTIONAL

7MHz/6MHz

AD7851

CONVST

Figure 47 shows the AD7851 interface to the ADSP-21xx. The

ADSP-21xx is the slave and the AD7851 is the master. The

AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in

the serial port control register should be set up as TFSR = RFSR

= 1 (need a frame sync for every transfer), SLEN = 15 (16-bit

word length), TFSW = RFSW = 1 (alternate framing mode for

transmit and receive operations), INVRFS = INVTFS = 1 (active

low RFS and TFS), IRFS = ITFS = 0 (external RFS and TFS),

and ISCLK = 0 (external serial clock). The CLKIN and

CONVST signals could be supplied from the ADSP-21xx or

from an external source. The AD7851 supplies the SCLK and

the SYNC signals to the ADSP-21xx and the reading and writing

takes place during conversion. The BUSY signal only indicates

when the conversion is finished and may not be required. The

data access and hold times of the ADSP-21xx and the AD7851

allow for a CLKIN of 7 MHz/6 MHz with a 5 V supply.

DSP

CLKIN

SCLK

56000/1/2/L002

SCK

DOUT

SRD

SC2

IRQ

SYNC

OPTIONAL

BUSY

DIN

MASTER

STD

SLAVE

DIN AT DGND FOR

NO WRITING TO PART

SM1

SM2

DV

DD

POLARITY

Figure 48. DSP56000/1/2/L002 Interface

AD7851 to TMS320C20/25/5x/LC5x Interface

Figure 49 shows the AD7851 to the TMS320Cxx interface. The

AD7851 is the master and operates in Interface Mode 5. For the

TMS320Cxx, the CLKX, CLKR, FSX, and FSR pins should all

be configured as inputs. The CLKX and the CLKR should be

connected together as should the FSX and FSR. Because the

AD7851 is the master and the reading and writing occurs during

the conversion, the BUSY only indicates when the conversion is

finished and thus may not be required. Again the data access and

hold times of the TMS320Cxx and the AD7851 allow for a

CLKIN of 7 MHz/6 MHz.

OPTIONAL

AD7851

CONVST

7MHz/6MHz

CLKIN

ADSP-21xx

SCLK

DOUT

SCK

DR

RFS

TFS

IRQ

SYNC

SLAVE

OPTIONAL

BUSY

DIN

DT

MASTER

OPTIONAL

AD7851

TMS320C20/

25/5x/LC5x

7MHz/6MHz

CONVST

CLKIN

SCLK

SM1

SM2

DIN AT DGND FOR

NO WRITING TO PART

CLKX

CLKR

DR

POLARITY

DV

DD

DOUT

SYNC

FSR

FSX

Figure 47. ADSP-21xx Interface

SLAVE

MASTER

OPTIONAL

AD7851 to DSP56000/1/2/L002 Interface

INT0

DT

BUSY

DIN

OPTIONAL

Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface.

Here the DSP5600x is the master and the AD7851 is the slave.

The AD7851 is in Interface Mode 3. The setting of the bits in

the registers of the DSP5600x would be for synchronous opera-

tion (SYN = 1), internal frame sync (SCD2 = 1), internal clock

(SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames

sync only active at beginning of the transfer (FSL1 = 0, FSL0 =

1). A gated clock can be used (GCK = 1) or if the SCLK is to

be tied to the CLKIN of the AD7851, then there must be a con-

tinuous clock (GCK = 0). Again the data access and hold times

of the DSP5600x and the AD7851 should allow for an SCLK of

7 MHz/6 MHz.

SM1

SM2

DIN AT DGND FOR

NO WRITING TO PART

POLARITY

DV

DD

Figure 49. TMS320C20/25/5x Interface

REV. B

–32–

AD7851

APPLICATION HINTS

Grounding and Layout

Evaluating the AD7851 Performance

The analog and digital supplies to the AD7851 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The part has very good

immunity to noise on the power supplies as can be seen by the

PSRR versus frequency graph. However, care should still be

taken with regard to grounding and layout.

The recommended layout for the AD7851 is outlined in the

evaluation board for the AD7851. The evaluation board package

includes a fully assembled and tested evaluation board, documen-

tation, and software for controlling the board from the PC via the

EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD

can be used in conjunction with the AD7851 Evaluation Board,

as well as many other Analog Devices evaluation boards ending in

the CB designator, to demonstrate/evaluate the ac and dc perfor-

mance of the AD7851.

The printed circuit board that houses the AD7851 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7851 is the only device requiring

an AGND to DGND connection, then the ground planes should

be connected at the AGND and DGND pins of the AD7851. If

the AD7851 is in a system where multiple devices require AGND

to DGND connections, the connection should still be made at

one point only, a star ground point which should be established as

close as possible to the AD7851.

The software allows the user to perform ac (Fast Fourier Trans-

form) and dc (histogram of codes) tests on the AD7851. It also

gives full access to all the AD7851 on-chip registers allowing for

various calibration and power-down options to be programmed.

AD785x Family

All parts are 12 bit, 200 kSPS, 3.0 V to 5.5 V, except the

AD7856 which is 14 bit, 285 kSPS, 5 V supply.

AD7853 – Single-Channel Serial

AD7854 – Single-Channel Parallel

AD7856 – Eight-Channel Serial

AD7858 – Eight-Channel Serial

AD7859 – Eight-Channel Parallel

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7851 to avoid noise coupling. The power

supply lines to the AD7851 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum in parallel with 0.1 µF ca-

pacitors to AGND. All digital supplies should have a 0.1 µF disc

ceramic capacitor to DGND. To achieve the best from these de-

coupling components, they must be placed as close as possible

to the device, ideally right up against the device. In systems

where a common supply voltage is used to drive both the AV_DD

and DV_DDof the AD7851, it is recommended that the system’s

AV_DDsupply is used. In this case, there should be a 10 Ω resistor

between the AV_DDpin and DV_DDpin. This supply should have the

recommended analog supply decoupling capacitors between the

AV_DDpin of the AD7851 and AGND and the recommended

digital supply decoupling capacitor between the DV_DDpin of the

AD7851 and DGND.

REV. B

–33–

AD7851

OUTLINE DIMENSIONS

24-Lead Plastic Dual In-Line Package [PDIP]

(N-24)

Dimensions shown in inches and (millimeters)

1.185 (30.01)

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

1.165 (29.59)

1.145 (29.08)

24

1

13

12

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.180

(4.57)

MAX

0.015 (0.38) MIN

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.100

(2.54)

BSC

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.060 (1.52) SEATING

0.050 (1.27)

0.045 (1.14)

PLANE

COMPLIANT TO JEDEC STANDARDS MO-095AG

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

24-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-24)

Dimensions shown in millimeters and (inches)

15.60 (0.6142)

15.20 (0.5984)

24

13

12

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

1

2.65 (0.1043)

2.35 (0.0925)

0.75 (0.0295)

0.25 (0.0098)

؋

45؇

0.30 (0.0118)

0.10 (0.0039)

8؇

0؇

0.51 (0.0201) SEATING

0.31 (0.0122)

1.27 (0.0500)

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COPLANARITY

0.10

PLANE

COMPLIANT TO JEDEC STANDARDS MS-013AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. B

–34–

AD7851

24-Lead Shrink Small Outline Package [SSOP]

(RS-24)

Dimensions shown in millimeters

8.50

8.20

7.90

24

1

13

12

8.20

7.80

7.40

5.60

5.30

5.00

1.85

1.75

1.65

0.10

COPLANARITY

2.00 MAX

0.95

0.75

0.55

8؇

4؇

0؇

0.25

0.09

0.65

BSC

0.38

0.22

0.05 MIN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-150AG

REV. B

–35–

AD7851

Revision History

Location

Page

3/04—Data Sheet changed from REV. A to REV. B.

Moved Page Index from Page 33 to Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Updated TERMINOLOGY section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Updated PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Updated Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Updated CONTROL REGISTER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Updated Status Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Updated Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Updated TYPICAL CONNECTION DIAGRAM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Updated Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Updated Figure 18 and Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Updated Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Updated Automatic Calibration on Power-On section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Updated Mode 4 and 5 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Updated AD7851 as a Read-Only ADC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Updated Figure 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Updated Figure 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Updated Figures 42 and 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Updated Figure 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

REV. B

–36–


型号：	AD7851KRZ3
厂家：	ADI
描述：	14-Bit 333 kSPS Serial A/D Converter 14位333 kSPS的串行A / D转换器转换器
文件：	总36页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7851KRZ3 [ADI]

相关型号：

AD7853

AD7853AN

AD7853AN

AD7853ANZ

AD7853ANZ

AD7853AR

AD7853AR

AD7853AR-REEL

AD7853AR-REEL

AD7853ARS

AD7853ARS

AD7853ARS-REEL7