AD7854LARS-REEL_技术文档

3 V to 5 V Single Supply, 200 kSPS

12-Bit Sampling ADC

a

AD7854/AD7854L*

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Specified for V_DDof 3 V to 5.5 V

Read-Only Operation

AV

AGND

DD

AD7854–200 kSPS; AD7854L–100 kSPS

System and Self-Calibration with Autocalibration on

Power-Up

AIN(+)

AIN(–)

AD7854/AD7854L

T/H

2.5V

REFERENCE

Low Power

DV

DD

AD7854: 15 mW (V_DD= 3 V)

AD7854L: 5.5 mW (V_DD= 3 V)

Automatic Power-Down After Conversion (25 ␮W)

Flexible Parallel interface

12-Bit Parallel / 8-Bit Parallel (AD7854)

28-Pin DIP, SOIC and SSOP Packages (AD7854)

COMP

BUF

REF

/

IN

REF

OUT

C

REF1

DGND

CHARGE

REDISTRIBUTION

DAC

APPLICATIONS

C

Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)

Pen Computers

Instrumentation and Control Systems

High Speed Modems

REF2

CLKIN

CONVST

BUSY

SAR + ADC

CONTROL

CALIBRATION

MEMORY

AND CONTROLLER

PARALLEL INTERFACE/CONTROL REGISTER

GENERAL DESCRIPTION

DB11–DB0

HBEN

CS

RD

WR

The AD7854/AD7854L is a high speed, low-power, 12-bit

ADC which operates from a single 3 V or 5 V power supply, the

AD7854 being optimized for speed and the AD7854L for low

power. The ADC powers up with a set of default conditions at

which time it can be operated as a read-only ADC. The ADC

contains self-calibration and system calibration options to en-

sure accurate operation over time and temperature and has a

number of power-down options for low power applications.

PRODUCT HIGHLIGHTS

1. Operation with either 3 V or 5 V power supplies.

2. Automatic calibration on power-up.

3. Flexible power management options including automatic

power-down after conversion.

The AD7854 is capable of 200 kHz throughput rate while the

AD7854L is capable of 100 kHz throughput rate. The input

track-and-hold acquires a signal in 500 ns and features a pseudo-

differential sampling scheme. The AD7854 and AD7854L input

voltage range is 0 to V_REF(unipolar) and –V_REF/2 to +V_REF/2,

centered at V_REF/2 (bipolar). The coding is straight binary in

unipolar mode and twos complement in bipolar mode. Input

signal range is to the supply and the part is capable of convert-

ing full-power signals to 100 kHz.

4. Operates with reference voltages from 1.2 V to A_VDD

.

5. Analog input ranges from 0 V to AV_DD

6. Self- and system-calibration.

7. Versatile parallel I/0 port.

.

8. Lower power version AD7854L.

CMOS construction ensures low power dissipation of typically

5.4 mW for normal operation and 3.6 µW in power-down mode.

The part is available in 28-pin, 0.3 inch wide dual-in-line pack-

age (DIP), 28-lead small outline (SOIC) and 28-lead small

shrink outline (SSOP) packages.

*Patent pending.

See Page 35 for data sheet index.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

PRELIMINARY TECHNICAL DATA

REV. 0

AD7854/AD7854L–SPECIFICATIONS^{1, 2}

(AV_DD= DV_DD= +3.0 V to +5.5 V, REF_IN/REF_OUT= 2.5 V

External Reference, f_CLKIN= 4 MHz (1.8 MHz for L Version); f_SAMPLE= 200 kHz (AD7854), 100 kHz (AD7854L); SLEEP = Logic High; T_A= T_MINto

T_MAX, unless otherwise noted.) Specifications in () apply to the AD7854L.

Parameter

A Version¹

B Version¹

S Version¹Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio³

(SNR)

70

71

70

dB min

Typically SNR is 72 dB

V_IN= 10 kHz Sine Wave, f_SAMPLE= 200 kHz

(100 kHz)

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

–78

–80

–78

dB max

V_IN= 10 kHz Sine Wave, f_SAMPLE= 200 kHz

(100 kHz)

V_IN= 10 kHz Sine Wave, f_SAMPLE= 200 kHz

(100 kHz)

Intermodulation Distortion (IMD)

Second Order Terms

–78

–80

–78

dB typ

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 200 kHz

(100 kHz)

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 200 kHz

(100 kHz)

Third Order Terms

DC ACCURACY

Resolution

Integral Nonlinearity

12

±1

±2

±1

12

±1

12

±1

Bits

LSB max

LSB typ

LSB max

±0.5

±1

±0.5

±1

5 V Reference V_DD= 5 V

Guaranteed No Missed Codes to 12 Bits

Differential Nonlinearity

Total Unadjusted Error

Unipolar Offset Error

Positive Full-Scale Error

Negative Full-Scale Error

Bipolar Zero Error

±1

±0.5

ANALOG INPUT

Input Voltage Ranges

0 to V_REF

Volts

i.e., AIN(+) – AIN(–) = 0 to V_REF, AIN(–) can be

biased up but AIN(+) cannot go below AIN(-).

i.e., AIN(+) – AIN(–) = –V_REF/2 to +V_REF/2, AIN(–)

should be biased to +V_REF/2 and AIN(+) can go below

AIN(–) but cannot go below 0 V.

±V_REF/2

Leakage Current

Input Capacitance

±1

20

±1

20

±1

20

µA max

pF typ

REFERENCE INPUT/OUTPUT

REF_INInput Voltage Range

Input Impedance

2.3/V_DD

150

2.3/V_DD

150

2.3/V_DD

150

V min/max

kΩ typ

Functional from 1.2 V

REF_OUTOutput Voltage

REF_OUTTempco

2.3/2.7

20

2.3/2.7

20

2.3/2.7

20

V min/max

ppm/°C typ

LOGIC INPUTS

Input High Voltage, V_INH

2.4

2.1

2.4

2.1

2.4

2.1

V min

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

Input Low Voltage, V_INL

0.8

0.6

0.8

0.6

0.8

0.6

V max

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

Input Current, I_IN

Input Capacitance, C_IN

±10

10

±10

10

±10

10

µA max

pF max

Typically 10 nA, V_IN= 0 V or V_DD

4

LOGIC OUTPUTS

Output High Voltage, V_OH

I_SOURCE= 200 µA

4

2.4

4

2.4

4

2.4

V min

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁴

Output Coding

0.4

±10

10

0.4

±10

10

0.4

±10

10

V max

µA max

pF max

I_SINK= 1.6 mA

Straight (Natural) Binary

Twos Complement

Unipolar Input Range

Bipolar Input Range

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time

4.5 (9)

0.5 (1)

4.5 (9)

0.5 (1)

4.5 (9)

0.5 (1)

µs max

µs min

(L Versions Only)

PRELIMINARY TECHNICAL DATA

–2–

REV. 0

AD7854/AD7854L

Parameter

A Version¹

B Version¹

S Version¹Units

Test Conditions/Comments

POWER REQUIREMENTS

AV_DD,DV_DD

+3.0/+5.5

5.5 (1.8)

+3.0/+5.5

5.5 (1.8)

+3.0/+5.5

5.5 (1.8)

V min/max

I_DD

Normal Mode⁵

mA max

AV_DD= DV_DD= 4.5 V to 5.5 V. Typically 4.5 mA

(1.5mA);

AV_DD= DV_DD= 3.0 V to 3.6 V. Typically 4.0 mA

(1.5 mA).

Sleep Mode⁶

With External Clock On

10

400

5

10

400

5

10

400

5

µA typ

µA max

Full power down. Power management bits in control

register set as PMGT1 = 1, PMGT0 = 0.

Partial power down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

Typically 1 µA. Full power down. Power management

bits in control register set as PMGT1 = 1,

PMGT0 = 0.

With External Clock Off

200

µA typ

Partial Power Down. Power management bits in

control register set as PMGT1 = 1, PMGT0 = 1.

V_DD= 5.5 V: Typically 25 mW (8); SLEEP = V_DD

V_DD= 3.6 V: Typically 15 mW (5.4); SLEEP = V_DD

Normal Mode Power Dissipation

30 (10)

20 (6.5)

30 (10)

20 (6.5)

30 (10)

20 (6.5)

mW max

Sleep Mode Power Dissipation

With External Clock On

55

36

27.5

55

36

27.5

55

36

27.5

µW typ

µW max

V_DD= 5.5 V; SLEEP = 0 V

V_DD= 3.6 V; SLEEP = 0 V

V_DD= 5.5 V: Typically 5.5 µW; SLEEP = 0 V

With External Clock Off

18

µW max

V_DD= 3.6 V: Typically 3.6 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span⁷

Gain Calibration Span⁷

+0.05 × V_REF/–0.05 × V_REF

+0.025 × V_REF/–0.025 × V_REF

V max/min Allowable Offset Voltage Span for Calibration

V max/min Allowable Full-Scale Voltage Span for Calibration

NOTES

¹Temperature ranges as follows: A, B Versions, –40°C to +85°C, S Version, –55°C to +125°C.

²Specifications apply after calibration.

³SNR calculation includes distortion and noise components.

⁴Sample tested @ +25°C to ensure compliance.

⁵All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital outputs. Analog inputs @ AGND.

⁶CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital outputs.

Analog inputs @ AGND.

⁷The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans

and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V_REF

and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V_REF± 0.025 × V_REF

(unipolar mode) and V_REF/2 ± 0.025 × V_REF(bipolar mode)). This is explained in more detail in the calibration section of the data sheet.

,

Specifications subject to change without notice.

–3–

PRELIMINARY TECHNICAL DATA

REV. 0

AD7854/AD7854L

(AV_DD= DV_DD= +3.0 V to +5.5 V; f_CLKIN= 4 MHz for AD7854 and 1.8 MHz for AD7854L;

T_A= T_MINto T_MAX, unless otherwise noted)

TIMING SPECIFICATIONS¹

Limit at T_MIN, T_MAX

(A, B, S Versions)

3 V

Parameter 5 V

Units

Description

2

f_CLKIN

500

4

500

4

kHz min

MHz max

ns min

ns max

µs max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

ms typ

Master Clock Frequency

1.8

100

50

4.5

10

15

5

1.8

100

50

4.5

10

15

5

L Version

CONVST Pulse Width

3

t₁

t₂

CONVST to BUSY ↑ Propagation Delay

Conversion Time = 18 t_CLKIN

L Version 1.8 MHz CLKIN. Conversion Time = 18 t_CLKIN

HBEN to RD Setup Time

HBEN to RD Hold Time

CS to RD to Setup Time

CS to RD Hold Time

RD Pulse Width

Data Access Time after RD

Bus Relinquish Time after RD

t_CONVERT

t₃

t₄

t₅

t₆

t₇₄

t₈

0

100

50

5

50

100

15

5

15

5

100

40

5

40

60

100

50

5

50

100

15

5

15

5

100

40

5

40

60

5

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

Minimum Time Between Reads

HBEN to WR Setup Time

HBEN to WR Hold Time

CS to WR Setup Time

CS to WR Hold Time

WR Pulse Width

Data Setup Time Before WR

Data Hold Time After WR

New Data Valid Before Falling Edge of BUSY

HBEN Low Pulse Duration

4

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

HBEN High Pulse Duration

Propagation Delay from HBEN Falling to Data Valid

Propagation Delay from HBEN Rising to Data Valid

CS↑ to BUSY ↑ in Calibration Sequence

Full Self-Calibration Time, Master Clock Dependent (125013

2.5 t_CLKIN

31.25

2.5 t_CLKIN

31.25

6

t_CAL

t_CLKIN

Internal DAC Plus System Full-Scale Cal Time, Master Clock

Dependent (111114 t_CLKIN

System Offset Calibration Time, Master Clock Dependent

(13899 t_CLKIN

)

6

t_CAL1

27.78

3.47

27.78

3.47

ms typ

)

6

t_CAL2

)

NOTES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V. See

Table TBD and timing diagrams for different interface modes and calibration.

²Mark/Space ratio for the master clock input is 40/60 to 60/40.

³The CONVST pulse width here only applies for normal operation. When the part is in power-down mode, a different CONVST pulse width applies (see Power-

Down section).

⁴Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁵t₉is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t ₉, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

⁶The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to

the 1.8 MHz master clock.

Specifications subject to change without notice.

PRELIMINARY TECHNICAL DATA

–4–

REV. 0

AD7854/AD7854L

ORDERING GUIDE

I

1.6mA

OL

Linearity

Error

Power

Dissipation Package

(mW)

Model

(LSB)¹

Option²

TO OUTPUT

+2.1V

AD7854AQ

AD7854SQ

AD7854AR

AD7853BR

±1

±1/2

±1

±1/2

±1

20

6.85

N-24

R-24

RS-24

R-24

RS-24

C

L

100pF

I

200µA

OH

AD7854ARS

AD7854LAR³

AD7854LARS³

EVAL-AD7854CB⁴

±1

Figure 1. Load Circuit for Digital Output Timing

Specifications

EVAL-CONTROL BOARD⁵

ABSOLUTE MAXIMUM RATINGS¹

NOTES

¹Linearity error refers to the integral linearity error.

²N = Plastic DIP; R = SOIC; RS = SSOP.

³L signifies the low power version.

(T_A= +25°C unless otherwise noted)

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

REF_IN/REF_OUTto AGND . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies². . . . . . . . ±10 mA

Operating Temperature Range

⁴This can be used as a stand-alone evaluation board or in conjunction with the

EVAL-CONTROL BOARD for evaluation/demonstration purposes.

⁵This board is a complete unit allowing a PC to control and communicate with

all Analog Devices, Inc. evaluation boards ending in the CB designator.

PINOUT FOR DIP, SOIC AND SSOP

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 25°C/W

Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

θ_JCThermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP)

Lead Temperature, Soldering

BUSY

CLKIN

1

2

28

27

CONVST

WR

3

26 DB11

RD

DB10

25

4

CS

REF /REF

IN

DB9

24

5

OUT

AD7854

TOP VIEW

(Not to Scale)

AV

6

23

22

21

20

19

18

17

16

15

DGND

DD

AGND

7

DV

DD

8

C

DB8

REF1

C

9

DB7

DB6

DB5

DB4

REF2

AIN(+)

10

11

12

13

14

AIN(–)

HBEN

DB0

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >? kV

DB3

DB2

DB1

NOTES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latchup.

–5–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

TERMINOLOGY

Total Harmonic Distortion

Integral Nonlinearity

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7853/AD7853L, it is

defined as:

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

2

(V₂+V₃+V₄+V₅+V₆

)

THD (dB) = 20log

V₁

Differential Nonlinearity

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Unadjusted Error

Peak Harmonic or Spurious Noise

This is the deviation of the actual code from the ideal code tak-

ing all errors into account (Gain, Offset, Integral Nonlinearity,

and other errors) at any point along the transfer function.

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for ADCs

where the harmonics are buried in the noise floor, it will be a

noise peak.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)

when operating in the unipolar mode.

Positive Full-Scale Error

Intermodulation Distortion

This applies to the unipolar and bipolar modes and is the deviation

of the last code transition from the ideal AIN(+) voltage after the

offset error has been adjusted out. For unipolar mode, the ideal

AIN(+) voltage is (AIN(–) + V_REF– 1.5 LSB). For bipolar mode,

the ideal AIN(+) voltage is (AIN(-) +VREF/2 – 1.5 LSB).

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

Negative Full-Scale Error

This applies to the bipolar mode only and is the deviation of the

first code transition (00 . . . 000 to 00 . . . 001) from the ideal

AIN(+) voltage (AIN(–) – V_REF/2 + 0.5 LSB).

Testing is performed using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used. In

this case, the second order terms are usually distanced in fre-

quency from the original sine waves while the third order terms

are usually at a frequency close to the input frequencies. As a

result, the second and third order terms are specified separately.

The calculation of the intermodulation distortion is as per the

THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

Bipolar Zero Error

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of

conversion. Track/Hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig-

nals up to half the sampling frequency (f_S/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76) dB

Thus for a 12-bit converter, this is 74 dB.

PRELIMINARY TECHNICAL DATA

–6–

REV. 0

AD7854/AD7854L

PIN FUNCTION DESCRIPTION

Mnemonic

Description

1

CONVST

Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold

mode and starts conversion. When this input is not used, it should be tied to DV_DD

.

2

RD

Read Input. Active low logic input. Used in conjunction with CS and HBEN to read from internal

registers.

3

4

5

WR

CS

Write Input. Active low logic input. Used in conjunction with CS and HBEN to write to internal registers.

Chip Select Input. Active low logic input. The device is selected when this input is active.

REF_IN/

REF_OUT

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears

at the pin. This pin can be overdriven by an external reference and can be taken as high as AV_DD. When

this pin is tied to AV_DD, then the C_REF1pin should also be tied to AV_DD

.

6

7

8

AV_DD

AGND

C_REF1

Analog Positive Supply Voltage, +3.0 V to +5.5 V.

Analog Ground. Ground reference for track/hold, reference and DAC.

Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the

internal DAC. The capacitor should be tied between the pin and AGND.

9

C_REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip

reference. The capacitor should be tied between the pin and AGND.

10

11

12

AIN(+)

AIN(–)

HBEN

Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time, and cannot go below AIN(–) when the unipolar input range is selected.

Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time.

High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a

read cycle with HBEN low. When HBEN is high then the high byte of data that is written to or read from

the part is on DB0 to DB7. When HBEN is low then the lowest byte of data being written to the part is on

DB0 to DB7. If reading from the part with HBEN low then the lowest 12 bits of data appear on pins DB0

to DB11. This allows a single read from the ADC or from the control register in a 16-bit bus system.

However, two reads are needed to access the calibration registers. Also, two writes are necessary to write to

any of the registers.

13–21 DB0–DB8

Data Bits 0 to 8. Three state data I/O pins that are controlled by CS, RD, WR and HBEN. Data output is

straight binary (unipolar mode) or twos complement (bipolar mode).

22

23

DV_DD

Digital Supply Voltage, +3.0 V to +5.5 V.

DGND

Digital Ground. Ground reference point for digital circuitry.

24–26 DB9–DB11

Data Bits 9 to 11. Three state data I/O pins that are controlled by CS, RD, WR and HBEN. Data output

is straight binary (unipolar mode) or twos complement (bipolar mode).

27

28

CLKIN

BUSY

Master Clock Signal for the device (4 MHz for AD7854, 1.8 MHz for AD7854L). Sets the conversion and

calibration times.

Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until

conversion is completed. BUSY is also used to indicate when the AD7854/AD7854L has completed its on-

chip calibration sequence.

–7–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

AD7854/AD7854L ON-CHIP REGISTERS

The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the

AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DV_DDfor operating the AD7854/AD7854L as a

read-only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-

bration, and software conversion start can be selected by writing to the part.

The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra-

tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and

calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first

8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the

8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each

transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to de-

termine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the address

bits, while Figure 2 shows the overall write register hierarchy.

Table I. Write Register Addressing

ADDR1

ADDR0 Comment

0

1

0

1

0

This combination does not address any register.

This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.

This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are writ-

ten to the selected calibration register.

1

This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to

the control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un-

til the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0

All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-

up setting. There is always four leading zeros when reading from the ADC output data register.

0

1

0

1

All successive read operations are from the TEST REGISTER.

All successive read operations are from the CALIBRATION REGISTERS.

All successive read operations are from the STATUS REGISTER.

RDSLT1, RDSLT0

DECODE

ADDR1, ADDR0

DECODE

00

01

TEST

10

11

01

TEST

10

11

ADC OUTPUT

DATA REGISTER

CALIBRATION

REGISTERS

CONTROL

REGISTER

CALIBRATION

REGISTERS

CONTROL

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

10

GAIN(1)

11

OFFSET(1)

10

GAIN(1)

11

00

01

00

01

CALSLT1, CALSLT0

DECODE

CALSLT1, CALSLT0

DECODE

Figure 3. Read Register Hierarchy/Address Decoding

REV. 0

Figure 2. Write Register Hierarchy/Address Decoding

PRELIMINARY TECHNICAL DATA

–8–

AD7854/AD7854L

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The

control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described be-

low. The power-up status of all bits is 0.

MSB

ZERO

PMGT1

PMGT0

RDSLT1

STCAL

RDSLT0

AMODE

CONVST

CALMD

CALSLT1

CALSLT0

LSB

Control Register Bit Function Description

Bit

Mnemonic

Comment

13

12

11

10

ZERO

These four bits must be set to 0 when writing to the control register.

9

8

PMGT1

PMGT0

Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various

power-down modes (See Power-Down section for more details).

7

6

RDSLT1

RDSLT0

Theses two bits determine which register is addressed for the read operations. See Table II.

5

AMODE

Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit

position selects range 0 to V_REF(i.e., AIN(+) – AIN(–) = 0 to V_REF). In this range AIN(+) cannot go

below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this

bit position selects range –V_REF/2 to +V_REF/2 (i.e., AIN(+) – AIN(–) = –V_REF/2 to +V_REF/2). AIN(+)

cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +V_REF/2 to allow

AIN(+) to go as low as AIN(–) –V_REF/2 V. Data coding is twos complement for this range.

4

3

CONVST

CALMD

Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration

(see Calibration section).

Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-

formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on the calibration registers for more details).

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

0

A full internal calibration is initiated. First the internal DAC is calibrated, then the

internal gain error and finally the internal offset error are removed. This is the default setting.

0

1

0

1

0

1

0

1

0

First the internal gain error is removed, then the internal offset error is removed.

The internal offset error only is calibrated out.

The internal gain error only is calibrated out.

A full system calibration is initiated. First the internal DAC is calibrated, followed by the

system gain error calibration, and finally the system offset error calibration.

1

0

1

0

1

First the system gain error is calibrated out followed by the system offset error.

The system offset error only is removed.

The system gain error only is removed.

–9–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

STATUS REGISTER

The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The

status register is selected by writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in

the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT = 1

READ STATUS REGISTER

Figure 4. Flowchart for Reading the Status Register

MSB

ZERO

ONE

ZERO

BUSY

ZERO

PMGT1

PMGT0

STCAL

ONE

AMODE

CALMD

CALSLT1 CALSLT0

LSB

Status Register Bit Function Description

Bit Mnemonic

Comment

15

14

ZERO

These six bits are always 0.

13

12

11

10

ZERO

9

8

PMGT1

PMGT0

Power Management Bits. These bits along with the SLEEP pin will indicate if the part is in a power-down

mode or not. See Table VI in Power-Down Section for description.

7

6

ONE

Both these bits are always 1.

5

4

3

AMODE

Analog Mode Bit. When this bit is a 0, the device is set up for the unipolar analog input range. When this

bit is a 1, the device is set up for the bipolar analog input range.

BUSY

Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration

in progress. When this bit is 0, there is no conversion or calibration in progress.

CALMD

Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a

system calibration is selected (see Table III).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in

progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate

which of the calibration registers are addressed for reading and writing (see section on the Calibration

Registers for more details).

PRELIMINARY TECHNICAL DATA

–10–

REV. 0

AD7854/AD7854L

CALIBRATION REGISTERS

The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read

from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the

user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-

dressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should

not attempt to read from and write to the calibration registers at the same time.

Table IV. Calibration Register Addressing

CALSLT1 CALSLT0

Comment

0

1

0

1

0

1

This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.

This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.

This combination addresses the Offset Register. One register in total.

This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers

When reading from the calibration registers there are always two

leading zeros for each of the registers.

When writing to the calibration registers a write to the control

register is required to set the CALSLT0 and CALSLT1 bits.

When reading from the calibration registers a write to the con-

trol register is required to set the CALSLT0 and CALSLT1 bits

and also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-

dresses the calibration registers for reading). The calibration

register pointer is reset on writing to the control register setting

the CALSLT1 and CALSLT0 bits, or upon completion of all

the calibration register write/read operations. When reset it

points to the first calibration register in the selected write/read

sequence. The calibration register pointer points to the gain

calibration register upon reset in all but one case, this case being

where the offset calibration register is selected on its own

(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-

bration register is being accessed, the calibration register pointer

is automatically incremented after each calibration register

write/read operation. The order in which the 10 calibration reg-

isters are arranged is shown in Figure 5. Read/Write operations

may be aborted at any time before all the calibration registers

have been accessed, and the next control register write opera-

tion resets the calibration register pointer. The flowchart in Fig-

ure 6 shows the sequence for writing to the calibration registers.

Figure 7 shows the sequence for reading from the calibration

registers.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

REGISTER

WRITE

OPERATION

OR

ABORT

?

NO

YES

FINISHED

Figure 6. Flowchart for Writing to the Calibration Registers

CALIBRATION REGISTERS

GAIN REGISTER

OFFSET REGISTER

(1)

(2)

(3)

CAL REGISTER

ADDRESS POINTER

DAC 1ST MSB REGISTER

DAC 8TH MSB REGISTER

(10)

CALIBRATION REGISTER ADDRESS POINTER POSITION IS

DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS

ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.

Figure 5. Calibration Register Arrangement

–11–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

±0.0006% of V_REFapproximately. The resolution can also be

expressed as ±(0.05 × V_REF)/2¹³volts. This equals ±0.015 mV,

with a 2.5 V reference. The maximum offset that can be com-

pensated for is ±5% of the reference voltage, which equates to

±125 mV with a 2.5 V reference and ±250 mV with a 5 V

reference.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT = 1,

RDSLT0 =0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

Q. If a +20 mV offset is present in the analog input signal and the

reference voltage is 2.5 V, what code needs to be written to the

offset register to compensate for the offset ?

READ CAL REGISTER

A. 2.5 V reference implies that the resolution in the offset reg-

ister is 5% × 2.5 V/2¹³= 0.015 mV. +20 mV/0.015 mV =

1310.72; rounding to the nearest number gives 1311. In

binary terms this is 00 0101 0001 1111, therefore decrease

the offset register by 00 0101 0001 1111.

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

REGISTER

READ

OPERATION

OR

ABORT

?

NO

This method of compensating for offset in the analog input sig-

nal allows for fine tuning the offset compensation. If the offset

on the analog input signal is known, there is no need to apply

the offset voltage to the analog input pins and do a system cali-

bration. The offset compensation can take place in software.

YES

FINISHED

Adjusting the Gain Calibration Register

The gain calibration register contains 16 bits. The two MSBs

are zero and the 14 LSBs contain gain data. As in the offset cali-

bration register the data bits in the gain calibration register are

binary weighted, with the MSB having a weighting of 2.5% of

the reference voltage. The gain register value is effectively multi-

plied by the analog input to scale the conversion result over the

full range. Increasing the gain register compensates for a

smaller analog input range and decreasing the gain register com-

pensates for a larger input range. The maximum analog input

range that the gain register can compensate for is 1.025 times

the reference voltage, and the minimum input range is 0.975

times the reference voltage.

Figure 7. Flowchart for Reading from the Calibration

Registers

Adjusting the Offset Calibration Register

The offset calibration register contains 16 bits. The two MSBs

are zero and the 14 LSBs contain offset data. By changing the

contents of the offset register, different amounts of offset on the

analog input signal can be compensated for. Increasing the

number in the offset calibration register compensates for nega-

tive offset on the analog input signal, and decreasing the num-

ber in the offset calibration register compensates for positive

offset on the analog input signal. The default value of the offset

calibration register is 0010 0000 0000 0000 approximately. This

is not the exact value, but the value in the offset register should

be close to this value. Each of the 14 data bits in the offset regis-

ter is binary weighted; the MSB has a weighting of 5% of the

reference voltage, the MSB-1 has a weighting of 2.5%, the

MSB-2 has a weighting of 1.25%, and so on down to the LSB

which has a weighting of 0.0006%. This gives a resolution of

PRELIMINARY TECHNICAL DATA

–12–

REV. 0

AD7854/AD7854L

CIRCUIT INFORMATION

track/hold goes from track to hold mode. The falling edge of the

CLKIN signal which follows the rising edge of CONVST ini-

tiates the conversion, provided the rising edge of CONVST (or

WR when converting via the control register) occurs typically at

least 10 ns before this CLKIN edge. The conversion takes

16.5 CLKIN periods from this CLKIN falling edge. If the

10 ns setup time is not met, the conversion takes 17.5 CLKIN

periods.

The AD7854/AD7854L is a fast, 12-bit single supply A/D con-

verter. The part requires an external 4 MHz/1.8 MHz master

clock (CLKIN), two C_REFcapacitors, a CONVST signal to start

conversion and power supply decoupling capacitors. The part

provides the user with track/hold, on-chip reference, calibration

features, A/D converter and parallel interface logic functions on

a single chip. The A/D converter section of the AD7854/

AD7854L consists of a conventional successive-approximation

converter based around a capacitor DAC. The AD7854/

AD7854L accepts an analog input range of 0 to +V_REF.V_REF

can be tied to V_DD. The reference input to the part connected

via a 150 kΩ resistor to the internal 2.5 V reference and to the

on-chip buffer.

The time required by the AD7854/AD7854L to acquire a signal

depends upon the source resistance connected to the AIN(+)

input. Please refer to the Acquisition Time section for more

details.

When a conversion is completed, the BUSY output goes low,

and the result of the conversion can be read by accessing the

data through the data bus. To obtain optimum performance

from the part, read or write operations should not occur during

the conversion or less than 200 ns prior to the next CONVST

rising edge. Reading/writing during conversion typically de-

grades the Signal to (Noise + Distortion) by less than 0.5 dBs.

The AD7854 can operate at throughput rates of over 200 kSPS

(up to 100 kSPS for the AD7854L).

A major advantage of the AD7854/AD7854L is that a conver-

sion can be initiated in software as well as applying a signal to

the CONVST pin. Another innovative feature of the AD7854/

AD7854L is self-calibration on power-up to give superior dc

accuracy. The part should be allowed some time after power-up

and after the CONVST signal is applied to perform this auto-

matic calibration before any reading or writing takes place. The

part is available in a 28-pin SSOP package and this offers the

user considerable spacing saving advantages over alternative

solutions. The AD7854L version typically consumes only

5.5 mW making it ideal for battery-powered applications.

With the AD7854L, 100 kSPS throughput can be obtained as

follows: the CLKIN and CONVST signals are arranged to give

a conversion time of 16.5 CLKIN periods as described above

and 1.5 CLKIN periods are allowed for the acquisition time.

With a 1.8 MHz clock, this gives a full cycle time of 10 µs,

which equates to a throughput rate of 100 kSPS.

CONVERTER DETAILS

The master clock for the part is applied to the CLKIN pin.

Conversion is initiated on the AD7854/AD7854L by pulsing the

CONVST input or by writing to the control register and setting

the CONVST bit to 1. On the rising edge of CONVST (or at

the end of the control register write operation), the on-chip

When using the software conversion start for maximum

throughput, the user must ensure the control register write

operation extends beyond the falling edge of BUSY. The falling

edge of BUSY resets the CONVST bit to 0 and allows it to be

reprogrammed to 1 to start the next conversion.

Figure 8. Typical Circuit

–13–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

TYPICAL CONNECTION DIAGRAM

DC/AC Applications

Figure 8 shows a typical connection diagram for the AD7854/

AD7854L. The AGND and the DGND pins are connected to-

gether at the device for good noise suppression. The first

CONVST applied after power-up starts the automatic calibra-

tion sequence. The WR line is tied to DV_DDto ensure that

there is no writing to the device. Applying the RD and CS sig-

nals causes the conversion result to be output on the 12 data pins.

Note that after power is applied to AV_DDand DV_DD, and the

CONVST signal is applied, the part requires (70 ms + 1/sample

rate) for the internal reference to settle and for the automatic

calibration on power-up to be completed.

For dc applications, high source impedances are acceptable,

provided there is enough acquisition time between conversions

to charge the 20 pF capacitor. For example with R_IN= 5 kΩ,

the required acquisition time is 922 ns.

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC low-

pass filter on the AIN(+) pin, as shown in Figure 11. In applica-

tions where harmonic distortion and signal to noise ratio are

critical, the analog input should be driven from a low impedance

source. Large source impedances significantly affect the ac per-

formance of the ADC. They may require the use of an input

buffer amplifier. The choice of the amplifier is a function of the

particular application.

For applications where power consumption is a major concern,

the power-down options can be programmed by writing to the

part. See Power-Down section for more detail on low power

applications.

The maximum source impedance depends on the amount of

total harmonic distortion (THD) that can be tolerated. The

THD increases as the source impedance increases. Figure 10

shows a graph of the total harmonic distortion vs. analog input

signal frequency for different source impedances. With the

setup as in Figure 11, the THD is at the –90 dB level. With a

source impedance of 1 kΩ and no capacitor on the AIN(+) pin,

the THD increases with frequency.

ANALOG INPUT

The equivalent analog input circuit is shown in Figure 9. Dur-

ing the acquisition interval the switches are both in the track

position and the AIN(+) charges the 20 pF capacitor through

the 125 Ω resistance. On the rising edge of CONVST switches

SW1 and SW2 go into the hold position retaining charge on the

20 pF capacitor as a sample of the signal on AIN(+). The

AIN(–) is connected to the 20 pF capacitor, and this unbalances

the voltage at Node A at the input of the comparator. The

capacitor DAC adjusts during the remainder of the conversion

cycle to restore the voltage at Node A to the correct value. This

action transfers a charge, representing the analog input signal, to

the capacitor DAC which in turn forms a digital representation

of the analog input signal. The voltage on the AIN(–) pin di-

rectly influences the charge transferred to the capacitor DAC at

the hold instant. If this voltage changes during the conversion

period, the DAC representation of the analog input voltage is

altered. Therefore it is most important that the voltage on the

AIN(–) pin remains constant during the conversion period. Fur-

thermore, it is recommended that the AIN(–) pin is always con-

nected to AGND or to a fixed dc voltage.

–72

THD VS. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

–76

–80

R

= 1kΩ

IN

–84

–88

–92

R

= 50Ω, 10nF

IN

AS IN FIGURE 13

0

20

40

60

80 100

INPUT FREQUENCY – kHz

TRACK

125Ω

Figure 10. THD vs. Analog Input Frequency

AIN(+)

AIN(–)

CAPACITOR

DAC

In a single supply application (both 3 V and 5 V), the V+ and

V– of the op amp can be taken directly from the supplies to the

AD7854/AD7854L which eliminates the need for extra external

power supplies. When operating with rail-to-rail inputs and out-

puts at frequencies greater than 10 kHz, care must be taken in

selecting the particular op amp for the application. In particular,

for single supply applications the input amplifiers should be

connected in a gain of –1 arrangement to get the optimum per-

formance. Figure 11 shows the arrangement for a single supply

application with a 50 Ω and 10 nF low-pass filter (cutoff fre-

quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a

capacitor with good linearity to ensure good ac performance.

Recommended single supply op amps are the AD820 and the

AD820-3V.

SW1

20pF

125Ω HOLD

NODE A

SW2

COMPARATOR

TRACK

HOLD

AGND

Figure 9. Analog Input Equivalent Circuit

Acquisition Time

The track-and-hold amplifier enters its tracking mode on the

falling edge of the BUSY signal. The time required for the

track-and-hold amplifier to acquire an input signal depends on

how quickly the 20 pF input capacitance is charged. There is a

minimum acquisition time of 400 ns. For large source imped-

ances, >2 kΩ, the acquisition time is calculated using the formula:

t

_ACQ= 9 × (R_IN+ 125 Ω) × 20 pF

where R_INis the source impedance of the input signal, and

125 Ω, 20 pF is the input R, C.

PRELIMINARY TECHNICAL DATA

–14–

REV. 0

AD7854/AD7854L

+3V TO +5V

10µF

0.1µF

10kΩ

TRACK AND HOLD

AMPLIFIER

AIN(+)

AIN(–)

10kΩ

V

V+

IC1

V–

V

= 0 TO V

V

IN

DB0

2’S

IN

REF

50Ω

(–V

/2 TO +V

/2)

REF

. . .

TO AIN(+) OF

AD7854/AD7854L

REF

COMPLEMENT

FORMAT

/2

DB11

REF

V

/2

10nF

(NPO)

REF

AD820

AD820-3V

10kΩ

AD7854/AD7854L

Figure 13. ±V_REF/2 about V_REF/2 Bipolar Input Configuration

Figure 11. Analog Input Buffering

Input Ranges

The analog input range for the AD7854/AD7854L is 0 V to

_REFin both the unipolar and bipolar ranges.

straight binary for the unipolar range with 1 LSB = FS/4096 =

3.3 V/4096 = 0.8 mV when V_REF= 3.3 V. The ideal input/

output transfer characteristic for the unipolar range is shown in

Figure 14.

V

The only difference between the unipolar range and the bipolar

range is that in the bipolar range the AIN(–) should be biased

up to at least +V_REF/2 and the output coding is twos comple-

ment (See Table V and Figures 14 and 15).

OUTPUT

CODE

111...111

111...110

111...101

111...100

Table V. Analog Input Connections

Analog Input

Range

Input Connections

Connection

Diagram

AIN(+)

AIN(–)

1

0 V to V_REF

V_IN

AGND

V_REF/2

Figure 12

Figure 13

FS

±V_REF/2²

1LSB =

000...011

000...010

000...001

000...000

4096

NOTES

¹Output code format is straight binary.

²Range is ±V_REF/2 biased about V_REF/2. Output code format is twos complement.

0V 1LSB

+FS –1LSB

Note that the AIN(–) pin on the AD7854/AD7854L can be bi-

ased up above AGND in the unipolar mode, or above V_REF/2 in

bipolar mode if required. The advantage of biasing the lower

end of the analog input range away from AGND is that the ana-

log input does not have to swing all the way down to AGND.

Thus, in single supply applications the input amplifier does not

have to swing all the way down to AGND. The upper end of the

analog input range is shifted up by the same amount. Care must

be taken so that the bias applied does not shift the upper end of

the analog input above the AV_DDsupply. In the case where the

reference is the supply, AV_DD, the AIN(–) should be tied to

AGND in unipolar mode or to AV_DD/2 in bipolar mode.

V

= (AIN(+) – AIN(–)), INPUT VOLTAGE

IN

Figure 14. AD7853/AD7853L Unipolar Transfer

Characteristic

Figure 13 shows the AD7854/AD7854L’s ±V_REF/2 bipolar ana-

log input configuration. AIN(+) cannot go below 0 ,V so for

the full bipolar range, AIN(–) should be biased to at least

+V_REF/2. Once again the designed code transitions occur mid-

way between successive integer LSB values. The output coding

is twos complement with 1 LSB = 4096 = 3.3 V/4096 = 0.8 mV.

The ideal input/output transfer characteristic is shown in Figure

15.

OUTPUT

CODE

111...111

TRACK AND HOLD

AIN(+)

AIN(–)

AMPLIFIER

V

= 0 TO V

REF

DB0

111...110

STRAIGHT

BINARY

FORMAT

IN

. . .

DB11

(V

/2) – 1LSB

REF

111...101

000...011

111...100

0V

AD7854/AD7854L

+ FS – 1LSB

/2) + 1 LSB

(V

REF

Figure 12. 0 to V_REFUnipolar Input Configuration

FS = V

V

REF

000...010

000...001

000...000

Transfer Functions

FS

1LSB =

For the unipolar range the designed code transitions occur mid-

way between successive integer LSB values (i.e., 1/2 LSB,

3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The output coding is

4096

V

/2

REF

V

= (AIN(+) – AIN(–)), INPUT VOLTAGE

IN

Figure 15. AD7854/AD7854L Bipolar Transfer Characteristic

PRELIMINARY TECHNICAL DATA

–15–

REV. 0

AD7854/AD7854L

REFERENCE SECTION

AD7854/AD7854L PERFORMANCE CURVES

Figure 18 shows a typical FFT plot for the AD7854 at 200 kHz

sample rate and 10 kHz input frequency.

For specified performance, it is recommended that when using

an external reference, this reference should be between 2.3 V

and the analog supply AV_DD. The connections for the reference

pins are shown below. If the internal reference is being used,

the REF_IN/REF_OUTpin should be decoupled with a 10 nF

capacitor to AGND very close to the REF_IN/REF_OUTpin. These

connections are shown in Figure 16.

0

AV = DV = 3.3V

DD

F

= 200kHz

= 10kHz

SAMPLE

–20

–40

–60

–80

IN

SNR = 72.04dB

THD = –88.43dB

If the internal reference is required for use external to the ADC,

it should be buffered at the REF_IN/REF_OUTpin and a 10 nF

capacitor should be connected from this pin to AGND. The typical

noise performance for the internal reference, with 5 V supplies is

150 nV/√Hz @ 1 kHz and dc noise is 100 µV p-p.

–100

–120

ANALOG SUPPLY

+3V TO +5V

0.1µF

10µF

0.1µF

0

20

40

60

80

100

FREQUENCY – kHz

AV

DD

DV

DD

C

REF1

Figure 18. FFT Plot

0.1µF

AD7854/

AD7854L

Figure 19 shows the SNR versus frequency for different supplies

and different external references.

REF2

0.01µF

74

AV = DV WITH 2.5V REFERENCE

REF /REF

IN

DD

OUT

UNLESS STATED OTHERWISE

73

72

71

70

69

5.0V SUPPLIES, WITH 5V REFERENCE

Figure 16. Relevant Connections Using Internal Reference

5.0V SUPPLIES

The REF_IN/REF_OUTpin may be overdriven by connecting it to

an external reference. This is possible due to the series resis-

tance from the REF_IN/REF_OUTpin to the internal reference.

5.0V SUPPLIES, L VERSION

3.3V SUPPLIES

This external reference can be in the range 2.3 V to AV_DD

.

When using AV_DDas the reference source, the 10 nF capacitor

from the REF_IN/REF_OUTpin to AGND should be as close as

possible to the REF_IN/REF_OUTpin, and also the C_REF1pin

should be connected to AV_DDto keep this pin at the same volt-

age as the reference. The connections for this arrangement are

shown in Figure 17. When using AV_DDit may be necessary to

add a resistor in series with the AV_DDsupply. This has the effect

of filtering the noise associated with the AV_DDsupply.

0

20

40

60

80

100

INPUT FREQUENCY – kHz

Figure 19. SNR vs. Frequency

Figure 20 shows the power supply rejection ratio versus fre-

quency for the part. The power supply rejection ratio is defined

as the ratio of the power in ADC output at frequency f to the

power of a full-scale sine wave.

Note that when using an external reference, the voltage present

at the REF_IN/REF_OUTpin is determined by the external refer-

ence source resistance and the series resistance of 150 kΩ from

the REF_IN/REF_OUTpin to the internal 2.5 V reference. Thus, a

low source impedance external reference is recommended.

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in ADC output, Pfs = power of a full-

scale sine wave. Here a 100 mV peak-to-peak sine wave is

coupled onto the AV_DDsupply while the digital supply is left

unaltered. Both the 3.3 V and 5.0 V supply performances are

shown.

ANALOG SUPPLY

+3V TO +5V

0.1µF

10µF

0.1µF

AV

DD

DV

DD

C

REF1

0.1µF

AD7854/

AD7854L

REF2

0.01µF

REF /REF

IN

OUT

Figure 17. Relevant Connections, AV_DDas the Reference

PRELIMINARY TECHNICAL DATA

–16–

REV. 0

AD7854/AD7854L

–78

–80

PMGT1 and PMGT0 bits in the control register. When both

these bits are 0 (default status on power-up), the AD7854/

AD7854L is in normal mode of operation . With these bits at 0,

1 the AD7854/AD7854L enters a full power-down mode after

every conversion. With these bits at 1, 0 the part enters a full

power-down mode, whether a conversion is in progress or not.

Finally, with these bits at 1, 1 the part enters partial power-

down after every conversion.

AV = DV = 3.3V/5.0V,

DD DD

100mVpk-pk SINE WAVE ON AV

DD

–82

–84

3.3V

5.0V

–86

–88

The advantage of partial power-down is that the part requires

significantly less time to “power-up” than from full power-

down. In partial power-down, the reference voltage stays pow-

ered up, so if this is being used external to the AD7854/

AD7854L it is still available even though the rest of the

AD7854/AD7854L is powered down. Table VI summarizes the

power management options while Table VII shows typical

power-up times when using the 2.5 V internal reference. The

capacitor values between C_REF1, C_REF2, REF_IN/REF_OUTand

AGND are also listed. The power-up time is defined as the time

taken for the output code to settle to within ±0.5 LSBs of its

final value. If a power-up time shorter than that quoted in Table

VII is used, the error associated with the output code increases.

For a power-up time of 10 µs from partial power-down mode,

the output code settles to within ±3 LSBs typically of its final

value. When using an external reference, the power-up time

required is less than the figures quoted in Table VII.

–90

0

20

40

60

80

100

INPUT FREQUENCY – kHz

Figure 20. PSRR vs. Frequency

POWER-DOWN OPTIONS

The AD7854/AD7854L should be left idle for (70 ms + 1/sample

rate) typically after the AV_DDand the DV_DDpower-up, and the

first CONVST signal is applied, to allow the internal reference

to settle and the automatic calibration on power-up to be com-

pleted. The SLEEP pin can be hardwired to DGND before

power-up as the part disables the function of the SLEEP pin

while the automatic calibration on power-up is being performed.

A typical connection diagram for a low power application is

shown in Figure 21.

The AD7854/AD7854L provides two power-down methods of

operation. These methods are full power-down and partial

power-down. These power-down methods are controlled by the

Figure 21. Typical Low Power Circuit

–17–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

CYCLE TIME

Table VI. Power Management Options

≥ 300µs

PMGT1 PMGT0

CONVST

Bit

Comment

0

Normal Operation (Default Condition

After Power-On)

BUSY

0

1

Full Power-Down if Not Calibrating or

Converting

POWER-UP

TIME

NORMAL

OPERATION

FULL

POWER-DOWN

1

0

1

Full Power-Down

Figure 22. Timing for using CONVST to "wake-up" the

Partial Power-Down if Not

Converting

AD7854/AD7854L

Writing to AD7854/AD7854L

Table VII. Power-Up Times

The sequence of events here uses the CONVST bit in the con-

trol register to start the conversion. Alternatively the CONVST

pin may be used as in Figure 22. When writing to the AD7854/

AD7854L there are a number of different ways to utilize the

power-down options. For applications which require throughput

rates of less than 2 kHz, a full/partial power-down mode combi-

nation, or a full power-down mode on its own, may be used.

For higher throughput rates the partial power-down mode

should be used. Table VIII shows the recommended power-

down mode to obtain the lowest current at a given throughput

rate.

Reference

Capacitor

(nF)

Power-Up

Power-Down Delay

Mode

C_REF1C_REF2

(nF)

(␮s)

100

10

0.1

Full

Partial

300

50

10

1

0.1

Full

Partial

300

50

POWER-UP/DOWN SEQUENCE

Table VIII. Recommended Power-Down Mode for Lowest I_DD

Power-up times and throughput rates quoted in this section are

based on using the 2.5 V internal reference. If an external refer-

ence is used and is powered on constantly, or if AV_DDis used as

the reference, then the power-up times are shorter and the

throughput rates higher.

Power-Down Mode

Maximum Throughput Rate

Full/Partial Combination

Partial

2 kHz

16 kHz

The CONVST pin may be used to wake the part from two of

the power down modes (full power-down if not converting and

partial power-down if not converting), rather than writing to the

control register to wake up the part. First, the part should be

put into one of these two power down modes by writing to the

device (setting PMGT1 = 0 and PMGT0 = 1, or setting both

PMGT1 and PMGT0 = 1). When using CONVST to wake the

part, it is the falling edge of the CONVST signal that “wakes”

it. CONVST must remain low for at least the power up time

quoted in Table VII when using the internal reference (CONVST

need only remain low for 50 µs when using an external refer-

ence). This allows the part to settle before the start of the next

conversion. Figure 22 shows the timing ofCONVST for bringing

the part out of full power down when using the internal reference.

Using Full and Partial Power-Down Combination

Using a full/partial power-down combination has the benefits of

the low current associated with a full power-down and the speed

of powering up from a partial power-down. It also gives the low-

est current for a given throughput rate, one third of the current

when using the full power-down mode on its own. Figure 23

shows the timing diagram for the full/partial power-down com-

bination and Figure 24 shows the flowchart for the sequence of

events. For the all 0s write operation described in the sequence,

only the two MSBs need to be 0 to ensure that the rest of the

data write is ignored. The supply current versus throughput rate

for this power up/power down sequence is shown in Figure 25.

Figure 23. Timing Sequence for Full/Partial Power-Down Combination

PRELIMINARY TECHNICAL DATA –18–

REV. 0

AD7854/AD7854L

1000

START

AD7854L (1.8MHz EXTERNAL CLOCK)

FULL/PARTIAL POWER-DOWN

POWER-ON, APPLY CONVST

AND CLKIN SIGNALS

100

10

WAIT 100ms FOR

AUTOMATIC CALIBRATION

WRITE TO CONTROL REGISTER SETTING

BITS CONVST = 1, PMGT1 = PMGT0 = 0

CONVERSION PERFORMED AND PART

ENTERS FULL POWER-DOWN

1

0

200 400 600 800 1000 1200 1400 1600 1800 2000

THROUGHPUT – Hz

READ DATA FROM DEVICE

Figure 25. Supply Current vs. Throughput Rate with Full/

Partial Power-Down Combination (Sequence as Illustrated

in Figures 25 and 26)

360µs BEFORE POWER-UP REQUIRED WRITE TO

CONTROL REGISTER SETTING PMGT1 = PMGT0 = 1

WAIT FOR 300µs POWER-UP TIME FROM

FULL TO PARTIAL POWER-DOWN MODE

Full Power-Down or Partial Power-Down

In some applications it may not be feasible to use a combination

of full and partial power-down as shown in Figures 25 and 26.

This may be for software overhead reasons or for applications

requiring throughput rates greater than 2 kHz.

WRITE TO CONTROL REGISTER SETTING

NORMAL OPERATION, PMGT1 = 0, PMGT0 = 1

Using full power-down only allows for a maximum throughput

rate of 2 kHz, but the supply current is three times or greater

than for the full/partial power-down combination sequence

described in Figures 25 and 26.

WAIT 50µs POWER-UP TIME

Figure 24. Flowchart for Full/Partial Power-Down Mode

Combination

Using partial power-down allows for throughput rates up to

16 kHz (if AV_DDis used as the reference, the throughput rates

can be > 16 kHz). Figures 28 and 29 show the timing/flowchart

for power-up/down when using the partial power-down mode

only. Figure 28 shows the Supply Current vs. Throughput rate

for this sequence.

Figure 26. Timing Sequence for Partial Power-Down Only

–19–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

CALIBRATION SECTION

START

Calibration Overview

The automatic calibration that is performed on power-up

ensures that the calibration options covered in this section are

not required in a significant amount of applications. A calibra-

tion does not have to be initiated unless the operating condi-

tions change (CLKIN frequency, analog input mode, reference

voltage, temperature, and supply voltages). The AD7854/

AD7854L has a number of calibration features that may be

required in some applications and there are a number of advan-

tages in performing these different types of calibration. First, the

internal errors in the ADC can be reduced significantly to give

superior dc performance; and second, system offset and gain

errors can be removed. This allows the user to remove reference

errors (whether it be internal or external reference) and to make

use of the full dynamic range of the AD7854/AD7854L by

adjusting the analog input range of the part for a specific system.

POWER-ON, APPLY CONVST

AND CLKIN SIGNALS

WAIT 100ms FOR

AUTOMATIC CALIBRATION

WRITE TO CONTROL REGISTER SETTING

BITS CONVST = 1, PMGT1 = PMGT0 = 1

CONVERSION PERFORMED AND PART

ENTERS FULL POWER-DOWN

READ DATA FROM DEVICE

60µs BEFORE POWER-UP REQUIRED WRITE TO

CONTROL REGISTER SETTING NORMAL OPERATION

PMGT1 = PMGT0 = 1

There are two main calibration modes on the AD7854/

AD7854L, self-calibration and system calibration. There are

various options in both self-calibration and system calibration as

outlined previously in Table III. All the calibration functions

are initiated by writing to the control register and setting the

STCAL bit to 1.

WAIT 50µs POWER-UP TIME

The duration of each of the different types of calibration is given

in Table IX for the AD7854 with a 4 MHz master clock. These

calibration times are master clock dependent. Therefore the

calibration times for the AD7854L (CLKIN = 1.8 MHz) are

larger than those quoted in Table IX.

Figure 27. Flowchart for Partial Power-Down Only

10000

AD7854L (1.8MHz EXTERNAL CLOCK)

PARTIAL POWER-DOWN

Table IX. Calibration Times (AD7854 with 4 MHz CLKIN)

1000

100

Type of Self- or System Calibration

Time

Full

Gain + Offset

Offset

31.25 ms

6.94 ms

3.47 ms

Gain

Automatic Calibration on Power-On

The automatic calibration on power-on is initiated by the first

CONVST pulse after the AV_DDand DV_DDpower on. From the

CONVST pulse the part internally sets a 32/72 ms (4 MHz/

1.8 MHz CLKIN) timeout. This time is large enough to ensure

that the internal reference has settled before the calibration is

performed. However, if an external reference is being used, this

reference must have stabilized before the automatic calibration

is initiated. This first CONVST pulse also triggers the BUSY

signal high and once the 32/72 ms has elapsed the BUSY signal

goes low. At this point the next CONVST pulse that is applied

initiates the automatic full self calibration. This CONVST pulse

again triggers the BUSY signal high and after 32/72 ms (4 MHz/

1.8 MHz CLKIN) the calibration is completed and the BUSY

signal goes low. This timing arrangement is shown in Figure 29.

The times in Figure 29 assume a 4 MHz / 1.8 MHz CLKIN

signal.

10

0

200 400 600 800 1000 1200 1400 1600 1800 2000

THROUGHPUT – Hz

Figure 28. Supply Current vs. Throughput Rate with Par-

tial Power-Down Only (Sequence as Illustrated in Figures

26 and 27)

PRELIMINARY TECHNICAL DATA

–20–

REV. 0

AD7854/AD7854L

In bipolar mode the midscale error is adjusted by an offset cali-

bration and the positive full-scale error is adjusted by the gain

calibration. In unipolar mode the zero-scale error is adjusted by

the offset calibration and the positive full-scale error is adjusted

by the gain calibration.

AV = DV

DD

CONVERSION IS INITIATED

ON THIS EDGE

DD

POWER ON

CONVST

Self-Calibration Timing

BUSY

Figure 30 shows the timing for a software full self-calibration.

Here the BUSY line stays high for the full length of the self-

calibration. A self-calibration is initiated by writing to the con-

trol register and setting the STCAL bit to 1. The BUSY line

goes high at the end of the write to the control register, and

BUSY goes low when the full self-calibration is complete after a

time t_CALas show in Figure 30.

32/72 ms

TIMEOUT PERIOD

32/72 ms

AUTOMATIC

CALIBRATION

DURATION

Figure 29. Timing arrangement for autocalibration on

power-on.

t₂₃

The CONVST signal is gated with the BUSY internally so that

as soon as the timeout is initiated by the first CONVST pulse all

subsequent CONVST pulses are ignored until the BUSY signal

goes low, 32/72 ms later. The CONVST pulse that follows after

the BUSY signal goes low initiates an automatic full self calibra-

tion. This takes a further 32/72 ms. After calibration, the part is

accurate to the 12-bit level and the specifications quoted on the

data sheet apply, and all subsequent CONVST pulses initiate

conversions. There is no need to perform another calibration

unless the operating conditions change or unless a system cali-

bration is required.

CS

DATA LATCHED INTO

CONTROL REGISTER

WR

Hi-Z

DATA

VALID

DATA

BUSY

t_CAL

This autocalibration at power-on is disabled if the user writes to

the control register before the autocalibration is initiated. If the

control register write operation occurs during the first 32/72 ms

timeout period, then the BUSY signal stays high for the 32/72

ms and the CONVST pulse that follows the BUSY going low

does not initiate an automatic full self calibration. It initiates a

conversion and all subsequent CONVST pulses initiate conver-

sions as well. If the control register write operation occurs when

the automatic full self calibration is in progress, then the calibra-

tion is not be aborted; the BUSY signal remains high until the

automatic full self calibration is complete.

Figure 30. Timing Diagram for Full Self-Calibration

For the self-(gain + offset), self-offset and self-gain calibrations,

the BUSY line is triggered high at the end of the write to the

control register and stays high for the full duration of the self-

calibration. The length of time for which BUSY is high depends

on the type of self-calibration that is initiated. Typical values are

given in Table IX. The timing diagram for the other self-

calibration options is similar to that outlined in Figure 30.

System Calibration Description

System calibration allows the user to remove system errors

external to the AD7854/AD7854L, as well as remove the errors

of the AD7854/AD7854L itself. The maximum calibration

range for the system offset errors is ±5% of V_REFand for the

system gain errors, it is ±2.5% of V_REF. If the system offset or

system gain errors are outside these ranges, the system calibration

algorithm reduces the errors as much as the trim range allows.

Self-Calibration Description

There are four different calibration options within the self-

calibration mode. There is a full self-calibration where the

DAC, internal offset, and internal gain errors are removed.

There is the (Gain + Offset) self-calibration which removes the

internal gain error and then the internal offset errors. The inter-

nal DAC is not calibrated here. Finally, there are the self-offset

and self-gain calibrations which remove the internal offset errors

and the internal gain errors respectively.

The internal capacitor DAC is calibrated by trimming each of

the capacitors in the DAC. It is the ratio of these capacitors to

each other that is critical, and so the calibration algorithm

ensures that this ratio is at a specific value by the end of the

calibration routine. For the offset and gain there are two

separate capacitors, one of which is trimmed during offset

calibration and one of which is trimmed during gain calibration.

–21–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

Figures 33 through 35 illustrate why a specific type of system

calibration might be used. Figure 31 shows a system offset cali-

bration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be removed by a system offset calibration.

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

REF

V

+ SYS OFFSET

SYS F.S.

– 1LSB

REF

SYS F.S.

– 1LSB

V

REF

V

REF

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

SYSTEM GAIN

CALIBRATION

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

SYS OFFSET

AGND

SYS OFFSET

AGND

REF

V

+ SYS OFFSET

REF

MAX SYSTEM OFFSET

IS ±5% OF V

MAX SYSTEM OFFSET

IS ±5% OF V

V

– 1LSB

V

– 1LSB

REF

SYSTEM OFFSET

CALIBRATION

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

Figure 33. System (Gain + Offset) Calibration

System Gain and Offset Interaction

SYS OFFSET

AGND

SYS OFFSET

AGND

The architecture of the AD7854/AD7854L leads to an interac-

tion between the system offset and gain errors when a system

calibration is performed. Therefore it is recommended to per-

form the cycle of a system offset calibration followed by a sys-

tem gain calibration twice. When a system offset calibration is

performed, the system offset error is reduced to zero. If this is

followed by a system gain calibration, then the system gain error

is now zero, but the system offset error is no longer zero. A sec-

ond sequence of system offset error calibration followed by a

system gain calibration is necessary to reduce system offset error

to below the 12-bit level. The advantage of doing separate sys-

tem offset and system gain calibrations is that the user has more

control over when the analog inputs need to be at the required

levels, and the CONVST signal does not have to be used.

MAX SYSTEM OFFSET

IS ±5% OF V

MAX SYSTEM OFFSET

IS ±5% OF V

REF

Figure 31. System Offset Calibration

Figure 32 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for a by a system gain calibration.

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

REF

SYS FULL S.

– 1LSB

SYS FULL S.

V – 1LSB

REF

V

REF

Alternatively, a system (gain + offset) calibration can be per-

formed. At the end of one system (gain + offset) calibration, the

system offset error is zero, while the system gain error is reduced

from its initial value. Three system (gain + offset) calibrations

are required to reduce the system gain error to below the 12-bit

error level. There is never any need to perform more than three

system (gain + offset) calibrations.

SYSTEM GAIN

CALIBRATION

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

AGND

Figure 32. System Gain Calibration

In bipolar mode the midscale error is adjusted for an offset cali-

bration and the positive full-scale error is adjusted for the gain

calibration; in unipolar mode the zero-scale error is adjusted for

an offset calibration and the positive full-scale error is adjusted

for a gain calibration.

Finally in Figure 33 both the system offset error and gain error

are removed by the system offset followed by a system gain cali-

bration. First the analog input range is shifted upwards by the

positive system offset and then the analog input range is

adjusted at the top end to account for the system full scale.

PRELIMINARY TECHNICAL DATA

–22–

REV. 0

AD7854/AD7854L

System Calibration Timing

The timing diagram for a system offset or system gain calibra-

tion is shown in Figure 35. Here again a write to the control

register initiates the calibration sequence. At the end of the con-

trol register write operation the BUSY line goes high and it

stays high until the calibration sequence is finished. The analog

input should be set at the correct level for a minimum setup

time (t_SETUP) of 100 ns before the CS rising edge and stay at the

correct level until the BUSY signal goes low.

The timing diagram in Figure 34 is for a software full system

calibration. It may be easier in some applications to perform

separate gain and offset calibrations so that the CONVST bit in

the control register does not have to be programmed in the

middle of the system calibration sequence. Once the write to the

control register setting the bits for a full system calibration is

completed, calibration of the internal DAC is initiated and the

BUSY line goes high. The full-scale system voltage should be

applied to the analog input pins, AIN(+) and AIN(–) at the start

of calibration. The BUSY line goes low once the DAC and

system gain calibration are complete. Next the system offset

voltage should be applied across the AIN(+) and AIN(–) pins

for a minimum setup time (t_SETUP) of 100 ns before the rising

edge of CS. This second write to the control register sets the

CONVST bit to 1 and at the end of this write operation the

BUSY signal is triggered high (note that a CONVST pulse can

be applied instead of this second write to the control register).

The BUSY signal is low after a time t_CAL2when the system offset

calibration section is complete. The full system calibration is now

complete.

t₂₃

CS

DATA LATCHED INTO

CONTROL REGISTER

WR

Hi-Z

DATA

VALID

DATA

BUSY

t_CAL2

t_SETUP

The timing for a system (gain + offset) calibration is very similar

to that of Figure 34, the only difference being that the time

t_CAL1is replaced by a shorter time of the order of t_CAL2as the

internal DAC is not calibrated. The BUSY signal signifies when

the gain calibration is finished and when the part is ready for the

offset calibration.

V

OR V

OFFSET

AIN

SYSTEM FULL SCALE

Figure 35. Timing Diagram for System Gain or System

Offset Calibration

DATA LATCHED INTO

CONTROL REGISTER

t₂₃

CS

WR

Hi-Z

DATA

VALID

DATA

VALID

DATA

BUSY

t_CAL2

t₂₃

t_CAL1

t_SETUP

V

t_OFFSET

AIN

SYSTEM FULL SCALE

Figure 34. Timing Diagram for Full System Calibration

–23–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

PARALLEL INTERFACE

Reading

The timing diagram for a read cycle is shown in Figure 36. The

CONVST and BUSY signals are not shown here as the read

cycle may occur while a conversion is in progress or after the

conversion is complete.

In the case where the AD7854/AD7854L is operated as a read-

only ADC, the WR pin can be tied permanently high. The read

operation need only consist of one read if the system has a 12-

bit or a 16-bit data bus.

When both the CS and RD signals are tied permanently low a

different timing arrangement results, as shown in Figure 37.

Here the data is output a time t20 before the falling edge of the

BUSY signal. This allows the falling edge of BUSY to be used

for latching the data. Again if HBEN is low during the conver-

sion the 12 LSBs of the 16-bit word will be output on pins DB0

to DB11. Bringing HBEN high causes the 8 MSBs of the 16-bit

word to be output on pins DB0 to DB7. Note that with this

arrangement the data lines are always active.

The HBEN signal is low for the first read and high for the sec-

ond read. This ensures that it is the lower 12 bits of the 16-bit

word are output in the first read and the 8 MSBs of the 16-bit

word are output in the second read. If required, the HBEN

signal may be high for the first read and low for the second

read to ensure that the high byte is output in the first read

and the lower byte in the second read. The CS and RD sig-

nals are gated together internally and level triggered active

low. Both CS and RD may be tied together as the timing speci-

fication for t5 and t6 are both 0 ns min. The data is output a

time t8 after both CS and RD go low. The RD rising edge

should be used to latch the data by the user and after a time t9

the data lines will go into their high impedance state.

t₁= 100ns MIN, t₂₀= 40ns MIN,

t₁₉

= t₂₀= 60ns MIN, t₂₁= t₂₂= 60ns MAX

t₁

CONVERSION IS INITIATED

ON THIS EDGE

CONVST

t_CONVERT

t₂

BUSY

t₁₉

t₂₀

In Figure 36, the first read outputs the 12 LSBs of the 16-bit

word on pins DB0 to DB11 (DB0 being the LSB of the 12-bit

read). The second read outputs the 8 MSBs of the 16-bit word

on pins DB0 to DB7 (DB0 being the LSB of the 8-bit read).

If the system has a 12-bit or a 16-bit data bus, only one read op-

eration is necessary to obtain the 12-bit conversion result (12

bits are output in the first read). A second read operation is not

required.

HBEN

DATA

t₂₁

t₂₂

t₁₈

NEW DATA

VALID

NEW DATA

VALID

(DB8–DB11)

NEW DATA

VALID

(DB0–DB11)

NEW DATA

VALID

(DB8–DB11)

OLD DATA VALID

(DB0–DB11)

ON PINS DB0 TO DB11

ON PINS DB0 TO DB7

Figure 37. Read Cycle Timing Diagram with CS and RD

Tied Low

If the system has an 8-bit data bus then two reads are needed.

Pins DB0 to DB7 should be connected the 8-bit data bus. Pins

DB8 to DB11 should be tied to DGND or DVDD via 10 kΩ

resistors. With this arrangement, HBEN is pulled low for the

first read and the 8 LSBs of the 16-bit word are output on pins

DB0 to DB7 (data on pins DB8 to DB11 will be ignored).

HBEN is pulled high for the second read and now the 8 MSBs

of the 16-bit word are output on pins DB0 to DB7.

t₃= 15ns MIN, t₄= 5ns MIN, t₅

= t₆= 0ns MIN,

t₈= 50ns MAX, t₉= 5/50ns MIN/MAX, t₁₀= 100ns MIN

HBEN

t₃

t₄

CS

t₁₀

t₅

t₆

t₇

RD

t₉

t₈

DATA

VALID

DATA

VALID

DATA

Figure 36. Read Cycle Timing Diagram Using CS and RD

PRELIMINARY TECHNICAL DATA

–24–

REV. 0

AD7854/AD7854L

Writing

The timing diagram for a write cycle is shown in Figure 38. The

CONVST and BUSY signals are not shown here as the write

cycle may occur while a conversion is in progress or after the

conversion is complete.

To write a 16-bit word to the AD7854/AD7854L, two 8-bit

writes are required. The HBEN signal must be low for the first

write and high for the second write. This ensures that it is the

lower 8 bits of the 16-bit word are latched in the first write and

the 8 MSBs of the 16-bit word are latched in the second write.

For both write operations the 8 bits of data should be present on

pins DB0 to DB7 (DB0 being the LSB of the 8-bit write). Any

data on pins DB8 to DB11 is ignored when writing to the

device. The CS and WR signals are gated together internally.

Both CS and WR may be tied together as the timing specifica-

tion for t₁₃and t₁₄are both 0 ns min. The data is latched on the

rising edge of WR. The data needs to be setup a time t₁₆before

the WR rising edge and held for a time t₁₇after the WR rising

edge.

t₁₁= 15ns MIN, t₁₂= 5ns MIN, t₁₃

= t₁₄= 0ns MIN,

t₁₅= 100ns MIN, t₁₆= 40ns MIN, t₁₇= 5ns MIN

HBEN

t₁₁

t₁₂

CS

t₁₀

t₁₃

t₁₄

t₁₆

WR

t₁₇

t₁₆

DATA

VALID

DATA

VALID

DATA

Figure 38. Write cycle timing diagram

Resetting the Parallel Interface

If random data has been inadvertently written to the test regis-

ter, it is necessary to write the 16-bit word 0100 0000 0000

0000 (in two 8-bit bytes) to restore the test register to its default

value.

–25–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

PARALLEL INTERFACING

AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x

A parallel interface between the AD7854/AD7854L and the

TMS32020, TMS320C25 and TMS320C5X family of DSPs

are shown in Figure 40. The memory mapped addresses chosen

for the AD7854/AD7854L should be chosen to fall in the I/O

memory space of the DSPs.

The parallel port on the AD7854/AD7854L allows the device to

be interfaced to microprocessors or DSP processors as a memory

mapped or I/O mapped device. The CS and RD inputs are

common to all memory peripheral interfacing. Typical inter-

faces to different processors are shown in Figures 39 to 42.

In all the interfaces shown, an external timer controls the

CONVST input of the AD7854/AD7854L and the BUSY out-

put interrupts the host DSP. Also, the HBEN pin is connected

to address line A0 (XA0 in the case of the TMS320C30). This

maps the AD7854/AD7854L to two locations in the processor

memory space, ADCaddr and ADCaddr+1. Thus when writing

to the ADC, first the 8 LSBs of the 16-bit are written to address

location ADCaddr and then the 8 MSBs to location ADCaddr+1.

All the interfaces use a 12-bit data bus, so onlyone read is needed

from location ADCaddr to access the ADC output data register

or the status register. To read from the other registers, the

8 MSBs must be read from location ADCaddr+1. Interfacing

to 8-bit bus systems is similar, except that two reads are

required to obtain data from all the registers.

The parallel interface on the AD7854/AD7854L is fast enough

to interface to the TMS32020 with no extra wait states. In the

TMS320C25 interface, data accesses may be slowed sufficiently

when reading from and writing to the part to require the inser-

tion of one wait state. In such a case, this wait state can be gen-

erated using the single OR gate to combine the CS and MSC

signals to drive the READY line of the TMS320C25, as shown

in Figure 40. Extra wait states are necessary when using the

TMS320C5x at their fastest clock speeds. Wait states can be

programmed via the IOWSR and CWSR registers (please see

TMS320C5x User Guide for details).

Data is read from the ADC using the following instruction:

IN D,ADCaddr

where D is the memory location where the data is to be stored

and ADCaddr is the I/O address of the AD7854/AD7854L.

AD7854/AD7854L to ADSP-21xx

Figure 39 shows the AD7854/AD7854L interfaced to the

ADSP-21xx series of DSPs as a memory mapped device. A

single wait state may be necessary to interface the AD7854/

AD7854L to the ADSP-21xx depending on the clock speed of

the DSP. This wait state can be programmed via the data

memory waitstate control register of the ADSP-21xx (please see

ADSP-2100 Family Users Manual for details). The following

instruction reads data from the AD7854/AD7854L:

Data is written to the ADC using the following two instructions:

OUT D8LSB, ADCaddr

OUT D8MSB, ADCaddr+1

where D8LSB is the memory location where the 8 LSBs of data

are stored, D8MSB is the location where the 8 MSBs of data are

stored and ADCaddr and ADCaddr+1 are the I/O memory

spaces that the AD7854/AD7854L is mapped into.

AX0 = DM(ADCaddr)

Data can be written to the AD7854/AD7854L using the

instructions:

A15–A1

TMS32020/

ADDRESS BUS

DM (ADCaddr) = AY0

TMS320C25/

TMS320C50*

ADDR

IS

EN

CS

DECODE

DM (ADCaddr+1) = AY1

AD7854/

AD7854L*

where ADCaddr is the address of the AD7854/AD7854L in

ADSP-21xx data memory, AX0 contains the data read from the

ADC, and AY0 contains the 8 LSBs and AY1 the 8 MSBs of

data written to the AD7854/AD7854L.

READY

TMS320C25

ONLY

MSC

A0

HBEN

STRB

WR

R/W

RD

A13–A1

ADSP-21xx*

BUSY

ADDRESS BUS

INTx

DB11–BD0

DATA BUS

D23–D0

ADDR

DECODE

DMS

EN

CS

AD7854/

AD7854L*

*ADDITIONAL PINS OMITTED FOR CLARITY

A0

HBEN

WR

RD

WR

Figure 40. AD7854/AD7854L to TMS32020/C25/C5x Paral-

lel Interface

RD

BUSY

IRQ2

DB11–BD0

DATA BUS

D23–D0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. AD7854/AD7854L to ADSP-21xx Parallel Interface

PRELIMINARY TECHNICAL DATA

–26–

REV. 0

AD7854/AD7854L

AD7854/AD7854L to DSP5600X

AD7854/AD7854L to TMS320C30

Figure 41 shows a parallel interface between the AD7854/

AD7854L and the TMS320C3X family of DSPs. The

AD7854/AD7854L is interfaced to the Expansion Bus of the

TMS320C3X. Two wait states are required in this interface.

These can be programmed using the WTCNT bits of the

Expansion Bus Control register (see TMS320C3X Users guide

for details). Data from the AD7854/AD7854L can be read

using the following instruction:

Figure 42 shows a parallel interface between the AD7854/

AD7854L and the DSP5600x series of DSPs. The AD7854/

AD7854L should be mapped into the top 64 locations of Y data

memory. If extra wait states are needed in this interface, they

can be programmed using the Port A bus control register (please

see DSP5600x User’s Manual for details). Data can be read

from the DSP5600x using the following instruction:

MOVE Y:ADCaddr, X0

LDI *ARn,Rx

Data can be written to the AD7854/AD7854L using the follow-

ing two instructions:

Data can be loaded into the AD7854/AD7854L using the

instructions:

MOVE X0, Y:ADCaddr

STI Ry,*ARn++

STI Rz,*ARn--

MOVE X1, Y:ADCaddr+1

Where ADCaddr is the address in the DSP5600X address space

where ARn is an auxiliary register containing the lower 16 bits

of the address of the AD7854/AD7854L in the TMS320C3X

memory space, Rx is the register into which the ADC data is

loaded during a load operation, Ry contains the 8 LSBs of

data and Rz contains the 8 MSBs of data to be written to the

AD7854/AD7854L.

to which the AD7854/AD7854L has been mapped.

A15–A1

ADDRESS BUS

DSP56000/

DSP56002*

X/Y

ADDR

CS

DECODE

DS

AD7854/

AD7854L*

A0

HBEN

XA12–XA1

EXPANSION ADDRESS BUS

WR

RD

WR

TMS320C30*

RD

ADDR

DECODE

CS

BUSY

AD7854/

IRQ

AD7854L*

DB11–BD0

DATA BUS

D23–D0

XA0

HBEN

IOSTRB

WR

XR/W

*ADDITIONAL PINS OMITTED FOR CLARITY

RD

BUSY

INTx

Figure 42. AD7854/AD7854L to DSP5600X Parallel Interface

DB11–BD0

EXPANSION DATA BUS

XD23–XD0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 41. AD7854/AD7854L to TMS320C30 Parallel

interface

–27–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

CONFIGURING THE AD7853/AD7853L

AD7853/AD7853L as a Read-Only ADC

The AD7853/AD7853L contains fourteen on-chip registers

which can be accessed via the serial interface. In the majority of

applications it is not necessary to access all of these registers.

Figure 23 outlines a flowchart of the sequence which is used to

configure the AD7853/AD7853L as a Read-Only ADC. In this

case there is no writing to the on-chip registers and only the

conversion result data is read from the part. Interface Mode 1

cannot be used in this case as it is necessary to write to the con-

trol register to set Interface Mode 1. Here the CLKIN signal is

applied directly after power-on, the CLKIN signal must be

present to allow the part to perform a calibration. This auto-

matic calibration is completed approximately 150 ms after

power-on.

PRELIMINARY TECHNICAL DATA

–28–

REV. 0

AD7854/AD7854L

Evaluating the AD7854/AD7854L Performance

APPLICATION HINTS

The recommended layout for the AD7854/AD7854L is outlined

in the evaluation board for the AD7854/AD7854L. The evalua-

tion board package includes a fully assembled and tested evalua-

tion board, documentation, and software for controlling the

board from the PC via the EVAL-CONTROL BOARD. The

EVAL-CONTROL BOARD can be used in conjunction with

the AD7854/AD7854L Evaluation board, as well as many other

Analog Devices evaluation boards ending in the CB designator,

to demonstrate/evaluate the ac and dc performance of the

AD7854/AD7854L.

Grounding and Layout

The analog and digital supplies of the AD7854/AD7854L are

independent and separately pinned out to minimize coupling

between the analog and digital sections of the device. The part

has very good immunity to noise on the power supplies as can

be seen by the PSRR versus frequency graph. However, care

should still be taken with regard to grounding and layout.

The printed circuit board on which the AD7854/AD7854L is

mounted should be designed such that the analog and digital

sections are separated and confined to certain areas of the

board. This facilitates the use of ground planes that can be

easily separated. A minimum etch technique is generally best

for ground planes as it gives the best shielding. Digital and

analog ground planes should only be joined in one place. If

the AD7854/AD7854L is the only device requiring an AGND

to DGND connection, then the ground planes should be

connected at the AGND and DGND pins of the AD7854/

AD7854L. If the AD7854/AD7854L is in a system where

multiple devices require AGND to DGND connections, the

connection should still be made at one point only, a star ground

point which should be established as close as possible to the

AD7854/AD7854L.

The software allows the user to perform ac (fast Fourier trans-

form) and dc (histogram of codes) tests on the AD7854/

AD7854L. It also gives full access to all the AD7854/AD7854L

on-chip registers allowing for various calibration and power-

down options to be programmed.

AD785x Family

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD7853 – Single Channel Serial

AD7854 – Single Channel Parallel

AD7858 – Eight Channel Serial

AD7859 – Eight Channel Parallel

Avoid running digital lines under the device as these couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7854/AD7854L to avoid noise coupling.

The power supply lines to the AD7854/AD7854L should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks and the data inputs should be

shielded with digital ground to avoid radiating noise to other

sections of the board and clock signals should never be run near

the analog inputs. Avoid crossover of digital and analog signals.

Traces on opposite sides of the board should run at right angles

to each other. This reduces the effects of feedthrough through

the board. A microstrip technique is by far the best but is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes

while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with a 10 µF tantalum capacitor in parallel with

0.1 µF disc ceramic capacitor to AGND. All digital supplies

should have a 0.1 µF disc ceramic capacitor to DGND. To

achieve the best performance from these decoupling compo-

nents, they must be placed as close as possible to the device,

ideally right up against the device. In systems where a common

supply voltage is used to drive both the AV_DDand DV_DDof the

AD7854/AD7854L, it is recommended that the system’s AV_DD

supply is used. In this case an optional 10 Ω resistor between

the AV_DDpin and DV_DDpin can help to filter noise from digital

circuitry. This supply should have the recommended analog

supply decoupling capacitors between the AV_DDpin of the

AD7854/AD7854L and AGND and the recommended digital

supply decoupling capacitor between the DV_DDpin of the

AD7854/AD7854L and DGND.

–29–

REV. 0

PRELIMINARY TECHNICAL DATA

AD7854/AD7854L

PAGE INDEX

Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Resetting the Parallel Interface . . . . . . . . . . . . . . . . . . . . . 25

PARALLEL INTERFACING . . . . . . . . . . . . . . . . . . . . . . . 26

AD7854/AD7854L to ADSP-21xx . . . . . . . . . . . . . . . . . . 26

Topic

Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PINOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7

AD7854/AD7854L ON-CHIP REGISTERS . . . . . . . . . . . . 8

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 8

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 11

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 11

Writing to/Reading from the Calibration Registers . . . . . . 11

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 12

Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 12

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 13

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . 13

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . 14

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AD7853/AD7853L PERFORMANCE CURVES . . . . . . . 16

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 17

POWER-UP/DOWN SEQUENCE . . . . . . . . . . . . . . . . . . 18

Writing to AD7854/AD7854L . . . . . . . . . . . . . . . . . . . . 18

Using Full and Partial Power-Down Combination . . . . . 18

Full Power-Down or Partial Power-Down . . . . . . . . . . . 19

CALIBRATION SECTION . . . . . . . . . . . . . . . . . . . . . . . 20

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System Calibration Description . . . . . . . . . . . . . . . . . . . . 21

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 23

PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 24

AD7854/AD7854L to TMS32020, TMS320C25 and

TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AD7854/AD7854L to TMS320C30 . . . . . . . . . . . . . . . . 26

AD7854/AD7854L to DSP5600x . . . . . . . . . . . . . . . . . . 27

CONFIGURING THE AD7853/AD7853L . . . . . . . . . . . . 28

AD7853/AD7853L as a Read-Only ADC . . . . . . . . . . . . . 28

APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Evaluating the AD7854/AD7854L Performance . . . . . . . 29

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 31

TABLE INDEX

#

I

Title

Page

Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8

Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8

II

III Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IV Calibrating Register Addressing . . . . . . . . . . . . . . . . . . 11

V

Analog Input Connections . . . . . . . . . . . . . . . . . . . . . . 15

VI Power Management Options . . . . . . . . . . . . . . . . . . . . 18

VII Power-Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VIII Recommended Power-Down Modes for Lowest I_DD. . 18

IX Calibration Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PRELIMINARY TECHNICAL DATA

–30–

REV. 0

AD7854/AD7854L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Pin Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

1

13

0.280 (7.11)

0.240 (6.10)

12

0.325 (8.25)

0.195 (4.95)

0.115 (2.93)

0.060 (1.52)

0.015 (0.38)

0.300 (7.62)

PIN 1

0.210

(5.33)

MAX

0.150

(3.81)

MIN

0.015 (0.381)

0.008 (0.204)

0.200 (5.05)

0.125 (3.18)

SEATING

PLANE

0.100

(2.54)

BSC

0.070 (1.77)

0.045 (1.15)

0.022 (0.558)

0.014 (0.356)

24-Pin Small Outline Package

(R-24)

24

13

0.299 (7.6)

0.291 (7.39)

0.414 (10.52)

PIN 1

0.398 (10.10)

12

1

0.096 (2.44)

0.608 (15.45)

0.089 (2.26)

0.596 (15.13)

0.03 (0.76)

0.02 (0.51)

0.042 (1.067)

0.018 (0.447)

6

0

°

0.01 (0.254)

0.006 (0.15)

0.019 (0.49)

0.014 (0.35)

0.05 (1.27)

BSC

0.013 (0.32)

0.009 (0.23)

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

24-Pin Shrink Small Outline Package

(RS-24)

24

13

0.212 (5.38)

0.205 (5.207)

0.311 (7.9)

0.301 (7.64)

PIN 1

12

1

0.07 (1.78)

0.328 (8.33)

0.318 (8.08)

0.066 (1.67)

0.037 (0.94)

8°

0°

0.022 (0.559)

0.008 (0.203)

0.002 (0.050)

0.0256 (0.65)

BSC

0.009 (0.229)

0.005 (0.127)

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

–31–

REV. 0

PRELIMINARY TECHNICAL DATA

–32–


型号：	AD7854LARS-REEL
厂家：	ADI
描述：	IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, SSOP-28, Analog to Digital Converter 光电二极管转换器
文件：	总32页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7854LARS-REEL [ADI]

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