AD7858_15_技术文档

3 V to 5 V Single Supply, 200 kSPS

8-Channel, 12-Bit Sampling ADC

a

AD7858/AD7858L

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Specified for V_DDof 3 V to 5.5 V

AD7858—200 kSPS; AD7858L—100 kSPS

System and Self-Calibration with Autocalibration on

Power-Up

Eight Single-Ended or Four Pseudo-Differential Inputs

Low Power

AV

DD

AGND

AIN1

AIN8

AD7858/

AD7858L

I/P

MUX

T/H

DV

DD

AD7858: 12 mW (V_DD= 3 V)

AD7858L: 4.5 mW (V_DD= 3 V)

2.5V

REFERENCE

COMP

Automatic Power-Down After Conversion (25 ␮W)

Flexible Serial Interface:

DGND

REF /REF

IN

BUF

OUT

8051/SPI™/QSPI™/␮P Compatible

24-Lead DIP, SOIC, and SSOP Packages

C

REF1

CHARGE

REDISTRIBUTION

DAC

APPLICATIONS

Battery-Powered Systems (Personal Digital Assistants,

Medical Instruments, Mobile Communications)

Pen Computers

Instrumentation and Control Systems

High-Speed Modems

CLKIN

C

REF2

CONVST

SAR AND ADC

CONTROL

CALIBRATION

MEMORY AND

CONTROLLER

BUSY

CAL

SLEEP

GENERAL DESCRIPTION

SERIAL INTERFACE/CONTROL REGISTER

The AD7858/AD7858L are high-speed, low-power, 12-bit

ADCs that operate from a single 3 V or 5 V power supply, the

AD7858 being optimized for speed and the AD7858L for low

power. The ADC powers up with a set of default conditions at

which time it can be operated as a read-only ADC. The ADC

contains self-calibration and system calibration options to en-

sure accurate operation over time and temperature and have a

number of power-down options for low-power applications.

The part powers up with a set of default conditions and can

operate as a read-only ADC.

DIN

DOUT

SCLK

SYNC

PRODUCT HIGHLIGHTS

1. Specified for 3 V and 5 V supplies.

2. Automatic calibration on power-up.

3. Flexible power management options including automatic

power-down after conversion.

The AD7858 is capable of 200 kHz throughput rate while the

AD7858L is capable of 100 kHz throughput rate. The input

track-and-hold acquires a signal in 500 ns and features a

pseudo-differential sampling scheme. The AD7858/AD7858L

voltage range is 0 to V_REFwith straight binary output coding.

Input signal range is to the supply and the part is capable of con-

verting full power signals to 100 kHz.

4. Operates with reference voltages from 1.2 V to V_DD

5. Analog input range from 0 V to V_DD

.

6. Eight single-ended or four pseudo-differential input channels.

7. System and self-calibration.

8. Versatile serial I/O port (SPI/QSPI/8051/µP).

9. Lower power version AD7858L.

CMOS construction ensures low power dissipation of typically

4.5 mW for normal operation and 1.15 mW in power-down

mode with a throughput rate of 10 kSPS (V_DD= 3 V). The part

is available in 24-lead, 0.3 inch-wide dual-in-line package

(DIP), 24-lead small outline (SOIC), and 24-lead small shrink

outline (SSOP) packages.

See page 31 for data sheet index.

SPI and QSPI are trademarks of Motorola, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD7858/AD7858L–SPECIFICATIONS^{1, 2}(AV_DD= DV_DD= +3.0 V to +5.5 V, REF_IN/REF_OUT= 2.5 V External

Reference unless otherwise noted, f_CLKIN= 4 MHz (1.8 MHz B Grade (0؇C to +70؇C), 1 MHz A and B Grades (–40؇C to +85؇C) for L Version); f_SAMPLE

200 kHz (AD7858), 100 kHz (AD7858L); SLEEP = Logic High; T_A= T_MINto T_MAX, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.

=

P

arameter

A Version¹B Version¹

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio³70

(SNR)

71

dB min

Typically SNR is 72 dB

V_IN= 10 kHz Sine Wave, f_SAMPLE= 200 kHz (100 kHz)

Total Harmonic Distortion (THD) –78

–78

dB max

V_IN= 10 kHz Sine Wave, f_SAMPLE= 200 kHz (100 kHz)

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

Second Order Terms

–78

–90

–80

–90

dB typ

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 200 kHz (100 kHz)

V_IN= 25 kHz

Third Order Terms

Channel-to-Channel Isolation

DC ACCURACY

Resolution

Integral Nonlinearity

Any Channel

12

1

12

1

0.5

Bits

LSB max

2.5 V External Reference V_DD= 3 V, V_DD= 5 V (B Grade Only)

5 V External Reference V_DD= 5 V

(L Version, 5 V External Reference, V_DD= 5 V)

(L Version)

Guaranteed No Missed Codes to 12 Bits. 2.5 V External

Reference V_DD= 3 V, 5 V External Reference, V_DD= 5 V

( 1)

1

Differential Nonlinearity

1

Total Unadjusted Error

Unipolar Offset Error

1

5

2.5

3)

1.5)

1.5

4

1

5

2.5

3)

1.5)

1.5

4

LSB typ

LSB max

Typically 2 LSBs

5 V External Reference, V_DD= 5 V

(L Version)

(

(L Version, 5 V External Reference, V_DD= 5 V)

Unipolar Offset Error Match

Positive Full-Scale Error

1.5

5 V External Reference, V_DD= 5 V

Positive Full-Scale Error Match

1

ANALOG INPUT

Input Voltage Ranges

0 to V_REF

Volts

i.e., AIN(+) – AIN(–) = 0 to V_REF, AIN(–) can be biased

up but AIN(+) cannot go below AIN(–)

Leakage Current

Input Capacitance

1

20

1

20

µA max

pF typ

REFERENCE INPUT/OUTPUT

REF_INInput Voltage Range

Input Impedance

2.3/V_DD

150

2.3/V_DD

150

V min/max

kΩ typ

Functional from 1.2 V

REF_OUTOutput Voltage

REF_OUTTempco

2.3/2.7

20

2.3/2.7

20

V min/max

ppm/°C typ

LOGIC INPUTS

Input High Voltage, V_INH

2.4

2.1

0.8

0.6

10

2.4

2.1

0.8

0.6

10

V min

V max

µA max

pF max

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

Typically 10 nA, V_IN= 0 V or V_DD

Input Low Voltage, V_INL

Input Current, I_IN

Input Capacitance, C_IN

4

10

LOGIC OUTPUTS

Output High Voltage, V_OH

I_SOURCE= 200 µA

4

2.4

0.4

10

V min

V max

µA max

pF max

AV_DD= DV_DD= 4.5 V to 5.5 V

AV_DD= DV_DD= 3.0 V to 3.6 V

I_SINK= 0.8 mA

2.4

0.4

10

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁴10

Output Coding

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

4.6 (18)

0.4 (1)

4.6

(10)

0.4 (1)

µs max

µs min

(L Versions Only, –40°C to +85°C, 1 MHz CLKIN)

(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)

(L Versions Only)

Track/Hold Acquisition Time

–2–

REV. B

AD7858/AD7858L

Parameter

A Version¹

B Version¹

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

AV_DD,DV_DD

+3.0/+5.5

V min/max

I_DD

Normal Mode⁵

6 (1.9)

5.5 (1.9)

6 (1.9)

5.5 (1.9)

mA max

AV_DD= DV_DD= 4.5 V to 5.5 V. Typically 4.5 mA (1.5)

AV_DD= DV_DD= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)

Sleep Mode⁶

With External Clock On

10

400

5

10

400

5

µA typ

µA max

Full Power-Down. Power Management Bits in Control

Register Set as PMGT1 = 1, PMGT0 = 0

Partial Power-Down. Power Management Bits in

Control Register Set as PMGT1 = 1, PMGT0 = 1

Typically 1 µA. Full Power-Down. Power Management Bits

in Control

With External Clock Off

Register Set as PMGT1 = 1, PMGT0 = 0

Partial Power-Down. Power Management Bits in Control

Register Set as PMGT1 = 1, PMGT0 = 1

200

µA typ

Normal-Mode Power Dissipation

33 (10.5)

20 (6.85)

33 (10.5)

20 (6.85)

mW max

V

_DD= 5.5 V. Typically 25 mW (8); SLEEP = V_DD

V_DD= 3.6 V. Typically 15 mW (5.4); SLEEP = V_DD

Sleep Mode Power Dissipation

With External Clock On

55

36

27.5

18

55

36

27.5

18

µW typ

µW max

V

_DD= 5.5 V. SLEEP = 0 V

_DD= 3.6 V. SLEEP = 0 V

_DD= 5.5 V. Typically 5.5 µW; SLEEP = 0 V

With External Clock Off

V_DD= 3.6 V. Typically 3.6 µW; SLEEP = 0 V

SYSTEM CALIBRATION

Offset Calibration Span⁷

Gain Calibration Span⁷

+0.05 × V_REF/–0.05 × V_REF

+1.025 × V_REF/–0.975 × V_REF

V max/min Allowable Offset Voltage Span for Calibration

V max/min Allowable Full-Scale Voltage Span for Calibration

NOTES

¹Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f_CLKIN= 1 MHz over –40°C to +85°C temperature range,

B Version f_CLKIN= 1.8 MHz over 0°C to +70°C temperature range.

²Specifications apply after calibration.

³SNR calculation includes distortion and noise components.

⁴Sample tested @ +25°C to ensure compliance.

⁵All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital outputs. Analog inputs @ AGND.

⁶CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital

outputs. Analog inputs @ AGND.

⁷The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage

spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)

0.05 × V_REF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be

V_REF0.025 × V_REF). This is explained in more detail in the Calibration section of the data sheet.

Specifications subject to change without notice.

REV. B

–3–

AD7858/AD7858L

(AV_DD= DV_DD= +3.0 V to +5.5 V; f_CLKIN= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;

T_A= T_MINto T_MAX, unless otherwise noted)

TIMING SPECIFICATIONS¹

Limit at T_MIN, T_MAX

(A, B Versions)

3 V

Parameter

5 V

Units

Description

2

f_CLKIN

500

4

1.8

1

4

100

50

4.6

10 (18)

–0.4 t_SCLK

ϯ0.4 t_SCLK

50

500

4

1.8

1

4

100

90

4.6

10 (18)

–0.4 t_SCLK

ϯ0.4 t_SCLK

90

115

60

30

0.4 t_SCLK

50

50/0.4 t_SCLK

50

130

90

kHz min

MHz max

ns min

Master Clock Frequency

L Version, 0°C to +70°C, B Grade Only

L Version, –40°C to +85°C

f_{SC3 LK}

t₁

CONVST Pulsewidth

CONVST↓ to BUSY↑ Propagation Delay

Conversion Time = 18 t_CLKIN

L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t_CLKIN

SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)

t₂

ns max

t_CONVERT

µs max

t₃

ns min

ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)

4

t₄₄

ns max

ns min

Delay from SYNC↓ Until DOUT Three-State Disabled

Delay from SYNC↓ Until DIN Three-State Disabled

Data Access Time After SCLK↓

Data Setup Time Prior to SCLK↑

Data Valid to SCLK Hold Time

SCLK High Pulsewidth

SCLK Low Pulsewidth

SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)

t₅₄

50

75

40

20

t₆

t₇

t₈

t₉

t₁₀

0.4 t_SCLK

30

30/0.4 t_SCLK

50

90

50

2.5 t_CLKIN

31.25

t₁₁

ns min/max (Continuous SCLK)

5

t₁₂

ns max

ms typ

Delay from SYNC↑ Until DOUT Three-State Enabled

t₁₃

t₁₄

Delay from SCLK↑ to DIN Being Configured as Output

Delay from SCLK↑ to DIN Being Configured as Input

CAL↑ to BUSY↑ Delay

6

t₁₅

2.5 t_CLKIN

31.25

t₁₆

t_CAL

CONVST↓ to BUSY↑ Delay in Calibration Sequence

Full Self-Calibration Time, Master Clock Dependent

7

(125013 t_CLKIN

Internal DAC Plus System Full-Scale Calibration Time, Master

Clock Dependent (111114 t_CLKIN

System Offset Calibration Time, Master Clock Dependent

(13899 t_CLKIN

)

7

t_CAL1

27.78

3.47

27.78

3.47

ms typ

)

7

t_CAL2

)

NOTES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

See Table XI and timing diagrams for different interface modes and Calibration.

²Mark/Space ratio for the master clock input is 40/60 to 60/40.

³The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply

(see Power-Down section).

⁴Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁵t₁₂is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t₁₂, quoted in the timing characteristics is the true bus

relinquish time of the part and is independent of the bus loading.

⁶t₁₄is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the

true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line

knowing that a bus conflict will not occur.

⁷The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to

the 1.8/1 MHz master clock.

Specifications subject to change without notice.

–4–

REV. B

AD7858/AD7858L

TYPICAL TIMING DIAGRAMS

1.6mA

I

Figures 2 and 3 show typical read and write timing diagrams for

serial Interface Mode 2. The reading and writing occurs after

conversion in Figure 2, and during conversion in Figure 3. To

attain the maximum sample rate of 100 kHz (AD7858L) or

200 kHz (AD7858), reading and writing must be performed

during conversion as in Figure 3. At least 400 ns acquisition

time must be allowed (the time from the falling edge of BUSY

to the next rising edge of CONVST) before the next conversion

begins to ensure that the part is settled to the 12-bit level. If the

user does not want to provide the CONVST signal, the conver-

sion can be initiated in software by writing to the control register.

OL

TO

OUTPUT

+2.1V

C

L

100pF

200␮A

I

OH

Figure 1. Load Circuit for Digital Output Timing

Specifications

t_CONVERT= 4.6␮s MAX, 10␮s MAX FOR L VERSION

t₁= 100ns MIN, t₄= 50/90ns MAX 5V/3V, t₇= 40/60ns MIN 5V/3V

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (I/P)

t₃

t₁₁

t₉

1

5

6

16

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t₄

t₁₀

t₁₂

t₆

DB11

THREE-STATE

THREE-

STATE

DB15

DB0

t₈

t₇

DB15

DB11

DB0

Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)

t_CONVERT= 4.6␮s MAX, 10␮s MAX FOR L VERSION

t₁= 100ns MIN, t₄= 50/90ns MAX 5V/3V, t₇= 40/60ns MIN 5V/3V

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (I/P)

t₃

t₁₁

t₉

1

5

6

16

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t₄

t₁₀

t₁₂

t₆

THREE-STATE

THREE-

STATE

DB15

DB11

DB0

t₈

t₇

DB15

DB11

DB0

Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)

REV. B

–5–

AD7858/AD7858L

ABSOLUTE MAXIMUM RATINGS¹

SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mW

(T_A= +25°C unless otherwise noted)

θ

_JAThermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

θ

_JCThermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

REF_IN/REF_OUTto AGND . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Input Current to Any Pin Except Supplies². . . . . . .

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

10 mA

²Transient currents of up to 100 mA will not cause SCR latch-up.

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θ

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions

are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATIONS

DIP, SOIC, AND SSOP

ORDERING GUIDE

Linearity Power

Error

Dissipation Package

(mW)

Model

(LSB)¹

Options²

1

24

CONVST

BUSY

SYNC

2

3

23

22

SCLK

AD7858AN

1

1/2

1

1/2

1

20

6.85

20

N-24

R-24

RS-24

SLEEP

CLKIN

AD7858BN

REF /REF

IN

4

5

21 DIN

AD7858LAN³

AD7858LBN³

AD7858AR

OUT

AD7858/

AD7858L

AV

20 DOUT

DD

AGND

6

19

18

DGND

TOP VIEW

(Not to Scale)

C

7

DV

DD

REF1

AD7858BR

20

C

8

17 CAL

AD7858LAR³

AD7858LBR³

AD7858LARS³

EVAL-AD7858CB⁴

EVAL-CONTROL BOARD⁵

6.85

REF2

AIN1

AIN8

16

9

10

11

AIN2

AIN3

AIN7

AIN6

15

14

13

AIN4 12

AIN5

NOTES

¹Linearity error here refers to integral linearity error.

²N = Plastic DIP; R = SOIC; RS = SSOP.

³L signifies the low-power version.

⁴This can be used as a stand-alone evaluation board or in conjunction with the EVAL-

CONTROL BOARD for evaluation/demonstration purposes.

⁵This board is a complete unit allowing a PC to control and communicate with all

Analog Devices evaluation boards ending in the CB designators.

–6–

REV. B

AD7858/AD7858L

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic

Description

Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode

and starts conversion. When this input is not used, it should be tied to DV_DD

1

CONVST

.

2

BUSY

Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL,

and remains high until conversion is completed. BUSY is also used to indicate when the AD7858/

AD7858L has completed its on-chip calibration sequence.

3

4

SLEEP

Sleep Input/Low-Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down including the

internal voltage reference provided there is no conversion or calibration being performed. Calibration

data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is

the reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this

REF_IN/REF_OUT

appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AV_DD

When this pin is tied to AV_DD,or when an externally applied reference approaches AV_DD, the C_REF1pin

should also be tied to AV_DD

.

5

6

7

AV_DD

AGND

C_REF1

Analog Positive Supply Voltage, +3.0 V to +5.5 V.

Analog Ground. Ground reference for track/hold, reference, and DAC.

Reference Capacitor (0.1 µF Multilayer Ceramic). This external capacitor is used as a charge source for

the internal DAC. The capacitor should be tied between the pin and AGND.

8

C_REF2

Reference Capacitor (0.01 µF Ceramic Disc). This external capacitor is used in conjunction with the on-

chip reference. The capacitor should be tied between the pin and AGND.

9–16 AIN1–AIN8

Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)

or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.

Both the positive and negative inputs cannot go below AGND or above AV_DDat any time. Also the posi-

tive input cannot go below the negative input. See Table III for channel selection.

17

CAL

Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets

all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting

a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This

input overrides all other internal operations. If the autocalibration is not required, this pin should be tied

to a logic high.

18

19

20

21

DV_DD

DGND

DOUT

DIN

Digital Supply Voltage, +3.0 V to +5.5 V.

Digital Ground. Ground reference point for digital circuitry.

Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can

act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).

22

CLKIN

Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali-

bration times.

23

24

SCLK

SYNC

Serial Port Clock. Logic Input. The user must provide a serial clock on this input.

Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read

and write operations (see Table IX).

REV. B

–7–

AD7858/AD7858L

TERMINOLOGY¹

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7858/AD7858L, it is

defined as:

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

(V₂²+ V₃²+ V₄²+ V₅²+ V₆²)

THD dB = 20 log

(

)

V

1

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

Total Unadjusted Error

Peak Harmonic or Spurious Noise

This is the deviation of the actual code from the ideal code tak-

ing all errors into account (Gain, Offset, Integral Nonlinearity, and

other errors) at any point along the transfer function.

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Unipolar Offset Error

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).

Positive Full-Scale Error

This is the deviation of the last code transition from the ideal

AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset

error has been adjusted out.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and

(fa – 2fb).

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of crosstalk between

the channels. It is measured by applying a full-scale 25 kHz

signal to the other seven channels and determining how much

that signal is attenuated in the channel of interest. The figure

given is the worst case for all channels.

Testing is performed using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used. In

this case, the second order terms are usually distanced in fre-

quency from the original sine waves, while the third order terms

are usually at a frequency close to the input frequencies. As a

result, the second and third order terms are specified separately.

The calculation of the intermodulation distortion is as per the

THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode and the end of

conversion. Track/hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within 1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (f_S/2), excluding dc. The ratio

is dependent on the number of quantization levels in the digitiza-

tion process; the more levels, the smaller the quantization noise.

The theoretical signal to (noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N +1.76) dB

Thus for a 12-bit converter, this is 74 dB.

¹AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–)

refers to the negative analog input of the pseudo differential pair or to AGND

depending on the channel configuration.

–8–

REV. B

AD7858/AD7858L

ON-CHIP REGISTERS

The AD7858/AD7858L powers up with a set of default conditions. The only writing required is to select the channel configuration.

Without performing any other write operations the AD7858/AD7858L still retains the flexibility for performing a full power-down

and a full self-calibration.

Extra features and flexibility, such as performing different power-down options, different types of calibrations including system

calibration, and software conversion start, can be selected by further writing to the part.

The AD7858/AD7858L contains a Control Register, ADC Output Data Register, Status Register, Test Register, and

10 Calibration Registers. The control register is write-only, the ADC output data register and the status register are read-only, and

the test and calibration registers are both read/write registers. The Test Register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine

which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are

written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the

overall write register hierarchy.

Table I. Write Register Addressing

ADDR1

ADDR0 Comment

0

1

This combination does not address any register so the subsequent 14 data bits are ignored.

This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test

register.

1

0

1

This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the Control Register, all subsequent read operations that follow will be from the selected regis-

ter until the read selection bits are changed in the Control Register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

0

All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up

default setting. There will always be 4 leading zeros when reading from the ADC Output Data Register.

0

1

0

1

All successive read operations will be from TEST REGISTER.

All successive read operations will be from CALIBRATION REGISTERS.

All successive read operations will be from STATUS REGISTER.

RDSLT1, RDSLT0

DECODE

ADDR1, ADDR0

DECODE

00

01

10

11

01

10

11

ADC OUTPUT

DATA REGISTER

TEST

REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

TEST

REGISTER

CALIBRATION

REGISTERS

CONTROL

REGISTER

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

DAC(8)

GAIN(1)

OFFSET(1)

10

GAIN(1)

11

OFFSET(1)

10

GAIN(1)

11

OFFSET(1)

00

01

00

01

CALSLT1, CALSLT0

DECODE

CALSLT1, CALSLT0

DECODE

Figure 4. Write Register Hierarchy/Address Decoding

Figure 5. Read Register Hierarchy/Address Decoding

REV. B

–9–

AD7858/AD7858L

CONTROL REGISTER

The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.

The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-

scribed below. The power-up status of all bits is 0.

MSB

SGL/DIFF

CH2

CH1

CH0

PMGT1

PMGT0

RDSLT1

STCAL

RDSLT0

2/3 MODE

CONVST

CALMD

CALSLT1

CALSLT0

LSB

CONTROL REGISTER BIT FUNCTION DESCRIPTION

Comment

Bit

Mnemonic

13

SGL/DIFF

A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position

configures the input channels in single-ended mode (see Table III).

12

11

10

CH2

CH1

CH0

These three bits are used to select the channel on which the conversion is performed. The channels can

be configured as eight single-ended channels or four pseudo-differential channels. The default selection

is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).

9

8

PMGT1

PMGT0

Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various

Power-Down Modes (see Power-Down section for more details).

7

6

RDSLT1

RDSLT0

Theses two bits determine which register is addressed for the read operations (see Table II).

5

2/3 MODE

Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by

default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to

1 in every write cycle.

4

3

CONVST

CALMD

Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration

(see Calibration section.)

Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. These bits have two functions.

With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per

formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on the Calibration Registers for more details).

–10–

REV. B

AD7858/AD7858L

Table III. Channel Selection

SGL/DIFF

CH2

CH1

CH0

AIN(+)*

AIN(–)*

0

1

0

1

0

1

AIN₁

AIN₃

AIN₅

AIN₇

AIN₂

AIN₄

AIN₆

AIN₈

0

1

0

1

0

1

0

1

AIN₂

AIN₄

AIN₆

AIN₈

AIN₁

AIN₃

AIN₅

AIN₇

1

0

1

0

1

0

1

AIN₁

AIN₃

AIN₅

AIN₇

AGND

1

0

1

0

1

0

1

AIN₂

AIN₄

AIN₆

AIN₈

AGND

*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,

*AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.

Table IV. Calibration Selection

CALMD

CALSLT1

CALSLT0

Calibration Type

0

A Full Internal Calibration is initiated where the Internal DAC is calibrated

followed by the Internal Gain Error, and finally the Internal Offset Error is

calibrated out. This is the default setting.

0

1

Here the Internal Gain Error is calibrated out followed by the Internal Offset

Error calibrated out.

0

1

0

1

0

This calibrates out the Internal Offset Error only.

This calibrates out the Internal Gain Error only.

A Full System Calibration is initiated here where first the Internal DAC is

calibrated followed by the System Gain Error, and finally the System Offset

Error is calibrated out.

1

0

1

Here the System Gain Error is calibrated out followed by the System Offset

Error.

1

0

1

This calibrates out the System Offset Error only.

This calibrates out the System Gain Error only.

REV. B

–11–

AD7858/AD7858L

STATUS REGISTER

The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The

status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits

in the status register are described below. The power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

MSB

ZERO

BUSY

SGL/DIFF

2/3 MODE

CH2

X

CH1

CH0

PMGT1

PMGT0

STCAL

RDSLT1

RDSLT0

CALMD

CALSLT1

CALSLT0

LSB

STATUS REGISTER BIT FUNCTION DESCRIPTION

Bit

15

Mnemonic

ZERO

Comment

This bit is always 0.

14

BUSY

Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion

or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.

13

12

11

10

SGL/DIFF

CH2

CH1

These four bits indicate the channel selected for conversion (see Table III).

CH0

9

8

PMGT1

PMGT0

Power management bits. These bits along with the SLEEP pin will indicate if the part is in a

power-down mode or not. See Table VI for description.

7

6

RDSLT1

RDSLT0

Both of these bits are always 1, indicating it is the status register being read (see Table II).

5

2/3 MODE

Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at

1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.

4

3

X

Don’t care bit.

CALMD

Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit

indicates a system calibration is selected (see Table IV).

2

1

0

CALSLT1

CALSLT0

STCAL

Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a

calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and

CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing

(see section on the Calibration Registers for more details).

–12–

REV. B

AD7858/AD7858L

CALIBRATION REGISTERS

The AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written

to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the

user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-

dressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not

attempt to read from and write to the calibration registers at the same time.

Table V. Calibration Register Addressing

CALSLT1 CALSLT0

Comment

0

1

0

1

0

1

This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.

This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.

This combination addresses the Offset Register. One register in total.

This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers

When reading from the calibration registers there will always be

two leading zeros for each of the registers. When operating in

Serial Interface Mode 1 the read operations to the calibration

registers cannot be aborted. The full number of read operations

must be completed (see section on Serial Interface Mode 1

Timing for more detail).

For writing to the calibration registers a write to the control

register is required to set the CALSLT0 and CALSLT1 bits.

For reading from the calibration registers a write to the control

register is required to set the CALSLT0 and CALSLT1 bits,

but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-

dresses the calibration registers for reading). The calibration

register pointer is reset on writing to the control register setting

the CALSLT1 and CALSLT0 bits, or upon completion of all

the calibration register write/read operations. When reset it

points to the first calibration register in the selected write/read

sequence. The calibration register pointer will point to the gain

calibration register upon reset in all but one case, this case being

where the offset calibration register is selected on its own

(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra-

tion register is being accessed the calibration register pointer will

be automatically incremented after each calibration register

write/read operation. The order in which the 10 calibration

registers are arranged is shown in Figure 7. The user may abort

at any time before all the calibration register write/read opera-

tions are completed, and the next control register write opera-

tion will reset the calibration register pointer. The flow chart in

Figure 8 shows the sequence for writing to the calibration regis-

ters and Figure 9 for reading.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

REGISTER

NO

WRITE

OPERATION

OR

ABORT

?

CALIBRATION REGISTERS

CAL REGISTER

(1)

(2)

(3)

GAIN REGISTER

OFFSET REGISTER

ADDRESS POINTER

YES

FINISHED

DAC 1ST MSB REGISTER

CALIBRATION REGISTER

ADDRESS POINTER

.

Figure8. FlowchartforWritingtotheCalibrationRegisters

POSITION IS DETERMINED

BY THE NUMBER OF

CALIBRATION REGISTERS

ADDRESSED AND THE

NUMBER OF READ/WRITE

OPERATIONS

(10)

DAC 8TH MSB REGISTER

Figure 7. Calibration Register Arrangements

REV. B

–13–

AD7858/AD7858L

Q. If a +20 mV offset is present in the analog input signal and the

reference voltage is 2.5 V what code needs to be written to the

offset register to compensate for the offset?

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,

RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

A. 2.5 V reference implies that the resolution in the offset regis-

ter is 5% × 2.5 V/2¹³= 0.015 mV. +20 mV/0.015 mV =

1310.72; rounding to the nearest number gives 1311. In

binary terms this is 0101 0001 1111. Therefore, decrease the

offset register by 0101 0001 1111.

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

This method of compensating for offset in the analog input

signal allows for fine tuning the offset compensation. If the

offset on the analog input signal is known, there will be no need

to apply the offset voltage to the analog input pins and do a

system calibration. The offset compensation can take place in

software.

READ CAL REGISTER

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

Adjusting the Gain Calibration Register

REGISTER

NO

READ

OPERATION

OR

ABORT

?

The gain calibration register contains 16 bits, two leading 0s

and 14 data bits. The data bits are binary weighted as in the

offset calibration register. The gain register value is effectively

multiplied by the analog input to scale the conversion result

over the full range. Increasing the gain register compensates for

a smaller analog input range and decreasing the gain register

compensates for a larger input range. The maximum analog

input range that the gain register can compensate for is 1.025

times the reference voltage, and the minimum input range is

0.975 times the reference voltage.

YES

FINISHED

Figure 9. Flowchart for Reading from the Calibration

Registers

Adjusting the Offset Calibration Register

The offset calibration register contains 16 bits, two leading zeros,

and 14 data bits. By changing the contents of the offset register

different amounts of offset on the analog input signal can be

compensated for. Increasing the number in the offset calibration

register compensates for negative offset on the analog input

signal, and decreasing the number in the offset calibration regis-

ter compensates for positive offset on the analog input signal.

The default value of the offset calibration register is 0010 0000

0000 0000 approximately. This is not an exact value, but the

value in the offset register should be close to this value. Each of

the 14 data bits in the offset register is binary weighted; the

MSB has a weighting of 5% of the reference voltage, the MSB-1

has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,

and so on down to the LSB which has a weighting of 0.0006%.

This gives a resolution of 0.0006% of V_REFapproximately.

More accurately the resolution is (0.05 × V_REF)/2¹³volts =

0.015 mV, with a 2.5 V reference. The maximum offset that

can be compensated for is 5% of the reference voltage, which

equates to 125 mV with a 2.5 V reference and 250 mV with

a 5 V reference.

–14–

REV. B

AD7858/AD7858L

CIRCUIT INFORMATION

conversion will take 17.5 CLKIN periods. The maximum speci-

The AD7858/AD7858L is a fast, 12-bit single supply A/D con-

verter. The part requires an external 4 MHz/1.8 MHz master

clock (CLKIN), two C_REFcapacitors, a CONVST signal to start

conversion, and power supply decoupling capacitors. The part

provides the user with track/hold, on-chip reference, calibration

features, A/D converter, and serial interface logic functions on a

single chip. The A/D converter section of the AD7858/AD7858L

consists of a conventional successive-approximation converter

based around a capacitor DAC. The AD7858/AD7858L accepts

an analog input range of 0 to +V_DDwhere the reference can be

tied to V_DD. The reference input to the part is buffered on-chip.

fied conversion time is 4.6 µs for the AD7858 (18t_CLKIN

,

CLKIN = 4 MHz) and 10 µs for the AD7858L (18t_CLKIN

,

CLKIN = 1.8 MHz). When a conversion is completed, the

BUSY output goes low, and then the result of the conversion

can be read by accessing the data through the serial interface.

To obtain optimum performance from the part, the read opera-

tion should not occur during the conversion or 400 ns prior to

the next CONVST rising edge. However, the maximum

throughput rates are achieved by reading/writing during conver-

sion, and reading/writing during conversion is likely to degrade

the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858

can operate at throughput rates up to 200 kHz, 100 kHz for the

AD7858L. For the AD7858 a conversion takes 18 CLKIN

periods; 2 CLKIN periods are needed for the acquisition time

giving a full cycle time of 5 µs (= 200 kHz, CLKIN = 4 MHz).

For the AD7858L 100 kHz throughput can be obtained as

follows: the CLKIN and CONVST signals are arranged to give

a conversion time of 16.5 CLKIN periods as described above,

1.5 CLKIN periods are allowed for the acquisition time. This

gives a full cycle time of 10 µs (=100 kHz, CLKIN = 1.8 MHz).

When using the software conversion start for maximum through-

put the user must ensure the control register write operation

extends beyond the falling edge of BUSY. The falling edge of

BUSY resets the CONVST bit to 0 and allows it to be repro-

grammed to 1 to start the next conversion.

A major advantage of the AD7858/AD7858L is that a conversion

can be initiated in software as well as applying a signal to the

CONVST pin. Another innovative feature of the AD7858/

AD7858L is self-calibration on power-up, which is initiated

having a capacitor from the CAL pin to AGND, to give superior

dc accuracy. See Automatic Calibration on Power-Up section.

The part is available in a 24-pin SSOP package and this offers

the user considerable space-saving advantages over alternative

solutions. The AD7858L version typically consumes only

5.5 mW making it ideal for battery-powered applications.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7858/AD7858L by pulsing

the CONVST input or by writing to the control register and

setting the CONVST bit to 1. On the rising edge of CONVST

(or at the end of the control register write operation), the on-

chip track/hold goes from track to hold mode. The falling edge

of the CLKIN signal that follows the rising edge of the CONVST

signal initiates the conversion, provided the rising edge of

CONVST occurs at least 10 ns typically before this CLKIN

edge. The conversion cycle will take 16.5 CLKIN periods from

this CLKIN falling edge. If the 10 ns setup time is not met, the

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7858/

AD7858L. The AGND and the DGND pins are connected

together at the device for good noise suppression. The CAL pin

has a 0.01 µF capacitor to enable an automatic self-calibration

on power-up. The conversion result is output in a 16-bit word

with four leading zeros followed by the MSB of the 12-bit result.

Note that after the AV_DDand DV_DDpower-up the part will

4MHz/1.8MHz OSCILLATOR

200kHz/100kHz PULSE GENERATOR

MASTER CLOCK

INPUT

0.1␮F

ANALOG SUPPLY

+3V TO +5V

10␮F

0.1␮F

CONVERSION

START INPUT

AV

DD

DV

DD

OSCILLOSCOPE

CLKIN

SCLK

AIN(+)

AIN(–)

0V TO 2.5V

INPUT

CH1

CH2

SERIAL CLOCK

INPUT

C

REF1

REF2

CONVST

SYNC

DIN

0.1␮F

0.01␮F

AD7858/

AD7858L

C

CH3

CH4

CH5

FRAME SYNC INPUT

SERIAL DATA INPUT

DV

DD

SLEEP

CAL

0.01␮F

DOUT

AGND

DGND

SERIAL DATA

OUTPUT

AUTO CAL ON

POWER-UP

4 LEADING

ZEROS FOR

ADC DATA

INTERNAL/

EXTERNAL

REFERENCE

DATA GENERATOR

0.1␮F

OPTIONAL

AD780/

REF-192

EXTERNAL

PULSE GENERATOR

REFERENCE

Figure 10. Typical Circuit

–15–

REV. B

AD7858/AD7858L

require approximately 150 ms for the internal reference to settle

and for the automatic calibration on power-up to be completed.

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC low-

pass filter on the AIN(+) pin as shown in Figure 13. In applica-

tions where harmonic distortion and signal to noise ratio are

critical the analog input should be driven from a low impedance

source. Large source impedances will significantly affect the ac

performance of the ADC. This may necessitate the use of an

input buffer amplifier. The choice of the op amp will be a func-

tion of the particular application.

For applications where power consumption is a major concern

then the SLEEP pin can be connected to DGND. See Power-

Down section for more detail on low power applications.

ANALOG INPUT

The equivalent circuit of the analog input section is shown in

Figure 11. During the acquisition interval the switches are both

in the track position and the AIN(+) charges the 20 pF capacitor

through the 125 Ω resistance. On the rising edge of CONVST

switches SW1 and SW2 go into the hold position retaining

charge on the 20 pF capacitor as a sample of the signal on

AIN(+). The AIN(–) is connected to the 20 pF capacitor, and

this unbalances the voltage at node A at the input of the com-

parator. The capacitor DAC adjusts during the remainder of the

conversion cycle to restore the voltage at node A to the correct

value. This action transfers a charge, representing the analog

input signal, to the capacitor DAC which in turn forms a digital

representation of the analog input signal. The voltage on the

AIN(–) pin directly influences the charge transferred to the

capacitor DAC at the hold instant. If this voltage changes dur-

ing the conversion period, the DAC representation of the analog

input voltage will be altered. Therefore it is most important that

the voltage on the AIN(–) pin remains constant during the conver-

sion period. Furthermore it is recommended that the AIN(–)

pin is always connected to AGND or to a fixed dc voltage.

When no amplifier is used to drive the analog input the source

impedance should be limited to low values. The maximum

source impedance will depend on the amount of total harmonic

distortion (THD) that can be tolerated. The THD will increase

as the source impedance increases and performance will de-

grade. Figure 12 shows a graph of the total harmonic distortion

versus analog input signal frequency for different source imped-

ances. With the setup as in Figure 13, the THD is at the –90 dB

level. With a source impedance of 1 kΩ and no capacitor on the

AIN(+) pin, the THD increases with frequency.

–72

THD vs. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

–76

R

= 1k⍀

IN

–80

–84

–88

–92

Acquisition Time

The track and hold amplifier enters its tracking mode on the

falling edge of the BUSY signal. The time required for the track

and hold amplifier to acquire an input signal will depend on

how quickly the 20 pF input capacitance is charged. The acqui-

sition time is calculated using the formula:

R

= 50⍀, 10nF

IN

AS IN FIGURE 13

0

20

40

60

80

100

t_ACQ= 9 ×(R +125 Ω)× 20 pF

IN

INPUT FREQUENCY – kHz

where R_INis the source impedance of the input signal, and

125 Ω, 20 pF is the input R, C.

Figure 12. THD vs. Analog Input Frequency

In a single supply application (both 3 V and 5 V), the V+ and

V– of the op amp can be taken directly from the supplies to the

AD7858/AD7858L which eliminates the need for extra external

power supplies. When operating with rail-to-rail inputs and

outputs, at frequencies greater than 10 kHz care must be taken

in selecting the particular op amp for the application. In particu-

lar for single supply applications the input amplifiers should be

connected in a gain of –1 arrangement to get the optimum per-

formance. Figure 13 shows the arrangement for a single supply

application with a 50 Ω and 10 nF low-pass filter (cutoff fre-

quency 320 kHz) on the AIN(+) pin. Note that the 10 nF is a

capacitor with good linearity to ensure good ac performance.

Recommended single supply op amps are the AD820 and the

AD820-3 V.

TRACK

125⍀

AIN(+)

SW1

HOLD

AIN(–)

125⍀

CAPACITOR

DAC

20pF

NODE A

SW2

COMPARATOR

HOLD

TRACK

C

REF2

Figure 11. Analog Input Equivalent Circuit

DC/AC Applications

For dc applications high source impedances are acceptable

provided there is enough acquisition time between conversions

to charge the 20 pF capacitor. The acquisition time can be

calculated from the above formula for different source imped-

ances. For example with R_IN= 5 kΩ, the required acquisition

time will be 922 ns.

+3V TO +5V

10␮F

50⍀

0.1␮F

10k⍀

V

IN

)

V+

(0 TO V

TO AIN(+) OF

AD7858/AD7858L

REF

V

10nF

(NPO)

REF

AD820

AD820-3V

V+

10k⍀

Figure 13. Analog Input Buffering

–16–

REV. B

AD7858/AD7858L

REFERENCE SECTION

Input Range

For specified performance, it is recommended that when using

an external reference this reference should be between 2.3 V

and the analog supply AV_DD. The connections for the relevant

reference pins are shown in the typical connection diagrams. If

the internal reference is being used, the REF_IN/REF_OUTpin

should have a 100 nF capacitor connected to AGND very close

to the REF_IN/REF_OUTpin. These connections are shown in

Figure 16.

The analog input range for the AD7858/AD7858L is 0 V to

V

_REF. The AIN(–) pin on the AD7858/AD7858L can be biased

up above AGND, if required. The advantage of biasing the

lower end of the analog input range away from AGND is that

the user does not need to have the analog input swing all the

way down to AGND. This has the advantage in true single-

supply applications that the input amplifier does not need to

swing all the way down to AGND. The upper end of the analog

input range is shifted up by the same amount. Care must be

taken so that the bias applied does not shift the upper end of the

analog input above the AV_DDsupply. In the case where the

reference is the supply, AV_DD, the AIN(–) must be tied to

AGND.

If the internal reference is required for use external to the ADC,

it should be buffered at the REF_IN/REF_OUTpin and a 100 nF

connected from this pin to AGND. The typical noise performance

for the internal reference, with 5 V supplies, is 150 nV/√Hz @

1 kHz and dc noise is 100 µV p-p.

ANALOG SUPPLY

+3V TO +5V

TRACK AND HOLD

AIN(+)

AMPLIFIER

10␮F

0.1␮F

V

= 0 TO V

REF

STRAIGHT

BINARY

FORMAT

IN

DOUT

AIN(–)

AV

DD

DV

DD

C

REF1

AD7858/

AD7858L

0.1␮F

AD7858/

AD7858L

REF2

Figure 14. 0 to V_REFInput Configuration

0.01␮F

0.1␮F

Transfer Function

For the AD7858/AD7858L input range the designed code tran-

sitions occur midway between successive integer LSB values

(i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS – 3/2 LSBs). The

output coding is straight binary with 1 LSB = FS/4096 = 3.3 V/

4096 = 0.8 mV when V_REF= 3.3 V. The ideal input/output

transfer characteristic is shown in Figure 15.

REF /REF

IN

OUT

Figure 16. Relevant Connections When Using Internal

Reference

The other option is that the REF_IN/REF_OUTpin be overdriven

by connecting it to an external reference. This is possible due to

the series resistance from the REF_IN/REF_OUTpin to the internal

reference. This external reference can have a range that includes

AV_DD. When using AV_DDas the reference source, the 100 nF

capacitor from the REF_IN/REF_OUTpin to AGND should be as

close as possible to the REF_IN/REF_OUTpin, and also the C_REF1

pin should be connected to AV_DDto keep this pin at the same

level as the reference. The connections for this arrangement are

shown in Figure 17. When using AV_DDit may be necessary to

add a resistor in series with the AV_DDsupply. This will have the

effect of filtering the noise associated with the AV_DDsupply.

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

FS

4096

1LSB =

000...010

000...001

000...000

ANALOG SUPPLY

+3V TO +5V

10␮F

0.1␮F

0V 1LSB

+FS –1LSB

= (AIN(+) – AIN(–)), INPUT VOLTAGE

V

IN

AV

DV

DD

Figure 15. AD7858/AD7858L Transfer Characteristic

C

REF1

0.1␮F

AD7858/

AD7858L

REF2

0.01␮F

0.1␮F

REF /REF

IN

OUT

Figure 17. Relevant Connections When Using AV_DDas the

Reference

REV. B

–17–

AD7858/AD7858L

PERFORMANCE CURVES

Figure 18 shows a typical FFT plot for the AD7858 at 200 kHz

sample rate and 10 kHz input frequency.

–78

–80

AV = DV = 3.3V/5.0V,

DD DD

100mVp-p SINE WAVE ON AV

DD

0

–82

–84

–86

AV = DV = 3.3V

DD

f

= 200kHz

= 10kHz

SAMPLE

3.3V

–20

–40

–60

–80

IN

SNR = 72.04dB

THD = –88.43dB

5.0V

–88

–90

0

20

40

60

80

100

INPUT FREQUENCY – kHz

–100

–120

Figure 20. PSRR vs. Frequency

POWER-DOWN OPTIONS

0

20

40

60

80

100

FREQUENCY – kHz

The AD7858 provides flexible power management to allow the

user to achieve the best power performance for a given through-

put rate. The power management options are selected by

programming the power management bits, PMGT1 and PMGT0,

in the control register and by use of the SLEEP pin. Table VI

summarizes the power-down options that are available and how

they can be selected by using either software, hardware, or a

combination of both. The AD7858 can be fully or partially

powered down. When fully powered down, all the on-chip cir-

cuitry is powered down and I_DDis 1 µA typ. If a partial power-

down is selected, then all the on-chip circuitry except the reference

is powered down and I_DDis 400 µA typ. The choice of full or par-

tial power-down does not give any significant improvement in

throughput with a power-down between conversions. This is

discussed in the next section–Power-Up Times. However, a

partial power-down does allow the on-chip reference to be used

externally even though the rest of the AD7858 circuitry is pow-

ered down. It also allows the AD7858 to be powered up faster

after a long power-down period when using the on-chip refer-

ence (See Power-Up Times–Using On-Chip Reference).

Figure 18. FFT Plot

Figure 19 shows the SNR vs. Frequency for different supplies

and different external references.

74

AV = DV WITH 2.5V REFERENCE

DD DD

UNLESS STATED OTHERWISE

73

72

71

70

5.0V SUPPLIES, WITH 5V REFERENCE

5.0V SUPPLIES

5.0V SUPPLIES, L VERSION

3.3V SUPPLIES

69

0

20

40

60

80

100

INPUT FREQUENCY – kHz

When using the SLEEP pin, the power management bits PMGT1

and PMGT0 should be set to zero (default status on power-up).

Bringing the SLEEP pin logic high ensures normal operation,

and the part does not power down at any stage. This may be

necessary if the part is being used at high throughput rates when

it is not possible to power down between conversions. If the user

wishes to power down between conversions at lower throughput

rates (i.e. <100 kSPS for the AD7858) to achieve better power

performances, then the SLEEP pin should be tied logic low.

Figure 19. SNR vs. Frequency

Figure 20 shows the Power Supply Rejection Ratio vs. Fre-

quency for the part. The Power Supply Rejection Ratio is de-

fined as the ratio of the power in adc output at frequency f to

the power of a full-scale sine wave.

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in adc output, Pfs = power of a

full-scale sine wave. Here a 100 mV peak-to-peak sine wave is

coupled onto the AV_DDsupply while the digital supply is left

unaltered. Both the 3.3 V and 5.0 V supply performances are

shown.

If the power-down options are to be selected in software only,

then the SLEEP pin should be tied logic high. By setting the

power management bits PMGT1 and PMGT0 as shown in

Table VI, a Full Power-Down, Full Power-Up, Full Power-

Down Between Conversions, and a Partial Power-Down Be-

tween Conversions can be selected.

–18–

REV. B

AD7858/AD7858L

Table VI. Power Management Options

PMGT1 PMGT0 SLEEP

a logic high. If the autocalibration is disabled, then the user must

take into account the time required by the AD7858 to power-up

before a self-calibration is carried out. This power-up time is the

time taken for the AD7858 to power up when power is first

applied (300 µs) typ) or the time it takes the external reference

to settle to the 12-bit level–whichever is the longer.

Bit

Comment

0

Full Power-Down if Not

Calibrating or Converting

(Default Condition

The AD7858 powers up from a full hardware or software

power-down in 5 µs typ. This limits the throughput which the

part is capable of to 104 kSPS for the AD7858 operating with a

4 MHz CLK and 66 kSPS for the AD7858L with a 1.8 MHz

CLK when powering down between conversions. Figure 22

shows how power-down between conversions is implemented

using the CONVST pin. The user first selects the power-down

between conversions option by using the SLEEP pin and the

power management bits, PMGT1 and PMGT0, in the control

register, (see last section). In this mode the AD7858 automati-

cally enters a full power-down at the end of a conversion, i.e.,

when BUSY goes low. The falling edge of the next CONVST

pulse causes the part to power up. Assuming the external refer-

ence is left powered up, the AD7858 should be ready for normal

operation 5 µs after this falling edge. The rising edge of CONVST

initiates a conversion so the CONVST pulse should be at least

5 µs wide. The part automatically powers down on completion

of the conversion.

After Power-On)

0

1

X

Normal Operation

(Independent of the SLEEP Pin)

Full Power-Down

Partial Power-Down if Not

Converting

1

0

1

X

A typical connection diagram for a low power application is

shown in Figure 21 (AD7858L is the low power version of the

AD7858).

CURRENT,

I = 1.5mA

TYP

1.8MHz

OSCILLATOR

0.1␮F

ANALOG

SUPPLY

+3V

10␮F 0.1␮F

MASTER

AV

DV

100kHz

PULSE

GENERATOR

CLOCK

INPUT

DD

START CONVERSION ON RISING EDGE

POWER-UP ON FALLING EDGE

0V TO 2.5V

INPUT

AIN(+)

CLKIN

AIN(–)

AD7858/

AD7858L

5␮s

C

REF1

CONVERSION

START INPUT

0.1␮F

CONVST

t

CONVERT

C

REF2

SERIAL CLOCK

INPUT

0.01␮F

BUSY

SCLK

AUTO POWER

DOWN AFTER

CONVERSION

SLEEP

CAL

POWER-UP

TIME

NORMAL

FULL

POWER-UP

TIME

SYNC

OPERATION POWER-DOWN

LOW

POWER

␮C/␮P

SERIAL DATA

OUTPUT

0.01␮F

Figure 22. Power-Up Timing When Using CONVST Pin

DOUT

DIN

AUTO CAL

ON

POWER-UP

NOTE: Where the software CONVST is used or automatic full

power-down, the part must be powered up in software with an

extra write setting PMGT1 = 0 and PMGT0 = 1 before a con-

version is initiated in the next write. Automatic partial power-

down after a calibration is not possible; the part must be

powered down manually. If software calibrations are to be used

when operating in the partial power-down mode, then three

separate writes are required. The first initiates the type of cali-

bration required, the second write powers the part down into

partial power-down mode, while the third write powers the part

up again before the next calibration command is issued.

AGND

DGND

SERIAL DATA

INPUT

REF /REF

IN

OUT

INTERNAL

REFERENCE

0.1␮F

OPTIONAL

EXTERNAL

REFERENCE

REF192

Figure 21. Typical Low Power Circuit

Using the Internal (On-Chip) Reference

POWER-UP TIMES

As in the case of an external reference, the AD7858 can power-

up from one of two conditions, power-up after the supplies are

connected or power-up from hardware/software power-down.

When using the on-chip reference and powering up when AV_DD

and DV_DDare first connected, it is recommended that the power-

up calibration mode be disabled as explained above. When using

the on-chip reference, the power-up time is effectively the time

it takes to charge up the external capacitor on the REF_IN/REF_OUT

pin. This time is given by the equation:

Using an External Reference

When the AD7858 is powered up, the part is powered up from

one of two conditions. First, when the power supplies are ini-

tially powered up and, secondly, when the part is powered up

from either a hardware or software power-down (see last section).

When AV_DDand DV_DDare powered up, the AD7858 should be

left idle for approximately 32 ms (4 MHz CLK) to allow for the

autocalibration if a 10 nF cap is placed on the CAL pin, (see

Calibration section). During power-up the functionality of the

SLEEP pin is disabled, i.e., the part will not power down until

the end of the calibration if SLEEP is tied logic low. The auto-

calibration on power-up can be disabled if the CAL pin is tied to

t

_UP= 9 × R × C

where R ≅ 150 kΩ and C = external capacitor.

REV. B

–19–

AD7858/AD7858L

The recommended value of the external capacitor is 100 nF;

this gives a power-up time of approximately 135 ms before a

calibration is initiated and normal operation should commence.

10

AD7858 (4MHz CLK)

When C_REFis fully charged, the power-up time from a hardware

or software power-down reduces to 5 µs. This is because an

internal switch opens to provide a high impedance discharge

path for the reference capacitor during power-down—see Figure

23. An added advantage of the low charge leakage from the

reference capacitor during power-down is that even though the

reference is being powered down between conversions, the

reference capacitor holds the reference voltage to within

0.5 LSBs with throughput rates of 100 samples/second and

over with a full power-down between conversions. A high input

impedance op amp like the AD707 should be used to buffer this

reference capacitor if it is being used externally. Note, if the

AD7858 is left in its power-down state for more than 100 ms,

the charge on C_REFwill start to leak away and the power-up

time will increase. If this long power-up time is a problem, the

user can use a partial power-down for the last conversion so the

reference remains powered up.

1

AD7858L (1.8MHz CLK)

0.1

0.01

0

5

15

25

THROUGHPUT – kSPS

35

45

10

20

30

40

50

Figure 24. Power vs. Throughput Rate

CALIBRATION SECTION

Calibration Overview

The automatic calibration that is performed on power-up en-

sures that the calibration options covered in this section will not

be required in a significant amount of applications. The user

will not have to initiate a calibration unless the operating condi-

tions change (CLKIN frequency, analog input mode, reference

voltage, temperature, and supply voltages). The AD7858/

AD7858L have a number of calibration features that may be

required in some applications and there are a number of advan-

tages in performing these different types of calibration. First,

the internal errors in the ADC can be reduced significantly to

give superior dc performance, and secondly, system offset and

gain errors can be removed. This allows the user to remove

reference errors (whether it be internal or external reference)

and to make use of the full dynamic range of the AD7858/

AD7858L by adjusting the analog input range of the part for a

specific system.

SWITCH OPENS

DURING POWER-DOWN

AD7858

REF /REF

IN

OUT

ON-CHIP

REFERENCE

EXTERNAL

CAPACITOR

TO OTHER

CIRCUITRY

BUF

Figure 23. On-Chip Reference During Power-Down

POWER VS. THROUGHPUT RATE

The main advantage of a full power-down after a conversion is

that it significantly reduces the power consumption of the part

at lower throughput rates. When using this mode of operation,

the AD7858 is only powered up for the duration of the conver-

sion. If the power-up time of the AD7858 is taken to be 5 µs

and it is assumed that the current during power-up is 4 mA typ,

then power consumption as a function of throughput can easily

be calculated. The AD7858 has a conversion time of 4.6 µs

with a 4 MHz external clock. This means the AD7858 con-

sumes 4 mA typ, (or 12 mW typ V_DD= 3 V) for 9.6 µs in every

conversion cycle if the device is powered down at the end of a

conversion. If the throughput rate is 1 kSPS, the cycle time is

1000 µs and the average power dissipated during each cycle is

(9.6/1000) × (12 mW) = 115 µW. The graph, Figure 24, shows

the power consumption of the AD7858 as a function of through-

put. Table VII lists the power consumption for various through-

put rates.

There are two main calibration modes on the AD7858/AD7858L,

self-calibration and system calibration. There are various op-

tions in both self-calibration and system calibration as outlined

previously in Table IV. All the calibration functions can be

initiated by pulsing the CAL pin or by writing to the control

register and setting the STCAL bit to one. The timing diagrams

that follow involve using the CAL pin.

The duration of each of the different types of calibrations is

given in Table VIII for the AD7858 with a 4 MHz master clock.

These calibration times are master clock dependent. Therefore,

the calibrating times for the AD7858L (CLKIN = 1.8 MHz)

will be longer than those quoted in Table VIII.

Table VIII. Calibration Times (AD7858 with 4 MHz CLKIN)

Type of Self- or

Table VII. Power Consumption vs. Throughput

System Calibration

Time

Throughput Rate

Power

Full

Offset + Gain

Offset

Gain

31.25 ms

6.94 ms

3.47 ms

1 kSPS

10 kSPS

115 µW

1.15 mW

–20–

REV. B

AD7858/AD7858L

Automatic Calibration on Power-On

For the self- (gain + offset), self-offset, and self-gain calibrations

the BUSY line will be triggered high by the rising edge of the

CAL signal (or the end of the write to the control register if

calibration is initiated in software) and will stay high for the

full duration of the self-calibration. The length of time that

the BUSY is high will depend on the type of self-calibration

that is initiated. Typical figures are given in Table VIII. The

timing diagrams for the other self-calibration options will be

similar to that outlined in Figure 25.

The CAL pin has a 0.15 µA pull-up current source connected

to it internally to allow for an automatic full self-calibration on

power-on. A full self-calibration will be initiated on power-on if

a capacitor is connected from the CAL pin to DGND. The

internal current source connected to the CAL pin charges up

the external capacitor and the time required to charge the exter-

nal capacitor will depend on the size of the capacitor itself. This

time should be large enough to ensure that the internal refer-

ence is settled before the calibration is performed. A 33 nF

capacitor is sufficient to ensure that the internal reference has

settled (see Power-Up Times) before a calibration is initiated

taking into account trigger level and current source variations

on the CAL pin. However, if an external reference is being

used, this reference must have stabilized before the automatic

calibration is initiated (a larger capacitor on the CAL pin

should be used if the external reference has not settled when the

autocalibration is initiated). Once the capacitor on the CAL pin

has charged, the calibration will be performed which will take

32 ms (4 MHz CLKIN). Therefore the autocalibration should

be complete before operating the part. After calibration, the

part is accurate to the 12-bit level and the specifications quoted

on the data sheet apply. There will be no need to perform

another calibration unless the operating conditions change or

unless a system calibration is required.

t₁= 100ns MIN,

t₁₅= 2.5 t_CLKINMAX,

t_CAL= 125013 t_CLKIN

t₁

CAL (I/P)

t₁₅

BUSY (O/P)

t_CAL

Figure 25. Timing Diagram for Full Self-Calibration

System Calibration Description

System calibration allows the user to take out system errors

external to the AD7858/AD7858L as well as calibrate the errors

of the AD7858/AD7858L itself. The maximum calibration

range for the system offset errors is 5% of V_REFand for the

system gain errors is 2.5% of V_REF. This means that the maxi-

mum allowable system offset voltage applied between the

AIN(+) and AIN(–) pins for the calibration to adjust out this

error is 0.05 × V_REF(i.e., the AIN(+) can be 0.05 × V_REFabove

AIN(–) or 0.05 × V_REFbelow AIN(–)). For the System gain error

the maximum allowable system full-scale voltage that can be

applied between AIN(+) and AIN(–) for the calibration to

adjust out this error is V_REF0.025 × V_REF( i.e., the AIN(+)

above AIN(–)). If the system offset or system gain errors are

outside the ranges mentioned the system calibration algorithm

will reduce the errors as much as the trim range allows.

Self-Calibration Description

There are four different calibration options within the self-

calibration mode. First, there is a full self-calibration where the

DAC, internal gain, and internal offset errors are calibrated out.

Then, there is the (Gain + Offset) self-calibration which cali-

brates out the internal gain error and then the internal offset

errors. The internal DAC is not calibrated here. Finally, there

are the self-offset and self-gain calibrations which calibrate out

the internal offset errors and the internal gain errors respectively.

The internal capacitor DAC is calibrated by trimming each of

the capacitors in the DAC. It is the ratio of these capacitors to

each other that is critical, and so the calibration algorithm en-

sures that this ratio is at a specific value by the end of the cali-

bration routine. For the offset and gain there are two separate

capacitors, one of which is trimmed when an offset or gain

calibration is performed. Again, it is the ratio of these capacitors

to the capacitors in the DAC that is critical and the calibration

algorithm ensures that this ratio is at a specified value for both

the offset and gain calibrations.

Figures 26 through 28 illustrate why a specific type of system

calibration might be used. Figure 26 shows a system offset

calibration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be accounted for by a system offset calibration.

MAX SYSTEM FULL SCALE

The zero-scale error is adjusted for an offset calibration, and

the positive full-scale error is adjusted for a gain calibration.

IS ؎2.5% FROM V

REF

V

+ SYS OFFSET

REF

V

–1LSB

V

– 1LSB

REF

Self-Calibration Timing

REF

SYSTEM OFFSET

CALIBRATION

The diagram of Figure 25 shows the timing for a full self-

calibration. Here the BUSY line stays high for the full length of

the self-calibration. A self-calibration is initiated by bringing the

CAL pin low (which initiates an internal reset) and then high

again or by writing to the control register and setting the STCAL

bit to 1 (note that if the part is in a power-down mode the CAL pulse-

width must take account of the power-up time ). The BUSY line is

triggered high from the rising edge of CAL (or the end of the

write to the control register if calibration is initiated in soft-

ware), and BUSY will go low when the full self-calibration is

complete after a time t_CALas shown in Figure 25.

ANALOG

INPUT

ANALOG

INPUT

RANGE

SYS OFFSET

AGND

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ؎5% OF V

MAX SYSTEM OFFSET

IS ؎5% OF V

REF

Figure 26. System Offset Calibration

REV. B

–21–

AD7858/AD7858L

Figure 27 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for by a system gain calibration.

system (gain + offset) calibrations will be sufficient. If the sys-

tem errors are large (close to the specified limits of the calibra-

tion range) three system (gain + offset) calibrations may be

required to reduced the offset and gain errors to at least the 12-

bit level. There will never be any need to perform more than

three system (offset + gain) calibrations.

MAX SYSTEM FULL SCALE

The zero scale error is adjusted for an offset calibration and the

positive full-scale error is adjusted for a gain calibration.

IS ؎2.5% FROM V

REF

SYS F.S.

V

– 1LSB

V

– 1LSB

REF

System Calibration Timing

SYSTEM GAIN

CALIBRATION

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

The calibration timing diagram in Figure 29 is for a full system

calibration where the falling edge of CAL initiates an internal

reset before starting a calibration (note that if the part is in power-

down mode the CAL pulsewidth must take account of the power-up

time). If a full system calibration is to be performed in software

it is easier to perform separate gain and offset calibrations so

that the CONVST bit in the control register does not have to be

programmed in the middle of the system calibration sequence.

The rising edge of CAL starts calibration of the internal DAC

and causes the BUSY line to go high. If the control register is

set for a full system calibration, the CONVST must be used

also. The full-scale system voltage should be applied to the

analog input pins from the start of calibration. The BUSY line

will go low once the DAC and System Gain Calibration are

complete. Next the system offset voltage is applied to the AIN

pin for a minimum setup time (t_SETUP) of 100 ns before the

rising edge of the CONVST and remain until the BUSY signal

goes low. The rising edge of the CONVST starts the system

offset calibration section of the full system calibration and also

causes the BUSY signal to go high. The BUSY signal will go

low after a time t_CAL2when the calibration sequence is com-

plete. In some applications not all the input channels may be

used. In this case it may be useful to dedicate two input chan-

nels for the system calibration, one which has the system offset

voltage applied to it, and one which has the system full scale

voltage applied to it. When a system offset or gain calibration is

performed, the channel selected should correspond to the sys-

tem offset or system full-scale voltage channel.

AGND

Figure 27. System Gain Calibration

Finally in Figure 28 both the system offset and gain are ac-

counted for by the a system offset followed by a system gain

calibration. First the analog input range is shifted upwards by

the positive system offset and then the analog input range is

adjusted at the top end to account for the system full scale.

MAX SYSTEM FULL SCALE

IS ؎2.5% FROM V

MAX SYSTEM FULL SCALE

IS ؎2.5% FROM V

REF

V

+ SYS OFFSET

SYS F.S.

–1LSB

REF

V

REF

V

– 1LSB

REF

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

SYSTEM GAIN

CALIBRATION

SYS OFFSET

AGND

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ؎5% OF V

MAX SYSTEM OFFSET

IS ؎5% OF V

REF

Figure 28. System (Gain + Offset) Calibration

System Gain and Offset Interaction

The inherent architecture of the AD7858/AD7858L leads to an

interaction between the system offset and gain errors when a

system calibration is performed. Therefore, it is recommended

to perform the cycle of a system offset calibration followed by a

system gain calibration twice. Separate system offset and system

gain calibrations reduce the offset and gain errors to at least the

12-bit level. By performing a system offset CAL first and a

system gain calibration second, priority is given to reducing the

gain error to zero before reducing the offset error to zero. If the

system errors are small, a system offset calibration would be

performed, followed by a system gain calibration. If the system

errors are large (close to the specified limits of the calibration

range), this cycle would be repeated twice to ensure that the

offset and gain errors were reduced to at least the 12-bit level.

The advantage of doing separate system offset and system gain

calibrations is that the user has more control over when the

analog inputs need to be at the required levels, and the

CONVST signal does not have to be used.

The timing for a system (gain + offset) calibration is very similar

to that of Figure 29 the only difference being that the time t_CAL1

will be replaced by a shorter time of the order of t_CAL2as the

internal DAC will not be calibrated. The BUSY signal will

signify when the gain calibration is finished and when the part is

ready for the offset calibration.

t₁= 100ns MIN, t₁₄= 50/90ns MIN 5V/3V,

t₁₅= 2.5 t

MAX, t_CAL1= 111114 t

,

CLKIN

t_CAL2= 13899 t_CLKIN

t₁

CAL (I/P)

t₁₅

BUSY (O/P)

t_CAL2

t_CAL1

t₁₆

Alternatively, a system (gain + offset) calibration can be

performed. It is recommended to perform three system (gain +

offset) calibrations to reduce the offset and gain errors to the

12-bit level. For the system (gain + offset) calibration priority is

given to reducing the offset error to zero before reducing the

gain error to zero. Thus if the system errors are small then two

CONVST (I/P)

t_SETUP

V

OFFSET

AIN (I/P)

SYSTEM FULL SCALE

Figure 29. Timing Diagram for Full System Calibration

–22–

REV. B

AD7858/AD7858L

The timing diagram for a system offset or system gain calibra-

tion is shown in Figure 30. Here again the CAL is pulsed and

the rising edge of the CAL initiates the calibration sequence (or

the calibration can be initiated in software by writing to the

control register). The rising edge of the CAL causes the BUSY

line to go high and it will stay high until the calibration se-

quence is finished. The analog input should be set at the correct

level for a minimum setup time (t_SETUP) of 100 ns before the rising

edge of CAL and stay at the correct level until the BUSY signal

goes low.

Resetting the Serial Interface

When writing to the part via the DIN line there is the possibility

of writing data into the incorrect registers, such as the test regis-

ter for instance, or writing the incorrect data and corrupting the

serial interface. The SYNC pin acts as a reset. Bringing the

SYNC pin high resets the internal shift register. The first data

bit after the next SYNC falling edge will now be the first bit of a

new 16-bit transfer. It is also possible that the test register con-

tents were altered when the interface was lost. Therefore, once

the serial interface is reset it may be necessary to write the 16-bit

word 0100 0000 0000 0010 to restore the test register to its

default value. Now the part and serial interface are completely

reset. It is always useful to retain the ability to program the

SYNC line from a port of the µController/DSP to have the

ability to reset the serial interface.

t₁

CAL (I/P)

t₁₅

BUSY (O/P)

Table X summarizes the interface modes provided by the

AD7858/AD7858L. It also outlines the various µP/µC to which

the particular interface is suited.

t_CAL2

t_SETUP

V

OR V

SYSTEM OFFSET

AIN (I/P)

SYSTEM FULL SCALE

Interface Mode 1 may only be set by programming the control

register (see section on Control Register).

Figure 30. Timing Diagram for System Gain or System

Offset Calibration

Some of the more popular µProcessors, µControllers, and the

DSP machines that the AD7858/AD7858L will interface to

directly are mentioned here. This does not cover all µCs, µPs,

and DSPs. A more detailed timing description on each of the

interface modes follows.

SERIAL INTERFACE SUMMARY

Table IX details the two interface modes and the serial clock

edges from which the data is clocked out by the AD7858/

AD7858L (DOUT Edge) and that the data is latched in on

(DIN Edge).

Table X. Interface Mode Description

In both interface Modes 1 and 2 the SYNC is gated with the

SCLK. Thus the SYNC↓ may clock out the MSB of data. Sub-

sequent bits will be clocked out by the Serial Clock, SCLK. The

condition for the SYNC↓ clocking out the MSB of data is as

follows:

Interface

Mode

␮Processor/

␮Controller

Comment

1

8XC51

8XL51

PIC17C42

(2-Wire)

(DIN Is an Input/

Output Pin)

The falling edge of SYNC will clock out the MSB if the serial clock

is low when the SYNC goes low.

2

68HC11

68L11

68HC16

PIC16C64

ADSP21xx

DSP56000

DSP56001

DSP56002

DSP56L002

(3-Wire, SPI)

(Default Mode)

If this condition is not the case, the SCLK will clock out the

MSB. If a noncontinuous SCLK is used, it should idle high.

Table IX. SCLK Active Edges

Interface Mode

Edge

DOUT Edge

DIN

1, 2

SCLK↓

SCLK↑

REV. B

–23–

AD7858/AD7858L

DETAILED TIMING SECTION

Mode 1 (2-Wire 8051 Interface)

automatically revert back to an input after a time, t₁₄. Note that

a continuous SCLK shown by the dotted waveform in Figure 35

can be used provided that the SYNC is low for only 16 clock

pulses in each of the read and write cycles.

The read and writing takes place on the DIN line and the con-

version is initiated by pulsing the CONVST pin (note that in

every write cycle the 2/3 MODE bit must be set to 1). The

conversion may be started by setting the CONVST bit in the

control register to 1 instead of using the CONVST pin.

In Figure 32 the SYNC line is tied low permanently and this

results in a different timing arrangement. With SYNC tied low

permanently the DIN pin will never be three-stated. The 16th

rising edge of SCLK configures the DIN pin as an input or an

output as shown in the diagram. Here no more than 16 SCLK

pulses must occur for each of the read and write operations.

Below in Figure 31 and in Figure 32 are the timing diagrams for

Operating Mode 1 in Table X where we are in the 2-wire inter-

face mode. Here the DIN pin is used for both input and output

as shown. The SYNC input is level triggered active low and can

be pulsed (Figure 31) or can be constantly low (Figure 32).

If reading from and writing to the calibration registers in this

interface mode, all the selected calibration registers must be

read from or written to. The read and write operations cannot

be aborted. When reading from the calibration registers, the

DIN pin will remain as an output for the full duration of all the

calibration register read operations. When writing to the calibra-

tion registers, the DIN pin will remain as an input for the full

duration of all the calibration register write operations.

In Figure 31 the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK the DIN is con-

figured as an output. When the SYNC is taken high the DIN is

three-stated. Taking SYNC low disables the three-state on the

DIN pin and the first SCLK falling edge clocks out the first data

bit. Once the 16 clocks have been provided the DIN pin will

t₃= –0.4t_SCLKMIN (NONCONTINUOUS SCLK) ؎0.4t_SCLKns MIN/MAX (CONTINUOUS SCLK),

t₆= 75/115ns MAX (5V/3V), t₇= 40/60ns MIN (5V/3V), t₈= 20/30ns MIN (5V/3V)

POLARITY PIN LOGIC HIGH

SYNC (I/P)

t₁₁

t₃

t₁₁

t₃

1

16

1

16

SCLK (I/P)

t₅

t₁₄

t₇

t₈

t₆

t₁₂

t₆

DB15

DB0

DB15

DB0

DIN (I/O)

THREE-STATE

DATA WRITE

DATA READ

DIN BECOMES AN INPUT

DIN BECOMES AN OUTPUT

Figure 31. Timing Diagram for Read/Write Operation with DIN as an Input/Output

(i.e., Mode 1)

t₆= 75/115ns MAX (5V/3V), t₇= 40/60ns MIN (5V/3V), t₈= 20/30ns MIN (5V/3V),

t₁₃= 90/130ns MAX (5V/3V), t₁₄= 50/90ns MIN (5V/3V)

POLARITY PIN LOGIC HIGH

1

16

1

6

16

SCLK (I/P)

t₁₄

t₇

t₈

t₆

t₁₃

DB0

t₆

DB0

DIN (I/O)

DB15

DATA WRITE

DATA READ

DIN BECOMES AN INPUT

Figure 32. Timing Diagram for Read/Write Operation with DIN as an Input/Output

and SYNC Input Tied Low (i.e., Interface Mode 1)

–24–

REV. B

AD7858/AD7858L

Mode 2 (3-Wire SPI/QSPI Interface Mode)

This is the DEFAULT INTERFACE MODE.

SYNC going low disables the three-state on the DOUT pin.

The first falling edge of the SCLK after the SYNC going low

clocks out the first leading zero on the DOUT pin. The DOUT

pin is three-stated again a time t₁₂after the SYNC goes high.

With the DIN pin the data input has to be set up a time t₇be-

fore the SCLK rising edge as the part samples the input data on

the SCLK rising edge in this case. If resetting the interface is

required, the SYNC must be taken high and then low.

In Figure 33 below we have the timing diagram for interface

Mode 2 which is the SPI/QSPI interface mode. Here the SYNC

input is active low and may be pulsed or tied permanently low.

If SYNC is permanently low, 16 clock pulses must be applied to

the SCLK pin for the part to operate correctly, otherwise with a

pulsed SYNC input a continuous SCLK may be applied pro-

vided SYNC is low for only 16 SCLK cycles. In Figure 33 the

t₃= –0.4t_SCLKMIN (NONCONTINUOUS SCLK) ؎0.4t_SCLKns MIN/MAX (CONTINUOUS SCLK),

t₆= 75/115ns MAX (5V/3V), t₇= 40/60ns MIN (5V/3V), t₈= 20/30ns MIN (5V/3V),

t₁₁= 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4t_SCLKns MIN/MAX

(CONTINUOUS SCLK) (5V/3V)

POLARITY PIN LOGIC HIGH

SYNC (I/P)

t₁₁

t₃

t₉

SCLK (I/P)

1

2

3

4

5

6

16

t₁₀

t₅

t₁₂

t₆

DB12

t₆

THREE-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB11

t₈

DB10

DB0

t₇

DB15

t₈

DB14

DB13

DB12

DB11

DB0

Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation

with DIN Input, DOUT Output, and SYNC Input

REV. B

–25–

AD7858/AD7858L

CONFIGURING THE AD7858/AD7858L

than one conversion. The options of using a hardware (pulsing

the CONVST pin) or software (setting the CONVST bit to 1)

conversion start, and reading/writing during or after conversion

are shown in Figures 34 and 35. If the CONVST pin is never

used then it should be tied to DV_DDpermanently. Where refer-

ence is made to the BUSY bit equal to a Logic 0, to indicate the

end of conversion, the user in this case would poll the BUSY bit

in the status register.

The AD7858/AD7858L contains 14 on-chip registers which can

be accessed via the serial interface. In the majority of applications it

will not be necessary to access all of these registers. Here the

CLKIN signal is applied directly after power-on; the CLKIN

signal must be present to allow the part to perform a calibration.

This automatic calibration will be completed approximately 32 ms

after the AD7858 has powered up (4 MHz CLK).

For accessing the on-chip registers it is necessary to write to the

part. To change the channel from the default channel setting

the user will be required to write to the part. To enable Serial

Interface Mode 1 the user must also write to the part. Figure 34

and 35 outline flowcharts of how to configure the AD7858/

AD7858L Serial Interface Modes 1 and 2 respectively. The

continuous loops on all diagrams indicate the sequence for more

Interface Mode 1 Configuration

Figure 34 shows the flowchart for configuring the part in Inter-

face Mode 1. This mode of operation can only be enabled by

writing to the control register and setting the 2/3 MODE bit.

Reading and writing cannot take place simultaneously in this

mode as the DIN pin is used for both reading and writing.

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

?

1

INITIATE

CONVERSION

YES

IN

SOFTWARE

?

NO

APPLY SYNC (IF REQUIRED), SCLK, WRITE

TO CONTROL REGISTER SETTING CHANNEL

TWO-WIRE MODE

APPLY SYNC (IF REQUIRED), SCLK,

WRITE TO CONTROL REGISTER

SETTING CHANNEL AND TWO-WIRE MODE

WRITE

TO CONTROL REGISTER SETTING CONVST

BIT TO 1 (SEE NOTE)

PULSE CONVST PIN

READ

DATA

DURING

CONVERSION

?

YES

WAIT APPROX. 200ns AFTER

CONVST RISING EDGE OR AFTER END

OF CONTROL REGISTER WRITE

NO

WAIT FOR BUSY SIGNAL TO GO LOW

OR

WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED), SCLK, READ

PREVIOUS CONVERSION RESULT ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DIN PIN

NOTE:

TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A

CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS THE ACQUISITION TIME (2 t_CLKIN

)

MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE

WRITE THE RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT

CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.

Figure 34. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1

–26–

REV. B

AD7858/AD7858L

Interface Mode 2 Configuration

that no valid data is written to any of the registers. When using

the software conversion start and transferring data during con-

version Note 1 must be obeyed.

Figure 35 shows the flowchart for configuring the part in Inter-

face Mode 2. In this case the read and write operations take

place simultaneously via the serial port. Writing all 0s ensures

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

?

2

INITIATE

CONVERSION YES

IN

SOFTWARE

?

NO

TRANSFER

DATA DURING

CONVERSION

?

YES

PULSE CONVST PIN

APPLY SYNC (IF REQUIRED), SCLK, WRITE

TO CONTROL REGISTER SETTING CHANNEL,

(SEE NOTE 1)

NO

WRITE TO CONTROL REGISTER

APPLY SYNC (IF REQUIRED), SCLK, WRITE

TO CONTROL REGISTER SETTING CHANNEL

TRANSFER

YES

SETTING CONVST BIT TO 1,

READ PREVIOUS RESULT ON

DOUT PIN (SEE NOTES 1&2)

DATA DURING

CONVERSION

?

WRITE TO CONTROL REGISTER SETTING

CONVST BIT TO 1, READ

WAIT APPROX 200ns AFTER

CONVST RISING EDGE

NO

CURRENT CONVERSION RESULT

ON DOUT PIN (SEE NOTE 2)

WAIT FOR BUSY SIGNAL TO GO LOW

OR

WAIT FOR BUSY BIT = 0

WAIT FOR BUSY SIGNAL TO GO LOW

APPLY SYNC (IF REQUIRED), SCLK, READ

PREVIOUS CONVERSION RESULT ON DOUT

PIN, AND WRITE CHANNEL SELECTION

OR

WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED), SCLK,

READ CURRENT CONVERSION RESULT

ON DOUT PIN, AND WRITE CHANNEL

SELECTION

NOTES

¹WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL REGISTER

WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS

TIME CAN IT BE REPROGRAMMED TO 1 TO START THE NEXT CONVERSION.

²TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS

THE ACQUISITION TIME (2 t_CLKIN) MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE WRITE THE

RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.

Figure 35. Flowchart for Setting Up, Reading, and Writing in Interface Mode 2

REV. B

–27–

AD7858/AD7858L

OPTIONAL

4MHz/1.8MHz

MICROPROCESSOR INTERFACING

AD7858/AD7858L

CONVST

In many applications, the user may not require the facility of

writing to most of the on-chip registers. The only writing neces-

sary is to set the input channel configuration. After this the

CONVST is applied, a conversion is performed, and the result

may be read using the SCLK to clock out the data from the

output register on to the DOUT pin. At the same time a write

operation occurs and this may consist of all 0s where no data is

written to the part or may set a different input channel configu-

ration for the next conversion. The SCLK may be connected to

the CLKIN pin if the user does not want to have to provide

separate serial and master clocks. With this arrangement the

SYNC signal must be low for 16 SCLK cycles for the read and

write operations.

8XC51/L51

MASTER

CLKIN

P3.1

SCLK

SLAVE

P3.0

DIN

(INT0/P3.2)

BUSY

SYNC

OPTIONAL

Figure 37. 8XC51/PIC16C42 Interface

AD7858/AD7858L to 68HC11/16/L11/PIC16C42 Interface

Figure 38 shows the AD7858/AD7858L SPI/QSPI interface to

the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to

the AD7858/AD7858L when the supply is 3 V. The AD7858/

AD7858L is in Interface Mode 2. The SYNC line is not used

and is tied to DGND. The µController is configured as the mas-

ter, by setting the MSTR bit in the SPCR to 1, and provides the

serial clock on the SCK pin. For all the µControllers the CPOL

bit is set to 1 and for the 68HC11/16/L11 the CPHA bit is set to

1. The CLKIN and CONVST signals can be supplied from the

µController or from separate sources. The BUSY signal can be

used as an interrupt to tell the µController when the conversion

is finished, then the reading and writing can take place. If re-

quired the reading and writing can take place during conversion

and there will be no need for the BUSY signal in this case.

CONVST

CONVERSION START

4MHz/1.8MHz

MASTER CLOCK

CLKIN

SCLK

SYNC SIGNAL TO

GATE THE SCLK

AD7858/

AD7858L

SYNC

SERIAL DATA INPUT

DIN

SERIAL DATA

OUTPUT

DOUT

Figure 36. Simplified Interface Diagram

AD7858/AD7858L to 8XC51 Interface

Figure 37 shows the AD7858/AD7858L interface to the

8XC51. The 8XL51 is for interfacing to the AD7858/AD7858L

when the supply is at 3 V. The 8XC51 only runs at 5 V. The

8XC51 is in Mode 0 operation. This is a two-wire interface

consisting of the SCLK and the DIN which acts as a bidirec-

tional line. The SYNC is tied low. The BUSY line can be used

to give an interrupt driven system but this would not normally

be the case with the 8XC51. For the 8XC51 12 MHz version

the serial clock will run at a maximum of 1 MHz so the serial

interface of the AD7858/AD7858L will only be running at

1 MHz. The CLKIN signal must be provided separately to the

AD7858/AD7858L from a port line on the 8XC51 or from a

source other than the 8XC51. Here the SCLK cannot be tied to

the CLKIN as the SYNC is tied low permanently. The CONVST

signal can be provided from an external timer or conversion can

be started in software if required. The sequence of events would

typically be to write to the control register via the DIN line setting

a conversion start and the 2-wire interface mode (this would be

performed in two 8-bit writes), wait for the conversion to be

finished (4.6 µs with 4 MHz CLKIN), read the conversion result

data on the DIN line (this would be performed in two 8-bits

reads), and repeat the sequence. The maximum serial frequency

will be determined by the data access and hold times of the

8XC51 and the AD7858/AD7858L.

OPTIONAL

AD7858/AD7858L

CONVST

4MHz/1.8MHz

DV

DD

68HC11/L11/16

CLKIN

SYNC

SCLK

DOUT

SPI

SS

SLAVE

HC16, QSPI

OPTIONAL

SCK

MASTER

MISO

IRQ

BUSY

DIN

MOSI

Figure 38. 68HC11 and 68HC16 Interface

For the 68HC16 the word length should be set to 16 bits, and

the SS line should be tied to the SYNC pin for the QSPI inter-

face. The micro-sequencer and RAM associated with the

68HC16 QSPI port can be used to perform a number of read

and write operations, and store the conversion results in

memory, independent of the CPU. This is especially useful when

reading the conversion results from all eight channels consecu-

tively. The command section of the QSPI port RAM would be

programmed to perform a conversion on one channel, read the

conversion result, perform a conversion on the next channel,

read the conversion result, and so on until all eight conversion

results are stored into the QSPI RAM.

–28–

REV. B

AD7858/AD7858L

AD7858/AD7858L to DSP56000/1/2/L002 Interface

A typical sequence of events would be to write to the control

register via the DIN line setting a conversion start and at the

same time reading data from the previous conversion on the

DOUT line (both the read and write operations would each be

two 8-bit operations, one 16-bit operation for the 68HC16),

wait for the conversion to be finished (= 4.6 µs for AD7858

with 4 MHz CLKIN), and then repeat the sequence. The maxi-

mum serial frequency will be determined by the data access and

hold times of the µControllers and the AD7858/AD7858L.

Figure 40 shows the AD7858/AD7858L to DSP56000/1/2/

L002 interface. Here the DSP5600x is the master and the

AD7858 is the slave. The AD7858/AD7858L is in Interface

Mode 2. The DSP56L002 is used when the AD7858/AD7858L

is being operated at 3 V. The setting of the bits in the registers

of the DSP5600x would be for synchronous operation (SYN =

1), internal frame sync (SCD2 = 1), gated internal clock (GCK

= 1, SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0). Since

a gated clock is used here the SCLK cannot be tied to the CLKIN

of the AD7858/AD7858L. The SCLK from the DSP5600x

must be inverted before it is applied to the AD7858/AD7858L.

Again the data access and hold times of the DSP5600x and

the AD7858/AD7858L allows for a SCLK of 4 MHz/1.8 MHz.

AD7858/AD7858L to ADSP-21xx Interface

Figure 39 shows the AD7858/AD7858L interface to the ADSP-

21xx. The ADSP-21xx is the master and the AD7858/AD7858L

is the slave. The AD7858/AD7858L is in Interface Mode 2.

For the ADSP-21xx the bits in the serial port control register

should be set up as TFSR = RFSR = 1 (need a frame sync for

every transfer), SLEN = 15 (16-bit word length), TFSW =

RFSW = 1 (alternate framing mode for transmit and receive

operations), INVRFS = INVTFS = 1 (active low RFS and

TFS), IRFS = 0, ITFS = 1 (External RFS and internal TFS),

and ISCLK = 1 (internal serial clock). The CLKIN and

CONVST signals can be supplied from the ADSP-21xx or

from an external source. The serial clock from the ADSP-21xx

must be inverted before the SCLK pin of the AD7858/AD7858L.

This SCLK could also be used to drive the CLKIN input of the

AD7858/AD7858L. The BUSY signal indicates when the con-

version is finished and may not be required. The data access

and hold times of the ADSP-21xx and the AD7858/AD7858L

allow for a serial clock of 4 MHz/1.8 MHz at 5 V and 3.3 MHz/

1.8 MHz at 3 V supplies.

OPTIONAL

AD7858/AD7858L

CONVST

4MHz/1.8MHz

DSP56000/1/2/L002

CLKIN

SCK

SRD

SC2

SCLK

DOUT

SYNC

SLAVE

MASTER

OPTIONAL

IRQ

BUSY

DIN

STD

Figure 40. DSP56000/1/2 Interface

OPTIONAL

AD7858/AD7858L

CONVST

4MHz/1.8MHz

CLKIN

SCLK

DOUT

SYNC

ADSP-21xx

SCK

DR

RFS

TFS

IRQ

MASTER

SLAVE

OPTIONAL

BUSY

DIN

DT

Figure 39. ADSP-21xx Interface

REV. B

–29–

AD7858/AD7858L

APPLICATION HINTS

Grounding and Layout

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum in parallel with 0.1 µF ca-

pacitors to AGND. All digital supplies should have a 0.1 µF

disc ceramic capacitor to AGND. To achieve the best from

these decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. In

systems where a common supply voltage is used to drive both

the AV_DDand DV_DDof the AD7858/AD7858L, it is recom-

mended that the system’s AV_DDsupply be used. In this case

there should be a 10 Ω resistor between the AV_DDpin and

DV_DDpin. This supply should have the recommended analog

supply decoupling capacitors between the AV_DDpin of the

AD7858/AD7858L and AGND and the recommended digital

supply decoupling capacitor between the DV_DDpin of the

AD7858/AD7858L and DGND.

The analog and digital supplies to the AD7858/AD7858L are

independent and separately pinned out to minimize coupling

between the analog and digital sections of the device. The part

has very good immunity to noise on the power supplies as can

be seen by the PSRR vs. Frequency graph. However, care

should still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7858/AD7858L

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. This facili-

tates the use of ground planes that can be separated easily. A

minimum etch technique is generally best for ground planes as

it gives the best shielding. Digital and analog ground planes

should only be joined in one place. If the AD7858/AD7858L is

the only device requiring an AGND to DGND connection,

then the ground planes should be connected at the AGND and

DGND pins of the AD7858/AD7858L. If the AD7858/

AD7858L is in a system where multiple devices require AGND

to DGND connections, the connection should still be made at

one point only, a star ground point which should be established

as close as possible to the AD7858/AD7858L.

Evaluating the AD7858/AD7858L Performance

The recommended layout for the AD7858/AD7858L is out-

lined in the evaluation board for the AD7858/AD7858L. The

evaluation board package includes a fully assembled and tested

evaluation board, documentation, and software for controlling

the board from the PC via the EVAL-CONTROL BOARD.

The EVAL-CONTROL BOARD can be used in conjunction

with the AD7858/AD7858L Evaluation board, as well as many

other Analog Devices evaluation boards ending in the CB desig-

nator, to demonstrate/evaluate the ac and dc performance of the

AD7858/AD7858L.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7858/AD7858L to avoid noise coupling.

The power supply lines to the AD7858/AD7858L should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board,

and clock signals should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on oppo-

site sides of the board should run at right angles to each other.

This will reduce the effects of feedthrough through the board. A

microstrip technique is by far the best but is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground planes while signals are

placed on the solder side.

The software allows the user to perform ac (fast Fourier trans-

form) and dc (histogram of codes) tests on the AD7858/

AD7858L. It also gives full access to all the AD7858/AD7858L

on-chip registers allowing for various calibration and power-

down options to be programmed.

AD785x Family

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD7853 – Single Channel Serial

AD7854 – Single Channel Parallel

AD7858 – Eight Channel Serial

AD7859 – Eight Channel Parallel

–30–

REV. B

AD7858/AD7858L

PAGE INDEX

Topic

Page No.

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

TYPICAL TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ON-CHIP REGISTERS

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 21

Self-Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System Calibration Description . . . . . . . . . . . . . . . . . . . . 21

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22

System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22

SERIAL INTERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23

Resetting The Serial Interface . . . . . . . . . . . . . . . . . . . . . 23

DETAILED TIMING SECTION

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24

Mode 2 (3-Wire SPI/QSPI Interface) . . . . . . . . . . . . . . . . 25

CONFIGURING THE AD7858/AD7858L . . . . . . . . . . . . 26

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 26

Interface Mode 2 Configuration . . . . . . . . . . . . . . . . . . . . 27

MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 28

AD7858/AD7858L–8XC51 Interface . . . . . . . . . . . . . . . 28

AD7858/AD7858L–68HC11/16/L11/PIC16C42

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9

CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CALIBRATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 13

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 13

Writing to/Reading from the Calibration Registers . . . . . . 13

Adjusting the Offset Calibration Registers . . . . . . . . . . . . 14

Adjusting the Gain Calibration Register . . . . . . . . . . . . . . 14

CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 15

CONVERTER DETAILS . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . 15

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REFERENCE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PERFORMANCE CURVES . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-DOWN OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-UP TIMES

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AD7858/AD7858L–ADSP-21xx Interface . . . . . . . . . . . . 29

AD7858/AD7858L–DSP56000/1/2/L002 Interface . . . . . 29

APPLICATION HINTS

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Evaluating the AD7858/AD7858L Performance . . . . . . . 30

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32

TABLE INDEX

#

Title

Page No.

Table I.

Table II.

Write Register Addressing . . . . . . . . . . . . . . . . . 9

Read Register Addressing . . . . . . . . . . . . . . . . . 9

Table III. Channel Selection . . . . . . . . . . . . . . . . . . . . . . 11

Table IV.

Table V.

Table VI.

Calibration Selection . . . . . . . . . . . . . . . . . . . . 11

Calibration Register Addressing . . . . . . . . . . . 13

Power Management Options . . . . . . . . . . . . . . 19

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19

POWER VS. THROUGHPUT RATE . . . . . . . . . . . . . . . . 20

CALIBRATION SECTION

Table VII. Power Consumption vs. Throughput . . . . . . . 20

Table VIII. Calibration Times (AD7858 with 4 MHz

CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table IX. SCLK Active Edges . . . . . . . . . . . . . . . . . . . . . 23

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 21

Table X.

Interface Mode Description . . . . . . . . . . . . . . . 23

REV. B

–31–

AD7858/AD7858L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Plastic DIP (N-24)

1.228 (31.19)

1.226 (31.14)

24

1

13

0.260 ؎0.001

(6.61 ؎0.03)

12

0.32 (8.128)

0.30 (7.62)

PIN 1

0.130 (3.30)

0.128 (3.25)

15؇

0

0.011 (0.28)

0.009 (0.23)

0.02 (0.5)

0.016 (0.41)

SEATING

PLANE

0.11 (2.79) 0.07 (1.78)

0.09 (2.28) 0.05 (1.27)

NOTES

1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH.

2. PLASTIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

24-Lead Small Outline Package (R-24)

0.608 (15.45)

0.596 (15.13)

24

1

13

12

0.096 (2.44)

0.089 (2.26)

PIN 1

0.03 (0.76)

0.02 (0.51)

0.042 (1.067)

0.018 (0.447)

6؇

0؇

0.05

(1.27)

BSC

0.019 (0.49)

0.014 (0.35)

0.01 (0.254)

0.006 (0.15)

SEATING

PLANE

0.013 (0.32)

0.009 (0.23)

NOTES

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

24-Lead Shrink Small Outline Package (RS-24)

0.328 (8.33)

0.318 (8.08)

24

13

12

1

0.07 (1.78)

PIN 1

0.066 (1.67)

8؇

0؇

0.037 (0.94)

0.022 (0.559)

0.015 (0.38)

0.010 (0.25)

0.0256

(0.65)

BSC

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

NOTES

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

–32–

REV. B


型号：	AD7858_15
厂家：	ADI
描述：	3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC
文件：	总32页 (文件大小：306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7858_15 [ADI]

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