AD7870 [ADI]
LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs; LC2MOS完成， 12位， 100千赫采样ADC
| 型号： | AD7870 |
| 厂家： | 
ADI |
| 描述： | LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs |
| 文件： | 总20页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Complete, 12-Bit, 100 kHz, Sampling ADCs
AD7870/AD7875/AD7876
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete Monolithic 12-Bit ADC w ith:
2 s Track/ Hold Am plifier
8 s A/ D Converter
On-Chip Reference
Laser-Trim m ed Clock
Parallel, Byte and Serial Digital Interface
72 dB SNR at 10 kHz Input Frequency
(AD7870, AD7875)
57 ns Data Access Tim e
Low Pow er: –60 m W typ
Variety of Input Ranges:
؎3 V for AD7870
0 V to +5 V for AD7875
؎10 V for AD7876
GENERAL D ESCRIP TIO N
T he AD7870/AD7875/AD7876 is a fast, complete, 12-bit A/D
converter. It consists of a track/hold amplifier, 8 µs successive-
approximation ADC, 3 V buried Zener reference and versatile
interface logic. T he ADC features a self-contained internal
clock which is laser trimmed to guarantee accurate control of
conversion time. No external clock timing components are re-
quired; the on-chip clock may he overridden by an external
clock if required.
P RO D UCT H IGH LIGH TS
1. Complete 12-Bit ADC on a Chip.
T he AD7870/AD7875/AD7876 provides all the functions
necessary for analog-to-digital conversion and combines a
12-bit ADC with internal clock, track/hold amplifier and
reference on a single chip.
2. Dynamic Specifications for DSP Users.
T he parts offer a choice of three data output formats: a single,
parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus ac-
cess times and standard control inputs ensure easy interfacing to
modern microprocessors and digital signal processors.
T he AD7870 and AD7875 are fully specified and tested for
ac parameters, including signal-to-noise ratio, harmonic dis-
tortion and intermodulation distortion.
3. Fast Microprocessor Interface.
All parts operate from ±5 V power supplies. T he AD7870 and
AD7876 accept input signal ranges of ±3 V and ±10 V, respec-
tively, while the AD7875 accepts a unipolar 0 V to +5 V input
range. T he parts can convert full power signals up to 50 kHz.
Data access times of 57 ns make the parts compatible with
modern 8- and 16-bit microprocessors and digital signal pro-
cessors. Key digital timing parameters are tested and guaran-
teed over the full operating temperature range.
T he AD7870/AD7875/AD7876 feature dc accuracy specifica-
tions such as linearity, full-scale and offset error. In addition,
the AD7870 and AD7875 are fully specified for dynamic perfor-
mance parameters including distortion and signal-to-noise ratio.
T he parts are available in a 24-pin, 0.3 inch-wide, plastic or her-
metic dual-in-line package (DIP). T he AD7870 and AD7875
are available in a 28-pin plastic leaded chip carrier (PLCC),
while the AD7876 is available and in a 24-pin small outline
(SOIC) package.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = +5 V ؎ 5%, V = –5 V ؎ 5%,
A6ND = DGND = 0 V, fCLK = 2.5 MHz external, unless otherwise stated. All Specifications T to Tmax unless otherwise noted.)
AD7870/AD7875/AD7876–SPECIFICATIONS
DD
SS
min
AD 7870
P aram eter
J, Al K, Bl L, Cl Sl
Tl
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal to Noise Ratio3 (SNR)
@ +25°C
T MIN to T MAX
T otal Harmonic Distortion (T HD)
70
70
–80
70
70
–80
72
71
–80
69
69
–78
69
69
–78
dB min
dB min
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically –86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Peak Harmonic or Spurious Noise
–80
–80
–80
–78
–78
dB max
T ypically –86 dB for 0 < VIN < 50 kHz
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
–80
–80
2
–80
–80
2
–80
–80
2
–78
–78
2
–78
–78
2
dB max
dB max
µs max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
T rack/Hold Acquisition T ime
DC ACCURACY
Resolution
12
12
12
12
12
12
12
Bits
Minimum Resolution for which
No Missing Codes are Guaranteed
Integral Nonlinearity
12
±1/2
12
12
Bits
±1/2
±1
±1
±5
±5
±5
±1/4 ±1/2
±1/2
±1
±5
±5
±5
±1/2
±1
±1
±5
±5
±5
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
±5
±5
±5
±5
±5
±5
Positive Full-Scale Error4
Negative Full-Scale Error4
ANALOG INPUT
Input Voltage Range
Input Current
±3
±3
±3
±3
±3
Volts
µA max
±500 ±500
±500 ±500 ±500
REFERENCE OUT PUT
REF OUT @ +25°C
2.99
3.01
±60
2.99
3.01
±60
±1
2.99 2.99
3.01 3.01
±35 ±60
2.99
3.01
±35
±1
V min
V max
ppm/°C max
mV max
REF OUT T empco
Reference Load Sensitivity (∆REF OUT /∆I) ±1
±1
±1
Reference Load Current Change (0–500 µA)
Reference Load Should Not Be Changed
During Conversion.
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10 ±10
±10 ±10
2.4
0.8
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to VDD
V max
µA max
µA max
pF max
Input Current (12/8/CLK Input Only)
5
Input Capacitance, CIN
10
10
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
4.0
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
Floating-State Output Capacitance5
±10
15
±10
15
±10 ±10
±10
15
µA max
pF max
15
15
CONVERSION T IME
External Clock (fCLK = 2.5 MHz)
Internal Clock
8
7/9
8
7/9
8
7/9
8
7/9
8
7/9
µs max
µs min/µs max
POWER REQUIREMENT S
VDD
VSS
IDD
ISS
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
V nom
V nom
mA max
mA max
mW max
±5% for Specified Performance
±5% for Specified Performance
T ypically 8 mA
T ypically 4 mA
T ypically 60 mW
Power Dissipation
95
95
95
95
95
NOT ES
1T emperature ranges are as follows: J, K, L Versions; 0°C to +70°C: A, B, C Versions; –25°C to +85°C: S, T Versions; –55°C to +125°C.
2VIN (pk-pk) = ±3 V.
3SNR calculation includes distortion and noise components.
4Measured with respect to internal reference and includes bipolar offset error.
5Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
AD7870/AD7875/AD7876
AD 7875/AD 7876
P aram eter
K, B1
L, C1
T1
Units
Test Conditions/Com m ents
DC ACCURACY
Resolution
12
12
12
Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity @ +25°C
T MIN to T MAX (AD7875 Only)
T MIN to T MAX (AD7876 Only)
Differential Nonlinearity
Unipolar Offset Error (AD7875 Only)
Bipolar Zero Error (AD7876 Only)
Full-Scale Error at +25°C2
Full-Scale T C2
12
±1
±1
±1
±1
±5
±6
±8
±60
2
12
±1/2
±1
±1/2
±1
±5
±2
±8
±35
2
12
±1
±1
±1
Bits
LSB max
LSB max
LSB max
±1.5/–1.0 LSB max
±5
±6
±8
±60
2
LSB max
LSB max
LSB max
ppm/°C max
µs max
T ypical Full-Scale Error Is ±1 LSB
T ypical T C is ±20 ppm/°C
T rack/Hold Acquisition T ime
DYNAMIC PERFORMANCE3 (AD7875 ONLY)
Signal-to-Noise Ratio4 (SNR)
@ +25°C
T MIN to T MAX
T otal Harmonic Distortion (T HD)
70
70
–80
72
71
–80
69
69
–78
dB min
dB min
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically –86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Peak Harmonic or Spurious Noise
–80
–80
–78
dB max
T ypically –86 dB for 0 < VIN < 50 kHz
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
–80
–80
–80
–80
–78
–78
dB max
dB max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
ANALOG INPUT
AD7875 Input Voltage Range
AD7875 Input Current
AD7876 Input Voltage Range
AD7876 Input Current
0 to +5 0 to +5 0 to +5
Volts
µA max
Volts
500
500
500
±10
±600
±10
±600
±10
±600
µA max
REFERENCE OUT PUT
REF OUT @ +25°C
2.99
3.01
±60
–1
2.99
3.01
±35
–1
2.99
3.01
±60
–1
V min
V max
ppm/°C max
mV max
REF OUT T empco
Reference Load Sensitivity (∆REF OUT /∆I)
T ypical T empco Is ±20 ppm/°C
Reference Load Current Change (0 µA–500 µA)
Reference Load Should Not Be Changed
During Conversion.
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to VDD
V max
µA max
µA max
pF max
Input Current (12/8/CLK Input Only)
5
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
Floating-State Output Capacitance5
10
15
10
15
10
15
µA max
pF max
CONVERSION T IME
External Clock (fCLK = 2.5 MHz)
Internal Clock
8
7/9
8
7/9
8
7/9
µs max
µs min/µs max
POWER REQUIREMENT S
NOT ES
As per AD7870
1T emperature ranges are as follows: AD7875: K, L Versions, 0 °C to +70°C; B, C Versions, –40°C to +85°C; T Version, –55°C to +125°C. AD7876: B, C Versions,
–40°C to +85°C; T Version, –55°C to +125°C.
2Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out.
Full-scale error refers to both positive and negative full-scale error for the AD7876.
3Dynamic performance parameters are not tested on the AD7876 but these are typically the same as for the AD7875.
4SNR calculation includes distortion and noise components.
5Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
AD7870/AD7875/AD7876
1, 2
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V. See Figures 9, 10, 11 and 12.)
TIMING CHARACTERISTICS
DD
SS
Lim it at TMIN, TMAX
Lim it at TMIN, TMAX
(S, T Versions)
P aram eter
(J, K, L, A, B, C Versions)
Units
Conditions/Com m ents
t1
t2
t3
t4
t53
t64
t7
50
0
60
0
70
57
5
50
0
50
0
75
0
70
70
5
50
0
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
CONVST Pulse Width
CS to RD Setup T ime (Mode 1)
RD Pulse Width
CS to RD Hold T ime (Mode 1)
RD to INT Delay
Data Access T ime after RD
Bus Relinquish T ime after RD
t8
t9
t10
t11
t12
t13
HBEN to RD Setup T ime
HBEN to RD Hold T ime
SSTRB to SCLK Falling Edge Setup T ime
SCLK Cycle T ime
SCLK to Valid Data Delay. CL = 35 pF
SCLK Rising Edge to SSTRB
0
0
100
370
135
20
100
10
100
60
120
200
0
100
370
150
20
100
10
100
60
120
200
0
5
6
t14
Bus Relinquish T ime after SCLK
t15
t16
t17
t18
t19
t20
CS to RD Setup T ime (Mode 2)
CS to BUSY Propagation Delay
Data Setup T ime Prior to BUSY
CS to RD Hold T ime (Mode 2)
HBEN to CS Setup T ime
0
0
0
0
HBEN to CS Hold T ime
NOT ES
1T iming specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are
specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on SDAT A and SSTRB and a 2 kΩ pull-up on SCLK. T he capacitance on all three outputs is 35 pF.
3t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
5SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6SDAT A will drive higher capacitive loads but this will add to t 12 since it increases the external RC time constant (4.7 kΩʈCL) and hence the time to reach 2.4 V.
Specifications subject to chance without notice.
ABSO LUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Digital Outputs to DGND . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating T emperature Range
Commercial (J, K, L Versions – AD7870) . . . 0°C to +70°C
a. High-Z to VOH
b. High-Z to VOL
Commercial (K, L Versions – AD7875) . . . . . 0°C to +70°C
Industrial (A, B, C Versions – AD7870) . . . . –25°C to +85°C
Industrial (B, C Versions – AD7875/AD7876)
Figure 1. Load Circuits for Access Tim e
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7870/AD7875/AD7876 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
AD7870/AD7875/AD7876
AD 7870 O RD ERING GUID E
Integral
Tem perature
Range
VIN Voltage
Range (V)
SNR
(dBs)
Nonlinearity P ackage
(LSB)
Model1, 2
O ption3
AD7870JN
AD7870KN
AD7870LN
AD7870JP
AD7870KP
AD7870LP
AD7870AQ
AD7870BQ
AD7870CQ
AD7870SQ4
AD7870T Q4
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
±3
±3
±3
±3
±3
±3
±3
±3
±3
±3
±3
70 min
70 min
72 min
70 min
70 min
72 min
70 min
70 min
72 min
70 min
70 min
±1/2 typ
±1 max
±1/2 max
±1/2 typ
±1 max
±1/2 max
±1/2 typ
±1 max
±1/2 max
±1/2 typ
±1 max
N-24
N-24
N-24
P-28A
P-28A
P-28A
Q-24
Q-24
Q-24
Q-24
Q-24
2
NOT ES
1To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet.
2Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.
3N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.
4Available to /883B processing only.
AD 7875 O RD ERING GUID E
Integral
Tem perature
Range
VIN Voltage
Range (V)
SNR
(dBs)
Nonlinearity P ackage
(LSB)
Model1, 2
O ption3
AD7875KN
AD7875LN
AD7875KP
AD7875LP
AD7875BQ
AD7875CQ
AD7875T Q4
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
0 to +5
70 min
72 min
70 min
72 min
70 min
72 min
70 min
±1 max
±1/2 max
±1 max
±1/2 max
±1 max
±1/2 max
±1 max
N-24
N-24
P-28A
P-28A
Q-24
Q-24
Q-24
NOT ES
1T o order MIL-STD-883, Class B. processed parts, add /883B to part number. Contact local sales office for military data sheet.
2Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.
3N = Narrow Plastic DlP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.
4Available to /883B processing only.
AD 7876 O RD ERING GUID E
Integral
Tem perature
Range
VIN Voltage
Range (V)
Nonlinearity
(LSB)
P ackage
O ption2
Model1
AD7876BN
AD7876CN
AD7876BR
AD7876CR
AD7876BQ
AD7876CQ
AD7876T Q3
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
±10
±10
±10
±10
±10
±10
±10
±1 max
±1/2 max
±1 max
±1/2 max
±1 max
±1/2 max
±1 max
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
NOT ES
1To order MIL-STD-883, Class B, processed parts, add /883B to the part number. Contact local sales office for military data sheet.
2N = Narrow Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
3Available to /883B processing only.
REV. B
–5–
AD7870/AD7875/AD7876
P IN FUNCTIO N D ESCRIP TIO N
D IP
P in
P in No. Mnem onic
Function
1
2
3
RD
BUSY/INT
CLK
Read. Active low logic input. T his input is used in conjunction with CS low to enable the data outputs.
Busy/Interrupt, Active low logic output indicating converter status. See timing diagrams.
Clock input. An external T T L-compatible clock may be applied to this input pin. Alternatively, tying this pin to
VSS enables the internal laser-trimmed clock oscillator.
4
DB11/HBEN Data Bit 11 (MSB)/High Byte Enable. T he function of this pin is dependent on the state of the 12/8/CLK input (see
below). When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin
becomes the HBEN logic input HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DB0/DB8
become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see T able I).
5
6
DB10/SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an
active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 kΩ pull-up
resistor is required on SSTRB.
DB9/SCLK
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated
serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at –5 V, then SCLK
runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an
open-drain output and requires an external 2 kΩ pull-up resistor.
7
DB8/SDAT A Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDAT A is an open-
drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data is valid on the fall-
ing edge of SCLK while SSTRB is low. An external 4.7 kΩ pull-up resistor is required on SDAT A.
8–11
DB7/LOW–
DB4/LOW
T hree-state data outputs controlled by CS and RD. T heir function depends on the 12/8/CLK and HBEN inputs.
With 12/8/CLK high, they are always DB7–DB4. With 12/8/CLK low or –5 V, their function is controlled by HBEN
(see T able I).
12
DGND
Digital Ground. Ground reference for digital circuitry.
13–16
DB3/DB11–
DB0/DB8
T hree-state data outputs which are controlled by CS and RD. T heir function depends on the 12/8/CLK and HBEN
inputs. With 12/8/CLK high, they are always DB3–DB0. With 12/8/CLK low or –5 V, their function is controlled by
HBEN (see T able I).
Table I. O utput D ata for Byte Inter facing
HBEN
HIGH
LOW
DB7/LOW DB6/LOW DB5/LOW DB4/LOW DB3/DB11
DB2/DB10 DB1/DB9 DB0/DB8
LOW
DB7
LOW
DB6
LOW
DB5
LOW
DB4
DB11(MSB)
DB3
DB10
DB2
DB9
DB1
DB8
DB0 (LSB)
17
18
19
20
21
22
VDD
Positive Supply, +5 V ± 5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
AGND
REF OUT
VIN
Voltage Reference Output. T he internal 3 V reference is provided at this pin. T he external load capability is 500 µA.
Analog Input. T he analog input range is ±3 V for the AD7870, ±10 V for the AD7876 and 0 V to +5 V for the AD7875.
Negative Supply, –5 V ± 5%.
VSS
12/8/CLK
T hree Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for-
mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous.
With this pin at –5 V, either byte or serial data is again available but SCLK is now continuous.
23
24
CONVST
CS
Convert Start. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.
T his input is asynchronous to the CLK input.
Chip Select. Active low logic input. T he device is selected when this input is active. With CONVST tied low, a new
conversion is initiated when CS goes low.
P IN CO NFIGURATIO NS1
D IP and SO IC 2
P LCC 2
1PIN CONFIGURATIONS ARE THE SAME FOR
THE AD7875 AND AD7876.
2THE AD7870 AND AD7875 ARE AVAILABLE IN
DIP AND PLCC; THE AD7870A IS AVAILABLE IN
PLASTIC DIP; THE AD7875 AND AD7876 ARE
AVAILABLE IN SOIC AND DIP.
REV. B
–6–
AD7870/AD7875/AD7876
CO NVERTER D ETAILS
to the conversion time plus the track/hold amplifier
acquisition time. For a 2.5 MH z input clock the throughput
rate is 10 µs max.
T he AD7870/AD7875/AD7876 is a complete 12-bit A/D con-
verter, requiring no external components apart from power
supply decoupling capacitors. It is comprised of a 12-bit suc-
cessive approximation ADC based on a fast settling voltage
output DAC, a high speed comparator and SAR, a track/hold
amplifier, a 3 V buried Zener reference, a clock oscillator and
control logic.
T he operation of the track/hold is essentially transparent to the
user. T he track/hold amplifier goes from its tracking mode to its
hold mode at the start of conversion. If the CONVST input is
used to start conversion then the track to hold transition occurs
on the rising edge of CONVST. If CS starts conversion, this
transition occurs on the falling edge of CS.
INTERNAL REFERENCE
T he AD7870/AD7875/AD7876 has an on-chip temperature
compensated buried Zener reference that is factory trimmed to
3 V ±10 mV. Internally it provides both the DAC reference
and the dc bias required for bipolar operation (AD7870 and
AD7876). T he reference output is available (REF OUT ) and
capable of providing up to 500 µA to an external load.
2
ANALO G INP UT
T he three parts differ from each other in the analog input volt-
age range that they can handle. T he AD7870 accepts ±3 V
input signals, the AD7876 accepts a ±10 V input range, while
the input range for the AD7875 is 0 V to +5 V.
Figure 5a shows the AD7870 analog input. T he analog input
range is ±3 V into an input resistance of typically 15 kΩ. T he
designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS–3/2 LSBs). T he output code is twos complement binary
with 1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. T he ideal input/
output transfer function is shown in Figure 6.
T he maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the ADC, it should be decoupled with a 200 Ω
resistor in series with a parallel combination of a 10 µF tanta-
lum capacitor and a 0.1 µF ceramic capacitor. These decoupling
components are required to remove voltage spikes caused by
the ADC’s internal operation.
Figure 5a. AD7870 Analog Input
Figure 3. Reference Circuit
T he AD7876 analog input structure is shown in Figure 5b. T he
analog input range is ±10 V into an input resistance of typically
33 kΩ. As before, the designed code transitions occur midway
between successive integer LSB values. T he output code is 2s
complement with 1 LSB = FS/4096 = 20 V/4096 = 4.88 mV.
T he ideal input/output transfer function is shown in Figure 6.
T he reference output voltage is 3 V. For applications using the
AD7875 or AD7876, a 5 V or 10 V reference may be required.
Figure 4 shows how to scale the 3 V REF OUT voltage to pro-
vide either a 5 V or 10 V external reference.
Figure 4. Generating a 5 V or 10 V Reference
TRACK-AND -H O LD AMP LIFIER
The track-and-hold amplifier on the analog input of the AD7870/
AD7875/AD7876 allows the ADC to accurately convert input
frequencies to 12-bit accuracy. T he input bandwidth of the
track/hold amplifier is much greater than the Nyquist rate of the
ADC even when the ADC is operated at its maximum through-
put rate. T he 0.1 dB cutoff frequency occurs typically at 500
kHz. The track/hold amplifier acquires an input signal to 12-bit
accuracy in less than 2 µs. T he overall throughput rate is equal
Figure 5b. AD7876 Analog Input
Figure 5c shows the analog input for the AD7875. T he input
range is 0 V to +5 V into an input resistance of typically 25 kΩ.
Once again, the designed code transitions occur midway
between successive integer LSB values. T he output code is
REV. B
–7–
AD7870/AD7875/AD7876
straight binary with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV.
T he ideal input/output transfer function is shown in Figure 7.
input voltage is 1/2 LSB below ground. T he trim procedure is as
follows: apply a voltage of –0.73 mV(–1/2 LSB) at V1 in Figure
8 and adjust the op amp offset voltage until the ADC output
code flickers between 1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full-scale) or the last code transition (ADC posi-
tive full scale). T he trim procedures for both cases are as follows
(see Figure 8).
Figure 5c. AD7875 Analog Input
Figure 8. Offset and Full-Scale Adjust Circuit
P ositive Full-Scale Adjust
Apply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Figure 6. AD7870/AD7876 Transfer Function
Negative Full-Scale Adjust
Apply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 1000 0000
0000 and 1000 0000 0001.
O FFSET AND FULL-SCALE AD JUSTMENT—AD 7876
T he offset and full-scale adjustment for the AD7876 is similar
to that just outlined for the AD7870. T he trim procedure, for
those applications that do require adjustment, is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at V1 and adjust the op
amp offset voltage until the ADC output code flickers between
1111 1111 1111 and 0000 0000 0000. Full-scale error can be
adjusted at either the first code transition (ADC negative full
scale) or the last code transition (ADC positive full scale). T he
trim procedure for both case is as follows (see Figure 8):
Figure 7. AD7875 Transfer Function
P ositive Full-Scale Adjust
O FFSET AND FULL-SCALE AD JUSTMENT—AD 7870
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal span the full analog input dynamic range. In such applica-
tions, offset and full-scale error will have to be adjusted to zero.
Apply a voltage of 9.9927 V (FS/2 –3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9976 V (FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
Where adjustment is required, offset error must be adjusted be-
fore full-scale error. T his is achieved by trimming the offset of
the op amp driving the analog input of the AD7870 while the
REV. B
–8–
AD7870/AD7875/AD7876
O FFSET AND FULL-SCALE AD JUSTMENT—AD 7875
Similar to the AD7870, most of the DSP applications in which
the AD7875 will be used will not require offset and full-scale
adjustment. For applications that do require adjustment, offset
error must be adjusted before full-scale (gain) error. T his is
achieved by applying an input voltage of 0.61 mV (1/2 LSB) to
V1 in Figure 8 and adjusting the op amp offset voltage until the
ADC output code flickers between 0000 0000 0000 and 0000
0000 0001. For full-scale adjustment, apply an input voltage of
4.9982 V (FS – 3/2 LSBs) to V1 and adjust R2 until the ADC
output code flickers between 1111 1111 1110 and 1111 1111
1111.
functions. Serial data is available during conversion with a word
length of 16 bits; four leading zeros, followed by the 12-bit con-
version result starting with the MSB. T he data is synchronized
to the serial clock output (SCLK) and framed by the serial
strobe (SSTRB). Data is clocked out on a low to high transition
of the serial clock and is valid on the falling edge of this clock
while the SSTRB output is low. SSTRB goes low within three
clock cycles after CONVST, and the first serial data bit (the first
leading zero) is valid on the first falling edge of SCLK. All three
serial lines are open-drain outputs and require external pull-up
resistors.
2
The serial clock out is derived from the ADC clock source,
which may be internal or external. Normally, SCLK is required
during the serial transmission only. In these cases, it can be shut
down at the end of conversion to allow multiple ADCs to share
a common serial bus. However, some serial systems (e.g.,
T MS32020) require a serial clock that runs continuously. Both
options are available on the AD7870/AD7875/AD7876 using
the 12/8/CLK input. With this input at –5 V, the serial clock
(SCLK) runs continuously; when 12/8/CLK is at 0 V, SCLK is
turned off at the end of transmission.
TIMING AND CO NTRO L
The AD7870/AD7875/AD7876 is capable of two basic operating
modes. In the first mode (Mode 1), the CONVST line is used to
start conversion and drive the track/hold into its hold mode. At
the end of conversion the track/hold returns to its tracking mode.
It is intended principally for digital signal processing and other
applications where precise sampling in time is required. In these
applications, it is important that the signal sampling occurs at ex-
actly equal intervals to minimize errors due to sampling uncer-
tainty or jitter. For these cases, the CONVST line is driven by a
timer or some precise clock source.
MO D E 1 INTERFACE
Conversion is initiated by a low going pulse on the CONVST
input. T he rising edge of this CONVST pulse starts conversion
and drives the track/hold amplifier into its hold mode. Conver-
sion will not be initiated if the CS is low. T he BUSY/INT status
output assumes its INT function in this mode. INT is normally
high and goes low at the end of conversion. T his INT line can
be used to interrupt the microprocessor. A read operation to the
ADC accesses the data and the INT line is reset high on the fall-
ing edge of CS and RD. T he CONVST input must be high
when CS and RD are brought low for the ADC to operate cor-
rectly in this mode. T he CS or RD input should not be hard-
wired low in this mode. Data cannot be read from the part
during conversion because the on-chip latches are disabled
when conversion is in progress. In applications where precise
sampling is not critical, the CONVST pulse can be generated
from a microprocessor WR line OR-gated with a decoded ad-
dress. In some applications, depending on power supply turn-on
time, the AD7870/AD7875/AD7876 may perform a conversion
on power-up. In this case, the INT line will power-up low and a
dummy read to the AD7870/AD7875/AD7876 will be required
to reset the INT line before starting conversion.
T he second mode is achieved by hard-wiring the CONVST line
low. T his mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS starts conversion and
the microprocessor will normally be driven into a WAIT state
for the duration of conversion by BUSY/INT.
D ATA O UTP UT FO RMATS
In addition to the two operating modes, the AD7870/AD7875/
AD7876 also offers a choice of three data output formats, one
serial and two parallel. T he parallel data formats are a single,
12-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. T he data format is controlled by the 12/8/
CLK input. A logic high on this pin selects the 12-bit parallel
output format only. A logic low or –5 V applied to this pin al-
lows the user access to either serial or byte formatted data.
T hree of the pins previously assigned to the four MSBs in paral-
lel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
T he three possible data output formats can be selected in either
of the modes of operation.
Figure 9 shows the Mode 1 timing diagram for a 12-bit parallel
data output format (12/8/CLK = +5 V). A read to the ADC at
the end of conversion accesses all 12 bits of data at the same
time. Serial data is not available for this data output format.
P ar allel O utput For m at
T he two parallel formats available on the part are a 12-bit wide
data word and a two-byte data word. In the first, all 12 bits of
data are available at the same time on DB11 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB11/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the ADC. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read op-
eration; with HBEN high, the upper four bits of the 12-bit word
are placed on the data bus. T hese four bits are right justified
and thereby occupy the lower nibble of data while the upper
nibble contains four zeros.
Ser ial O utput For m at
Serial data is available on the AD7870/AD7875/AD7876 when
the 12/8/CLK input is at 0 V or –5 V and in this case the DB10/
SSTRB, DB9/SCLK and DB8/SDAT A pins assume their serial
Figure 9. Mode 1 Tim ing Diagram , 12-Bit Parallel Read
REV. B
–9–
AD7870/AD7875/AD7876
Figure 10. Mode 1 Tim ing Diagram , Byte or Serial Read
T he Mode 1 timing diagram for byte and serial data is shown in
Figure 10. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD. T his first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (Figure 10 shows low
byte only for example). T he diagram shows both a noncontinu-
ously and a continuously running clock (dashed line).
its BUSY function. BUSY goes low at the start of conversion,
stays low during the conversion and returns high when the con-
version is complete. It is normally used in parallel interfaces to
drive the microprocessor into a WAIT state for the duration of
conversion.
Figure 11 shows the Mode 2 timing diagram for the 12-bit par-
allel data output format (12/8/CLK = +5 V). In this case, the
ADC behaves like slow memory. T he major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. T he
user does not have to worry about servicing interrupts or ensur-
ing that software delays are long enough to avoid reading during
conversion.
MO D E 2 INTERFACE
T he second interface mode is achieved by hard wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. T he track/hold amplifier goes into the hold mode on the
falling edge of CS. In this mode, the BUSY/INT pin assumes
Figure 11. Mode 2 Tim ing Diagram , 12-Bit Parallel Read
REV. B
–10–
AD7870/AD7875/AD7876
2
Figure 12. Mode 2 Tim ing Diagram , Byte or Serial Read
T he Mode 2 timing diagram for byte and serial data is shown in
Figure 12. For two-byte data read, the lower byte (DB0–DB7)
has to be accessed first since HBEN must be low to start con-
version. T he ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation of the serial functions is identical between
Mode 1 and Mode 2. T he timing diagram of Figure 12 shows
both a noncontinuously and a continuously running SCLK
(dashed line).
sine-wave signal of very low distortion to the VIN input which is
sampled at a 100 kHz sampling rate. A Fast Fourier T ransform
(FFT ) plot is generated from which the SNR data can be ob-
tained. Figure 13 shows a typical 2048 point FFT plot of the
AD7870KN/AD7875KN with an input signal of 25 kHz and a
sampling frequency of 100 kHz. T he SNR obtained from this
graph is 72.6 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
D YNAMIC SP ECIFICATIO NS
T he AD7870 and AD7875 are specified and 100% tested for
dynamic performance specifications as well as traditional dc
specifications such as integral and differential nonlinearity. Al-
though the AD7876 is not production tested for ac parameters,
its dynamic performance is similar to the AD7870 and AD7875.
T he ac specifications are required for signal processing applica-
tions such as speech recognition, spectrum analysis and high
speed modems. T hese applications require information on the
ADC’s effect on the spectral content of the input signal. Hence,
the parameters for which the AD7870 and AD7875 are speci-
fied include SNR, harmonic distortion, intermodulation distor-
tion and peak harmonics. T hese terms are discussed in more
detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. T he signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. T he theoretical signal-to-noise ratio for a sine wave input
is given by
Figure 13. FFT Plot
Effective Num ber of Bits
T he formula given in (1) relates SNR to the number of bits.
Rewriting the formula, as in (2), it is possible to get a measure
of performance expressed in effective number of bits (N).
SNR = (6.02N + 1.76) dB
(1)
SNR – 1.76
N =
(2)
where N is the number of bits. T hus for an ideal 12-bit con-
verter, SNR = 74 dB.
6.02
T he effective number of bits for a device can be calculated di-
rectly from its measured SNR.
REV. B
–11–
AD7870/AD7875/AD7876
Figure 14 shows a typical plot of effective number of bits versus
frequency for an AD7870KN/AD7875KN with a sampling fre-
quency of 100 kHz. T he effective number of bits typically falls
between 11.7 and 11.85 corresponding to SNR figures of 72.2
and 73.1 dB.
Figure 14. Effective Num ber of Bits vs. Frequency
Total H ar m onic D istor tion (TH D )
T HD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. For the AD7870/AD7875, T HD is defined
as
Figure 15. IMD Plot
AC Linear ity P lot
V2 2 +V3 2 +V4 2 +V5 2 +V6
2
When a sine wave of specified frequency is applied to the VIN
input of the AD7870/AD7875 and several million samples are
taken, a histogram showing the frequency of occurrence of each
of the 4096 ADC codes can be generated. From this histogram
data it is possible to generate an ac integral linearity plot as
shown in Figure 16. T his shows very good integral linearity per-
formance from the AD7870/AD7875 at an input frequency of
25 kHz. T he absence of large spikes in the plot shows good dif-
ferential linearity. Simplified versions of the formulae used are
outlined below.
THD = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. T he T HD is also derived from the FFT plot of
the ADC output spectrum.
Inter m odulation D istor tion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second or-
der terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
V(i) –V(o)
4096
INL(i) =
–i
V( fs) –V(o)
where INL(i) is the integral linearity at code i. V(fs) and V(o)
are the estimated full-scale and offset transitions and V(i) is the
estimated transition for the ith code.
Using the CCIF standard, where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. T he second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. T he calculation of the intermodu-
lation distortion is as per the T HD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs. In this
case, the input consists of two, equal amplitude, low distortion
sine waves. Figure 15 shows a typical IMD plot for the AD7870/
AD7875.
V(i) the estimated code transition point is derived as follows:
π cum(i)
[
]
V(i) = –A • Cos
N
where A is the peak signal amplitude,
N is the number of histogram samples
and cum(i) = Σin=0V(n) occurrences
P eak H ar m onic or Spur ious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
Figure 16. AC INL Plot
REV. B
–12–
AD7870/AD7875/AD7876
MICRO P RO CESSO R INTERFACE
T he AD7870/AD7875/AD7876 has a wide variety of interfacing
options. It offers two operating modes and three data-output for-
mats. Fast data access times allow direct interfacing to most mi-
croprocessors including the DSP processors.
P ar allel Read Inter facing
Figures 17 to 19 show interfaces to the ADSP-2100, T MS32010
and the T MS32020 DSP processors. T he ADC is operating in
Mode 1, parallel read for all three interfaces. An external timer
controls conversion start asynchronously to the microprocessor.
At the end of each conversion the ADC BUSY/INT interrupts
the microprocessor. T he conversion result is read from the ADC
with the following instruction:
2
ADSP-2100: MR0 = DM(ADC)
T MS32010: IN D,ADC
T MS32020: IN D,ADC
Figure 19. TMS32020 Parallel Interface
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
Two Byte Read Inter facing
68008 Interface
ADC = AD7870/AD7875/AD7876 Address
Figure 20 shows an 8-bit bus interface for the MC68008 micro-
processor. For this interface, the 12/8/CLK input is tied to 0 V
and the DB11/HBEN pin is driven from the microprocessor
least significant address bit. Conversion start control is provided
by the microprocessor. In this interface example, a Move in-
struction from the ADC address both starts a conversion and
reads the conversion result.
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the CONVST signal from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note: a read operation
must not be attempted during conversion.
MOVEW ADC,DO
ADC = AD7870/AD7875/AD7876 address
D0 = 68008 D0 register
T his is a two byte read instruction. During the first read opera-
tion BUSY, in conjunction with CS, forces the microprocessor
to WAIT for the ADC conversion. At the end of conversion the
ADC low byte (DB7–DB0) is loaded into D15–D8 of the D0
register and the ADC high byte (DB15–DB7) is loaded into
D7–D0 of the D0 register. T he following Rotate instruction to
the D0 register swaps the high and low bytes to the correct
format.
R0L = 8, D0.
Note: while executing the two byte read instruction above,
WAIT states are inserted during the first read operation only
and not for the second.
Figure 17. ADSP-2100 Parallel Interface
Figure 18. TMS32010 Parallel Interface
Figure 20. MC68008 Byte Interface
REV. B
–13–
AD7870/AD7875/AD7876
Ser ial Inter facing
Figures 21 to 24 show the AD7870/AD7875/AD7876 config-
ured for serial interfacing. In all four interfaces, the ADC is con-
figured for Mode 1 operation. T he interfaces show a timer
driving the CONVST input, but this could be generated from a
decoded address if required. T he SCLK, SDAT and SSTRB are
open-drain outputs. If these are required to drive capacitive
loads in excess 35 pF, buffering is recommended.
DSP56000 Serial Interface
Figure 22. NEC7720 Serial Interface
TMS32020 Serial Interface
Figure 21 shows a serial interface between the AD7870/
AD7875/AD7876 and the DSP56000. T he interface arrange-
ment is two-wire with the ADC configured for noncontinuous
clock operation (12/8/CLK = 0 V). T he DSP56000 is config-
ured for normal mode asynchronous operation with gated clock.
It is also set up for a 16-bit word with SCK and SC1 as inputs
and the FSL control bit set to a 0. In this configuration, the
DSP56000 assumes valid data on the first falling edge of SCK.
Since the ADC provides valid data on this first edge, there is no
need for a strobe or framing pulse for the data. SCLK and
SDAT A are gated off when the ADC is not performing a con-
version. During conversion, data is valid on the SDAT A output
of the ADC and is clocked into the receive data shift register of
the DSP56000. When this register has received 16 bits of data,
it generates an internal interrupt on the DSP56000 to read the
data from the register.
Figure 23 shows a serial interface between the AD7870/ AD7875/
AD7876 and the T MS32020. T he AD7870/AD7875/AD7876 is
configured for continuous clock operation. Note, the ADC will
not interface correctly to the T MS32020 if the ADC is config-
ured for a noncontinuous clock. Data is clocked into the data
receive register (DRR) of the T MS32020 during conversion. As
with the previous interfaces, when a 16-bit word is received by
the T MS32020 it generates an internal interrupt to read the
data from the DRR.
Figure 23. TMS32020 Serial Interface
ADSP-2101/ADSP-2102 Serial Interface
Figure 24 shows a serial interface between the AD7870/AD7875/
AD7876 and the ADSP-2101/ADSP-2102. T he ADC is config-
ured for continuous clock operation. Data is clocked into the
serial port register of the ADSP-2101/ADSP-2102 during con-
version. As with the previous interfaces, when a 16-bit data
word is received by the ADSP-2101/ADSP-2102 an internal mi-
croprocessor interrupt is generated and the data is read from the
serial port register.
Figure 21. DSP56000 Serial Interface
T he DSP56000 and AD7870/AD7875/AD7876 can also be
configured for continuous clock operation (12/8/CLK = –5 V).
In this case, a strobe pulse is required by the DSP56000 to indi-
cate when data is valid. T he SSTRB output of the ADC is in-
verted and applied to the SC1 input of the DSP56000 to
provide this strobe pulse. All other conditions and connections
are the same as for gated clock operation.
NEC7720/77230 Serial Interface
A serial interface between the AD7870/AD7875/AD7876 and
the NEC7720 is shown in Figure 22. In the interface shown, the
ADC is configured for continuous clock operation. T his can be
changed to a noncontinuous clock by simply tying the 12/8/CLK
input of the ADC to 0 V with all other connections remaining
the same. T he NEC7720 expects valid data on the rising edge of
its SCK input and therefore an inverter is required on the
SCLK output of the ADC. T he NEC7720 is configured for a
16-bit data word. Once the 16 bits of data have been received
by the SI register of the NEC7720, an internal interrupt is gen-
erated to read the contents of the SI register.
Figure 24. ADSP-2101/ADSP-2102 Serial Interface
T he NEC77230 interface is similar to that just outlined for the
NEC7720. However, the clock input of the NEC77230 is
SICLK. Additionally, no inverter is required between the ADC
SCLK output and this SICLK input since the NEC77230 as-
sumes data is valid on the falling edge of SICLK.
REV. B
–14–
AD7870/AD7875/AD7876
STAND -ALO NE O P ERATIO N
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
T he AD7870/AD7875/AD7876 can be used in its Mode 2, par-
allel interface mode for stand-alone operation. In this case, con-
version is initiated with a pulse to the ADC CS input. T his
pulse must be longer than the conversion time of the ADC. T he
BUSY output is used to drive the RD input. Data is latched
from the ADC DB0–DB11 outputs to an external latch on the
rising edge of BUSY.
D ATA ACQ UISITIO N BO ARD
Figure 28 shows the AD7870/AD7875/AD7876 in a data acqui-
sition circuit. T he corresponding printed circuit board (PCB)
layout and silkscreen are shown in Figures 29 to 31. T he board
layout has three interface ports: one serial and two parallel. One
of the parallel ports is directly compatible with the ADSP-2100
evaluation board expansion connector.
T he only additional component required for a full data acquisi-
tion system is an antialiasing filter. A component grid is pro-
vided near the analog input on the PCB, which may be used for
such a filter or any other input conditioning circuitry. T o facili-
tate this option there is a shorting plug (labelled LK1 on the
PCB) on the analog input track. If this shorting plug is used, the
analog input connects to the buffer amplifier driving the ADC;
if this shorting plug is omitted, a wire link can be used to con-
nect the analog input to the PCB component grid.
2
INTERFACE CO NNECTIO NS
T here are two parallel connectors labeled SKT 4 and SKT 6 and
one serial connector labeled SKT 5. A shorting plug option
(LK3 in Figure 28) on the ADC 12/8/CLK input configures
the ADC for the appropriate interface (see Pin Function
Description).
Figure 25. Stand-Alone Operation
AP P LICATIO N H INTS
Good printed circuit board (PCB) layout is as important as the
overall circuit design itself in achieving high speed A/D perfor-
mance. T he designer has to be conscious of noise both in the
ADC itself and in the preceding analog circuitry. Switching
mode power supplies are not recommended as the switching
spikes will feed through to the comparator causing noisy code
transitions. Other causes of concern are ground loops and digi-
tal feedthrough from microprocessors. T hese are factors which
influence any ADC, and a proper PCB layout which minimizes
these effects is essential for best performance.
SKT 6 is a 96-contact (3-ROW) Eurocard connector that is
directly compatible with the ADSP-2100 Evaluation Board
Prototype Expansion Connector. T he expansion connector on
the ADSP-2100 has eight decoded chip enable outputs labeled
ECE1 to ECE8. ECE6 is used to drive the ADC CS input on
the data acquisition board. T o avoid selecting on board RAM
sockets at the same time, LK6 on the ADSP-2100 board must
be removed. In addition, the ADSP-2100 expansion connector
has four interrupts labelled EIRQ0 to EIRQ3. T he ADC BUSY/
INT output connects to EIRQ0. T here is a single wait state gen-
erator connected to EDMACK to allow the ADC to interface to
the faster versions of the ADSP-2100.
LAYO UT H INTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. T ake
care not to run any digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
SKT 4 is a 26-way (2-ROW) IDC connector. T his connector
contains all the signal contacts as SKT 6 with the exception of
EDMACK which is connected to SKT 6 only. It also contains
decoded R/W and STRB inputs which are necessary for
T MS32020 interfacing. T he SKT 4 pinout is shown in Fig-
ure 26.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AGND pin or as close as
possible to the ADC. Connect all other grounds and the
AD7870/AD7875/AD7876 DGND to this single analog ground
point. Do not connect any other digital grounds to this analog
ground point.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. T he use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise. T he circuit layout of Figures
30 and 31 have both analog and digital ground planes which are
kept separated and only joined together at the AD7870/
AD7875/AD7876 AGND pin.
NO ISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
Figure 26. SKT4, IDC Connector Pinout
REV. B
–15–
AD7870/AD7875/AD7876
SKT 5 is a 9-way D-type connector that is meant for serial inter-
facing only. An inverted DB9/SCLK output is also provided on
this connector for systems that accept data on a rising clock
edge. T he SKT 5 pinout is shown in Figure 27.
SKT 1, SKT 2 and SKT 3 are three BNC connectors which pro-
vide input connections for the analog input, the CONVST input
and an external clock input. T he use of an external clock source
is optional; there is a shorting plug (LK2) on the ADC CLK in-
put that must be connected to either –5 V (for the ADCs own
internal clock) or to SKT 3.
P O WER SUP P LY CO NNECTIO NS
T he PCB requires two analog power supplies and one 5 V digi-
tal supply . T he analog supplies are labelled V+ and V–, and the
range for both supplies is 12 V to 15 V (see silkscreen in Figure
29). Connection to the 5 V digital supply is made through any
of the connectors (SKT 4 to SKT 6). T he –5 V supply required
by the ADC is generated from a voltage regulator on the V–
power supply input (IC3 in Figure 27).
Figure 27. SKT5, D-Type Connector Pinout
SH O RTING P LUG O P TIO NS
CO MP O NENT LIST
T here are seven shorting plug options that must be set before
using the board. T hese are outlined below:
IC1
IC2
AD711 Op Amp
AD7870/AD7875/AD7876 Analog-to-
Digital Converter
MC79L05 –5 V Regulator
74HC00 Quad NAND Gate
74HC74 Dual D-T ype Flip Flop
LK1 Connects the analog input to a buffer amplifier. T he
analog input may also be connected to a component grid
for signal conditioning.
IC3
IC4
IC5
LK2 Selects either the ADC internal clock or an external
clock source.
C1, C3, C5, C7,
C9, C11
C2, C4, C6, C8,
C10, C12
10 µF Capacitors
LK3 Configures the ADC 12/8/CLK input for the appropri-
0.1 µF Capacitors
ate serial or parallel interface.
LK4 Connects the ADC RD input directly to the two parallel
connectors or to a decoded STRB and R/W input. T his
shorting plug setting depends on the microprocessor e.g.,
the T MS32010 has a separate RD output while the
T MS32020 has STRB and R/W outputs.
R1, R2
R3*, R5*
R4*
10 kΩ Pull-Up Resistors
4.7 kΩ Pull-Up Resistors
2 kΩ Pull-Up Resistor
Shorting Plugs
LK1, LK2
LK5– Connect the pull-up resistors R3, R4 and R5 to SSTRB,
LK7 SCLK and SDAT A. T hese shorting plugs should be
removed for parallel interfacing.
LK3, LK4
LK5, LK6, LK7
SKT 1, SKT 2, SKT 3 BNC Sockets
SKT 4
SKT 5
SKT 6
26-Contact (2-Row) IDC Connector
9-Contact D-T ype Connector
96-Contact (3-Row) Eurocard Connector
*Required for Serial Communication only.
REV. B
–16–
AD7870/AD7875/AD7876
2
Figure 28. Data Acquisition Circuit Using the AD7870/AD7875/AD7876
Figure 29. PCB Silkscreen for Figure 28
–17–
REV. B
AD7870/AD7875/AD7876
Figure 30. PCB Com ponent Side Layout for Figure 28
Figure 31. PCB Solder Side Layout for Figure 28
REV. B
–18–
AD7870/AD7875/AD7876
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic D IP (N-24)
28-P in P LCC (P -28A)
2
24-P in Cer dip (Q -24)
24-P in SO IC (R-24)
REV. B
–19–
–20–
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