AD7880BN [ADI]
LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADC; LC2MOS +5 V单电源，低功耗， 12位采样ADC
| 型号： | AD7880BN |
| 厂家： | 
ADI |
| 描述： | LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADC |
| 文件： | 总16页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS Single +5 V Supply,
Low Power, 12-Bit Sampling ADC
a
AD7880
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
12-Bit Monolithic A/ D Converter
66 kHz Throughput Rate
12 s Conversion Tim e
VDD
3 s On-Chip Track/ Hold Am plifier
Low Pow er
Pow er Save Mode: 2 m W typ
Norm al Operation: 25 m W typ
70 dB SNR
SAMPLING
COMPARATOR
R
R
V
LOW POWER
CONTROL
CIRCUIT
MODE
INA
+
–
V
INB
VREF
12-BIT DAC
Fast Data Access Tim e: 57 ns
Sm all 24-Lead SOIC and 0.3" DIP Packages
AGND
CS
SAR +
COUNTER
APPLICATIONS
CLKIN
CONTROL
LOGIC
Battery Pow ered Portable System s
Digital Signal Processing
Speech Recognition and Synthesis
High Speed Modem s
CONVST
RD
THREE
STATE
BUFFERS
BUSY
AD7880
Control and Instrum entation
DB11 DB0
DGND
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7880 is a high speed, low power, 12-bit A/D converter
which operates from a single +5 V supply. It consists of a 3 µs
track/hold amplifier, a 12 µs successive-approximation ADC,
versatile interface logic and a multiple-input-range circuit. T he
part also includes a power save feature.
1. Fast Conversion T ime.
12 µs conversion time and 3 µs acquisition time allow for
large input signal bandwidth. T his performance is ideally
suited for applications in areas such as telecommunications,
audio, sonar and radar signal processing.
An internal resistor network allows the part to accept both uni-
polar and bipolar input signals while operating from a single
+5 V supply. Fast bus access times and standard control inputs
ensure easy interfacing to modern microprocessors and digital
signal processors.
2. Low Power Consumption.
2 mW power consumption in the power-down mode makes
the part ideally suited for portable, hand held, battery pow-
ered applications.
3. Multiple Input Ranges.
T he AD7880 features a total throughput time of 15 µs and can
convert full power signals up to 33 kHz with a sampling fre-
quency of 66 kHz.
T he part features three user-determined input ranges, 0 V to
+5 V, 0 V to 10 V and ±5 V. T hese unipolar and bipolar
ranges are achieved with a 5 V only power supply.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7880 is also fully
specified for dynamic performance parameters including har-
monic distortion and signal-to-noise ratio.
T he AD7880 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. T he part is available in a 24-pin, 0.3 inch-wide, plastic or
hermetic dual-in-line package (DIP) as well as a small 24-lead
SOIC package.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +5 V ؎ 5%, V = V , AGND = DGND = O V, fCLKIN = 2.5 MHz, MODE = V
DD
DD
REF
DD
AD7880–SPECIFICATIONS unless otherwise noted. All Specifications T
MIN to TMAX unless otherwise noted.)
P aram eter
B Versions1
C Versions1 Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR)
70
70
dB min
T ypically SNR Is 72 dB
VIN = 1 kHz Sine Wave, fSAMPLE = 66 kHz
VIN = 1 kHz Sine Wave, fSAMPLE = 66 kHz
VIN = 1 kHz, fSAMPLE = 66 kHz
T otal Harmonic Distortion (T HD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order T erms
–80
–80
–80
–80
dB typ
dB typ
–80
–80
–80
–80
dB typ
dB typ
fa = 0.983 kHz, fb = 1.05 kHz, fSAMPLE = 66 kHz
fa = 0.983 kHz, fb = 1.05 kHz, fSAMPLE = 66 kHz
T hird Order T erms
DC ACCURACY
Resolution
12
12
Bits
All DC ACCURACY Specifications Apply for
the T hree Analog Input Ranges
Integral Nonlinearity
Differential Nonlinearity
Full-Scale Error
Bipolar Zero Error
Unipolar Offset Error
±1
±1
±15
±10
±5
±1
±1
±5
±5
±5
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed Monotonic
ANALOG INPUT
Input Voltage Ranges
0 to VREF
0 to 2 VREF
±VREF
10
5/12
5/12
0 to VREF
0 to 2 VREF
±VREF
10
5/12
5/12
Volts
Volts
Volts
MΩ min
kΩ min/max
kΩ min/max
See Figure 5
See Figure 6
See Figure 7
0 to VREF Range
8 kΩ typical: 0 to 2 VREF Range
8 kΩ typical: ±VREF Range
Input Resistance
REFERENCE INPUT
VREF (For Specified Performance)
IREF
5
1.5
2.5/VDD
5
1.5
2.5/VDD
V
±5%: Normally VREF = VDD (See Reference Input Section)
mA max
V min/max
Nominal Reference Range
See Figure 3 for Degradation in Performance Down to 2.5 V
LOGIC INPUT S
CONVST, RD, CS, CLKIN
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
V max
µA max
pF max
VIN = 0 V or VDD
4
Input Capacitance, CIN
MODE INPUT
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
4
1
4
1
V min
V max
µA max
pF max
±125
10
±125
10
VIN = 0 V or VDD
4
Input Capacitance, CIN
LOGIC OUT PUT S
DB11–DB0, BUSY
Output High Voltage, VOH
Output Low Voltage, VOL
DB11–DB0
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 400 µA
ISINK = 1.6 mA
Floating-State Leakage Current
Floating-State Output Capacitance4
±10
10
±10
10
µA max
pF max
CONVERSION
Conversion T ime
T rack/Hold Acquisition T ime
12
3
12
3
µs max
µs max
fCLKIN = 2.5 MHz
POWER REQUIREMENT S
VDD
+5
+5
V nom
±5% for Specified Performance
IDD
Normal Power Mode @ +25°C
TMIN to T MAX
Power Save Mode @ +25°C
TMIN to T MAX
7.5
10
750
1
7.5
10
750
1
mA max
mA max
µA max
mA max
T ypically 4 mA; MODE = VDD
T ypically 5 mA; MODE = VDD
Logic Inputs @ 0 V or VDD; MODE = 0 V
Logic Inputs @ 0 V or VDD; MODE = 0 V
Power Dissipation
Normal Power Mode @ +25°C
TMIN to T MAX
Power Save Mode @ +25°C
TMIN to T MAX
37.5
50
3.75
5
37.5
50
3.75
5
mW max
mW max
mW max
mW max
VDD = 5 V: T ypically 20 mW; MODE = VDD
VDD = 5 V: T ypically 25 mW; MODE = VDD
VDD = 5 V: T ypically 2 mW; MODE = 0 V
VDD = 5 V: T ypically 2.5 mW; MODE = 0 V
NOT ES
1T emperature ranges are as follows: B/C Versions, –40°C to +85°C.
2VIN = 0 to VREF
3SNR calculation includes distortion and noise components.
4Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. 0
AD7880
1
(V = +5 V ؎ 5%, V = V , AGND = DGND = 0 V)
DD
REF
DD
TIMING CHARACTERISTICS
Lim it at +25؇C
Lim it at TMIN, TMAX
(All Versions)
P aram eter
(All Versions)
Units
Conditions/Com m ents
t1
t2
t3
t4
t5
t6
50
130
0
50
130
0
ns min
ns min
ns min
ns min
ns min
ns min
ns max
CONVST Pulse Width
CONVST to BUSY Falling Edge
BUSY to CS Setup T ime
CS to RD Setup T ime
0
0
0
0
CS to RD Hold T ime
60
57
75
70
RD Pulse Width
2
t7
Data Access T ime after RD
Bus Relinquish T ime after RD
3
t8
5
50
5
50
ns min
ns max
NOT ES
1T iming specifications in bold print are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. T he measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. T his means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
t1
Table I. Truth Table
TRACK/HOLD
GOES INTO HOLD
CONVST
BUSY
t 2
CS
CONVST
RD
Function
tCONVERT
1
1
0
0
1
j
1
1
X
1
0
Not Selected
Start Conversion g
Enable ADC Data
Data Bus T hree Stated
t3
1
CS
t 5
t4
ABSO LUTE MAXIMUM RATINGS*
t6
RD
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
t8
t 7
THREE-STATE
DATA
VALID
DB0 – DB11
VINA, VINB to AGND (Figure 5) . . . . . . –0.3 V to VDD + 0.3 V
VINA to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 VDD + 0.6 V
VINA to AGND (Figure 7) . . . . . –VDD – 0.3 V to VDD + 0.3 V
Figure 1. Tim ing Diagram
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
1.6mA
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
TO OUTPUT
PIN
+2.1V
50pF
200µA
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 2. Load Circuit for Access and Relinquish Tim e
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7880 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. 0
AD7880
O RD ERING GUID E
P IN CO NFIGURATIO N
Bipolar
Error
V
24
23
22
21
20
19
V
DD
1
2
3
4
5
6
7
8
9
INA
Full-Scale Zero
Error
(LSBs)
V
Tem perature
Range
P ackage
INB
MODE
DB11
Model
(LSBs) O ption*
AGND
V
REF
AD7880BN –40°C to +85°C ±15
AD7880BQ –40°C to +85°C ±15
AD7880CN –40°C to +85°C ±5
AD7880CQ –40°C to +85°C ±5
AD7880BR –40°C to +85°C ±15
AD7880CR –40°C to +85°C ±5
±10
±10
±5
±5
±10
±5
N-24
Q-24
N-24
Q-24
R-24
R-24
DB10
DB9
DB8
DB7
CS
AD7880
TOP VIEW
CONVST
(Not to Scale)
RD
18
17
16
15
14
13
BUSY
DB6
DB5
DB4
DB3
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).
CLKIN
DGND
DB0
10
11
12
DB1
DB2
P IN FUNCTIO N D ESCRIP TIO N
P in
No.
P in
Mnem onic Function
1
2
3
4
5
6
VINA
Analog Input.
VINB
Analog Input.
AGND
VREF
Analog Ground.
Voltage Reference Input. T his is normally tied to VDD
.
CS
Chip Select. Active Low Logic input. T he device is selected when this input is active.
CONVST
Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con-
version. T his input is asynchronous to the CLKIN and is independent of CS and RD.
7
8
9
RD
Read. Active Low Logic Input. T his input is used in conjunction with CS low to enable data outputs.
Active Low Logic Output. T his status line indicates converter status. BUSY is low during conversion.
BUSY
CLKIN
Clock Input. T T L-compatible logic input. Used as the clock source for the A/D converter. T he mark/
space ratio of the clock can vary from 40/60 to 60/40.
10
DGND
Digital Ground.
11 . . . 22
23
DB0–DB11 T hree-State Data Outputs. T hese become active when CS and RD are brought low.
MODE
MODE Input. T his input is used to put the device into the power save mode (MODE = 0 V). During
normal operation, the MODE input will be a logic high (MODE = VDD).
24
VDD
Power Supply. T his is nominally +5 V.
REV. 0
–4–
AD7880
CIRCUIT INFO RMATIO N
R
R
T he AD7880 is a +5 V single supply 12-bit A/D converter. T he
part requires no external components apart from a 2.5 MHz ex-
ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. T he charge balancing comparator
used in the AD7880 provides the user with an inherent track-
and-hold function. T he ADC is specified to work with sampling
rates up to 66 kHz.
VINA
+
–
VINB
VDAC
Figure 4. AD7880 Input Circuit
T he AD7880 accommodates three separate input ranges, 0 to
REF, 0 to 2 VREF and ±VREF. T he input configurations corre-
CO NVERTER D ETAILS
T he AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. T he rising edge of the CONVST pulse places the track/hold
amplifier into “HOLD” mode. T he conversion cycle then takes
between 26 and 28 clock periods. T he maximum specified con-
version time is 12 µs. T his corresponds to a conversion cycle
time of 28 clock periods with a CLKIN frequency of 2.5 MHz
and also includes internal propagation delays. During conver-
sion the BUSY output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the BUSY output will go to a high level, and the result of the
conversion can be read by bringing CS and RD low.
V
sponding to these ranges are shown in Figures 5, 6 and 7.
With VREF = VDD and using a nominal VDD of +5 V, the input
ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in
T able II.
Table II. Analog Input Ranges
Input Connections
Analog Input
Range
Connection
D iagram
VREF
VINA
VINB
0 V to +5 V
0 V to +10 V
±5 V
VDD
VDD
VDD
VIN
VIN
VIN
VIN
AGND
VREF
Figure 5
Figure 6
Figure 7
T he track/hold amplifier acquires a 12-bit input signal in 3 µs.
T he overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a
2.5 MHz input clock the throughput time is 15 µs.
SAMPLING
COMPARATOR
R
R
VIN = 0 TO VREF
0 TO VREF
V
INA
+
–
REFERENCE INP UT
For specified performance, it is recommended that the reference
input be tied to VDD. T he part, however, will operate with a ref-
erence down to 2.5 V though with reduced performance specifi-
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
V
INB
VREF
VREF
12-BIT DAC
AGND
versus VREF
.
VREF must not be allowed to go above VDD by more than
100 mV.
Figure 5. 0 to VREF Unipolar Input Configuration
74
F = 51.2kHz
SAMPLING
COMPARATOR
S
R
72
F
= 2.525kHz
V
IN = 0 TO 2VREF
IN
0 TO VREF
VINA
T = 25 C
+
–
A
R
70
68
V
INB
VREF
VREF
12-BIT DAC
AGND
66
64
62
60
Figure 6. 0 to 2 VREF Unipolar Input Configuration
SAMPLING
R
COMPARATOR
±
= VREF
V
2
3
4
5
IN
0 TO VREF
V
VREF – Volts
INA
+
–
R
V
Figure 3. SNR vs. VREF
INB
VREF
VREF
12-BIT DAC
ANALO G INP UT
AGND
T he AD7880 has two analog input pins, VINA and VINB. Figure
4 shows the input circuitry to the ADC sampling comparator.
T he on-board attenuator network, made up of equal resistors,
allows for various input ranges.
Figure 7. ±VREF Bipolar Input Configuration
–5–
REV. 0
AD7880
T he AD7880 has two unipolar input ranges, 0 V to 5 V and 0 V
to 10 V. Figure 5 shows the analog input for the 0 V to 5 V
range. T he designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). T he output code is straight binary
with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The same applies
for the 0 V to 10 V range, as shown in Figure 6, except that the
LSB size is bigger. In this case 1 LSB = FS/4096 = 10 V/4096 =
2.44 mV. T he ideal input/output transfer characteristic for both
these unipolar ranges is shown in Figure 8.
CLO CK INP UT
T he AD7880 is specified to operate with a 2.5 MHz clock con-
nected to the CLKIN input pin. T his pin may be driven directly
by CMOS or T T L buffers. T he mark/space ratio on the clock
can vary from 40/60 to 60/40. As the clock frequency is slowed
down, it can result in slightly degraded accuracy performance.
T his is due to leakage effects on the hold capacitor in the inter-
nal track-and-hold amplifier. Figure 10 is a typical plot of accu-
racy versus clock frequency for the ADC.
2.5
2.0
1.5
OUTPUT
CODE
111...111
111...110
111...101
111...100
1.0
0.5
0.0
000...011
FS
4096
1LSB =
000...010
1.5
2.5
3.5
0.5
000...001
000...000
CLOCK FREQUENCY – MHz
1LSB
+
FS – 1LSB
0V
Figure 10. Norm alized Linearity Error vs. Clock Frequency
VIN INPUT VOLTAGE
TRACK/H O LD AMP LIFIER
Figure 8. AD7880 Unipolar Transfer Characteristic
T he charge balanced comparator used in the AD7880 for the
A/D conversion provides the user with an inherent track/hold
function. T he track/hold amplifier acquires an input signal to
12-bit accuracy in less than 3 µs. T he overall throughput time is
equal to the conversion time plus the track/hold amplifier acqui-
sition time. For a 2.5 MHz input clock, the throughput time is
15 µs.
Figure 7 shows the AD7880’s ±5 V bipolar analog input con-
figuration. Once again the designed code transitions occur mid-
way between successive integer LSB values. T he output code is
straight binary with 1 LSB = FS/4096 = 10 V/4096 = 2.44 mV.
T he ideal bipolar input/output transfer characteristic is shown in
Figure 9.
OUTPUT
CODE
T he operation of the track/hold amplifier is essentially transpar-
ent to the user. T he track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the ris-
ing edge of CONVST as shown in Figure 1.
111...111
111...110
O FFSET AND FULL-SCALE AD JUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
100...101
100...000
011...111
–
FS
2
–
1LSB
+1LSB
+
FS
2
– 1LSB
FS = 10V
FS
011...110
000...001
000...000
1LSB =
4096
T he following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent off-
set of the op amp driving the input to the ADC as well as tweak-
ing an additional external potentiometer as shown in Figure 11.
0V
IN INPUT VOLTAGE
V
Figure 9. AD7880 Bipolar Transfer Characteristic
REV. 0
–6–
AD7880
R1
Signal-to-Noise Ratio (SNR)
10 kΩ
SNR is the measured signal-to-noise ratio at the output of the
ADC. T he signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. T he theoretical signal to noise ratio for a sine wave input
is given by:
V
1
R2
+
–
500 Ω
V
INA
R4
10 kΩ
R3
AD7880*
R5
10 kΩ
10 kΩ
AGND
SNR = (6.02 N + 1.76) dB
(1)
*ADDITIONAL PINS OMITTED FOR CLARITY
where N is the number of bits.
T hus for an ideal 12-bit converter, SNR = 74 dB.
Figure 11. Offset and Full-Scale Adjust Circuit
T he output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input which is
sampled at a 66 kHz sampling rate. A Fast Fourier T ransform
(FFT ) plot is generated from which the SNR data can be ob-
tained. Figure 12 shows a typical 2048 point FFT plot of the
AD7880 with an input signal of 2.5 kHz and a sampling fre-
quency of 61 kHz. T he SNR obtained from this graph is 73 dB.
It should be noted that the harmonics are taken into account
when calculating the SNR.
Unipolar Adjustm ents
In the case of the 0 V to 5 V unipolar input configuration, unipolar
offset error must be adjusted before full-scale error. Adjustment is
achieved by trimming the offset of the op amp driving the ana-
log input of the AD7880. T his is done by applying an input
voltage of 0.61 mV (1/2 LSB) to V1 in Figure 11 and adjusting
the op amp offset voltage until the ADC output code flickers
between 0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.9982 V (FS–3/2 LSBs) is
applied to V1 and R2 is adjusted until the output code flickers
between 1111 1111 1110 and 1111 1111 1111.
T he same procedure is required for the 0 V to 10 V input con-
figuration of Figure 6. An input voltage of 1.22 mV (1/2 LSB) is
applied to V1 in Figure 11 and the op amp’s offset voltage is
adjusted until the ADC output code flickers between 0000 0000
0000 and 0000 0000 0001. For full-scale adjustment, an input
voltage of 9.9963 V (FS–3/2 LSBs) is applied to V1 and R2 is
adjusted until the output code flickers between 1111 1111 1110
and 1111 1111 1111.
Bipolar Adjustm ents
Bipolar zero and full-scale errors for the bipolar input configura-
tion of Figure 7 are adjusted in a similar fashion to the unipolar
case. Again, bipolar zero error must be adjusted before full-scale
error. Bipolar zero error adjustment is achieved by trimming the
offset of the op amp driving the analog input of the AD7880
while the input voltage is 1/2 LSB below ground. T his is done
by applying an input voltage of –1.22 mV (1/2 LSB) to V1 in
Figure 11 and adjusting the op amp offset voltage until the
ADC output code flickers between 0111 1111 1111 and 1000
0000 0000. For full-scale adjustment, an input voltage of
4.9982 V (FS/2–3/2 LSBs) is applied to V1 and R2 is adjusted
until the output code flickers between 1111 1111 1110 and
1111 1111 1111.
Figure 12. FFT Plot
Effective Num ber of Bits
T he formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
SNR −1. 76
N =
D YNAMIC SP ECIFICATIO NS
(2)
6.02
T he AD7880 is specified and tested for dynamic performance
specifications as well as traditional dc specifications such as
integral and differential nonlinearity. T he ac specifications are
required for signal processing applications such as speech recog-
nition, spectrum analysis and high speed modems. T hese appli-
cations require information on the ADC’s effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7880 is specified include SNR, harmonic distortion, inter-
modulation distortion and peak harmonics. T hese terms are dis-
cussed in more detail in the following sections.
T he effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 13 shows a plot of effective number of bits versus input
frequency for an AD7880 with a sampling frequency of 61 kHz.
T he effective number of bits typically remains better than 11.5
for frequencies up to 12 kHz.
–7–
REV. 0
AD7880
12
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. T he second order terms
are usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. T he calculation of the inter-
modulation distortion is as per the T HD specification where it is
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs. In this
case, the input consists of two, equal amplitude, low distortion,
sine waves. Figure 14 shows a typical IMD plot for the
AD7880.
11.5
11
10.5
10
SAMPLE FREQUENCY = 61kHz
TA = 25 C
15
INPUT FREQUENCY – kHz
30.5
Figure 13. Effective Num ber of Bits vs. Frequency
Total H ar m onic D istor tion (TH D )
T HD is the ratio of the rms sum of harmonics to the rms value
of the fundamental. For the AD7880, T HD is defined as:
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD = 20 log
(3)
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. T he T HD is also derived from the FFT plot of
the ADC output spectrum.
Inter m odulation D istor tion
Figure 14. IMD Plot
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second or-
der terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
P eak H ar m onic or Spur ious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
REV. 0
–8–
AD7880
MICRO P RO CESSO R INTERFACING
TIMER
T he AD7880 high speed bus timing allows direct interfacing to
real time digital signal processors, DSPs, as well as modern high
speed, 16-bit microprocessors. Suitable microprocessor inter-
faces are shown in Figures 15 through 20.
PA2
PA0
ADDRESS BUS
ADDR
CONVST
CS
AD 7880–AD SP -2100 Inter face
DECODE
Figure 15 shows an interface between the AD7880 and the
ADSP-2100. Conversion is initiated using a timer to drive the
CONVST input asynchronously to the microprocessor. T his al-
lows very accurate control of the sampling instant. When con-
version is complete, the AD7880 BUSY line goes high. An
inverter on this BUSY output drives the IRQ line low thus pro-
viding an interrupt to the ADSP-2100 when conversion is com-
pleted. T he conversion result is then read from the AD7880 into
the ADSP-2100 with the following instruction:
MEN
EN
TMS32010
AD7880*
RD
DEN
INT
BUSY
DB11
DB0
MR0 = DM(ADC)
D15
D0
DATA BUS
where MR0 is the ADSP-2100 MR0 Register and
where ADC is the AD7880 address.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7880–TMS32010 Interface
AD 7880–TMS320C25 Inter face
DMA13
DMA0
TIMER
ADDRESS BUS
Figure 17 shows an interface between the AD7880 and the
T MS320C25. As with the two previous interfaces, conversion is
initiated with a timer, and the processor is interrupted when the
conversion sequence is completed. T he T MS320C25 does not
have a separate RD output to drive the AD7880 RD input di-
rectly. T his has to be generated from the processor STRB and
R/W outputs with the addition of some logic gates. T he RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7880 using the follow-
ing instruction:
CONVST
ADDR
DECODE
CS
DMS
EN
AD7880*
ADSP-2100
(ADSP-2101/
ADSP-2102)
DMRD (RD)
IRQn
RD
BUSY
IN D,ADC
DB11
DB0
where D is Data Memory Address and
where ADC is the AD7880 address.
DMD15
DMD0
DATA BUS
TIMER
A15
* ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
A0
Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102)
Interface
ADDR
CONVST
DECODE
CS
EN
AD 7880-AD SP -2101/AD SP -2102 Inter face
IS
T he interface outlined in Figure 15 also forms the basis for an
interface between the AD7880 and the ADSP-2101/ADSP-2102.
T he READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. T he instruction used to read a conversion result is as out-
lined for the ADSP-2100.
AD7880*
TMS320C25
BUSY
INTn
STRB
R/W
RD
READY
MSC
DB11
DB0
AD 7880-TMS32010 Inter face
An interface between the AD7880 and the T MS32010 is shown
in Figure 16. Once again the conversion is initiated using an ex-
ternal timer and the T MS32010 is interrupted when conversion
is completed. T he following instruction is used to read the con-
version result from the AD7880:
D15
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7880–TMS320C25 Interface
IN D,ADC
Some applications may require that the conversion be initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7880 CONVST from the address bus so that
where D is Data Memory Address and
where ADC is the AD7880 address.
–9–
REV. 0
AD7880
a write operation starts a conversion. Data is read at the end of
the conversion sequence as before. Figure 19 shows an example
of initiating conversion using this method. A similar implemen-
tation can be used for DSPs. Note that for all interfaces, a read
operation should not be attempted during conversion.
ADDRESS BUS
ADDR
DECODE
8086
CS
AD 7880–MC68000 Inter face
AD7880*
An interface between the AD7880 and the MC68000 is shown
in Figure 18. As before, conversion is initiated using an external
timer. T he AD7880 BUSY line can be used to interrupt the
processor or, alternatively, software delays can ensure that con-
version has been completed before a read to the AD7880 is at-
tempted. Because of the nature of its interrupts, the 68000
requires additional logic (not shown in Figure 18) to allow it to
be interrupted correctly. For further information on 68000 in-
terrupts, consult the 68000 users manual.
ALE
LATCH
CONVST
RD
WR
RD
DB11
DB0
AD15
AD0
ADDRESS/DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
T he MC68000 AS and R/W outputs are used to generate a
separate RD input signal for the AD7880. CS is used to drive
the 68000 DTACK input to allow the processor to execute a
normal read operation to the AD7880. T he conversion results
are read using the following 68000 instruction:
Figure 19. AD7880–8086 Interface
AD 7880–6809 Inter face
T he AD7880 can also interface quite easily with 8-bit micro-
processors. T he 12-bit parallel data output from the AD7880
can be read into the microprocessor as an 8+4 byte structure.
Figure 20 shows an interface to the MC6809 8-bit microproces-
sor. As in previous cases, conversion is initiated using an exter-
nal timer. At the end of conversion, BUSY triggers a one-shot
which drives the IRQ interrupt input of the microprocessor. A
double read is then performed to two unique addresses. T he
first read fetches the lower 8 bits (DB0–DB7) and loads the
74HC374 latch with the upper 4 bits (DB8–DB11). T he sec-
ond read fetches these upper 4 bits.
MOVE.W ADC, D0
where D0 is the 68000 D0 register
where ADC is the AD7880 address
TIMER
A15
A0
ADDRESS BUS
MC68000
ADDR
CONVST
DECODE
CS
RD
AS
EN
DTACK
A15
AD7880*
TIMER
ADDRESS BUS
A0
R/W
ADDR
DECODE
CONVST
DB11
DB0
MC6809
CS
AD7880*
D15
D0
R/W
E
DATA BUS
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
ONE
SHOT
IRQ
BUSY
Figure 18. AD7880–MC68000 Interface
AD 7880–8086 Inter face
CLK
D3
D0
OE
DB11
DB8
DB7
Q3
Q0
Figure 19 shows an interface between the AD7880 and the
8086 microprocessor. Unlike the previous interface examples,
the microprocessor initiates conversion. T his is achieved by gat-
ing the 8086 WR signal with a decoded address output (differ-
ent to the AD7880 CS address). Conversion is initiated and the
result is read from the AD7880 using the following instruction:
74HC374
DB0
D7
D0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
MOV AX, ADC
where AX is the 8086 accumulator and
where ADC is the AD7880 address
Figure 20. AD7880–6809 Interface
REV. 0
–10–
AD7880
AP P LICATIO N H INTS
LK2
A
B
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
T he AD7880’s comparator is required to make bit decisions on
an LSB size of 1.22 mV. T o achieve this, the designer must be
conscious of noise both in the ADC itself and in the preceding
analog circuitry. Switching mode power supplies are not recom-
mended, as the switching spikes will feed through to the com-
parator causing noisy code transitions. Other causes of concern
are ground loops and digital feedthrough from microprocessors.
T hese are factors which influence any ADC, and a proper PCB
layout which minimizes these effects is essential for best
performance.
V+
V+
VDD
C2
0.1µF
C1
10µF
ANALOG
INPUT
LK1
V+
SKT1
+
–
IC1
V–
TO ADC
C4
0.1µF
C3
10µF
LAYO UT H INTS
V–
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. T ake
care not to run digital tracks alongside analog signal tracks.
Guard (screen) the analog input with AGND.
A B
LK3
Figure 21. Analog Input Buffering
When it is required to drive the AD7880 with the 0 V to 10 V
input range, an external supply must be connected to V+ (see
Figure 21).
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7880 AGND pin or as
close as possible to the AD7880. Connect all other grounds and
the AD7880 DGND to this single analog ground point. Do not
connect any other digital grounds to this analog ground point.
In bipolar operation, positive and negative supplies must be
connected to V+ and V–.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. T he use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise. T he circuit layout of Fig-
ures 26 and 27 have both analog and digital ground planes
which are kept separated and only joined together at the
AD7880 AGND pin.
T he AD711 is a general purpose op amp which could be used
to drive the analog input of the AD7880.
P O WER-D O WN CO NTRO L (MO D E INP UT)
T he AD7880 is designed for systems which need to have mini-
mum power consumption. T his includes such applications as
hand held, portable battery powered systems and remote moni-
toring systems. As well as consuming minimum power under
normal operating conditions, typically 20 mW, the AD7880
can be put into a power-down or sleep mode when not required
to convert signals. When in this power-down mode, the
AD7880 consumes approximately 2 mW of power.
NO ISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
T he AD7880 is powered down by bringing the MODE input
pin to a Logic Low in conjunction with keeping the RD input
control High. T he AD7880 will remain in the power-down
mode until MODE is brought to a Logic High again. T he
MODE input should be driven with CD4000 or HCMOS logic
levels.
ANALO G INP UT BUFFERING
T o achieve specified performance, it is recommended that the
analog input (VINA, VINB) be driven from a low impedance
source. T his necessitates the use of an input buffer amplifier.
T he choice of op amp will be a function of the particular appli-
cation and the desired analog input range. T he data acquisition
circuit, described in this data sheet allows for various op amp
configurations. Figure 21 shows the analog input buffer circuit.
It is recommended that one “dummy” conversion be imple-
mented before reading conversion data from the AD7880 after
it has been in the power-down mode. T his is required to reset
all internal logic and control circuitry. In a remote monitoring
system where, say, 10 conversions are required to be taken with
a sampling interval of 1 second, an additional 11th conversion
must be carried out. Figure 22 gives a plot of power consumption
T he options available to drive the supply of the op amp are:
Single +5 V (derived from PCB 5 V supply)
CONVERTING
CONVERTING
20
POWER
CONSUMPTION – mW
Dual Supply (externally supplied to V+ and V–)
±5 V, ±12 V or ±15 V
POWER-DOWN
POWER-DOWN
1.65 x 10 –4
2
0
1
2
T he simplest configuration is the 0 V to 5 V range of Figure 5.
A single supply 5 V op amp is recommended for such an imple-
mentation. T his will allow for operation of the AD7880 in the 0
V to 5 V unipolar range without supplying an external supply to
V+ and V–. T he 5 V supply is derived from the systems
+5 V VDD supply.
TIME – secs
Figure 22. Power Consum ption for Norm al Operation
and Power-Down Operation vs. Tim e
–11–
REV. 0
AD7880
as a function of time for such operation. T he total conversion
time for each cycle is 11 × 15 µs (where 15 µs is the time taken
for a single conversion) corresponding to 1.65 × 10–4 secs.
Hence:
LK1
Connects the analog input to a buffer amplifier. T he
analog input may also be connected to a component
grid for signal conditioning.
LK2, LK3 Allows for various op amp power supplies to be
used to drive the input buffer of the AD7880. Ex-
ternal supplies may be connected to V+ and V–.
Alternatively, the AD7880’s +5 V system supply
and AGND can be selected to drive a single supply
op amp.
Average Power
= PowerCONVERT ING + PowerPOWER-DOWN
= {20 mW × (1.65 × 10–4)/(10)}
+ {2 mW × (9.9998)/(10)}
= 2.029 mW
LK4
Configures the various analog input ranges, 0 V to
5 V, 0 V to 10 V or ±5 V.
AD 7880 D ATA ACQ UISITIO N LAYO UT
Figure 24 shows the AD7880 in a data acquisition circuit. T he
corresponding printed circuit board (PCB) layout and
silkscreen are shown in Figures 25 to 27.
LK5
Selects reference input to VREF of AD7880. Nor-
mally connected to VDD. An external reference
could also be wired in.
T he only additional component required for a full data acquisi-
tion system is an antialiasing filter. T here is a component grid
provided near the analog input on the PCB which may be used
for such a filter or any other input conditioning circuitry. T o fa-
cilitate this option there is a shorting link (labeled LK1 on the
PCB) on the analog input track. With LK1 in place, the analog
input connects to the buffer amplifier driving the AD7880.
With LK1 removed, a wire link is needed to connect the analog
input to the PCB component grid.
LK6
LK7
Selects power-down or sleep mode. T he shorting
plug is connected to VDD for normal operation.
Connects the AD7880 RD input directly to the RD
input of SKT 4 or to a decoded STRB and R/W
input. T his shorting plug setting depends on the
microprocessor, e.g., the T MS320C25 requires a
decoded RD signal.
1
3
2
R/W
STRB
N/C
4
6
RD
CS
INTERFACE CO NNECTIO NS
T he data acquisition board contains a parallel connection port
labeled SKT 4. T his is a 26-contact IDC Connector and pro-
vides for direct microprocessor connection to the board. T his
connector, the pinout of which is shown in Figure 23, contains
all data, control and status signals of the AD7880 (with the ex-
ception of the CONVST and the CLKIN inputs both of which
are provided via SKT 2 and SKT 3 respectively). It also contains
decoded R/W and STRB inputs which are necessary for inter-
facing to many microprocessors including the T MS320C25 and
the Motorola 68000 series. Link LK7 selects RD directly or al-
ternatively, the decoded version. Note that the AD7880 CS in-
put must be decoded prior to the AD7880 evaluation board.
5
N/C
BUSY
7
8
BUSY
N/C
N/C
DB10
DB8
DB6
DB4
DB2
DB0
9
10
12
14
16
18
20
11
13
15
DB11
DB9
DB7
DB5
DB3
DB1
17
19
21
23
25
22
24
26
SKT 1, SKT 2 and SKT 3 are three sub-miniature connectors
(SMC) which provide input connections for the analog input,
the CONVST input and the CLKIN input. T hree different in-
put ranges can be accepted by the AD7880 each of which is
configured by selecting shorting plug options A, B or C of LK4.
Position A corresponds to the 0 V to 5 V unipolar configuration
of Figure 5, position B corresponds to the bipolar ±5 V configu-
ration of Figure 7 and position C allows for a 0 V to +10 V uni-
polar range as shown in Figure 6.
+
+
5V
5V
GND
GND
Figure 23. SKT4, IDC Connector Pinout
CO MP O NENT LIST
IC1
Op Amp*
IC2
AD7880 Analog-to-Digital Converter
74HC00 Quad NAND Gate
10 µF Capacitors
IC3
P O WER SUP P LY CO NNECTIO NS
C1, C3, C5
C2, C4, C6, C7
R1, R2
T he PCB requires a single +5 V power supply (labeled VDD).
Good decoupling allows this supply to drive the AD7880 VDD
which also drives the VREF input as well as the op amp power
supply. In circumstances where bipolar ±5 V or a unipolar 0 V
to 10 V input ranges are required, provision has been allowed
for the connection of separate op amp power supplies (±15 V,
±12 V, ±5 V, etc.) to V+ and V–. LK2 and LK3 shorting links
allow for the selection of user defined op amp power supplies or
the on-board single +5 V supply.
0.1 µF Capacitors
10 kΩ Pull-up Resistors
Shorting Links
LK1, LK2, LK3
LK4, LK5, LK6
LK7
SKT1, SKT2, SKT3 Sub-Miniature Connectors
Vendor No: Sealectro 50-051-0000 (Socket)
Vendor No: Sealectro 50-007-0000 (Plug)
SKT 4
26-Contact (2 Row) IDC Connector
LINK O P TIO NS
T here are seven link options which must be set before using the
board. T hese are outlined below:
NOT E
*See ANALOG INPUT BUFFERING section.
.
REV. 0
–12–
AD7880
Figure 24. Data Acquisition Circuit Using the AD7880
Figure 25. PCB Silkscreen for Figure 24
–13–
REV. 0
AD7880
Figure 26. PCB Com ponent Side Layout for Figure 24
Figure 27. PCB Solder Side Layout for Figure 24
REV. 0
–14–
AD7880
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-Lead P lastic D IP (N-24)
1.228 (31.19)
1.226 (31.14)
24
13
12
0.260 ± 0.001
(6.61 ± 0.03)
1
0.32 (8.128)
0.30 (7.62)
PIN 1
0.130 (3.30)
0.128 (3.25)
SEATING
PLANE
0.011 (0.28)
0.009 (0.23)
0.02 (0.5)
0.11 (2.79)
0.09 (2.28)
0.07 (1.78)
0.05 (1.27)
0.016 (0.41)
15°
0
NOTES:
1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
24-Lead Cerdip (Q-24)
24
13
12
0.295
(7.493)
MAX
1
0.320 (8.128)
0.291 (7.4)
1.290 (32.77) MAX
0.225
(5.715)
MAX
0.180
(4.572)
MAX
SEATING
PLANE 0.125
(3.175)
0.070 (1.778)
0.020 (0.508)
0.012 (0.305)
MIN
0.110 (2.794)
0.009 (2.286)
TYP
0.021 (0.533)
0.015 (0.381)
TYP
0.065 (1.651)
0.055 (1.397)
15°
0°
0.008 (0.203)
1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
2. CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
24-Lead SO IC (R-24)
0.614 (15.6)
0.598 (15.2)
24
13
0.299 (7.6)
0.291 (7.4)
0.419 (10.65)
0.394 (10.00)
1
12
PIN 1
0.104 (2.65)
0.093 (2.35)
0.03 (0.75)
0.01 (0.25)
8°
0°
0.05
(1.27)
BSC
0.019 (0.49)
0.014 (0.35)
0.012 (0.3)
0.004 (0.1)
0.05 (1.27)
0.013 (0.32)
0.009 (0.23)
0.016 (0.40)
–15–
REV. 0
–16–
相关型号：
AD7880CR-REEL
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24, SOIC-24, Analog to Digital Converter
ADI
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