AD7889ARS-2 [ADI]
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, SSOP-16, Analog to Digital Converter;
| 型号： | AD7889ARS-2 |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, SSOP-16, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总41页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage Controller for Touch Screens
AD7879/AD7889
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
/REF
CC
4-wire touch screen interface
1.6 V to 3.6 V operation
X– Y– X+ Y+
Median and averaging filter to reduce noise
Automatic conversion sequencer and timer
User-programmable conversion parameters
Auxiliary analog input/battery monitor (0.5 V to 5 V)
1 optional GPIO
X+
X–
REF–
REF–
REF+
Y+
Y–
Interrupt outputs (INT, PENIRQ)
Touch-pressure measurement
Wake-up on touch function
12-BIT
SAR ADC
RESULT
REGISTERS
GND
TEMPERATURE
SENSOR
Shutdown mode: 6 μA maximum
12-ball, 1.6 mm × 2 mm WLCSP
16-lead, 4 mm × 4 mm LFCSP
AD7879/
AD7879-1/
AD7889/
CONTROL
REGISTERS
AD7889-1
APPLICATIONS
Personal digital assistants
Smart handheld devices
Touch screen monitors
Point-of-sale terminals
Medical devices
SEQUENCER
AND TIMER
SERIAL PORT
TO
RESULT
REGISTERS
CS/
DIN/ DOUT/ SCL
ADD0 ADD1 SDA
Cell phones
Figure 1.
GENERAL DESCRIPTION
The AD7879/AD7889 are 12-bit successive approximation
analog-to-digital converters (SAR ADCs) with a synchronous
serial interface and low on-resistance switches for driving 4-wire
resistive touch screens. The AD7879/AD7889 work with a very
low power supply—a single 1.6 V to 3.6 V supply—and feature
throughput rates of 105 kSPS. The devices include a shutdown
mode that reduces current consumption to less than 6 μA.
The AD7879/AD7889 have a programmable pin that can operate
as an auxiliary input to the ADC, as a battery monitor, or as a
GPIO. In addition, a programmable interrupt output can operate
in three modes: as a general-purpose interrupt to signal when
DAV
new data is available (
INT
), as an interrupt to indicate when
limits are exceeded (
), or as a pen-down interrupt when the
PENIRQ
screen is touched (
). The AD7879/AD7889 offer temp-
erature measurement and touch-pressure measurement.
To reduce the effects of noise from LCDs and other sources, the
AD7879/AD7889 contain a preprocessing block. The prepro-
cessing function consists of a median filter and an averaging
filter. The combination of these two filters provides a more robust
solution, discarding the spurious noise in the signal and keeping
only the data of interest. The size of both filters is programmable.
Other user-programmable conversion controls include variable
acquisition time and first conversion delay; up to 16 averages
can be taken per conversion. The AD7879/AD7889 can run in
slave mode or standalone (master) mode, using an automatic
conversion sequencer and timer.
The AD7879 is available in a 12-ball, 1.6 mm × 2 mm WLCSP
and in a 16-lead, 4 mm × 4 mm LFCSP. The AD7889 is available
in a backside-coated version of the WLCSP. Both parts support
an SPI interface (AD7879/AD7889) or an I2C interface
(AD7879-1/AD7889-1).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
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Last content update 08/29/2013 03:44 pm
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AD7879W: Low Voltage Controller for Touch Screens Data Sheet
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Screen Applications
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EVALUATION KITS & SYMBOLS & FOOTPRINTS
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View the Evaluation Boards and Kits page for the AD7879
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AD7889
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AD7879/AD7889
TABLE OF CONTENTS
Features .............................................................................................. 1
Auxiliary Input ........................................................................... 18
Battery Input ............................................................................... 18
Limit Comparison...................................................................... 18
GPIO ............................................................................................ 18
Conversion Timing ........................................................................ 20
Register Map ................................................................................... 21
Detailed Register Descriptions ..................................................... 22
Control Registers ............................................................................ 26
Control Register 1 ...................................................................... 26
Control Register 2 ...................................................................... 28
Control Register 3 ...................................................................... 29
Interrupts..................................................................................... 30
Synchronizing the AD7879/AD7889 to the Host CPU ........ 31
Serial Interface ................................................................................ 32
SPI Interface................................................................................ 32
I2C-Compatible Interface .......................................................... 34
Grounding and Layout .................................................................. 37
Lead Frame Chip Scale Packages ............................................. 37
WLCSP Assembly Considerations........................................... 37
Outline Dimensions....................................................................... 38
Ordering Guide .......................................................................... 39
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
SPI Timing Specifications (AD7879/AD7889)......................... 4
I2C Timing Specifications (AD7879-1/AD7889-1).................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Touch Screen Principles ............................................................ 13
Measuring Touch Screen Inputs............................................... 14
Touch-Pressure Measurement .................................................. 15
Temperature Measurement ....................................................... 15
Median and Averaging Filters....................................................... 17
AUX/VBAT/GPIO Pin................................................................... 18
REVISION HISTORY
11/10—Rev. B to Rev. C
Changes to GPIO Interrupt Enable (Bit 12, Control Register 3,
Address 0x03) Section ................................................................... 19
Changes to Table 13 ....................................................................... 22
Changes to ADC Channel (Control Register 1, Bits[14:12])
Section.............................................................................................. 26
Changes to Power Management (Control Register 2,
Changes to Table 2............................................................................ 3
Added Conversion Timing Section.............................................. 20
Added Figure 34.............................................................................. 29
1/10—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 37
Changes to Ordering Guide .......................................................... 38
Bits[15:14]) Section........................................................................ 27
DAV
Changes to
—Data Available Interrupt Section................. 29
INT
Changes to
—Out-of-Limit Interrupt Section .................... 29
3/09—Rev. 0 to Rev. A
Changes to Writing Data Section................................................. 31
Changes to Reading Data Section and Figure 40....................... 32
Changes to Figure 41...................................................................... 33
Changes to Writing Data over the I2C Bus Section.................... 34
Changes to Figure 44...................................................................... 35
Updated Outline Dimensions....................................................... 37
Changes to Ordering Guide.......................................................... 38
Added AD7889 and Backside-Coated WLCSP......... Throughout
Change to Battery Monitor, Input Voltage Range Parameter..... 3
Changes to Table 4............................................................................ 6
Added Thermal Resistance Section and Table 5;
Renumbered Sequentially................................................................ 6
Changes to Pin Configurations and Function Descriptions
Section................................................................................................ 7
Added Table 7.................................................................................... 8
Changes to First Method Section ................................................. 15
Changes to Median and Averaging Filters Section .................... 17
10/08—Revision 0: Initial Version
Rev. C | Page 2 of 40
AD7879/AD7889
SPECIFICATIONS
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC ACCURACY
Resolution
12
11
Bits
Bits
LSB
No Missing Codes
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Negative DNL
12
±3
LSB size = 390 µV.
LSB size = 390 µV.
−0.99
2
±±
LSB
LSB
LSB
LSB
µV rms
dB
MHz
MHz
Positive DNL
Offset Error1, 2
±2
Gain Error1, 2
±4
Noise3
70
±0
2
Power Supply Rejection3
Internal Clock Frequency
Internal Clock Accuracy
SWITCH DRIVERS
On Resistance1
1.8
2.2
Y+, X+
Y−, X−
±
5
Ω
Ω
ANALOG INPUTS
Input Voltage Range
DC Leakage Current
Input Capacitance
Accuracy
0
VCC
V
±0.1
30
0.3
µA
pF
%
TEMPERATURE MEASUREMENT
Temperature Range
Resolution
−40
+85
°C
°C
°C
0.3
±2
Accuracy2
Calibrated at 25°C.
Uncalibrated accuracy.
VIN = 0 V or VCC.
BATTERY MONITOR
Input Voltage Range
Input Impedance3
Accuracy
0.5
5
5
V
kΩ
%
1±
2
LOGIC INPUTS (DIN, SCL, CS, SDA, GPIO)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VCC
V
V
µA
pF
0.3 × VCC
0.01
10
3
Input Capacitance, CIN
LOGIC OUTPUTS (DOUT, GPIO, SCL, SDA, INT)
Output High Voltage, VOH
VCC − 0.2
V
Output Low Voltage, VOL
0.4
V
Floating-State Leakage Current
Floating-State Output Capacitance2
CONVERSION RATE3
±0.1
5
µA
pF
Conversion Time
9.5
µs
Including 2 µs of acquisition time, MAV
filter off. 2 µs of additional time is required
if MAV filter is on.
Throughput Rate
105
kSPS
Rev. C | Page 3 of 40
AD7879/AD7889
Parameter
Min
Typ
Max
3.±
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VCC
ICC
1.±
2.±
V
Specified performance.
Digital inputs = 0 V or VCC.
ADC on, PM = 10.
ADC and temperature sensor are off; the
reference and oscillator are on; PM = 01
or 11.
Converting Mode
Static
480
40±
±50
µA
µA
Shutdown Mode
0.5
±
µA
PM = 00.
1 See the Terminology section.
2 Guaranteed by characterization; not production tested.
3 Sample tested at 25°C to ensure compliance.
SPI TIMING SPECIFICATIONS (AD7879/AD7889)
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V.
Table 2.
Parameter1
Limit
5
5
Unit
Description
fSCL
t1
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
CS falling edge to first SCL falling edge
SCL high pulse width
SCL low pulse width
DIN setup time
DIN hold time
DOUT access time after SCL falling edge
CS rising edge to DOUT high impedance
SCL rising edge to CS high
t2
t3
t4
t5
t±
t7
20
20
15
15
20
1±
15
t8
1 Guaranteed by design; not production tested.
CS
t1
t2
t8
t3
15
15
1
2
3
16
1
2
16
SCL
t4
t5
LSB
MSB
DIN
t6
t7
DOUT
MSB
LSB
Figure 2. Detailed SPI Timing Diagram
Rev. C | Page 4 of 40
AD7879/AD7889
I2C TIMING SPECIFICATIONS (AD7879-1/AD7889-1)
VCC = 1.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
timed from a voltage level of 1.4 V.
Table 3.
Parameter1
Limit
400
0.±
1.3
0.±
100
300
0.±
0.±
1.3
Unit
Description
fSCL
t1
t2
t3
t4
t5
t±
t7
t8
tR
tF
kHz max
µs min
µs min
µs min
ns min
ns min
µs min
µs min
µs min
ns max
ns max
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus-free time between stop and start conditions, tBUF
Clock/data rise time
300
300
Clock/data fall time
1 Guaranteed by design; not production tested.
tR
tF
t1
t2
SCL
t3
t7
t1
t6
t5
t4
SDA
t8
STOP START
START
STOP
Figure 3. Detailed I2C Timing Diagram
Rev. C | Page 5 of 40
AD7879/AD7889
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Parameter
Rating
VCC to GND
Analog Input Voltage to GND
AUX/VBAT to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1 10 mA
−0.3 V to +3.± V
−0.3 V to VCC + 0.3 V
−0.3 V to +5 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
Table 5. Thermal Resistance
Package Type1
12-Ball WLCSP
1±-Lead LFCSP
θJA
75
30.4
Unit
°C/W
°C/W
1 4-layer board.
ESD Rating (X+, Y+, X−, Y−)
200µA
I
OL
Air Discharge Human Body Model
Contact Human Body Model
ESD Rating (All Other Pins)
Human Body Discharge
Field-Induced Charged Device Model
Machine Model
15 kV
10 kV
TO OUTPUT
PIN
1.4V
C
50pF
4 kV
1 kV
0.2 kV
L
200µA
I
OH
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−±5°C to +150°C
150°C
Figure 4. Circuit Used for Digital Timing
Power Dissipation
WLCSP (4-Layer Board)
ESD CAUTION
8±± mW
LFCSP (4-Layer Board)
2.138 W
IR Reflow Peak Temperature
Lead Temperature (Soldering 10 sec)
2±0°C (±0.5°C)
300°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page ± of 40
AD7879/AD7889
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
BALL A1
INDICATOR
1
2
3
1
2
3
AUX/
VBAT/
GPIO
AUX/
VBAT/
GPIO
VCC/REF
VCC/REF
X+
X+
A
B
A
B
PENIRQ/
INT/DAV
PENIRQ/
INT/DAV
Y+
ADD0
Y+
CS
DOUT
SCL
DIN
GND
X–
Y–
SDA ADD1
X–
Y–
C
D
C
D
SCL
GND
TOP VIEW
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
(BALL SIDE DOWN)
Not to Scale
Figure 5. AD7879/AD7889 WLCSP Pin Configuration
Figure 6. AD7879-1/AD7889-1 WLCSP Pin Configuration
Table 6. Pin Function Descriptions, WLCSP
Ball No.
AD7879/ AD7879-1/
AD7889
AD7889-1
Mnemonic
Description
1A
1A
AUX/VBAT/GPIO This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure-
ment input to the ADC ( VBAT ), or as a general-purpose digital input/output (GPIO).
1B
1B
PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure-
ment exceeds the preprogrammed limits (INT), or when new data is available in the registers
(DAV). Active low, internal 50 kΩ pull-up resistor.
1C
N/A
1C
1D
2A
N/A
2B
DOUT
SDA
SCL
VCC/REF
CS
SPI Serial Data Output for the AD7879/AD7889.
I2C Serial Data Input and Output for the AD7879-1/AD7889-1.
Serial Interface Clock Input.
Power Supply Input and ADC Reference.
Chip Select for the SPI Serial Interface on the AD7879/AD7889. Active low.
N/A
1D
2A
2B
N/A
ADD0
I2C Address Bit 0 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine
an address for the AD7879-1/AD7889-1 (see Table 25).
2C
N/A
N/A
2C
DIN
ADD1
SPI Serial Data Input to the AD7879/AD7889.
I2C Address Bit 1 for the AD7879-1/AD7889-1. This pin can be tied high or low to determine
an address for the AD7879-1/AD7889-1 (see Table 25).
2D
2D
GND
Ground. Ground reference point for all circuitry on the AD7879/AD7889. All analog input
signals and any external reference signal should be referred to this voltage.
3A
3B
3C
3D
3A
3B
3C
3D
X+
Y+
X−
Y−
Touch Screen Input Channel.
Touch Screen Input Channel.
Touch Screen Input Channel.
Touch Screen Input Channel.
Rev. C | Page 7 of 40
AD7879/AD7889
PIN 1
PIN 1
INDICATOR
INDICATOR
12 PENIRQ/INT/DAV
11 NC
12 PENIRQ/INT/DAV
11 NC
Y+
NC
NC
X–
1
2
3
4
Y+
NC
NC
X–
1
2
3
4
AD7879
TOP VIEW
(Not to Scale)
AD7879-1
TOP VIEW
(Not to Scale)
10 NC
10 NC
9
DOUT
9
SDA
NOTES
1. NC = NO CONNECT
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
Figure 7. AD7879 LFCSP Pin Configuration
Figure 8. AD7879-1 LFCSP Pin Configuration
Table 7. Pin Function Descriptions, LFCSP
Pin No.
AD7879
AD7879-1 Mnemonic
Description
1
1
Y+
NC
Touch Screen Input Channel.
No Connect.
2, 3, 10, 11
2, 3, 10, 11
4
5
4
5
X−
Y−
Touch Screen Input Channel.
Touch Screen Input Channel.
±
N/A
N/A
±
DIN
ADD1
SPI Serial Data Input to the AD7879.
I2C Address Bit 1 for the AD7879-1. This pin can be tied high or low to determine an address
for the AD7879-1 (see Table 25).
7
7
GND
Ground. Ground reference point for all circuitry on the AD7879. All analog input signals and
any external reference signal should be referred to this voltage.
8
8
SCL
Serial Interface Clock Input.
9
N/A
12
N/A
9
12
DOUT
SDA
SPI Serial Data Output for the AD7879.
I2C Serial Data Input and Output for the AD7879-1.
PENIRQ/INT/DAV Interrupt Output. This pin is asserted when the screen is touched (PENIRQ), when a measure-
ment exceeds the preprogrammed limits (INT), or when new data is available in the registers
(DAV). Active low, internal 50 kΩ pull-up resistor.
13
13
AUX/VBAT/GPIO
This pin can be programmed as an auxiliary input to the ADC (AUX), as a battery measure-
ment input to the ADC ( VBAT ), or as a general-purpose digital input/output (GPIO).
14
N/A
14
CS
Chip Select for the SPI Serial Interface on the AD7879. Active low.
I2C Address Bit 0 for the AD7879-1. This pin can be tied high or low to determine an address
for the AD7879-1 (see Table 25).
N/A
ADD0
15
1±
15
1±
VCC/REF
X+
Power Supply Input and ADC Reference.
Touch Screen Input Channel.
EP
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be soldered
to the ground plane.
Rev. C | Page 8 of 40
AD7879/AD7889
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 2.6 V, fSCL = 2 MHz, unless otherwise noted.
475
470
465
460
455
450
445
440
1.0
0.8
0.6
0.4
0.2
2.6V
0
3.6V
–0.2
–0.4
–0.6
–0.8
–1.0
1.6V
435
430
425
–40
–25
–10
10
25
40
55
70
85
–40
–25
–10
10
25
40
55
70
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Supply Current vs. Temperature
Figure 12. Change in ADC Gain vs. Temperature
700
600
500
400
300
200
100
0
1.0
0.8
0.6
0.4
1.6V
0.2
2.6V
0
–0.2
–0.4
–0.6
–0.8
–1.0
3.6V
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
(V)
–40
–25
–10
10
25
40
55
70
85
V
TEMPERATURE (°C)
CC
Figure 10. Supply Current vs. VCC
Figure 13. Change in ADC Offset vs. Temperature
4.0
3.5
3.0
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–40
–25
–10
10
25
50
75
100
0
512
1024
1536
2048
2560
3072
3584
4096
TEMPERATURE (°C)
CODE
Figure 11. Full Power-Down IDD vs. Temperature
Figure 14. ADC INL
Rev. C | Page 9 of 40
AD7879/AD7889
1.0
0.8
0.6
0.4
0.2
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
–0.2
–0.4
X+ TO V
Y+ TO V
CC
–0.6
–0.8
–1.0
CC
X– TO GND
Y– TO GND
1
501
1001 1501
2001 2501 3001 3501 4001
CODE
–40
–25
–10
10
25
40
55
70
85
TEMPERATURE (°C)
Figure 15. ADC DNL
Figure 17. Switch On Resistance vs. Temperature
(X+, Y+: Pin to VCC; X−, Y−: Pin to GND)
7
6
5
4
3
2
1
0
2370
2369
2368
2367
2366
2365
2364
2363
X+ TO V
Y+ TO V
X– TO GND
Y– TO GND
CC
CC
2362
2361
2360
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
(V)
–40 –25 –15 –5
5
15 25 35 45 55 65 75 85
V
TEMPERATURE (°C)
CC
Figure 16. Switch On Resistance vs. VCC
(X+, Y+: Pin to VCC; X−, Y−: Pin to GND)
Figure 18. ADC Code vs. Temperature (Fixed Analog Input)
Rev. C | Page 10 of 40
AD7879/AD7889
1400
1200
1000
800
600
400
200
0
MEAN: –1.98893
SD: 0.475534
250
200
150
100
50
0
–4
–3
–2
–1
0
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
ERROR (%)
V
CC
Figure 19. Temperature Code vs. VCC for 25°C
Figure 21. Typical Uncalibrated Accuracy for the Battery Channel (25°C)
0
–20
–40
SNR = 61.58dB
THD = 72.34dB
–60
–80
–100
–120
–140
–160
FREQUENCY (Hz)
Figure 20. Typical FFT Plot for the Auxiliary Channels at 25 kHz Sampling
Rate and 1 kHz Input Frequency
Rev. C | Page 11 of 40
AD7879/AD7889
TERMINOLOGY
Gain Error
Differential Nonlinearity (DNL)
Gain error is the deviation of the last code transition
(111 … 110 to 111 … 111) from the ideal (VREF − 1 LSB)
after the offset error has been calibrated out.
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
Offset Error
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale at 1 LSB below
the first code transition and full scale at 1 LSB above the last
code transition.
Offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (AGND + 1 LSB).
On Resistance
On resistance is a measure of the ohmic resistance between the
drain and the source of the switch drivers.
Rev. C | Page 12 of 40
AD7879/AD7889
THEORY OF OPERATION
PLASTIC FILM WITH
TRANSPARENT, RESISTIVE
COATING ON BOTTOM SIDE
The AD7879/AD7889 are a complete 12-bit data acquisition
system for digitizing positional inputs from a 4-wire resistive
touch screen. To support this function, data acquisition on the
AD7879/AD7889 is highly programmable to ensure accurate
and noise-free results from the touch screen.
CONDUCTIVE ELECTRODE
ON BOTTOM SIDE
Y+
The core of the AD7879/AD7889 is a high speed, low power,
12-bit analog-to-digital converter (ADC) with an input multi-
plexer, on-chip track-and-hold, and on-chip clock. Conversion
results are stored in on-chip result registers. The results from
the auxiliary input or the battery input can be compared with
high and low limits stored in limit registers to generate an out-
X–
Y–
X+
INT
of-limit interrupt (
).
The AD7879/AD7889 also contain low resistance analog
switches to switch the X and Y excitation voltages to the touch
screen and to the on-chip temperature sensor. The high speed
SPI serial bus provides control of the devices, as well as com-
munication with the devices. The AD7879-1/AD7889-1 are
available with an I2C interface.
CONDUCTIVE ELECTRODE
ON TOP SIDE
PLASTIC FILM WITH
TRANSPARENT, RESISTIVE
COATING ON TOP SIDE
LCD SCREEN
Figure 22. Basic Construction of a Touch Screen
The Y layer has conductive electrodes running along the top
and bottom edges, allowing the application of an excitation
voltage down the Y layer from top to bottom.
Operating from a single supply from 1.6 V to 3.6 V, the AD7879/
AD7889 offer a throughput rate of 105 kHz. The device is avail-
able in a 1.6 mm × 2 mm, 12-ball wafer level chip scale package
(WLCSP) and in a 4 mm × 4 mm, 16-lead lead frame chip scale
package (LFCSP).
Provided that the layers are of uniform resistivity, the voltage
at any point between the two electrodes is proportional to the
horizontal position for the X layer and the vertical position for
the Y layer.
The AD7879/AD7889 have an on-chip sequencer that schedules
a sequence of preprogrammed conversions. The conversion
sequence starts automatically when the screen is touched or
at preset intervals, using the on-board timer.
When the screen is touched, the two layers make contact. If
only the X layer is excited, the voltage at the point of contact
and, therefore, the horizontal position, can be sensed at one of
the Y layer electrodes. Similarly, if only the Y layer is excited,
the voltage and, therefore, the vertical position, can be sensed
at one of the X layer electrodes. By switching alternately
between X and Y excitation and measuring the voltages, the
X and Y coordinates of the contact point can be determined.
To ensure that the AD7879/AD7889 work well with different
touch screens, the user can select the acquisition time. A
programmable delay ensures that the voltage on the touch
screen settles before a measurement is taken.
To help reduce noise in the system, the ADC takes up to 16
conversion results from each channel and writes the average of
the results to the register. To further improve the performance
of the AD7879/AD7889, the median filter can also be used if
there is noise present in the system.
In addition to measuring the X and Y coordinates, it is also
possible to estimate the touch pressure by measuring the
contact resistance between the X and Y layers. The AD7879/
AD7889 are designed to facilitate this measurement.
TOUCH SCREEN PRINCIPLES
A 4-wire touch screen consists of two flexible, transparent,
resistive-coated layers that are normally separated by a small
air gap (see Figure 22). The X layer has conductive electrodes
running down the left and right edges, allowing the application
of an excitation voltage across the X layer from left to right.
Rev. C | Page 13 of 40
AD7879/AD7889
Figure 23 shows an equivalent circuit of the analog input structure
of the AD7879/AD7889, showing the touch screen switches, the
main analog multiplexer, the ADC, and the dual 3-to-1 multi-
plexer that selects the reference source for the ADC.
The voltage seen at the input to the ADC in Figure 24 is
RY −
VIN =VCC
×
(1)
RYTOTAL
The advantage of the single-ended method is that the touch
screen excitation voltage is switched off when the signal is
acquired. Because a screen can draw over 1 mA, this is a
significant consideration for a battery-powered system.
V
CC
X+
X–
Y+
Y–
The disadvantage of the single-ended method is that voltage
drops across the switches can introduce errors. Touch screens
can have a total end-to-end resistance ranging from 200 Ω to
900 Ω. By taking the lowest screen resistance of 200 Ω and a
X– Y– GND X+ Y+
V
CC
INPUT
MUX
DUAL 3-TO-1 MUX
typical switch resistance of 14 Ω, the user can reduce the apparent
excitation voltage to 200/228 × 100 = 87% of its actual value. In
addition, the voltage drop across the low-side switch adds to the
ADC input voltage. This introduces an offset into the input
voltage; thus, it can never reach 0.
AUX/VBAT/GPIO
REF–
REF+
TEMPERATURE
SENSOR
12-BIT SUCCESSIVE
APPROXIMATION ADC
WITH TRACK-AND-HOLD
IN+
Ratiometric Method
Figure 23. Analog Input Structure
The ratiometric method illustrated in Figure 25 shows the
negative input of the ADC reference connected to Y− and the
positive input connected to Y+. Thus, the screen excitation
voltage provides the reference for the ADC. The input of the
ADC is connected to X+ to determine the Y position.
The AD7879/AD7889 can be set up to automatically convert
either specific input channels or a sequence of channels. The
results of the ADC conversions are stored in the result registers.
When measuring the ancillary analog inputs (AUX, TEMP, or
VBAT), the ADC uses a VCC reference and the measurement is
referred to GND.
V
CC
Y+
X+
MEASURING TOUCH SCREEN INPUTS
When measuring the touch screen inputs, it is possible to use
VCC as a reference or instead to use the touch screen excitation
voltage as the reference and to perform a ratiometric, differential
measurement. The differential method is the default method
REF+
ADC
REF–
INPUT
(VIA MUX)
TOUCH
SCREEN
Y–
DFR
and is selected by clearing the SER/
bit (Bit 9 in Control
Register 2) to 0. The single-ended method is selected by setting
this bit to 1.
GND
Figure 25. Ratiometric Conversion of Touch Screen Inputs
Single-Ended Method
For greater accuracy, the ratiometric method has two significant
advantages. One is that the reference to the ADC is provided
from the actual voltage across the screen; therefore, any voltage
dropped across the switches has no effect. The other advantage
is that because the measurement is ratiometric, it does not
matter if the voltage across the screen varies in the long term.
However, it must not change after the signal has been acquired.
Figure 24 illustrates the single-ended method for the Y position.
For the X position, the excitation voltage is applied to X+ and
X− and the voltage is measured at Y+.
V
CC
Y+
X+
V
REF
The disadvantage of the ratiometric method is that the screen
must be powered up at all times because it provides the reference
voltage for the ADC.
REF+
ADC
REF–
INPUT
(VIA MUX)
TOUCH
SCREEN
Y–
GND
Figure 24. Single-Ended Conversion of Touch Screen Inputs
Rev. C | Page 14 of 40
AD7879/AD7889
Second Method
TOUCH-PRESSURE MEASUREMENT
The second method requires the user to know the resistance of
the X-plate and Y-plate tablets. Three touch screen conversions
are required: a measurement of the X position (XPOSITION), the
Y position (YPOSITION), and the Z1 position.
The pressure applied to the touch screen by a pen or finger can
also be measured with the AD7879/AD7889 using some simple
calculations. The contact resistance between the X and Y plates
is measured, providing a good indication of the size of the
depressed area and, therefore, the applied pressure. The area of
the spot that is touched is proportional to the size of the object
touching it. The size of this resistance (RTOUCH) can be calculated
using two different methods.
The following equation also calculates the touch resistance
(RTOUCH):
R
R
TOUCH = RXPLATE × (XPOSITION/4096) × [(4096/Z1) − 1] −
YPLATE × [1 − (YPOSITION/4096)]
(3)
First Method
The first method requires the user to know the total resistance
of the X-plate tablet (RX). Three touch screen conversions are
required: measurement of the X position, XPOSITION (Y+ input);
measurement of the X+ input with the excitation voltage applied
to Y+ and X− (Z1 measurement); and measurement of the Y−
input with the excitation voltage applied to Y+ and X− (Z2
measurement). These three measurements are illustrated in
Figure 26.
TEMPERATURE MEASUREMENT
A temperature measurement option called the single-conversion
method is available on the AD7879/AD7889. The conversion
method requires only a single measurement on ADC Channel
001. The results are stored in the temperature conversion result
register (Address 0x0D). The AD7879/AD7889 do not provide
an explicit output of the temperature reading; the system must
perform some external calculations. This method is based on
an on-chip diode measurement.
The AD7879/AD7889 have two special ADC channel settings
that configure the X and Y switches for the Z1 and Z2 measure-
ments and store the results in the Z1 and Z2 result registers. The
Z1 measurement is selected by setting the CHNL ADD[2:0] bits
to 101 in Control Register 1 (Address 0x01); the result is stored
in the X+ (Z1) result register (Address 0x0A). The Z2 measurement
is selected by setting the CHNL ADD[2:0] bits to 100 in Control
Register 1 (Address 0x01); the result is stored in the Y− (Z2)
result register (Address 0x0B).
The acquisition time is fixed at 16 ms for temperature
measurement.
Conversion Method
The conversion method makes use of the fact that the tempera-
ture coefficient of a silicon diode is approximately −2.1 mV/°C.
However, this small change is superimposed on the diode forward
voltage, which can have a wide tolerance. Therefore, it is necessary
to calibrate by measuring the diode voltage at a known temperature
to provide a baseline from which the change in forward voltage
with temperature can be measured. This method provides a
resolution of approximately 0.3°C and a predicted accuracy
of 2°C.
The touch resistance (RTOUCH) can then be calculated using the
following equation:
R
TOUCH = (RXPLATE) × (XPOSITION/4096) × [(Z2/Z1) − 1]
(2)
MEASURE
X POSITION
The temperature limit comparison is performed on the result
in the temperature conversion result register (Address 0x0D),
which is the measurement of the diode forward voltage. The
values programmed into the high and low limits should be
referenced to the calibrated diode forward voltage to make
accurate limit comparisons.
X+
Y+
TOUCH
RESISTANCE
X–
Y+
Y–
X+
MEASURE
Z1 POSITION
TOUCH
RESISTANCE
Y–
Y+
X–
X+
TOUCH
RESISTANCE
Y–
X–
MEASURE
Z2 POSITION
Figure 26. Three Measurements Required for Touch Pressure
Rev. C | Page 15 of 40
AD7879/AD7889
Temperature Calculations
Example
If an explicit temperature reading in degrees Celsius is required,
calculate for the single-measurement method as follows:
Using VCC = 2.5 V as reference,
Degrees per LSB = (2.5/4096)/−2.1 × 10−3 = −0.291
1. Calculate the scale factor of the ADC in degrees per LSB.
The ADC output is 983 decimal at 25°C, equivalent to a diode
forward voltage of 0.6 V.
Degrees per LSB = ADC LSB size/−2.1 mV =
(VCC/4096)/−2.1 mV
The ADC output at TAMB is 880.
2. Save the ADC output, DCAL, at the calibration temperature,
∆T = (880 − 983) × −0.291 = 30°C
TCAL
3. Take the ADC reading, DAMB, at the temperature to be
measured, TAMB
.
TAMB = 25 + 30 = 55°C
.
4. Calculate the difference in degrees between TCAL and TAMB by
∆T = (DAMB − DCAL) × degrees per LSB
5. Add ∆T to TCAL
.
Rev. C | Page 1± of 40
AD7879/AD7889
MEDIAN AND AVERAGING FILTERS
As explained in the Touch Screen Principles section, touch
screens are composed of two resistive layers, normally placed
over an LCD screen. Because these layers are in close proximity
to the LCD screen, noise can be coupled from the screen onto
these resistive layers, causing errors in the touch screen
positional measurements.
When both filter values are 00, only one measurement is
transferred to the register map.
The number specified with the MED1 and MED0 settings must
be greater than or equal to the number specified with the AVG1
and AVG0 settings. If both settings specify the same number,
the median filter is switched off.
The AD7879/AD7889 contain a filtering block to process the
data and discard the spurious noise before sending the infor-
mation to the host. The purpose of this block is not only the
suppression of noise; the on-chip filtering also greatly reduces
the host processing loading.
Table 10. Median Averaging Filters (MAVF) Settings
Setting
Function
M = A
Median filter is disabled; output is the average of
A converted results
M > A
M < A
Output is the average of the middle A values from
the array of M measurements
The processing function consists of two filters that are applied
to the converted results: the median filter and the averaging filter.
Not possible because the median filter size is always
larger than the averaging window size
The median filter suppresses the isolated out-of-range noise and
sets the number of measurements to be taken. These measurements
are arranged in a temporary array, where the first value is the
smallest measurement and the last value is the largest measure-
ment. Bit 6 and Bit 5 in Control Register 2 (MED1, MED0) set
the window of the median filter and, therefore, the number of
measurements taken.
Example
In this example, MED1, MED0 = 11 and AVG1, AVG0 = 10;
the median filter has a window size of 16. This means that 16
measurements are taken and arranged in descending order in a
temporary array.
The averaging window size in this example is 8. The output is
the average of the middle eight values of the 16 measurements
taken with the median filter.
Table 8. Median Filter Size
MED1
MED0
Number of Measurements
0
0
1
1
0
1
0
1
Median filter disabled
4
8
1±
12-BIT SAR
ADC
MEDIAN
FILTER
AVERAGING
FILTER
CONVERTED
RESULTS
16 MEASUREMENTS
ARRANGED
AVERAGE OF
MIDDLE 8 VALUES
The averaging filter size determines the number of values to
average. Bit 8 and Bit 7 in Control Register 2 (AVG1, AVG0)
set the average to 2, 4, 8, or 16 samples. Only the final averaged
result is written into the result register.
6
2
13
4
16
5
15
10
9
3
11
8
1
12
14
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 9. Averaging Filter Size
M = 16
A = 8
9
AVG1
AVG0
Filter Size
10
11
12
13
14
15
16
0
0
1
1
0
1
0
1
Average of 2 middle samples
Average of 4 middle samples
Average of 8 middle samples
Average of 1± samples
Figure 27. Median and Averaging Filter Example
It takes approximately 2 μs to sort the data in the rank filter
(tSORT in Figure 34); tSORT adds to the update rate of the AD7879.
Rev. C | Page 17 of 40
AD7879/AD7889
AUX/VBAT/GPIO PIN
The AUX/VBAT/GPIO pin on the AD7879/AD7889 can be
programmed as an auxiliary input to the ADC, as a battery
monitoring input, or as a general-purpose digital input/output.
To select the auxiliary measurement, set the ADC channel
address to 011 (Bits[14:12] in Control Register 1, Address 0x01).
To select a battery measurement, set the ADC channel address
to 010. To select the GPIO function, set Bit 13 in Control
Register 2 (Address 0x02) to 1.
LIMIT COMPARISON
The AUX measurement and the battery measurement can
be compared with high and low limits stored on chip. An
out-of-limit result generates an alarm output at the
INT
pin
PENIRQ INT DAV INT
(
/
/
) when the
function is enabled. The
high limit for both channels is stored in the AUX/VBAT high
limit register (Address 0x04), and the low limit is stored in the
AUX/VBAT low limit register (Address 0x05).
AUXILIARY INPUT
After a measurement from either AUX or VBAT is taken, it
is compared with the high and low limits. The out-of-limit
comparison sets a status bit in Control Register 3. Separate
status bits for the high limit and the low limit indicate which
limit was exceeded. The interrupt sources can be masked by
clearing the corresponding enable bit in Control Register 3.
The AD7879/AD7889 have an auxiliary analog input, AUX.
When the auxiliary input function is selected, the signal on the
AUX pin (AUX/VBAT/GPIO) is connected directly to the ADC
input. This channel has a full-scale input range from 0 V to VCC.
The ADC channel address for AUX is 011 (Bits[14:12] in
Control Register 1, Address 0x01), and the result is stored in
the AUX/VBAT result register (Address 0x0C).
GPIO
The AD7879/AD7889 have one general-purpose logic input/
output pin, GPIO (AUX/VBAT/GPIO). To enable GPIO, set Bit
13 in Control Register 2 to 1. If this bit is set to 0, the
AUX/VBAT function is active on the pin. If the GPIO is not
enabled, the other GPIO configuration bits have no effect.
BATTERY INPUT
The AD7879/AD7889 can monitor battery voltages from 0.5 V
to 5 V when the BAT measurement is selected. Figure 28 shows
a block diagram of a battery voltage monitored through the VBAT
pin. The voltage to the VCC pin (VCC/REF) of the AD7879/AD7889
is maintained at the desired supply voltage via the dc-to-dc
converter, and the input to the converter is monitored. This
voltage on VBAT is divided by 4 internally, so that a 5 V battery
voltage is presented to the ADC as 1.25 V. To conserve power,
the divider circuit is on only during the sampling of a voltage on
VBAT. Note that the possible maximum input is 5 V.
The GPIO data bit is Bit 12 in Control Register 2.
Direction (Bit 11, Control Register 2, Address 0x02)
Bit 11 sets the direction of the GPIO pin (AUX/VBAT/GPIO).
When GPIO DIR = 0, the pin is an output. Setting or clearing
the GPIO data bit (Bit 12 in Control Register 2) outputs a value
on the GPIO pin.
The ADC channel address for VBAT is 010 (Bits[14:12] in
Control Register 1, Address 0x01), and the result is stored in
the AUX/VBAT result register (Address 0x0C).
When GPIO DIR = 1, the pin is an input. An input value on the
GPIO pin sets or clears the GPIO data bit (Bit 12 in Control
Register 2). GPIO data register bits are read-only when GPIO
DIR = 1.
DC-TO-DC
CONVERTER
Polarity (Bit 10, Control Register 2, Address 0x02)
BATTERY
0.5V TO 5V
V
CC
When GPIO POL = 0, the GPIO pin is active low. When GPIO
POL = 1, the GPIO pin is active high. How this bit affects the
GPIO operation also depends on the GPIO DIR bit.
VBAT
12kΩ
SW
0.125V TO 1.25V
ADC
If GPIO POL = 1 and GPIO DIR = 1, a 1 at the input pin sets
the corresponding GPIO data register bit to 1. A 0 at the input
pin clears the corresponding GPIO data bit to 0.
4kΩ
If GPIO POL = 1 and GPIO DIR = 0, a 1 in the GPIO data
register bit puts a 1 on the corresponding GPIO output pin. A 0
in the GPIO data register bit puts a 0 on the GPIO output pin.
Figure 28. Block Diagram of Battery Measurement Circuit
The maximum battery voltage that the AD7879/AD7889 can
measure changes when a different reference voltage is used. The
maximum voltage that is measurable is VCC × 4 because this
voltage gives a full-scale output from the ADC. The battery
voltage can be calculated using the following formula:
If GPIO POL = 0 and GPIO DIR = 1, a 1 at the input pin sets
the corresponding GPIO data bit to 0. A 0 at the input pin clears
the corresponding GPIO data bit to 1.
If GPIO POL = 0 and GPIO DIR = 0, a 1 in the GPIO data
register bit puts a 0 on the corresponding GPIO output pin. A 0
in the GPIO data register bit puts a 1 on the GPIO output pin.
VBAT (V) = [(Register Value) × VCC × 4]/4095
Rev. C | Page 18 of 40
AD7879/AD7889
GPIO Interrupt Enable (Bit 12, Control Register 3,
Address 0x03)
INT
is asserted if the GPIO data register bit is set when the
INT
GPIO is configured as an input, provided that
is enabled.
INT
The GPIO pin can operate as an interrupt source to trigger the
is triggered only when the GPIO is configured as an input,
that is, when GPIO DIR = 1.
INT
INT
output. This is controlled by Bit 12 in Control Register 3.
If the GPIO ALERT interrupt enable bit is set to 0, the GPIO can
INT INT
is cleared only when the GPIO signal or the GPIO enable
bit changes.
trigger
. If this bit is set to 1, the GPIO cannot trigger
.
Rev. C | Page 19 of 40
AD7879/AD7889
CONVERSION TIMING
Conversion timing or update rate is the rate at which the
AD7879 provides converted values from the ADC so that the
XY positions in the touch screen can be updated. In other
words, the update rate is the timing required to give valid
measurements in the sequencer.
Conversion time per channel depends on the number of
samples to be converted. The number of samples is pro-
grammed using the following median filter settings:
TCHANNEL = TMEASURE × MED
TCHANNEL
TCHANNEL
_
_
MIN =9.5 μs (ACQ = 2 μs, MED = 0)
Figure 29 shows conversion timing for a conversion sequence.
MAX = 376 μs (ACQ = 16 μs, MED = 16)
VBAT/AUX
X+
Y+
Z1
Z2
TEMP
Update Rate = [FCD + (TMEASURE × MED)] × N + FCD + TMR
where:
F
C
D
F
C
D
F
C
D
F
C
D
F
C
D
T
T
T
T T T
MEASURE MEASURE MEASURE
MEASURE
MEASURE
MEASURE
N = number of channels to be measured (1 to 6).
MED = median filter setting (1, 4, 8, 16).
TMR = timer setting (0 μs to 9.4 ms).
× M
× M
× M
× M
× M
× M
Figure 29. Conversion Timing Sequence
FCD is required before each touch screen measurement (X+,
Y+, Z1, and Z2). This time is required to allow the screen inputs
to settle before converting. If the sequence does not contain any
screen channel (VBAT, AUX, or TEMP), only one FCD is added
at start of the sequence. At the end of the sequence, there is
always another FCD.
The total update rate depends on the median filter settings and
the number of channels in the conversion sequence. The timer
setting (TMR) allows the user more flexibility to program the
update rate.
For example, if
T
MEASURE is the time required to perform one measurement in
the conversion sequence.
ACQ = 4 us
MED = 8
TMEASURE = [ACQ (2 μs, 4 μs, 8 μs, 16 μs) + TCONV (7.5 μs) + TSORT
(2 μs)]
N = 2
where:
FCD = 1.024 ms
ACQ is the acquisition time which is programmable in Control
Register 1. For temperature measurements, ACQ is fixed at 16 μs.
TMR = 620 μs
TMEASURE = 4 + 7.5 + 2 = 13.5 μs
TCHANNEL = (13.5 × 8) = 108 μs
Then
TCONV (typical ADC conversion time) is specified at 7.5 μs.
TSORT is the time needed to sort the new sample within the
median filter array. The TSORT value is approximately 2 μs. If a
median filter is not used (MED =0), the TSORT value is 0.
Update rate = [1024 + 108] × 2 + 1024 + 620 = 3.9 ms
TMEASURE_MIN = 9.5 μs (ACQ = 2 μs, no median filter)
Rev. C | Page 20 of 40
AD7879/AD7889
REGISTER MAP
Table 11. Register Table
Address1
0x00
Register Name
Description
Default Value
Type
R/W
R/W
Unused
Unused
0x0000
0x0000
0x01
Control Register 1
Pen interrupt enable, channel selection for manual conversion,
ADC mode, acquisition time, and conversion timer
0x02
0x03
Control Register 2
Control Register 3
ADC power management, GPIO control, pen interrupt mode,
averaging, median filter, software reset, and FCD
Status of high/low limit comparisons for TEMP and AUX/VBAT,
and enable bits to allow them to become interrupts; channel
selection for slave/master mode
0x4040
0x0000
R/W
R/W
0x04
0x05
0x0±
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
AUX/VBAT high limit
AUX/VBAT low limit
TEMP high limit
TEMP low limit
X+
Y+
X+ (Z1)
Y− (Z2)
AUX/VBAT
TEMP
AUX/VBAT high limit for comparison
AUX/VBAT low limit for comparison
TEMP high limit for comparison
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
R/W
R
R
R
R
R
TEMP low limit for comparison
X+ measurement for Y position
Y+ measurement for X position
X+ measurement for touch-pressure calculation (Z1)
Y− measurement for touch-pressure calculation (Z2)
AUX/VBAT voltage measurement
Temperature conversion measurement
R
R
Revision and device ID Revision and device ID
0x0379
(AD7879-1/AD7889-1)
0x037A
R
(AD7879/AD7889)
1 Do not write to addresses outside the register map.
Rev. C | Page 21 of 40
AD7879/AD7889
DETAILED REGISTER DESCRIPTIONS
All addresses and default values are expressed in hexadecimal.
Table 12. Control Register 1
Default
Value
Address Bit Name
0x01
Data Bit
Description
Disable PENIRQ 15
Pen interrupt enable.
0x0000
0 = PENIRQ is enabled.
1 = PENIRQ is disabled and INT is enabled.
ADC channel address for manual conversion (ADC mode = 01).
111 = X+ input (Y position).
110 = Y+ input (X position).
101 = X+ (Z1) input for touch-pressure calculation.
100 = Y− (Z2) input (used for touch-pressure measurement).
011 = AUX input.1
CHNL ADD[2:0] [14:12]
010 = VBAT input.1
001 = temperature measurement.
000 = not applicable.
ADC MODE[1:0] [11:10]
ADC mode.
00 = no conversion.
01 = single conversion.2
10 = conversion sequence (slave mode).2
11 = conversion sequence (master mode).
ADC acquisition time.
ACQ[1:0]
TMR[7:0]
[9:8]
[7:0]
00 = 4 clock periods (2 µs).
01 = 8 clock periods (4 µs).
10 = 1± clock periods (8 µs).
11 = 32 clock periods (1± µs).
Note that the acquisition time does not apply to the temperature sensor channels;
the temperature channel has a constant settling time of 1± μs.
Conversion interval timer.
Starts at 550 µs (00000001) and continues to 9.440 ms (11111111) in steps of 35 µs
(see Table 18).
Note that, in slave mode, the conversion interval timer starts to count as soon as the
conversion sequence is finished; in master mode, it starts to count again only if the
screen remains touched. If the screen is released, the timer stops counting and, on
the next screen touch, a conversion starts immediately.
1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected in Control Register 3 and GPIO is disabled, AUX is
ignored and VBAT is measured.
2 Note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in Control Register 1 (Address 0x01) Bits[7:0] = 0x00 at
the end of the conversion sequence.
Rev. C | Page 22 of 40
AD7879/AD7889
Table 13. Control Register 2
Default
Value
Address Bit Name
Data Bit Description
[15:14] ADC power management.
0x02
PM[1:0]
0x4040
00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered down.
01 = analog blocks to be powered down depend on the ADC mode.
If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are powered
down and must wake up when the user touches the screen.
If ADC mode is slave mode, the ADC and temperature sensor are powered down when not
being used. They wake up automatically when required. The oscillator and bias are powered
up because they are needed to measure time. This also applies to the single-conversion mode.
10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode.
11 = same as 01.
GPIO EN
13
GPIO enable.
0 = AUX/VBAT channel active.
1 = GPIO enabled on AUX/VBAT/GPIO pin.
GPIO data bit.
GPIO DAT
GPIO DIR
12
11
GPIO direction.
0 = output.
1 = input.
GPIO POL
SER/DFR
AVG[1:0]
10
9
GPIO polarity.
0 = GPIO pin is active low.
1 = GPIO pin is active high.
Selects normal (single-ended) or ratiometric (differential) conversion.
0 = ratiometric (differential).
1 = normal (single-ended).
ADC averaging.
[8:7]
00 = 2 middle values averaged (one measurement when median filter is disabled).
01 = 4 middle values averaged.
10 = 8 middle values averaged.
11 = 1± values averaged.
MED[1:0]
[±:5]
Median filter size.
00 = median filter disabled.
01 = 4 measurements.
10 = 8 measurements.
11 = 1± measurements.
SW/RST
4
Software reset; digital logic is reset when this bit is set.
ADC first conversion delay.1
FCD[3:0]
[3:0]
Starts at 128 µs (default) and continues to 4.09± ms in steps of 128 µs (see Table 22).
1 This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the
ADC to power up.
Rev. C | Page 23 of 40
AD7879/AD7889
Table 14. Control Register 3
Default
Value
Address
Bit Name
Data Bit
Description
0x03
TEMP MASK
15
TEMP mask bit.
0x0000
0 = temperature measurement is allowed to cause interrupt.
1 = temperature measurement is not allowed to cause interrupt.
AUX/VBAT mask bit.
AUX/VBAT MASK
INT MODE
14
13
0 = AUX/VBAT measurement is allowed to cause interrupt.
1 = AUX/VBAT measurement is not allowed to cause interrupt.
DAV/INT mode select.
0 = enable DAV mode.
1 = enable INT mode.
Note that this bit overrides any mask bits associated with individual channels.
GPIO interrupt enable.
GPIO ALERT
12
0 = GPIO can cause an alert on the INT output.
1 = mask GPIO from causing an alert on the INT output.
1 = AUX/VBAT below low limit.
AUX/VBAT LOW
11
10
9
AUX/VBAT HIGH
1 = AUX/VBAT above high limit.
TEMP LOW
TEMP HIGH
X+
1 = TEMP below low limit.
8
1 = TEMP above high limit.
7
1 = include measurement of Y position (X+ input).
1 = include measurement of X position (Y+ input).
1 = include Z1 touch-pressure measurement (X+ input).
1 = include measurement of Z2 touch-pressure measurement (Y− input).
1 = include measurement of AUX channel.1
1 = include measurement of battery monitor (VBAT).1
1 = include temperature measurement.
Unused.
Y+
±
Z1
5
Z2
4
AUX
3
VBAT
2
TEMP
Not used
1
0
1 If GPIO is enabled in Control Register 2 (Bit 13), AUX and VBAT are both ignored. If AUX and VBAT are both selected and GPIO is disabled, AUX is ignored and VBAT is
measured.
Table 15. Limit Registers
Default
Value
Address
0x04
0x05
0x0±
0x07
Register Name
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
Description
AUX/VBAT high limit
AUX/VBAT low limit
TEMP high limit
TEMP low limit
User-programmable AUX/VBAT high limit register
User-programmable AUX/VBAT low limit register
User-programmable TEMP high limit register
User-programmable TEMP low limit register
0x0000
0x0000
0x0000
0x0000
Rev. C | Page 24 of 40
AD7879/AD7889
Table 16. Measurement Result Registers (Read Only)
Address
Register Name Data Bits
Description
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x08
0x09
0x0A
0x0B
0x0C
X+
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Measured X+ input with Y excitation (Y position)
Measured Y+ input with X excitation (X position)
Measured X+ input with X − and Y+ excitation (touch-pressure calculation Z1)
Measured Y − input with X− and Y+ excitation (touch-pressure calculation Z2)
AUX/VBAT voltage measurement
Y+
X+ (Z1)
Y− (Z2)
AUX/VBAT
TEMP
0x0D
Temperature conversion measurement
Table 17. Revision and Device ID Register (Read Only)
Address
Data Bits
[15:12]
[11:8]
Description
Default Value
0x0E
Unused
Revision and device ID bits
Device ID
0x0379 (AD7879-1/AD7889-1)
0x037A (AD7879/AD7889)
[7:0]
Rev. C | Page 25 of 40
AD7879/AD7889
CONTROL REGISTERS
15
0
DISABLE CHNL CHNL CHNL ADC
PENIRQ ADD2 ADD1 ADD0 MODE1 MODE0
ADC
ACQ1 ACQ0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Figure 30. Control Register 1
CONTROL REGISTER 1
ADC Mode (Control Register 1, Bits[11:10])
Control Register 1 (Address 0x01) contains the ADC channel
address and the ADC mode bits. It sets the acquisition time and
the timer. It also contains a bit to disable the pen interrupt.
Control Register 1 should always be the last register programmed
prior to starting conversions. Its power-on default value is 0x0000.
To change any parameter after conversion has begun, the part
must first be put into ADC Mode 00. Make the changes, and
then reprogram Control Register 1, ensuring that it is always
the last register programmed before conversions begin.
The mode bits select the operating mode of the ADC. The
AD7879/AD7889 have three operating modes. These modes are
selected by writing to the mode bits in Control Register 1. If the
mode bits are set to 00, no conversion is performed.
Table 20. Mode Selection
ADC
MODE1
ADC
MODE0
Function
0
0
0
1
Do not convert (default)
Single-channel conversion; the device is
in slave mode
Timer (Control Register 1, Bits[7:0])
1
1
0
1
Sequence 0; the device is in slave mode
Sequence 1; the device is in master mode
The TMR bits in Control Register 1 set the conversion interval
timer, which enables the ADC to perform a conversion sequence
at regular intervals from 550 µs (00000001) up to 9.440 ms
(11111111) in increments of 35 µs (see Table 18). The default
value of these bits is 00000000, which enables the ADC to
perform one conversion only.
If the mode bits are set to 01, a single conversion is performed
on the channel selected by writing to the channel bits of Control
Register 1 (Bits[14:12]). At the end of the conversion, if the TMR
bits in Control Register 1 are set to 00000000, the mode bits
revert to 00 and the ADC returns to no convert mode until a
new conversion is initiated by the host. Setting the TMR bits to
a value other than 00000000 causes the conversion to be repeated.
In slave mode, the timer starts as soon as the conversion sequence
is finished. In master mode, the timer starts at the end of a conver-
sion sequence only if the screen remains touched. If the touch is
released at any stage, the timer stops. The next time that the
screen is touched, a conversion sequence begins immediately.
The AD7879/AD7889 can also be programmed to automatically
convert a sequence of selected channels. The two modes for this
type of conversion are slave mode and master mode.
Table 18. Timer Selection
For slave mode operation, the channels to be digitized are selected
by setting the corresponding bits in Control Register 3. Conversion
is initiated by writing 10 to the mode bits of Control Register 1.
The ADC then digitizes the selected channels and stores the
results in the corresponding result registers. At the end of the
conversion, if the TMR bits in Control Register 1 are set to
00000000, the mode bits revert to 00 and the ADC returns to no
convert mode until a new conversion is initiated by the host.
Setting the TMR bits to a value other than 00000000 causes the
conversion sequence to be repeated.
TMR[7:0]
00000000
00000001
00000010
00000011
…
11111101
11111110
11111111
Conversion Interval
Convert one time only (default)
Every 550 µs
Every 585 µs
Every ±20 µs
…
Every 9.370 ms
Every 9.405 ms
Every 9.440 ms
Acquisition Time (Control Register 1, Bits[9:8])
For master mode operation, the channels to be digitized are
written to Control Register 3. Master mode is then selected by
writing 11 to the mode bits in Control Register 1. In this mode,
the wake-up on touch feature is active; therefore, conversion
does not begin immediately. The AD7879/AD7889 wait until
the screen is touched before beginning the sequence of conver-
sions. The ADC then digitizes the selected channels, and the
results are written to the result registers. Before beginning
another sequence of conversions, the AD7879/AD7889 wait for
the screen to be touched again or for a timer event if the screen
remains touched.
The ACQ bits in Control Register 1 allow the selection of acquisi-
tion times for the ADC of 2 µs (default), 4 µs, 8 µs, or 16 µs. The
user can program the ADC with an acquisition time suitable for
the type of signal being sampled. For example, signals with large
RC time constants can require longer acquisition times.
Table 19. Acquisition Time Selection
ACQ1
ACQ0
Acquisition Time
0
0
1
1
0
1
0
1
4 clock periods (2 µs)
8 clock periods (4 µs)
1± clock periods (8 µs)
32 clock periods (1± µs)
Rev. C | Page 2± of 40
AD7879/AD7889
ADC Channel (Control Register 1, Bits[14:12])
For both single-channel and sequential conversion, a normal
DFR
conversion (single-ended) is selected by setting the SER/
bit in Control Register 2 (Bit 9). Ratiometric (differential)
The ADC channel address is selected by Bits[14:12] of Control
Register 1 (CHNL ADD2 to CHNL ADD0). A complete list of
channel addresses is given in Table 21.
DFR
conversion is selected by clearing the SER/
bit.
PENIRQ
Enable (Control Register 1, Bit 15)
For single-channel conversion, the channel address is selected
by writing the appropriate code to the CHNL ADD2 to CHNL
ADD0 bits in Control Register 1.
The AD7879/AD7889 have a dual function output that performs
PENIRQ INT
as
or
depending on the pen interrupt enable bit
For sequential channel conversion, the channels to be converted
are selected by setting the bits corresponding to the channel
number in Control Register 3 for slave and master mode
sequencing.
(Bit 15 of Control Register 1). When this bit is set to 0, the pin
functions as a pen interrupt and goes low whenever the screen
is touched. When the pen interrupt enable bit is set to 1, the pen
interrupt request is disabled and the pin functions as an interrupt
INT
when a measurement exceeds a preprogrammed limit (
).
Table 21. Codes for Selecting Input Channel and Normal or Ratiometric Conversion
SER/DFR
Channel
CHNL ADD[2:0] Analog Input
X Switches
Y Switches
REF+
Y+
X+
Y+
Y+
VCC
VCC
VCC
REF−
Y−
X−
X−
X−
GND
GND
GND
0
1
2
3
4
5
±
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
111
110
101
100
011
010
001
000
111
110
101
100
011
010
001
000
X+ (Y position)
Y+ (X position)
X+ (Z1 touch pressure)
Y− (Z2 touch pressure)
AUX
Off
On
On
Off
X+ off, X− on
X+ off, X− on
Off
Off
Off
Y+ on, Y− off
Y+ on, Y− off
Off
Off
Off
VBAT
TEMP
Invalid address
7
8
9
12
13
14
15
X+ (Y position)
Y+ (X position)
X+ (Z1 touch pressure)
Y− (Z2 touch pressure)
AUX
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
VBAT
TEMP
Invalid address
Rev. C | Page 27 of 40
AD7879/AD7889
15
0
GPIO GPIO GPIO GPIO SER/
EN DAT DIR POL DFR
SW/
RST
AVG1 AVG0 MED1 MED0
FCD3 FCD2 FCD1 FCD0
PM1 PM0
Figure 31. Control Register 2
CONTROL REGISTER 2
Power Management (Control Register 2, Bits[15:14])
Control Register 2 (Address 0x02) contains the ADC power
DFR
The power management (PM) bits in Control Register 2 allow
the power management features of the ADC to be programmed
(see Table 23). If the PM bits are set to 00, the ADC is in full
shutdown. This setting overrides any setting of the mode bits in
Control Register 1. Power management overrides the ADC modes.
management bits, the GPIO settings, the SER/
bit (to
choose the single-ended or differential method of touch screen
measurement), the averaging and median filter settings, a bit
that allows resetting of the part, and the first conversion delay
bits. Its power-on default value is 0x4040. See the Detailed
Register Descriptions section for more information about the
control registers.
Table 23. Power Management Selection
PM1
PM0
Function
0
0
Full shutdown; ADC, oscillator, bias, and temp-
erature sensor are turned off. The only way to
exit this mode is to write to the part over the
serial interface and change the PM bits. This
setting overrides any other setting on the
part, including the ADC mode bits.
For information about the averaging and median filter settings,
see the Median and Averaging Filters section. For information
about the GPIO settings, see the GPIO section.
First Conversion Delay (Control Register 2, Bits[3:0])
The first conversion delay (FCD) bits in Control Register 2
program a delay from 128 µs (default) up to 4.096 ms before
the first conversion to allow the ADC time to power up. This
delay also occurs before conversion of the X and Y coordinate
channels to allow extra time for screen settling, and after the
0
1
The analog blocks to be powered down
depend on the ADC mode setting. In master
mode, the ADC, bias, temperature sensor, and
oscillator are powered down and must wake
up when the user touches the screen. In slave
mode, the ADC and temperature sensor are
powered down when not being used. They
wake up automatically when required. The
oscillator and bias are powered up because
they are needed to measure time. This setting
also applies to the single-conversion mode.
PENIRQ
last conversion in a sequence to precharge
.
Table 22. First Conversion Delay Selection
FCD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Delay
128 µs
25± µs
384 µs
512 µs
±40 µs
7±8 µs
89± µs
1.024 ms
1.152 ms
1.280 ms
1.53± ms
1.792 ms
2.048 ms
2.5±0 ms
3.584 ms
4.09± ms
1
1
0
1
The ADC, bias, and oscillator are powered up
continuously, irrespective of ADC mode.
Same as 01.
Rev. C | Page 28 of 40
AD7879/AD7889
15
TEMP
0
AUX/
VBAT
MASK
AUX/ AUX/
VBAT VBAT
LOW HIGH
INT GPIO
MODE ALERT
TEMP TEMP
LOW HIGH
NOT
USED
X+
Y+
Z1
Z2
AUX VBAT TEMP
MASK
Figure 32. Control Register 3
CONTROL REGISTER 3
START OF
CONVERSION
SEQUENCE
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
SET CHANNEL
Sequencer (Control Register 3, Bits[7:0])
YES
FCD
REQ’D?
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
NO
FCD
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
WAIT FOR
ACQUISITION
ACQ
CONVERT DATA
Figure 32 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
YES
RANK NEW
YES
DATA
MAV FILTER
ENABLED
?
(WAIT t
)
SORT
NO
00
IDLE
MEDIAN
ADC MODE?
NO
# OF SAMPLES
1
TAKEN?
01
10
11
MASTER MODE
SINGLE
SLAVE MODE
CONVERSION
TRANSFER DATA
TO REGISTERS
AVERAGE DATA
WAIT FOR
FIRST TOUCH
CONVERSION
SEQUENCE
YES
SET ALERT AND
INTERRUPT
OUT-OF-
LIMIT?
CONVERSION
SEQUENCE
YES
TIMER = 00?
NO
NO
NO
END OF
SEQUENCE
?
NO
SCREEN
TOUCHED?
START TIMER
YES
YES
1
MEDIAN # MEANS MEDIAN
FILTER SIZE.
WAIT FOR TIMER
FCD
YES
TIMER = 00?
NO
Figure 34. Conversion Sequence
START TIMER
WAIT FOR TIMER
NO
SCREEN
TOUCHED?
YES
Figure 33. Conversion Modes
Rev. C | Page 29 of 40
AD7879/AD7889
PENIRQ
—Pen Interrupt
INTERRUPTS
PENIRQ
PENIRQ
The AD7879/AD7889 have a dual function interrupt output,
The pen interrupt request output (
the screen is touched and the
) goes low whenever
enable bit is set to 0
INT
PENIRQ
INT
output
), as an
, as well as a pen-down interrupt,
. The
DAV
can be configured as a data available interrupt (
PENIRQ
(Control Register 1, Bit 15). When
the pen interrupt request output is disabled.
enable is set to 1,
INT
out-of-limit interrupt (
), or as a GPIO interrupt.
The pen interrupt equivalent output circuitry is shown in
Figure 36. This digital logic output has an internal 50 kΩ pull-
up resistor, so it does not need an external pull-up. The
DAV
—Data Available Interrupt
The behavior of the interrupt output is controlled by Bit 13 in
INT
Control Register 3. In default mode (Bit 13 = 0),
as a data available interrupt (
finish a conversion or a conversion sequence, the interrupt is
asserted to let the host know that new ADC data is available in
the result registers.
operates
). When the AD7879/AD7889
PENIRQ
PENIRQ
output idles high, and the
circuitry is always
DAV
enabled in master mode (ADC mode = 11), except during
conversions.
V
CC
Y+
V
CC
50kΩ
DAV
While the ADC is idle or is converting,
is high. When the
PENIRQ
X+
ADC has finished converting and new data has been written to
DAV
X–
TOUCH
SCREEN
the result registers,
goes low. Reading the result registers
PENIRQ
ENABLE
DAV
DAV
is also reset if a new con-
resets
to a high condition.
version is started by the AD7879/AD7889 because the timer
expired. The host should read the result registers only when
Y–
DAV
DAV
is low. To ensure correct operation of the
mode
PENIRQ
Figure 36.
Output Equivalent Circuit
when using the SPI interface, it is necessary to write 0x0000
to Register 0x81 after a set of register reads. This clears the
internal data read signal.
PENIRQ
When the screen is touched,
an interrupt request to the host. When the screen touch ends,
goes low. This generates
PENIRQ
immediately goes high if the ADC is idle. If the ADC
PENIRQ
is converting,
goes high when the ADC becomes idle.
DAV
PENIRQ
The
Figure 37.
operation for these two conditions is shown in
tCONV
AD7879/
AD7889
STATUS
SETUP
BY HOST
ADC
NEW DATA HOST READS
RESULTS
IDLE
CONVERTING AVAILABLE
IDLE
NOT
TOUCHED
NOT
TOUCHED
SCREEN
PENIRQ
TOUCHED
DAV
Figure 35. Operation of
Output
PENIRQ
DETECTS
TOUCH
When the on-board timer is programmed to perform automatic
conversions, limited time is available to the host to read the
result registers before another sequence of conversions begins.
PENIRQ
DETECTS
RELEASE
ADC
ADC IDLE
DAV
The
signal is reset high when the timer expires, and the
DAV
STATUS
host should not access the result registers while
is high.
RELEASE NOT
DETECTED
NOT
TOUCHED
NOT
TOUCHED
SCREEN
PENIRQ
TOUCHED
INT
—Out-of-Limit Interrupt
PENIRQ
DETECTS
TOUCH
INT
The
pin operates as an alarm or interrupt output when
PENIRQ
Bit 13 in Control Register 3 (Address 0x03) is set to 1. The
output goes low if any one of the interrupt sources is asserted.
The results of high and low limit comparisons on the AUX,
VBAT, and TEMP channels are interrupt sources. An out-of-
limit comparison sets a status bit in the interrupt register. A
separate status bit for the high limit and the low limit on each
channel indicates which limit was exceeded. The interrupt
sources can be masked by setting the corresponding enable bit
in this register to 1. There is one enable bit per channel.
DETECTS
RELEASE
ADC
CONVERTING
ADC
ADC IDLE
ADC IDLE
STATUS
PENIRQ
Figure 37.
Operation for ADC Idle and ADC Converting
Rev. C | Page 30 of 40
AD7879/AD7889
INT DAV
or
and enable
using Bit 15 in Control Register 1 and
SYNCHRONIZING THE AD7879/AD7889 TO THE
HOST CPU
Bit 13 in Control Register 3. The host can then enter sleep mode
to conserve power. The wake-up on touch feature of the
AD7879/AD7889 is active in this mode; therefore, when the
screen is touched, the programmed sequence of conversions
The two methods for synchronizing the AD7879/AD7889 to its
host CPU are slave mode (in which the mode bits are set to 01
or 10) and master mode (in which the mode bits set to 11).
INT DAV
automatically begins. When the
or
signal is asserted,
PENIRQ
In master mode (ADC mode bits = 11),
PENIRQ
can be used
the host reads the new data available in the AD7879/AD7889
result registers and returns to sleep mode. This method can
significantly reduce the load on the host.
as an interrupt to the host. When
goes low to indicate
that the screen has been touched, the host is awakened. The
host can then program the AD7879/AD7889 to convert in any
mode and read the results after the conversions are completed.
PENIRQ
Figure 38 shows how the
PENIRQ
circuit is enabled. The wake-up
circuit are enabled only in master
on touch circuit and the
INT DAV
or
In master mode,
can also be used as an interrupt to
PENIRQ INT DAV
mode (ADC mode = 11). In slave mode, the
INT DAV
/
/
the host. The host should first define a conversion sequence in
Control Register 3, initialize the AD7879/AD7889 in Mode 11,
pin can output only
or
signals.
YES
YES
ADC MODE = 11?
MASTER MODE
ENABLE
PENIRQ
DETECTION
CIRCUIT
ENABLE
WAKE-UP
ON TOUCH
TOUCH SCREEN TOUCHED
TO THE DIGITAL CORE
PENIRQ/INT/DAV PIN
TOUCH SCREEN TOUCHED
0
1
DAV
(END OF CONVERSION SEQUENCE)
0
1
INT/DAV/GPIO ALERT
INT
(GPIO ALERT/OUT OF LIMITS)
CONTROL REGISTER 1
BIT 15
CONTROL REGISTER 3
BIT 13
Figure 38. Master Mode Operation
Rev. C | Page 31 of 40
AD7879/AD7889
SERIAL INTERFACE
The AD7879 and AD7879-1 (and the AD7889 and AD7889-1)
differ only in the serial interface provided on the part. The
AD7879 and the AD7889 are available with a serial peripheral
interface (SPI). The AD7879-1 and the AD7889-1 are available
with an I2C-compatible interface. It is recommended that
addresses outside the register map not be written to.
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates
a write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
SPI INTERFACE
The AD7879/AD7889 have a 4-wire SPI. The SPI has a data
input pin (DIN) for inputting data to the device, a data output
pin (DOUT) for reading data back from the device, and a data
clock pin (SCL) for clocking data into and out of the device. A
Writing Data
Data is written to the AD7879/AD7889 in 16-bit words. The
first word written to the device is the command word, with the
read/write bit set to 0. The master then supplies the 16-bit input
data-word on the DIN line. The AD7879/AD7889 clock the
data into the register addressed in the command word. If there
is more than one word of data to be clocked in, the AD7879/
AD7889 automatically increment the address pointer and clock
the next data-word into the following register.
CS
CS
chip select pin ( ) enables or disables the serial interface.
is
required for correct operation of the SPI interface. Data is
clocked out of the AD7879/AD7889 on the falling edge of SCL,
and data is clocked into the device on the rising edge of SCL.
SPI Command Word
All data transactions on the SPI bus begin with the master
The AD7879/AD7889 continue to clock in data on the DIN line
CS
taking
from high to low and sending out the command
CS
until the master ends the write transition by pulling
high or
word. This indicates to the AD7879/AD7889 whether the
transaction is a read or a write and gives the address of the
register from which to begin the data transfer. The bit map in
Table 24 shows the SPI command word.
until the address pointer reaches its maximum value. The AD7879/
AD7889 address pointer does not wrap. When the address
pointer reaches its maximum value, any data provided by the
master on the DIN line is ignored by the AD7879/AD7889.
Table 24. SPI Command Word
MSB
15
1
LSB
14
13
12
11
10
[9:0]
1
1
0
0
R/W Register address
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
16-BIT DATA
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
CW
8
DIN
SCL
CS
D15 D14 D13
D2
D1
D0
t2
t4
t5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t3
NOTES
1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE COMMAND WORD AND 16 BITS FOR DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SINGLE WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 39. Single Register Write, SPI Timing
Rev. C | Page 32 of 40
AD7879/AD7889
16-BIT COMMAND WORD
R/W STARTING REGISTER ADDRESS
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
ENABLE WORD
CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10
CW CW
CW
3
CW CW CW
DIN
D15 D14
D1
D0
D15
D1
D0
D14
D15
49
9
8
7
6
5
4
2
1
0
SCL
CS
1
2
3
4
11
12
13
14
5
6
7
8
9
10
15
16
17
18
31
32
33
34
47
48
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 40. Sequential Register Write, SPI Timing
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
CW
8
DIN
SCL
CS
X
X
X
X
X
X
t2
t4
t5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t3
t6
D15 D14 D13
16-BIT READBACK DATA
t7
DOUT
D2
D1
D0
XXX
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
NOTES
1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 41. Single Register Readback, SPI Timing
Reading Data
The AD7879/AD7889 continue to clock out data on the DOUT
line provided that the master continues to supply the clock signal
A read transaction begins when the master writes the command
word to the AD7879/AD7889 with the read/write bit set to 1. The
master then supplies 16 clock pulses per data-word to be read,
and the AD7879/AD7889 clock out data from the addressed
register on the DOUT line. The first data-word is clocked out
on the first falling edge of SCL following the command word,
as shown in Figure 41.
CS
on SCL. The read transaction ends when the master takes
high.
If the AD7879/AD7889 address pointer reaches its maximum
value, the AD7879/AD7889 repeatedly clock out data from the
addressed register. The address pointer does not wrap.
Rev. C | Page 33 of 40
AD7879/AD7889
16-BIT COMMAND WORD
R/W STARTING REGISTER ADDRESS
ENABLE WORD
CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10
DIN
X
X
X
X
X
X
X
X
X
9
8
7
6
5
4
3
2
1
0
SCL
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
DOUT
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14
D1
D0
D1
D0
D15 D14
D15
READBACK DATA FOR
NEXT REGISTER ADDRESS
READBACK DATA FOR
STARTING REGISTER
ADDRESS
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE DOUT PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON’T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 42. Sequential Register Readback, SPI Timing
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
I2C-COMPATIBLE INTERFACE
The AD7879-1/AD7889-1 support the industry standard 2-wire
I2C serial interface protocol. The two wires associated with the
I2C timing are the SCL and SDA inputs. SDA is an I/O pin that
allows both register write and register readback operations. The
AD7879-1/AD7889-1 are always slave devices on the I2C serial
interface bus.
W
7-bit address (MSB first) plus a R/ bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus then remain idle
while the selected device waits for data to be read from or written
The devices have a 7-bit device address, Address 0101 1XX. The
lower two bits are set by tying the ADD0 and ADD1 pins high or
low. The AD7879-1/AD7889-1 respond when the master device
sends its device address over the bus. The AD7879-1/AD7889-1
cannot initiate data transfers on the bus.
W
to it. If the R/ bit is a 0, the master writes to the slave device.
W
If the R/ bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses (eight bits of data followed by an acknowledge bit from
the slave device). Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period because a low-to-high transition when the clock
is high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
Table 25. I2C Device Addresses for the AD7879-1/AD7889-1
ADD1
ADD0
I2C Address
0101 100
0101 101
0101 110
0101 111
0
0
1
1
0
1
0
1
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCL remains high. If the AD7879-1/
AD7889-1 encounter a stop condition, they return to the idle
condition.
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows.
Rev. C | Page 34 of 40
AD7879/AD7889
START
AD7879-1/AD7889-1 DEVICE ADDRESS
REGISTER ADDRESS[A7:A0]
A7 A6 A1 A0
SDA
SCL
DEV DEV DEV DEV
DEV DEV
A1
DEV
A2
R/W ACK
A6
A5
A4
A3
A0
t1
t3
1
2
3
4
11
16
5
6
7
8
9
10
17
t2
STOP
START
AD7879-1/AD7889-1
DEVICE ADDRESS
REGISTER DATA[D15:D8]
ACK D15 D14 D9
REGISTER DATA[D7:D0]
D1
t8
DEV DEV DEV
D8 ACK
t4
D7
D0
ACK
36
D6
t5
29
A6
1
A5
2
A4
3
t6
t7
18
19
20
25
26
27
28
34
35
37
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE Xs ARE DON'T CARE BITS.
4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 43. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process of writing to the AD7879-1/AD7889-1 over the I2C
bus is shown in Figure 43 and Figure 45. The device address is
All registers on the AD7879-1/AD7889-1 have 16 bits. Two
consecutive 8-bit data bytes are combined and written to the
16-bit registers. To avoid errors, all writes to the device must
contain an even number of data bytes.
W
sent over the bus followed by the R/ bit set to 0. This is followed
To end the transaction, the master generates a stop condition on
SDA, or it generates a repeat start condition if the master is to
maintain control of the bus.
by one byte of data that contains the 8-bit address of the internal
data register to be written. The bit map in Table 26 shows the
register address byte.
Reading Data over the I2C Bus
Table 26. I2C Register Address Byte
To read from the AD7879-1/AD7889-1, the address pointer
register must first be set to the address of the required internal
register. The master performs a write transaction and writes to
the AD7879-1/AD7889-1 to set the address pointer. The master
then outputs a repeat start condition to keep control of the bus
or, if this is not possible, the master ends the write transaction
with a stop condition. A read transaction is initiated, with the
MSB
LSB
7
6
5
4
3
2
1
0
Register Address
Bit 4 Bit 3
Bit 7
Bit ±
Bit 5
Bit 2
Bit 1
Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
W
R/ bit set to 1.
The AD7879-1/AD7889-1 address pointer register automatically
increments after each write. This allows the master to sequentially
write to all registers on the AD7879-1/AD7889-1 in the same
write transaction. However, the address pointer register does
not wrap after the last address.
The AD7879-1/AD7889-1 supply the upper eight bits of data
from the addressed register in the first readback byte, followed
by the lower eight bits in the next byte. This is shown in Figure 44
and Figure 45.
Because the address pointer automatically increments after each
read, the AD7879-1/AD7889-1 continue to output readback data
until the master puts a no acknowledge and a stop condition on
the bus. If the address pointer reaches its maximum value and
the master continues to read from the part, the AD7879-1/
AD7889-1 repeatedly send data from the last register addressed.
Any data written to the AD7879-1/AD7889-1 after the address
pointer has reached its maximum value is discarded.
Rev. C | Page 35 of 40
AD7879/AD7889
START
AD7879-1/AD7889-1
DEVICE ADDRESS
REGISTER ADDRESS[A7:A0]
A7 A6 A1 A0 ACK
SDA
SCL
DEV DEV DEV DEV DEV DEV DEV
R/W ACK
A6
A5
A4
A3
A2
A1
A0
t1
t3
1
2
3
4
5
6
7
8
9
10
11
16
17
18
t2
P
AD7879-1/AD7889-1
DEVICE ADDRESS
AD7879-1/AD7889-1
DEVICE ADDRESS
REGISTER DATA[D7:D0]
D1 D0
D6
t5
30
SR
t8
DEV DEV
A6 A5
DEV DEV
A1
DEV DEV DEV
D7
ACK
ACK
R/W
A0
A6
A5
A4
USING
REPEATED
START
t7
t4
t6
1
25
26
27
28
29
35
36
37
2
3
19
P
20
21
AD7879-1/AD7889-1
DEVICE ADDRESS
REGISTER DATA[D7:D0]
D1
D6
t5
30
P
S
DEV DEV
A6 A5
DEV DEV
A1
D7
D0
ACK
ACK
R/W
A0
SEPARATE
READ AND
WRITE
TRANSACTIONS
t4
25
26
27
28
29
35
36
37
19
20
21
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE TWO LSB Xs ARE DON'T CARE BITS.
5. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. THE R/W BIT IS SET TO 1 TO INDICATE A READBACK OPERATION.
Figure 44. Example of I2C Timing for Single Register Readback Operation
WRITE
7-BIT DEVICE
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
. . .
S
P
W
ADDRESS
READ (USING REPEATED START)
7-BIT DEVICE
ADDRESS
REGISTER ADDR
[7:0]
7-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
READ DATA
READ DATA
LOW BYTE [7:0]
LOW BYTE [7:0] . . . HIGH BYTE [15:8]
S
R
P
W
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
7-BIT DEVICE
ADDRESS
REGISTER ADDR
[7:0]
7-BIT DEVICE
ADDRESS
READ DATA
R
READ DATA
READ DATA
READ DATA
LOW BYTE [7:0]
LOW BYTE [7:0] . . . HIGH BYTE [15:8]
S
P
S
P
W
HIGH BYTE [15:8]
OUTPUT FROM MASTER S = START BIT
W = WRITE BIT
P = STOP BIT
SR = REPEATED START BIT
R = READ BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
OUTPUT FROM
AD7879-1/AD7889-1
Figure 45. Example of Sequential I2C Write and Readback Operation
Rev. C | Page 3± of 40
AD7879/AD7889
GROUNDING AND LAYOUT
of at least 0.25 mm between the thermal pad and the inner
edges of the land pattern on the PCB. Thermal vias can be used
on the PCB thermal pad to improve the thermal performance of
the package. If vias are used, incorporate them into the thermal
pad at a 1.2 mm pitch grid. The via diameter should be between
0.3 mm and 0.33 mm, and the via barrel should be plated with
1 oz. of copper to plug the via.
For detailed information on grounding and layout considerations
for the AD7879/AD7889, refer to the AN-577 Application Note,
Layout and Grounding Recommendations for Touch Screen
Digitizers.
LEAD FRAME CHIP SCALE PACKAGES
The lands on the lead frame chip scale package (CP-16-10) are
rectangular. The printed circuit board (PCB) pad for these lands
should be 0.1 mm longer than the package land length and
0.05 mm wider than the package land width. Center the land on
the pad to maximize the solder joint size.
Connect the PCB thermal pad to GND.
WLCSP ASSEMBLY CONSIDERATIONS
For detailed information on the WLCSP PCB assembly and
reliability, see the AN-617 Application Note, MicroCSP™ Wafer
Level Chip Scale Package.
The bottom of the lead frame chip scale package has a central
thermal pad. The thermal pad on the PCB should be at least as
large as this exposed pad. To avoid shorting, provide a clearance
VOLTAGE
REGULATOR
MAIN
BATTERY
0.1µF
0.1µF TO 10µF
(OPTIONAL)
16
15 14
13
HOST
CS
12
1
2
INT
Y+
NC
NC
X–
PENIRQ/INT/DAV
NC
11
SCLK
MISO
MOSI
AD7879/
AD7889
10
9
3
4
NC
DOUT
TOUCH
SCREEN
5
6
7
8
NC = NO CONNECT
Figure 46. Typical Application Circuit
Rev. C | Page 37 of 40
AD7879/AD7889
OUTLINE DIMENSIONS
0.65
0.59
0.53
1.67
1.61
1.55
0.17
0.15
0.13
SEATING
PLANE
3
2
1
A
BALL 1
IDENTIFIER
2.07
2.01
1.95
B
C
D
0.36
0.32
0.28
1.50
REF
0.50
REF
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.10 MAX
0.37
0.35
0.33
COPLANARITY
0.28
0.24
0.20
Figure 47. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-1)
Dimensions shown in millimeters
0.650
0.59
0.540
5
1.555
1.505
1.455
0
.040 MAX
SEATING
PLANE
0.020 MIN
3
2
1
A
BALL 1
IDENTIFIER
2.055
2.005
1.955
B
C
D
0.340
0.320
0.300
1.50
REF
0.50
REF
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.10 MAX
0.380
0.355
0.330
COPLANARITY
1.00
REF
0.270
0.240
0.210
Figure 48. 12-Ball, Backside-Coated Wafer Level Chip Scale Package [WLCSP]
(CB-12-5)
Dimensions shown in millimeters
4.00
BSC SQ
0.60 MAX
0.60 MAX
0.65 BSC
PIN 1
INDICATOR
13
16
1
12
9
PIN 1
INDICATOR
2.50
2.35 SQ
2.20
TOP
VIEW
EXPOSED
3.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
4
8
5
0.25 MIN
0.80 MAX
0.65 TYP
12° MAX
1.95 BSC
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
Rev. C | Page 38 of 40
AD7879/AD7889
ORDERING GUIDE
Temperature
Range
Serial Interface
Description
Package
Model1
Package Description
12-Ball WLCSP
12-Ball WLCSP
1±-Lead LFCSP_VQ
1±-Lead LFCSP_VQ
12-Ball WLCSP
12-Ball WLCSP
1±-Lead LFCSP_VQ
1±-Lead LFCSP_VQ
Option
CB-12-1
CB-12-1
CP-1±-10
CP-1±-10
CB-12-1
CB-12-1
CP-1±-10
CP-1±-10
CB-12-5
CB-12-5
CB-12-5
CB-12-5
CB-12-5
Branding
T2Y
T2Y
AD7879ACBZ-RL
AD7879ACBZ-500R7
AD7879ACPZ-RL
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
SPI Interface
SPI Interface
SPI Interface
SPI Interface
I2C Interface
I2C Interface
I2C Interface
I2C Interface
SPI Interface
SPI Interface
I2C Interface
I2C Interface
I2C Interface
SPI Interface
I2C Interface
AD7879ACPZ-500R7
AD7879-1ACBZ-RL
AD7879-1ACBZ-500R7
AD7879-1ACPZ-RL
AD7879-1ACPZ-500R7
AD7889ACBZ-RL
AD7889ACBZ-500R7
AD7889-1ACBZ-RL
AD7889-1ACBZ-RL7
AD7889-1ACBZ-500R7
EVAL-AD7879EBZ
EVAL-AD7879-1EBZ
T0Q
T0Q
12-Ball, Backside-Coated WLCSP
12-Ball, Backside-Coated WLCSP
12-Ball, Backside-Coated WLCSP
12-Ball, Backside-Coated WLCSP
12-Ball, Backside-Coated WLCSP
Evaluation Board
T3R
T3R
T3Q
T3Q
T3Q
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. C | Page 39 of 40
AD7879/AD7889
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07667-0-11/10(C)
Rev. C | Page 40 of 40
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