AD7890AR-4_技术文档

2

LC MOS 8-Channel, 12-Bit

Serial, Data Acquisition System

a

AD7890

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

Fast 12-Bit ADC w ith 5.9 ␮s Conversion Tim e

Eight Single-Ended Analog Input Channels

Selection of Input Ranges:

؎10 V for AD7890-10

0 V to ؉4.096 V for AD7890-4

0 V to ؉2.5 V for AD7890-2

MUX SHA REF OUT/

V_DD

OUT IN

REF IN

2kΩ

SIGNAL

SCALING*

+2.5V

REFERENCE

V_IN1

V_IN2

SIGNAL

SCALING*

AD7890

Allow s Separate Access to Multiplexer and ADC

On-Chip Track/ Hold Am plifier

On-Chip Reference

High Speed, Flexible, Serial Interface

Single Supply, Low Pow er Operation (50 m W m ax)

Pow er-Dow n Mode (75 ␮W typ)

SIGNAL

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

V_IN8

SCALING*

C_EXT

SIGNAL

SCALING*

M

U

X

SIGNAL

SCALING*

CONVST

SIGNAL

SCALING*

12-BIT

ADC

SIGNAL

SCALING*

TRACKHOLD

SIGNAL

SCALING*

OUTPUT/CONTROL REGISTER

CLOCK

GENERAL D ESCRIP TIO N

The AD7890 is an eight-channel 12-bit data acquisition system.

The part contains an input multiplexer, an on-chip track/hold

amplifier, a high-speed 12-bit ADC, a +2.5 V reference and a high

speed, serial interface. The part operates from a single +5 V supply

and accepts an analog input range of ±10 V (AD7890-10), 0 V to

+4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2).

AGND AGND

DGND CLK

IN

SCLK

DATA SMODE

IN

TFS

DATA

OUT

RFS

*NO SCALING ON AD7890-2

Power dissipation in normal mode is low at 30 mW typ and the

part can be placed in a standby (power-down) mode if it is not

required to perform conversions. T he AD7890 is fabricated in

Analog Devices’ Linear Compatible CMOS (LC²MOS) process,

a mixed technology process that combines precision bipolar cir-

cuits with low power CMOS logic. T he part is available in a

24-pin, 0.3" wide, plastic or hermetic dual-in-line package or in

a 24-pin small outline package (SOIC).

T he multiplexer on the part is independently accessible. T his

allows the user to insert an antialiasing filter or signal condition-

ing, if required, between the multiplexer and the ADC. T his

means that one antialiasing filter can be used for all eight chan-

nels. Connection of an external capacitor allows the user to

adjust the time given to the multiplexer settling to include any

external delays in the filter or signal conditioning circuitry.

Output data from the AD7890 is provided via a high speed bidi-

rectional serial interface port. T he part contains an on-chip con-

trol register, allowing control of channel selection, conversion

start and power-down via the serial port. Versatile, high speed

logic ensures easy interfacing to serial ports on microcontrollers

and digital signal processors.

P RO D UCT H IGH LIGH TS

1. Complete 12-Bit Data Acquisition System on a Chip

T he AD7890 is a complete monolithic ADC combining an

eight-channel multiplexer, 12-bit ADC, +2.5 V reference and

a track/hold amplifier on a single chip.

2. Separate Access to Multiplexer and ADC

In addition to the traditional dc accuracy specifications such as

linearity, full-scale and offset errors, the AD7890 is also speci-

fied for dynamic performance parameters including harmonic

distortion and signal-to-noise ratio.

T he AD7890 provides access to the output of the multiplexer

allowing one antialiasing filter for eight channels—a consid-

erable saving over the eight antialiasing filters required if the

multiplexer was internally connected to the ADC.

3. High Speed Serial Interface

T he part provides a high speed serial interface for easy

connection to serial ports of microcontrollers and DSP

processors.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

(V = +5 V, AGND = DGND = 0 V, REF IN = +2.5 V, f_{CLK IN}= 2.5 MHz external,

DD

AD7890–SPECIFICATIONS

MUX OUT connect to SHA IN. All specifications T_MINto T_MAXunless otherwise noted.)

P aram eter

A Versions¹B Versions S Version

Units

Test Conditions/Com m ents

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio²

T otal Harmonic Distortion (T HD)²

Peak Harmonic or Spurious Noise²

Intermodulation Distortion

2nd Order T erms

Using External CONVST. Any Channel

f_IN= 10 kHz Sine Wave, f_SAMPLE= 100 kHz³

fa = 9 kHz, fb = 9.5 kHz, f_SAMPLE= 100 kHz³

70

–78

–79

70

–78

–79

70

–78

–79

dB min

dB max

–80

dB typ

dB max

3rd Order T erms

Channel-to-Channel Isolation²

f_IN= 1 kHz Sine Wave

DC ACCURACY

Resolution

12

Bits

Minimum Resolution for Which

No Missing Codes Are Guaranteed 12

12

±0.5

±1

±2.5

2

12

Bits

Relative Accuracy²

±1

±2.5

2

±1

±2.5

2

LSB max

Differential Nonlinearity²

Positive Full-Scale Error²

Full-Scale Error Match⁴

AD7890-2, AD7890-4

Unipolar Offset Error²

Unipolar Offset Error Match

AD7890-10 Only

±2

2

±2

2

±2

2

LSB max

Negative Full-Scale Error²

±2

±4

2

±2

±4

2

±2

±4

2

LSB max

Bipolar Zero Error²

Bipolar Zero Error Match

ANALOG INPUT S

AD7890-10

Input Voltage Range

Input Resistance

AD7890-4

±10

20

±10

20

±10

20

Volts

kΩ min

Input Voltage Range

Input Resistance

AD7890-2

0 to +4.096

11

0 to +4.096 0 to +4.096

Volts

kΩ min

11

Input Voltage Range

Input Current

0 to +2.5

50

0 to +2.5

50

0 to +2.5

200

Volts

nA max

MUX OUT OUT PUT

Output Voltage Range

Output Resistance

0 to +2.5

Volts

(AD7890-10, AD7890-4)

(AD7890-2)

3/5

2

3/5

2

3/5

2

kΩ min/kΩ max

kΩ max

Assuming V_INIs Driven from Low Impedance

SHA IN INPUT

Input Voltage Range

Input Current

0 to +2.5

±50

0 to +2.5

±50

0 to +2.5

±50

Volts

nA max

REFERENCE OUT PUT /INPUT

REF IN Input Voltage Range

Input Impedance

2.375/2.625

1.6

10

2.5

±10

±20

25

2.375/2.625 2.375/2.625 V min/V max

2.5 V ± 5%

1.6

10

2.5

±10

±20

25

1.6

10

2.5

±10

±25

25

kΩ min

pF max

V nom

mV max

ppm/°C typ

kΩ nom

Resistor Connected to Internal Reference Node

Input Capacitance⁵

REF OUT Output Voltage

REF OUT Error @ +25°C

T _MINto T _MAX

REF OUT T emperature Coefficient

REF OUT Output Impedance

2

LOGIC INPUT S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

±10

10

2.4

0.8

±10

10

2.4

0.8

±10

10

V min

V_DD= 5 V ± 5%

V_IN= 0 V to V_DD

V max

µA max

pF max

5

Input Capacitance, C_IN

–2–

REV. 0

AD7890

P aram eter

A Versions¹B Versions S Version

Units

Test Conditions/Com m ents

LOGIC OUT PUT S

Output High Voltage, V_OH

Output Low Voltage, V_OL

Serial Data Output Coding

AD7890-10

4.0

0.4

4.0

0.4

4.0

0.4

V min

V max

I_SOURCE= 200 µA

I_SINK= 1.6 mA

2s Complement

AD7890-4

AD7890-2

Straight (Natural) Binary

CONVERSION RAT E

Conversion T ime

5.9

2

5.9

2

5.9

2

µs max

f_{CLK IN}= 2.5 MHz, MUX OUT

Connected to SHA IN

T rack/Hold Acquisition T ime^{2, 5}

POWER REQUIREMENT S

V_DD

I_DD(Normal Mode)

I_DD(Standby Mode)⁶@ +25°C

Power Dissipation

+5

10

15

+5

10

15

+5

10

15

V nom

mA max

µA typ

±5% for Specified Performance

Logic Inputs = 0 V or V_DD

Normal Mode

Standby Mode @ +25°C

50

75

50

75

50

75

mW max

µW typ

T ypically 30 mW

NOT ES

¹T emperature ranges are as follows: A, B Versions: –40°C to –85°C; S Version: –55°C to +125°C.

²See T erminology.

³T his sample rate is only achievable when tiling the part in external clocking mode.

⁴Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.

⁵Sample tested @ +25°C to ensure compliance.

⁶Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.

Specifications subject to change without notice.

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ABSO LUTE MAXIMUM RATINGS*

(T _A= +25°C unless otherwise noted)

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND

AD7890-10, AD7890-4 . . . . . . . . . . . . . . . . . . . . . . . ±17 V

AD7890-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to AGND . . . –0.3 V to V_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to V_DD+ 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage T emperature Range . . . . . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . +260°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 70°C/W

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . +300°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead T emperature, Soldering

O RD ERING GUID E

Tem perature

Range

Linearity

Error

P ackage

O ption*

Model

AD7890AN-2

AD7890BN-2

AD7890AR-2

AD7890BR-2

AD7890SQ-2

AD7890AN-4

AD7890BN-4

AD7890AR-4

AD7890BR-4

AD7890SQ-4

AD7890AN-10

AD7890BN-10

AD7890AR-10

AD7890BR-10

AD7890SQ-10

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

–55°C to +125°C

±1 LSB

±1/2 LSB

±1 LSB

±1/2 LSB

±1 LSB

±1/2 LSB

±1 LSB

±1/2 LSB

±1 LSB

±1/2 LSB

±1 LSB

±1/2 LSB

±1 LSB

N-24

R-24

Q-24

N-24

R-24

Q-24

N-24

R-24

Q-24

NOT E

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*N = Plastic DIP; Q = Cerdip; R = SOIC.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7890 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

AD7890

TIMING CHARACTERISTICS

(V = +5 V ؎ 5%, AGND = DGND = 0 V, REF IN = +2.5 V, f_{CLK IN}= 2.5 MHz external, MUX OUT

connected to SHA IN.)

DD

1, 2

Lim it at T_MIN, T_MAX

P aram eter

(A, B, S Versions)

Units

Conditions/Com m ents

3

f_CLKIN

100

2.5

0.3 × t_{CLK IN}

0 3 × t_{CLK IN}

25

5.9

100

kHz min

MHz max

ns min

Master Clock Frequency. For Specified Performance

t_{CLK IN LO}

t_{CLK IN HI}

Master Clock Input Low T ime

Master Clock Input High T ime

Digital Output Rise T ime. T ypically 10 ns

Digital Output Fall T ime. T ypically 10 ns

Conversion T ime

ns min

tr⁴

ns max

µs max

ns min

tf⁴

t_CONVERT

t_CST

CONVST Pulse Width

Self-Clocking Mode

t₁

t₂

t_{CLK IN HI}+ 50

25

t_{CLK IN HI}

t_{CLK IN LO}

20

40

50

0

t_{CLK IN}+ 50

0

20

10

20

ns max

ns nom

ns max

ns min

ns max

ns min

RFS Low to SCLK Falling Edge

RFS Low to Data Valid Delay

SCLK High Pulse Width

5

t₃

t₄

t₅

SCLK Low Pulse Width

5

SCLK Rising Edge to Data Valid Delay

SCLK Rising Edge to RFS Delay

Bus Relinquish T ime after Rising Edge of SCLK

TFS Low to SCLK Falling Edge

t₆₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

Data Valid to TFS Falling Edge Setup T ime (A2 Address Bit)

Data Valid to SCLK Falling Edge Setup T ime

Data Valid to SCLK Falling Edge Hold T ime

TFS to SCLK Falling Edge Hold T ime

External-Clocking Mode

t₁₃

t₁₄

20

40

50

35

20

50

90

20

10

15

40

ns min

ns max

ns min

ns max

ns min

ns max

ns min

RFS Low to SCLK Falling Edge Setup T ime

RFS Low to Data Valid Delay

SCLK High Pulse Width

5

t₁₅

t₁₆

t₁₇

SCLK Low Pulse Width

5

SCLK Rising Edge to Data Valid Delay

RFS to SCLK Falling Edge Hold T ime

Bus Relinquish T ime after Rising Edge of RFS

Bus Relinquish T ime after Rising Edge of SCLK

TFS Low to SCLK Falling Edge Setup T ime

Data Valid to SCLK Falling Edge Setup T ime

Data Valid to SCLK Falling Edge Hold T ime

TFS to SCLK Falling Edge Hold T ime

t₁₈

t₁₉

6

t_19A

t₂₀

t₂₁

t₂₂

t₂₃

NOT ES

¹Sample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

²See Figures 8 to 11.

³T he AD7890 is production tested with f_{CLK IN}at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.

⁴Specified using 10% and 90% points on waveform of interest.

⁵T hese numbers are measured with the load circuit of Figure I and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁶T hese numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. T his means that the times quoted in the timing characteristics are the true bus re-

linquish times of the part and as such are independent of external bus loading capacitances.

1.6mA

TO OUTPUT

+2.1V

50pF

200µA

Figure 1. Load Circuit for Access Tim e and Bus Relinquish Tim e

REV. A

–4–

AD7890

P IN FUNCTIO N D ESCRIP TIO N

P in

Mnem onic

D escription

Analog Ground. Ground reference for track/hold, comparator and DAC.

1

2

AGND

SMODE

Control Input. Determines whether the part operates in its External Clocking (slave) or Self-Clocking

(master) serial mode. With SMODE at a logic low, the part is in its Self-Clocking serial mode with

RFS and SCLK as outputs. T his Self-Clocking mode is useful for connection to shift registers or to

serial ports of DSP processors. With SMODE at a logic high, the part is in its External Clocking

serial mode with SCLK and RFS as inputs. T his External Clocking mode is useful for connection to

the serial port of microcontrollers such as the 8XC51 and the 68HCXX and for connection to the

serial ports of DSP processors.

3

4

DGND

C_EXT

Digital Ground. Ground reference for digital circuitry.

External Capacitor. An external capacitor is connected to this pin to determine the length of the

internal pulse (see CONVST input and Control Register section). Larger capacitances on this pin

extend the pulse to allow for settling time delays through an external antialiasing filter or signal

conditioning circuitry.

5

CONVST

Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold

into hold and initiates conversion provided that the internal pulse has timed out (see Control

Register section). If the internal pulse is active when the CONVST goes high, the track/hold will not

go into hold until the pulse times out. If the internal pulse has timed out when CONVST goes high,

the rising edge of CONVST drives the track/hold into hold and initiates conversion.

6

7

CLK IN

SCLK

Clock Input. An external T T L-compatible clock is applied to this input pin to provide the clock

source for the conversion sequence. In the Self-Clocking serial mode, the SCLK output is derived

from this CLK IN pin.

Serial Clock Input. In the External Clocking (slave) mode (see Serial Interface section) this is an

externally applied serial clock which is used to load serial data to the control register and to access

data from the output register. In the Self-Clocking (master) mode, the internal serial clock, which is

derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data

to the control register and to access data from the output register.

8

9

TFS

RFS

T ransmit Frame Synchronization Pulse. Active low logic input with serial data expected after the

falling edge of this signal.

Receive Frame Synchronization Pulse. In the External Clocking mode, this pin is an active low logic

input with RFS provided externally as a strobe or framing pulse to access serial data from the output

register. In the Self-Clocking mode, it is an active low output which is internally generated and

provides a strobe or framing pulse for serial data from the output register. For applications which

require that data be transmitted and received at the same time, RFS and TFS should be connected

together.

10

11

DAT A OUT

DAT A IN

Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three

address bits of the Control register and the 12 bits of conversion data. Serial data is valid on the

falling edge of SCLK for sixteen edges after RFS goes low. Output coding from the ADC is 2s

complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2.

Serial Data Input. Serial data to be loaded to the control register is provided at this input. T he first

five bits of serial data are loaded to the control register on the first five falling edges of SCLK after

TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low.

12

13

V_DD

Positive supply voltage, +5 V ± 5%.

MUX OUT

Multiplexer Output. T he output of the multiplexer appears at this pin. T he output voltage range

from this output is 0 V to +2.5 V for the nominal analog input range to the selected channel. T he

output impedance of this output is nominally 3.5 kΩ. If no external antialiasing filter is required,

MUX OUT should be connected to SHA IN.

14

SHA IN

T rack/Hold Input. T he input to the on-chip track/hold is applied to this pin. It is a high impedance

input and the input voltage range is 0 V to +2.5 V.

15

16

AGND

V_IN1

Analog Ground. Ground reference for track/hold, comparator and DAC.

Analog Input Channel 1. Single-ended analog input. T he analog input range on is ±10 V

(AD7890-10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be con-

verted is selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaran-

teed break-before-make operation.

REV. A

–5–

AD7890

P in

Mnem onic

D escription

17

V_IN2

V_IN3

V_IN4

V_IN5

V_IN6

V_IN7

V_IN8

Analog Input Channel 2. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

18

19

20

21

22

23

24

Analog Input Channel 3. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

Analog Input Channel 4. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

Analog Input Channel 5. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

Analog Input Channel 6. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

Analog Input Channel 7. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

Analog Input Channel 8. Single-ended analog input. T he analog input range on is ±10 V (AD7890-

10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). T he channel to be converted is

selected using the A0, A1 and A2 bits in the control register. T he multiplexer has guaranteed

break-before-make operation.

REF OUT/REF IN Voltage Reference Output/Input. T he part can be used with either its own internal reference or with

an external reference source. T he on-chip +2.5 V reference voltage is provided at this pin. When

using this internal reference as the reference source for the part, REF OUT should decoupled to

AGND with a 0.1 µF disc ceramic capacitor. T he output impedance of this reference source is typi-

cally 2 kΩ. When using an external reference source as the reference voltage for the part, the refer-

ence source should be connected to this pin. T his overdrives the internal reference and provides the

reference source for the part. T he REF IN input is buffered on-chip. T he nominal reference voltage

for correct operation of the AD7890 is +2.5 V.

P IN CO NFIGURATIO N

D IP and SO IC

1

2

3

4

24

23

22

AGND

SMODE

DGND

REF OUT/REF IN

V

IN8

V

IN7

C

21

20

19

V

EXT

IN6

CONVST

CLK IN

SCLK

5

6

7

V

IN5

AD7890

TOP VIEW

(Not to Scale)

V

IN4

18

17

V

IN3

V

TFS

8

9

IN2

16

15

14

V

RFS

IN1

10

11

12

DATA OUT

DATA IN

AGND

SHA IN

MUX OUT

V

13

DD

REV. A

–6–

AD7890

TERMINO LO GY

Channel-to-Channel Isolation

Signal to (Noise + D istor tion) Ratio

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 1 kH z signal to any one of the other seven inputs and

determining how much that signal is attenuated in the chan-

nel of interest. T he figure given is the worst case across all

eight channels.

T his is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. T he signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

T he ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. T he theoretical signal to (noise + distortion) ratio

for an ideal N-bit converter with a sine wave input is given by:

Relative Accur acy

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

D iffer ential Nonlinear ity

T hus for a 12-bit converter, this is 74 dB.

T his is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total H ar m onic D istor tion

T otal harmonic distortion (T HD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7890, it is defined as:

P ositive Full-Scale Er r or (AD 7890-10)

T his is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal (4 × REF IN – 1 LSB) after the Bipolar

Zero Error has been adjusted out.

V₂²+V₃²+V₄²+V₅²+V₆²

THD (dB) = 20 log

V₁

P ositive Full-Scale Er r or (AD 7890-4)

T his is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (1.638 × REF IN – 1 LSB) after the

Unipolar Offset Error has been adjusted out.

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

P ositive Full-Scale Er r or (AD 7890-2)

P eak H ar m onic or Spur ious Noise

T his is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (REF IN – 1 LSB) after the Unipolar

Offset Error has been adjusted out.

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Bipolar Zer o Er r or (AD 7890-10)

T his is the deviation of the midscale transition (all 0s to all 1s)

from the ideal 0 V (AGND).

Unipolar O ffset Er r or (AD 7890-2, AD 7890-4)

T his is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal 0 V (AGND).

Inter m odulation D istor tion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which

neither m nor n are equal to zero. For example, the second order

terms include (fa + fb) and (fa – fb), while the third order terms

include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Negative Full-Scale Er r or (AD 7890-10)

T his is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal (–4 × REF IN + 1 LSB) after Bipolar

Zero Error has been adjusted out.

Tr ack/H old Acquisition Tim e

T rack/Hold acquisition time is the time required for the output

of the track/hold amplifier to reach its final value, within ±1/2 LSB,

after the end of conversion (the point at which the track/hold

returns to track mode). It also applies to situations where a

change in the selected input channel takes place or where there

is a step input change on the input voltage applied to the selected

V_INinput of the AD7890. It means that the user must wait for

the duration of the track/hold acquisition time after the end of

conversion or after a channel change/step input change to V_IN

before starting another conversion, to ensure that the part oper-

ates to specification.

T he AD7890 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second and third order terms are of differ-

ent significance. T he second order terms are usually distanced

in frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. T he calculation of the intermodulation distortion is as

per the T HD specification where it is the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

fundamental expressed in dBs.

REV. A

–7–

AD7890

CO NTRO L REGISTER

CO NVERTER D ETAILS

T he Control Register for the AD7890 contains 5 bits of infor-

mation as described below. Six serial clock pulses must be pro-

vided to the part in order to write data to the Control Register

(seven if the write is required to put the part in Standby Mode).

If TFS returns high before six serial clock cycles then no data

transfer takes place to the Control Register and the write cycle

will have to be restarted to write the data to the Control Regis-

ter. If, however, the CONV bit of the register (see below) is set

to a Logic 1, then a conversion will be initiated whenever a

Control Register write takes place regardless of how many serial

clock cycles the TFS remains low for. T he default (power-on)

condition of all bits in the Control Register is 0.

T he AD7890 is an eight-channel, 12-bit, single supply, serial

data acquisition system. It provides the user with signal scaling,

multiplexer, track/hold, reference, A/D converter and versatile

serial logic functions on a single chip. T he signal scaling allows

the part to handle ±10 V input signals (AD7890-10) and 0 V to

+4.096 V input signals (AD7890-4) while operating from a

single +5 V supply. T he AD7890-2 contains no signal scaling

and accepts an analog input range of 0 V to +2.5 V. T he part

operates from a +2.5 V reference which can be provided from

the part’s own internal reference or from an external reference

source.

Unlike other single chip data acquisition solutions, the AD7890

provides the user with separate access to the multiplexer and the

A/D converter. T his means that the flexibility of separate multi-

plexer and ADC solutions is not sacrificed with the one-chip

solution. With access to the multiplexer output, the user can

implement external signal conditioning between the multiplexer

and the track/hold. It means that one antialiasing filter can be

used on the output of the multiplexer to provide the antialiasing

function for all eight channels.

MSB

A2

A1

A0

CONV

ST BY

A2

A1

A0

Address Input. T his input is the most significant

address input for multiplexer channel selection.

Address Input. T his is the 2nd most significant

address input for multiplexer channel selection.

Conversion is initiated on the AD7890 either by pulsing the

CONVST input or by writing a Logic 1 to the CONV bit of the

Control Register. When using the hardware CONVST input, on

the rising edge of the CONVST signal, the on-chip track/hold

goes from track to hold mode and the conversion sequence is

started provided the internal pulse has timed out. T his internal

pulse (which appears at the C_EXTpin) is initiated whenever the

multiplexer address is loaded to the AD7890 Control Register.

T his pulse goes from high to low when a serial write to the part

is initiated. It starts to discharge on the sixth falling clock edge

of SCLK in a serial write operation to the part. T he track/hold

cannot go into hold and conversion cannot be initiated until the

C_EXTpin has crossed its trigger point of 2.5 V. T he discharge

time of the voltage on C_EXTdepends upon the value of capacitor

connected to the C_EXTpin (see C_EXTFunctioning section). T he

fact that the pulse is initiated every time a write to the control

register takes place means that the software conversion start and

track/hold signal is always delayed by the internal pulse.

Address Input. Least significant address input for

multiplexer channel selection. When the address is

written to the control register, an internal pulse is

initiated, the pulse width of which is determined by

the value of capacitance on the C_EXTpin. When this

pulse is active, it ensures the conversion process

cannot be activated. T his allows for the multiplexer

settling time and track/hold acquisition time before

the track/hold goes into hold and conversion is

initiated. In applications where there is an anti-

aliasing filter between MUX OUT and SHA IN, the

filter settling time can be taken into account before

the input at SHA IN is sampled. When the internal

pulse times out, the track/hold goes into hold and

conversion is initiated.

CONV

Conversion Start. Writing a 1 to this bit initiates a

conversion in a similar manner to the CONVST

input. Continuous conversion starts do not take place

when there is a 1 in this location. T he internal pulse

and the conversion process are initiated after the

sixth serial clock cycle of the write operation if a 1 is

written to this bit. With a 1 in this bit, the hardware

conversion start i.e., the CONVST input, is

disabled. Writing a 0 to this bit enables the hard-

ware CONVST input.

T he conversion clock for the part is generated from the clock

signal applied to the CLK IN pin of the part. Conversion time

for the AD7890 is 5.9 µs from the rising edge of the hardware

CONVST signal and the track/hold acquisition time is 2 µs. T o

obtain optimum performance from the part, the data read opera-

tion or Control Register write operation should not occur during

the conversion or during 500 ns prior to the next conversion.

T his allows the part to operate at throughput rates up to

117 kHz in the external clocking mode and achieve data sheet

specifications. T he part can operate at slightly higher through-

put rates (up to 127 kHz), again in external clocking mode with

degraded performance (see T iming and Control section). T he

throughput rate for self-clocking mode is limited by the serial

clock rate to 78 kHz.

ST BY

Standby Mode Input. Writing a 1 to this bit places

the device in its standby or power-down mode.

Writing a 0 to this bit places the device in its normal

operating mode. T he part does not enter its standby

mode until the seventh falling edge of SCLK in a

write operation. T herefore, the part requires seven

serial clock pulses in its serial write operation if it is

required to put the part into standby.

All unused inputs should be connected to a voltage within the

nominal analog input range to avoid noise pickup. On the

AD7890-10, if any one of the input channels which are not be-

ing converted goes more negative than –12 V, it can interfere

with the conversion on the selected channel.

REV. A

–8–

AD7890

CIRCUIT D ESCRIP TIO N

Analog Input Section

T he AD7890 is offered as three part types, the AD7890-10

which handles a ±10 V input voltage range, the AD7890-4

which handles a 0 V to +4.096 V input range and the AD7890-2

which handles a 0 V to +2.5 V input voltage range.

tions occur on successive integer LSB values (i.e., 1 LSB,

2 LSBs, 3 LSBs . . . ). Output coding is straight (natural)

binary with 1 LSB = FS/4096 = 4.096 V/4096 = 1 mV. T he

ideal input/output transfer function is shown in T able II.

MUX OUT

+2.5V

REFERENCE

AD7890-10

2kΩ

Figure 2 shows the analog input section for the AD7890-10.

T he analog input range for each of the analog inputs is ±10 V

into an input resistance of typically 33 kΩ. T his input is benign

with no dynamic charging currents with the resistor attenuator

stage followed by the multiplexer and in cases where MUX

OUT is connected to SHA IN this is followed by the high input

impedance stage of the track/hold amplifier. T he designed code

transitions occur on successive integer LSB values (i.e., 1 LSB,

2 LSBs, 3 LSBs...). Output coding is 2s complement binary

with 1 LSB – FS/4096 = 20 V/4096 = 4.88 mV. The ideal input/

output transfer function is shown in T able I.

REF OUT/

REF IN

TO ADC

REFERENCE

CIRCUITRY

6kΩ

200Ω*

V

INX

9.38kΩ

AD7890-4

AGND

*EQUIVALENT ON-RESISTANCE OF MULTIPLEXER

Figure 3. AD7890-4 Analog Input Structure

MUX OUT

Table II. Ideal Input/O utput Code Table for the AD 7890-4

D igital O utput

+2.5V

REFERENCE

2kΩ

REF OUT/

REF IN

Analog Input¹

Code Transition

TO ADC

REFERENCE

CIRCUITRY

+FSR – 1 LSB²(4.095 V)

+FSR – 2 LSBs (4.094 V)

+FSR – 3 LSBs (4.093 V)

111 . . . 110 to 111 . . . 111

111 . . . 101 to 111 . . . 110

111 . . . 100 to 111 . . . 101

7.5kΩ

30kΩ

200Ω*

V

INX

10kΩ

AGND + 3 LSBs (0.003 V)

AGND + 2 LSBs (0.002 V)

AGND + 1 LSB (0.001 V)

000 . . . 010 to 000 . . . 011

000 . . . 001 to 000 . . . 010

000 . . . 000 to 000 . . . 001

AD7890-10

AGND

*EQUIVALENT ON-RESISTANCE OF MULTIPLEXER

NOT ES

¹FSR is full-scale range and is 4.096 V with REF IN +2.5 V.

²1 LSB = FSR/4096 = 1 mV with REF IN = +2.5 V.

Figure 2. AD7890-10 Analog Input Structure

AD7890-2

Table I. Ideal Input/O utput Code Table for the AD 7890-10

D igital O utput

T he analog input section for the AD7890-2 contains no biasing

resistors and the selected analog input connects to the multi-

plexer and in cases where MUX OUT is connected to SHA IN

this is followed by the high input impedance stage of the track/

hold amplifier. The analog input range is, therefore, 0 V to +2.5 V

into a high impedance stage with an input current of less than

50 nA. The designed code transitions occur on successive integer

LSB values (i.e., l LSB, 2 LSBs, 3 LSBs . . . FS-1 LSBs). Out-

put coding is straight (natural) binary with 1 LSB = FS/4096 =

2.5 V/4096 = 0.61 mV. T he ideal input/output transfer function

is shown in T able III.

Analog Input¹

Code Transition

+FSR/2 – 1 LSB²(9.995117 V)

+FSR/2 – 2 LSBs (9.990234 V)

+FSR/2 – 3 LSBs (9.985352 V)

011 . . . 110 to 011 . . . 111

011 . . . 101 to 011 . . . 110

011 . . . 100 to 011 . . . 101

AGND + 1 LSB (0.004883 V)

AGND (0.000000 V)

AGND – 1 LSB (–0.004883 V)

000 . . . 000 to 000 . . . 001

111 . . . 111 to 000 . . . 000

111 . . . 110 to 111 . . . 111

–FSR/2 + 3 LSBs (–9.985352 V) 100 . . . 010 to 100 . . . 011

–FSR/2 + 2 LSBs (–9.990234 V) 100 . . . 001 to 100 . . . 010

–FSR/2 + 1 LSB (–9.995117 V)

Table III. Ideal Input/O utput Code Table for the AD 7890-2

D igital O utput

100 . . . 000 to 100 . . . 001

NOT ES

¹FSR is full-scale range and is 20 V with REF IN = +2.5 V.

²1 LSB = FSR/4096 = 4.883 mV with REF IN = +2.5 V.

Analog Input¹

Code Transition

+FSR – 1 LSB²(2.499390 V)

+FSR – 2 LSBs (2.498779 V)

+FSR – 3 LSBs (2.498169 V)

111 . . . 110 to 111 . . . 111

111 . . . 101 to 111 . . . 110

111 . . . 100 to 111 . . . 101

AD7890-4

Figure 3 shows the analog input section for the AD7890-4. T he

analog input range for each of the analog inputs is ±10 V into

an input resistance of typically 15 kΩ. T his input is benign with

no dynamic charging currents with the resistor attenuator stage

followed by the multiplexer and in cases where MUX OUT is

connected to SHA IN this is followed by the high input imped-

ance stage of the track/hold amplifier. T he designed code transi-

AGND + 3 LSBs (0.001831 V)

AGND + 2 LSBs (0.001221 V)

AGND + 1 LSB (0.000610 V)

000 . . . 010 to 010 . . . 011

000 . . . 001 to 001 . . . 010

000 . . . 000 to 000 . . . 001

NOT ES

¹FSR is full-scale range and is 2.5 V with REF IN = +2.5 V.

²1 LSB = FSR/4096 = 0.61 mV with REF IN = +2.5 V.

REV. A

–9–

AD7890

If the application requires a reference with a tighter tolerance or

the AD7890 needs to be used with a system reference, then the

user has the option of connecting an external reference to this

REF OUT /REF IN pin. T he external reference will effectively

overdrive the internal reference and thus provide the reference

source for the ADC. T he reference input is buffered but has a

nominal 2 kΩ resistor connected to the AD7890’s internal refer-

ence. Suitable reference sources for the AD7890 include the

AD680, AD780 and REF-43 precision +2.5 V references.

Tr ack/H old Section

T he SH A IN input on the AD7890 connects directly to the

input stage of the track/hold amplifier. T his is a high impedance

input with input leakage currents of less than 50 nA. Connect-

ing the MUX OUT pin directly to the SHA IN pin connects the

multiplexer output directly to the track/hold amplifier. T he

input voltage range for this input is 0 V to +2.5 V. If external

circuitry is connected between MUX OUT and SHA IN, then

the user must ensure that the input voltage range to the SH A

IN input is 0 V to +2.5 V to ensure that the full dynamic range

of the converter is utilized.

Tim ing and Contr ol Section

The AD7890 is capable of two interface modes, selected by the

SMODE input. The first of these is a self-clocking mode where the

part provides the frame sync, serial clock and serial data at the end

of conversion. In this mode the serial clock rate is determined by

the master clock rate of the part (at CLK IN input). The second

mode is an external clocking mode where the user provides the

frame sync and serial clock signals to obtain the serial data from the

part. In this second mode, the user has control of the serial clock

rate up to a maximum of 10 MHz. The two modes are discussed in

more detail in the Serial Interface section.

T he track/hold amplifier on the AD7890 allows the ADC to

accurately convert an input sine wave of full-scale amplitude to

12-bit accuracy. T he input bandwidth of the track/hold is

greater than the Nyquist rate of the ADC even when the ADC is

operated at its maximum throughput rate of 117 kHz (i.e., the

track/hold can handle input frequencies in excess of 58 kHz).

T he track/hold amplifier acquires an input signal to 12-bit accu-

racy in less than 2 µs. T he operation of the track/hold is essen-

tially transparent to the user. T he track/hold amplifier goes from

its tracking mode to its hold mode at the start of conversion.

T he start of conversion is the rising edge of CONVST (assum-

ing the internal pulse has timed out) for hardware conversion

starts and for software conversion starts is the point where the

internal pulse is timed out. T he aperture time for the track/hold

(i.e., the delay time between the external CONVST signal and

the track/hold actually going into hold) is typically 15 ns. For

software conversion starts, the time depends on the internal

pulse widths. T herefore, for software conversion starts, the sam-

pling instant is not very well defined. For sampling systems

which require well defined, equidistant sampling, it may not be

possible to achieve optimum performance from the part using

the software conversion start. At the end of conversion, the part

returns to its tracking mode. T he acquisition time of the track/

hold amplifier begins at this point.

T he part also provides hardware and software conversion start

features. T he former provides a well-defined sampling instant

with the track/hold going into hold on the rising edge of the

CONVST signal. For the software conversion start, a write to

the CONV bit to the Control Register initiates the conversion

sequence. However, for the software conversion start an internal

pulse has to time out before the input signal is sampled. T his

pulse, plus the difficult in maintaining exactly equal delays

between each software conversion start command, means that

the dynamic performance of the AD7890 may have difficulty

meeting spec when used in software conversion start mode.

The AD7890 provides separate channel select and conversion start

control. This allows the user to optimize the throughput rate of the

system. Once the track/hold has gone into hold mode, the input

channel can be updated and the input voltage can settle to the new

value while the present conversion is in progress.

Refer ence Section

T he AD7890 contains a single reference pin, labelled

REF OUT /REF IN, which either provides access to the part’s

own +2.5 V reference or to which an external +2.5 V reference

can be connected to provide the reference source for the part.

T he part is specified with a +2.5 V reference voltage. Errors in

the reference source will result in gain errors in the AD7890’s

transfer function and will add to the specified full-scale errors

on the part. On the AD7893-10, it will also result in an offset

error injected in the attenuator stage.

Assuming the internal pulse has timed out before the CONVST

pulse is exercised, the conversion will consist of 14.5 master

clock cycles. In the self-clocking mode, the conversion time is

defined as the time from the rising edge of CONVST to the fall-

ing edge of RFS (i.e., when the device starts to transmit its con-

version result). T his time includes the 14.5 master clock cycles

plus the updating of the output register and delay time in out-

putting the RFS signal, resulting in a total conversion time of

5.9 µs maximum. Figure 4 shows the conversion timing for the

AD890 when used in the Self-Clocking (Master) Mode with

hardware CONVST. T he timing diagram assumes that the

internal pulse is not active when the CONVST signal goes high.

T o ensure this, the channel address to be converted should be

selected by writing to the Control Register prior to the

CONVST pulse. Sufficient setup time should be allowed

between the Control Register write and the CONVST to ensure

that the internal pulse has timed out. T he duration of the inter-

nal pulse (and hence the duration of setup time) depends on the

T he AD7890 contains an on-chip +2.5 V reference. T o use this

reference as the reference source for the AD7890, simply con-

nect a 0.1 µF disc ceramic capacitor from the REF OUT / REF

IN pin to AGND. T he voltage which appears at this pin is inter-

nally buffered before being applied to the ADC. If this reference

is required for use external to the AD7890, it should be buffered

as the source impedance of this output is 2 kΩ nominal. T he

tolerance on the internal reference is ±10 mV at 25°C with a

typical temperature coefficient of 25 ppm/°C and a maximum

error over temperature of ±25 mV.

value of C_EXT

.

REV. A

–10–

AD7890

CONVST (I)

TRACK/HOLD

GOES INTO HOLD

t_CONVERT

RFS (O)

SCLK (O)

THREE-STATE

DATA OUT (O)

NOTE

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

Figure 4. Self-Clocking {Master) Mode Conversion Sequence

When using the device in the External-Clocking Mode, the out-

put register can be read at any time and the most up-to-date

conversion result will be obtained. However, reading data from

the output register or writing data to the Control Register dur-

ing conversion or during the 500 ns prior to the next CONVST

will result in reduced performance from the part. A read opera-

tion to the output register has most effect on performance with

the signal-to-noise ratio likely to degrade especially when higher

serial clock rates are used while the code flicker from the part

will also increase (see AD7890 Performance section).

the next rising edge of CONVST to optimize the settling of the

track/hold before the next conversion is initiated. T he diagram

shows the read operation and the write operation taking place in

parallel. On the sixth falling edge of SCLK in the write sequence

the internal pulse will be initiated. Assuming MUX OUT is

connected to SHA IN, 2 µs are required between this sixth fall-

ing edge of SCLK and the rising edge of CONVST to allow for

the full acquisition time of the track/hold amplifier. With the

serial clock rate at its maximum of 10 MHz, the achievable

throughput rate for the part is 5.9 µs (conversion time) plus

0.6 µs (six serial clock pulses before internal pulse is initiated)

plus 2 µs (acquisition time). T his results in a minimum through-

put time of 8.5 µs (equivalent to a throughput rate of 117 kHz).

If the part is operated with a slower serial clock, it will impact

the achievable throughput rate for optimum performance.

Figure 5 shows the timing and control sequence required to

obtain optimum performance from the part in the external

clocking mode. In the sequence shown, conversion is initiated

on the rising edge of CONVST and new data is available in the

output register of the AD7890 5.9 µs later. Once the read oper-

ation has taken place, a further 500 ns should be allowed before

CONVST

SCLK

RFS

TFS

t_CONVERT

500ns MIN

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

SERIAL READ

& WRITE

OPERATIONS

READ & WRITE

START COMMAND

OPERATIONS SHOULD END

500ns PRIOR TO NEXT

RISING EDGE OF CONVST

Figure 5. External Clocking (Slave) Mode Tim ing

Sequence for Optim um Perform ance

REV. A

–11–

AD7890

CONVST

SCLK

RFS

TFS

t_CONVERT

500ns MIN

µP INT

SERVICE OR

POLLING

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

SERIAL READ

& WRITE

OPERATIONS

READ & WRITE

NEXT CONVST

RISING EDGE

OPERATIONS SHOULD

END 500ns PRIOR TO

NEXT RISING EDGE OF

ROUTINE

CONVST

Figure 6. CONVST Used as Status Signal in External Clocking Mode

C_EXTFUNCTIO NING

In the Self-Clocking Mode, the AD7890 indicates when conver-

sion is complete by bringing the RFS line low and initiating a

serial data transfer. In the external clocking mode, there is no

indication of when conversion is complete. In many applica-

tions, this will not be a problem as the data can be read from the

part during conversion or after conversion. However, applica-

tions which want to achieve optimum performance from the

AD7890 will have to ensure that the data read does not occur

during conversion or during 500 ns prior to the rising edge of

CONVST. T his can be achieved in either of two ways. T he first

is to ensure in software that the read operation is not initiated

until 5.9 µs after the rising edge of CONVST. T his will only be

possible if the software knows when the CONVST command is

issued. T he second scheme would be to use the CONVST sig-

nal as both the conversion start signal and an interrupt signal.

T he simplest way to do this would be to generate a square wave

signal for CONVST with high and low times of 5.9 µs (see Fig-

ure 6). Conversion is initiated on the rising edge of CONVST.

T he falling edge of CONVST occurs 5.9 µs later and can be

used as either an active low or falling edge-triggered interrupt

signal to tell the processor to read the data from the AD7890.

Provided the read operation is completed 500 ns before the ris-

ing edge of CONVST, the AD7890 will operate to specification.

T he C_EXTinput on the AD7890 provides a means of determin-

ing how long after a new channel address is written to the part

that a conversion can take place. T he reason behind this is

two-fold. Firstly, when the input channel to the AD7890 is

changed, the input voltage on this new channel is likely to be

very different from the previous channel voltage. T herefore, the

part’s track/hold has to acquire the new voltage before an accu-

rate conversion can take place. An internal pulse delays any con-

version start command (as well as the signal to send the track/

hold into hold) until after this pulse has timed out. T he second

reason is to allow the user to connect external antialiasing or sig-

nal conditioning circuitry between MUX OUT and SHA IN.

T his external circuitry will introduce extra settling time into the

system. T he C_EXTpin provides a means for the user to extend

the internal pulse to take this extra settling time into account.

Basically, varying the value of the capacitor on the C_EXTpin var-

ies the duration of the internal pulse. Figure 7 shows the rela-

tionship between the value of the C_EXTcapacitor and the

internal delay.

64

56

T = +85 °C

A

T his scheme limits the throughput rate to 11.8 µs minimum.

However, depending upon the response time of the micropro-

cessor to the interrupt signal and the time taken by the proces-

sor to read the data, this may the fastest which the system could

have operated. In any case, the CONVST signal does not have

to have a 50:50 duty cycle. T his can be tailored to optimize the

throughput rate of the part for a given system.

T

= +25 °C

48

40

32

24

16

8

A

T

= –40 °C

A

Alternatively, the CONVST signal can be used as a normal nar-

row pulse width. T he rising edge of CONVST can be used as an

active high or rising edge-triggered interrupt. A software delay

of 5.9 µs can then be implemented before data is read from the

part.

0

250

500

750 1000 1250 1500 1750 2000

CAPACITANCE – pF

C

EXT

Figure 7. Internal Pulse Width vs. C_EXT

REV. A

–12–

AD7890

T he duration of the internal pulse can be seen on the C_EXTpin.

T he C_EXTpin goes from a low to a high when a serial write to

the part is initiated (on the falling edge of TFS). It starts to

discharge on the sixth falling edge of SCLK in the serial write

operation. Once the C_EXTpin has discharged to crossing its

nominal trigger point of 2.5 V, the internal pulse is timed out.

SERIAL INTERFACE

The AD7890’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers and digital signal processors.

A serial read to the AD7890 accesses data from the output reg-

ister via the DAT A OUT line. A serial write to the AD7890

writes data to the Control Register via the DAT A IN line.

T he internal pulse is initiated each time a write operation to the

Control Register takes place. As a result, the pulse is initiated

and the conversion process delayed for all software conversion

start commands. For hardware conversion start, it is possible to

separate the conversion start command from the internal pulse.

T wo different modes of operation are available, optimized for

different types of interface where the AD7890 can act either as

master in the system (it provides the serial clock and data fram-

ing signal) or acts as slave (an external serial clock and framing

signal can be provided to the AD7890). T hese two modes,

labelled Self-Clocking Mode and External Clocking Mode, are

discussed in detail in the following sections.

If the multiplexer output (MUX OUT ) is connected directly to

the track/hold input (SHA IN), then no external settling has to

be taken into account by the internal pulse width. In applica-

tions where the multiplexer is switched and conversion is not

initiated until more than 2 µs after the channel is changed (as is

possible with a hardware conversion start), the user does not

have to worry about connecting any capacitance to the C_EXT

pin. T he 2 µs equates to the track/hold acquisition time of the

AD7890. In applications where the multiplexer is switched and

conversion is initiated at the same time (such as with a software

conversion start), a 120 pF capacitor should be connected to

C_EXTto allow for the acquisition time of the track/hold before

conversion is initiated.

Self-Clocking Mode

T he AD7890 is configured for its Self-Clocking Mode by tying

the SMODE pin of the device to a logic low. In this mode, the

AD7890 provides the serial clock signal and the serial data

framing signal used for the transfer of data from the AD7890.

T his Self-Clocking Mode can be used with processors which

allow an external device to clock their serial port including most

digital signal processors.

Read O per ation

Figure 8 shows a timing diagram for reading from the AD7890

in the Self-Clocking mode. At the end of conversion, RFS goes

low and the serial clock (SCLK) and serial data (DAT A OUT )

outputs become active. Sixteen bits of data are transmitted with

one leading zero, followed by the three address bits of the Con-

trol Register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the ris-

ing edge of SCLK and is valid on the falling edge of SCLK. T he

RFS output remains low for the duration of the sixteen clock

cycles. On the sixteenth rising edge of SCLK, the RFS output is

driven high and DAT A OUT is disabled.

If external circuitry is connected between MUX OUT and SHA

IN, then the extra settling time introduced by this circuitry will

have to be taken into account. In the case where the multiplexer

change command and the conversion start command are sepa-

rated, they need to be separated by greater than the acquisition

time of the AD7890 plus the settling time of the external cir-

cuitry if the user does not have to worry about the C_EXTcapaci-

tance. In applications where the multiplexer is switched and

conversion is initiated at the same time (such as with a software

conversion start), the capacitor on C_EXTneeds to allow for the

acquisition time of the track/hold plus the settling-time of the

external circuitry before conversion is initiated.

RFS (O)

t₆

t₁

t₃

SCLK (O)

t₅

t₄

t₇

t₂

3-STATE

LEADING

DB0

DATA OUT (O)

NOTE

DB10

A2

A1

A0

DB11

ZERO

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

Figure 8. Self-Clocking (Master) Mode Output Register Read

REV. A

–13–

AD7890

TFS (I)

t₁₂

t₈

t₃

SCLK (O)

t₉

t₁₁

t₄

t₁₀

DON'T

CARE

DON'T

CARE

DON'T

CARE

DATA IN (I)

NOTE

A0

A2

A1

STBY

CONV

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

Figure 9. Self-Clocking (Master) Mode Control Register Write

transmitted with one leading zero, followed by the three address

bits in the Control Register, followed by the 12-bit conversion

result starting with the MSB. If RFS goes low during the high

time of SCLK, the leading zero is clocked out from the falling

edge of RFS (as per Figure 10). If RFS goes low during the low

time of SCLK, the leading zero is clocked out on the next rising

edge of SCLK. T his ensures that, regardless of whether RFS

goes low during a high time or low time of SCLK, the leading

zero is valid on the first falling edge of SCLK after RFS goes

low, provided t₁₄and t₁₇are adhered to. Serial data is clocked

out of the device on the rising edge of SCLK and is valid on the

falling edge of SCLK. At the end of the read operation, the

DAT A OUT line is three-stated by a rising edge on either the

SCLK or RFS inputs, whichever occurs first. If a serial read

from the output register is in progress when conversion is com-

plete, the updating of the output register is deferred until the

serial data read is complete and RFS returns high.

Wr ite O per ation

Figure 9 shows a write operation to the Control Register of the

AD7890. T he TFS input is taken low to indicate to the part that

a serial write is about to occur. TFS going low initiates the

SCLK output and this is used to clock data out of the proces-

sors serial port and into the Control Register of the AD7890.

T he AD7890 Control Register requires only five bits of data.

T hese are loaded on the first five clock cycles of the serial clock

with data on all subsequent clock cycles being ignored. How-

ever, the part requires six serial clock cycles to load data to the

Control Register. Serial data to be written to the AD7890 must

be valid on the falling edge of SCLK.

Exter nal-Clocking Mode

T he AD7890 is configured for its external clocking mode by ty-

ing the SMODE pin of the device to a logic high. In this mode,

SCLK and RFS of the AD7890 are configured as inputs. T his

external-clocking mode is designed for direct interface to sys-

tems which provide a serial clock output which is synchronized

to the serial data output including microcontrollers such as the

80C51, 87C51, 68HC11 and 68HC05 and most digital signal

processors.

Wr ite O per ation

Figure 11 shows a write operation to the Control Register of the

AD7890. As with the Self-Clocking mode, the TFS input goes

low to indicate to the part that a serial write is about to occur.

As before, the AD7890 Control Register requires only five bits

of data. T hese are loaded on the first five clock cycles of the se-

rial clock with data on all subsequent clock cycles being ignored.

However, the part requires six serial clocks to load data to the

Control Register. Serial data to be written to the AD7890 must

be valid on the falling edge of SCLK.

Read O per ation

Figure 10 shows the timing diagram for reading from the

AD7890 in the external-clocking mode. RFS goes low to access

data from the AD7890. T he serial clock input does not have to

be continuous. T he serial data can be accessed in a number of

bytes. However, RFS must remain low for the duration of the

data transfer operation. Once again, sixteen bits of data are

RFS (I)

t₁₈

t₁₃

t₁₅

SCLK (I)

t₁₉

t₁₆

t₁₇

t₁₄

t_19A

LEADING

ZERO

3-STATE

DATA OUT (O)

NOTE

DB10

A2

A1

A0

DB11

DB0

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT

Figure 10. External Clocking (Slave) Mode Output Register Read

REV. A

–14–

AD7890

TFS (I)

t₂₀

t₂₃

SCLK (I)

t₂₂

t₂₁

DON'T

CARE

DON'T

CARE

DON'T

CARE

DATA IN (I)

NOTE

A0

CONV

STBY

A2

A1

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.

Figure 11. External Clocking (Slave) Mode Control Register Write

AD 7890–8051 Inter face

SIMP LIFYING TH E INTERFACE

Figure 12 shows an interface between the AD7890 and the

8XC51 microcontroller. T he AD7890 is configured for its ex-

ternal clocking mode while the 8XC51 is configured for its

Mode 0 serial interface mode. T he diagram shown in Figure 12

makes no provisions for monitoring when conversion is complete

on the AD7890 (assuming hardware conversion start is used).

T o monitor the conversion time on the AD7890 a scheme such

as outlined previously with CONVST can be used. T his can be

implemented in two ways. One is to connect the CONVST line

to another parallel port bit which is configured as an input. T his

port bit can then be polled to determine when conversion is

complete. An alternative is to use an interrupt driven system in

which case the CONVST line should be connected to the INT1

input of the 8XC51.

T o minimize the number of interconnect lines to the AD7890,

the user can connect the RFS and TFS lines of the AD7890

together and read and write from the part simultaneously. In

this case, new control register data should be provided on the

DAT A IN line selecting the input channel and possibly provid-

ing a conversion start command while the part provides the

result from the conversion just completed on the DAT A OUT

line.

In the self-clocking mode, this means that the part provides all

the signals for the serial interface. It does require that the

microprocessor has the data to be written to the Control

Register available in its output register when the part brings the

TFS line low. In the external clocking mode, it means that the

user only has to supply a single frame synchronization signal to

control both the read and write operations.

Since the 8XC51 contains only one serial data line, the DAT A

OUT and DAT A IN lines of the AD7890 must be connected to-

gether. T his means that the 8XC51 cannot communicate with

the output register and Control Register of the AD7890 at the

same time. T he 8XC51 outputs the LSB first in a write opera-

tion so care should be taken in arranging the data which is to be

transmitted to the AD7890. Similarly, the AD7890 outputs the

MSB first during a read operation while the 8XC51 expects the

LSB first. T herefore, the data that is to be read into the serial

port needs to be rearranged before the correct data word from

the AD7890 is available in the microcontroller.

Care must be taken with this scheme that the read operation is

completed before the next conversion starts if the user wants to

obtain optimum performance from the part. In the case of the

software conversion start, the conversion command is written to

the Control Register on the sixth serial clock edge. However, the

read operation continues for another 10 serial clock cycles. T o

avoid reading during the sampling instant or during conversion,

the user should ensure that the internal pulse width is suffi-

ciently long (by choosing C_EXT) so that the read operation is

completed before the next conversion sequence begins. Failure

to do this will result in significantly degraded performance from

the part, both in terms of signal-to-noise ratio and dc param-

eters. In the case of a hardware conversion start, the user should

ensure that the delay between the sixth falling edge of the serial

clock in the write operation and the next rising edge of

T he serial clock rate from the 8XC51 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7890 can operate. As a result, the time to read data from

the part will actually be longer than the conversion time of the

part. T his means that the AD7890 cannot run at its maximum

throughput rate when used with the 8XC51.

CONVST is greater than the internal pulse width.

V

DD

MICRO P RO CESSO R/MICRO CO NTRO LLER INTERFACE

T he AD7890’s flexible serial interface allows for easy connec-

tion to the serial ports of DSP processors and microcontrollers.

Figures 12 through 15 show the AD7890 interfaced to a num-

ber of different microcontrollers and DSP processors. In some

of the interfaces shown, the AD7890 is configured as the master

in the system, providing the serial clock and frame sync for the

read operation while in others it acts as a slave with these signals

provided by the microprocessor.

SMODE

P1.0

P1.1

RFS

TFS

AD7890

8XC51

DATA OUT

DATA IN

P3.0

P3.1

SCLK

Figure 12. AD7890 to 8XC51 Interface

REV. A

–15–

AD7890

AD 7890–68H C11 Inter face

In the scheme shown, the maximum serial clock frequency

which the ADSP-2101 can provide is 6.25 MHz. T his allows

the AD7890 to be operated at a sample rate of 111 kHz. If it is

desirable to operate the AD7890 at its maximum throughput

rate of 117 kHz, an external serial clock of 10 MHz can be pro-

vided to drive the serial clock input of both the AD7890 and the

ADSP-2101.

An interface circuit between the AD7890 and the 68HC11

microcontroller is shown in Figure 13. For the interface shown,

the AD7890 is configured for its external clocking mode while

the 68HC11’s SPI port is used and the 68HC11 is configured in

its single-chip mode. T he 68HC11 is configured in the master

mode with its CPOL bit set to a logic zero and its CPHA bit set

to a logic one.

T o monitor the conversion time on the AD7890 a scheme, such

as outlined in previous interfaces with CONVST, can be used.

T his can be implemented by connecting the CONVST line

directly to the IRQ2 input of the ADSP-2101. An alternative to

this, where the user does not have to worry about monitoring

the conversion status, is to operate the AD7890 in its Self-

Clocking Mode. In this scheme, the actual interface connections

would remain the same as in Figure 14 but now the AD7890

provides the serial clock and receive frame synchronization sig-

nals. Using the AD7890 in its Self-Clocking Mode, limits the

throughput rate of the system as the serial clock rate is limited

to 2.5 MHz.

As with the previous interface, there are no provisions for moni-

toring when conversion is complete on the AD7890. T o monitor

the conversion time on the AD7890 a scheme, such as outlined

in the previous interface with CONVST, can be used. T his can

be implemented in two ways. One is to connect the CONVST

line to another parallel port bit which is configured as an input.

T his port bit can then be polled to determine when conversion

is complete. An alternative is to use an interrupt driven system

in which case the CONVST line should be connected to the

IRQ input of the 68HC11.

DV

DD

AD 7890–D SP 56000 Inter face

SS

SMODE

Figure 15 shows an interface circuit between the AD7890 and

the DSP56000 DSP processor. T he AD7890 is configured for

its external clocking mode. T he DSP56000 is configured for

normal mode, synchronous operation with continuous clock. It

is also set up for a 16-bit word with SCK and SC2 as outputs.

T he FSL bit of the DSP56000 should be set to 0.

PC0

PC1

RFS

TFS

AD7890

68HC11

SCK

SCLK

MISO

MOSI

DATA OUT

DATA IN

T he RFS and TFS inputs of the AD7890 are connected

together so data is transmitted to and from the AD7890 at the

same time. With the DSP56000 in synchronous mode, it pro-

vides a common frame synchronization pulse for read and write

operations on its SC2 output. T his is inverted before being

applied to the RFS and TFS inputs of the AD7890.

Figure 13. AD7890 to 68HC11 Interface

T he serial clock rate from the 68HC11 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7890 can operate. As a result, the time to read data from

the part will actually be longer than the conversion time of the

part. T his means that the AD7890 cannot run at its maximum

throughput rate when used with the 68HC11.

T o monitor the conversion time on the AD7890 a scheme, such

as outlined in previous interface examples with CONVST, can

be used. T his can be implemented by connecting the CONVST

line directly to the IRQA input of the DSP56000.

DV

DD

AD 7890–AD SP -2101 Inter face

SMODE

An interface circuit between the AD7890 and the ADSP-2101

DSP processor is shown in Figure 14. T he AD7890 is config-

ured for its external clocking mode with the ADSP-2101 provid-

ing the serial clock and frame synchronization signals. T he

RFS1 and T FS1 inputs are outputs are configured for active low

operation.

SC2

RFS

TFS

DSP56000

AD7890

SCK

SRD

STD

SCLK

DATA OUT

DATA IN

DV

DD

SMODE

RFS1

TFS1

RFS

TFS

Figure 15. AD7890 to DSP56000 Interface

AD 7890–TMS320C25/30 Inter face

AD7890

ADSP-2101

SCLK1

SCLK

Figure 16 shows an interface circuit between the AD7890 and

the T MS320C25/30 DSP processor. T he AD7890 is configured

for its Self-Clocking Mode where it provides the serial clock and

frame synchronization signals. However, the T MS320C25/30

requires a continuous serial clock. In the scheme outlined here,

the AD7890’s master clock signal, CLK IN, is used to provide

the serial clock for the processor. T he AD7890’s output SCLK,

DR1

DATA OUT

DATA IN

DT1

Figure 14. AD7890 to ADSP-2101 Interface

REV. A

–16–

AD7890

to which the serial data is referenced, is a delayed version of the

CLK IN signal. T he typical delay between the CLK IN and

SCLK is 20 ns and will be no more than 50 ns over supplies and

temperature. T herefore, there will still be sufficient setup time

for DAT A OUT to be clocked into the DSP on the edges of the

CLK IN signal. When writing data to the AD7890, the processor’s

data hold time is sufficiently long to cater for the delay between

the two clocks. T he AD7890’s RFS signal connects to both the

FSX and FSR inputs of the processor. T he processor can gener-

ate its own FSX signal so if required the interface can be modi-

fied so that the RFS and TFS signals are separated and the

processor generates the FSX signal which is connected to the

TFS input of the AD7890.

driven from a low impedance stage. T his will remove any effects

from the variation of the part’s multiplexer on-resistance with

input signal voltage and will also remove any effects of a high

source impedance at the sampling input of the track/hold. With

an external antialiasing filter in place, the additional settling-

time associated with the filter should be accounted for by using

a larger capacitance on C_EXT

.

AD 7890 P ERFO RMANCE

Linear ity

T he linearity of the AD7890 is primarily determined by the

on-chip 12-bit D/A converter. T his is a segmented DAC which

is laser trimmed for 12-bit integral linearity and differential lin-

earity. T ypical relative numbers for the part are ±1/4 LSB while

the typical DNL errors are ±1/2 LSB.

In the scheme outlined here, the user does not have to worry

about monitoring the end of conversion. Once conversion is

complete, the AD7890 takes care of transmitting back its con-

version result to the processor. Once the sixteen bits of data

have been received by the processor into its serial shift register,

it generates an internal interrupt. Since RFS and TFS are con-

nected together, data is transmitted to the Control Register of

the AD7890 whenever the AD7890 transmits its conversion

result. T he user just has to ensure that the word to be written to

the AD7890 Control Register is set up prior to the end of con-

version. As part of the interrupt routine which recognizes that

data has been read in, the processor can set up the data which it

is going to write to the Control Register next time around.

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT , for example)

in ac applications. In a sampling A/D converter like the

AD7890, all information about the analog input appears in the

baseband from dc to 1/2 the sampling frequency. T he input

bandwidth of the track/hold exceeds the Nyquist bandwidth

and, therefore, an antialiasing filter should be used to remove

unwanted signals above f_S/2 in the input signal in applications

where such signals exist.

Figure 17 shows a histogram plot for 8192 conversions of a dc

input using the AD7890. T he analog input was set at the centre

of a code transition. T he timing and control sequence used was

as per Figure 5 where the optimum performance of the ADC

was achieved. T he same performance will be achieved in self-

clocking mode where the part transmits its data after conversion

is complete. It can be seen that almost all the codes appear in

the one output bin indicating very good noise performance from

the ADC. T he rms noise performance for the AD7890-2 for the

above plot was 81 µV. Since the analog input range, and hence

LSB size, on the AD7893-4 is 1.638 times what it is for the

AD7893-2, the same output code distribution results in an out-

put rms noise of 143 µV for the AD7893-4. For the AD7890-10,

with an LSB size eight times that of the AD7890-2, the code distri-

bution represents an output rms noise of 648 µV.

CLK INPUT

CLK IN

SMODE

TMS320C25/C30

FSR

FSX

RFS

TFS

AD7890

CLKX

CLKR

DR

SCLK

DATA OUT

DATA IN

DX

9000

SAMPLING FREQUENCY = 102.4kHz

A

Figure 16. AD7890 to TMS320C25/30 Interface

ANTIALIASING FILTER

T

= +25°C

8000

7000

6000

5000

4000

3000

2000

1000

0

T he AD7890 provides separate access to the multiplexer and

ADC via the MUX OUT and SHA IN pins. One of the reasons

for this is to allow the user to implement an antialiasing filter

between the multiplexer and the ADC. Inserting the antialiasing

filter at this point has the advantage that one antialiasing filter

can suffice for all eight channels rather than a separate antialias-

ing filter for each channel if they were to be placed prior to the

multiplexer.

T he antialiasing filter inserted between the MUX OUT and

SHA IN pins will generally be a low-pass filter to remove high

frequency signals which could possibly be aliased back in-band

during the sampling process. It is recommended that this filter is

an active filter, ideally with the MUX OUT of the AD7890 driv-

ing a high impedance stage and the SHA IN of the part being

(X–4) (X–3) (X–2) (X–1)

X

(X+1) (X+2) (X+3) (X+4)

CODE

Figure 17. Histogram of 8192 Conversions of a DC Input

REV. A

–17–

AD7890

8000

7000

6000

5000

4000

In the external clocking mode, it is possible to write data to the

Control Register or read data from the output register while a

conversion is in progress. T he same data is presented in Figure

18 as in Figure 17 except that in this case the output data read

for the device occurs during conversion. T hese results are

achieved with a serial clock rate of 2.5 MHz. If a higher serial

clock rate is used, the code transition noise will degrade from

that shown in the plot of Figure 18. T his has the effect of inject-

ing noise onto the die while bit decisions are being made and

this increases the noise generated by the AD7890. T he histo-

gram plot for 8192 conversions of the same dc input now shows

a larger spread of codes with the rms noise for the AD7890-2

increasing to 170 µV. T his effect will vary depending on where

the serial clock edges appear with respect to the bit trials of the

conversion process. It is possible to achieve the same level of

performance when reading during conversion as when reading

after conversion depending on the relationship of the serial clock

edges to the bit trial points (i.e., the relationship of the serial

clock edges to the CLK IN edges). T he bit decision points

on the AD7890 are on the falling edges of the master clock

(CLK IN) during the conversion process. Clocking out new

data bits at these points (i.e. the rising edge of SCLK) is the

most critical from a noise standpoint. T he most critical bit deci-

sions are the MSBs, so to achieve the level of performance out-

lined in Figure 18, reading within 1 µs after the rising edge of

CONVST should be avoided.

SAMPLING FREQUENCY =

102.4kHz

T

= +25°C

A

3000

2000

1000

0

(X–4) (X–3) (X–2) (X–1)

X

(X+1) (X+2) (X+3) (X+4)

CODE

Figure 19. Histogram of 8192 Conversions with Write

During Conversion

D ynam ic P er for m ance

T he AD7890 contains an on-chip track/hold, allowing the part

to sample input signals up to 50 kHz on any of its input chan-

nels. Many of the AD7890’s applications will simply require it

to sequence through low frequency input signals across its eight

channels. T here may be some applications, however, for which

the dynamic performance of the converter out to 40 kHz input

frequency is of interest. It is recommended for these wider band

sampling applications that the hardware conversion start method

is used for reasons outlined previously.

8000

SAMPLING FREQUENCY =

102.4kHz

= +25°C

7000

T

A

T hese applications require information on the ADC’s effect on

the spectral content of the input signal. Signal to (Noise +

Distortion), total harmonic distortion, peak harmonic or spuri-

ous and intermodulation distortion are all specified. Figure 20

shows a typical FFT plot of a 10 kHz, 0 V to +2.5 V input after

being digitized by the AD7890-2 operating at a 102.4 kHz sam-

pling rate. T he signal to (Noise + Distortion) is 71.5 dB and the

total harmonic distortion is –85 dB. It should be noted that

reading data from the part during conversion at 10 MHz serial

clock does have a significant impact on dynamic performance.

T herefore, for sampling applications, it is recommended not to

read data during conversion.

6000

5000

4000

3000

2000

1000

0

(X–4) (X–3) (X–2) (X–1)

X

(X+1) (X+2) (X+3) (X+4)

CODE

F = /2

0

Figure 18. Histogram of 8192 Conversions with Read

During Conversion

SAMPLE RATE = 102.4 kHz

INPUT FREQUENCY = 10 kHz

SNR = 71.5 dB

–30

Writing data to the Control Register also has the effect of intro-

ducing digital activity onto the part while conversion is in

progress. However, since there are no output drivers active dur-

ing a write operation, the amount of current flowing on the die

is less than for a read operation. T herefore, the amount of noise

injected into the die is less than for a read operation. Figure 19

shows the effect of a write operation during conversion. T he his-

togram plot for 8192 conversions of the same dc input now

shows a larger spread of codes than for ideal conditions but

smaller than for a read operation. T he resulting rms noise for

the AD7890-2 is 110 µV. In this case, the serial clock frequency

was 10 MHz.

T

= +25°C

A

–60

–90

–120

0

25.6

51.2

FREQUENCY – kHz

SNR IS SIGNAL TO (NOISE + DISTORTION) RATIO.

Figure 20. AD7890 FFT Plot

REV. A

–18–

AD7890

12

Effective Num ber of Bits

T he formula for Signal to (Noise + Distortion) Ratio (See T er-

minology section) is related to the resolution or number of bits

in the converter. Rewriting the formula, below, gives a measure

of performance expressed in effective number of bits (N):

11.5

N = (SNR — 1.76)/6.02

11

10.5

10

where SNR is Signal to (Noise + Distortion) Ratio

The effective num ber of bits for a device can be calculated

fr om its m easur ed Signal to (Noise + D istor tion) Ratio. Fig-

ur e 21 shows a typical plot of effective num ber of bits ver sus

fr equency for the AD 7890-2 fr om dc to 40 kH z. The sam pling

fr equency is 102.4 kH z. The plot shows that the AD 7890 con-

ver ts an input sine wave of 40 kH z to an effective num ber s of

bits of 11 which equates to a Signal to (Noise + D istor tion)

level of 68 dB.

0

20

40

INPUT FREQUENCY – kHz

Figure 21. Effective Num ber of Bits vs. Frequency

REV. A

–19–

AD7890

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

P lastic D IP (N-24)

13

24

0.260 ± 0.001

(6.61 ± 0.03)

PIN 1

12

1

0.32 (8.128)

0.30 (7.62)

1.228 (31.19)

1.226 (31.14)

0.130 (3.30)

0.128 (3.25)

SEATING

PLANE

15

0

°

0.011 (0.28)

0.009 (0.23)

0.02 (0.5)

0.016 (0.41)

0.11 (2.79)

0.09 (2.28)

0.07 (1.78)

0.05 (1.27)

NOTES

1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

Cer dip (Q -24)

24

13

0.295 (7.493)

MAX

PIN 1

1

12

0.320 (8.128)

0.290 (7.366)

1.290 (32.77) MAX

0.180

(4.572)

MAX

0.225

(5.715)

MAX

0.012 (0.305)

0.008 (0.203)

TYP

0.125

(3.175)

MIN

0.070 (1.778)

0.020 (0.508)

15

°

0

°

0.065 (1.651)

0.055 (1.397)

TYP

0.021 (0.533)

0.015 (0.381)

TYP

0.110 (2.794)

0.090 (2.286)

TYP

SEATING

PLANE

1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

2. CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

SO IC (R-24)

0.419 (10.65)

0.394 (10.00)

15.6 (0.614)

15.2 (0.598)

13

12

24

0.299 (7.6)

0.291 (7.4)

1

0.03 (0.75)

0.01 (0.25)

0.019 (0.49)

0.014 (0.35)

0.050 (1.27)

0.104 (2.65)

0.093 (2.35)

0.013 (0.32)

0.009 (0.23)

0° - 8°

0.012 (0.3)

0.004 (0.1)

0.005 (1.27)

0.016 (0.40)

REV. A

–20–


型号：	AD7890AR-4
厂家：	ADI
描述：	LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition System LC2MOS 8通道， 12位串行数据采集系统转换器模数转换器光电二极管
文件：	总20页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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