AD7891_技术文档

LC²MOS 8-Channel, 12-Bit

a

High Speed Data Acquisition System

AD7891

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Fast 12-Bit ADC with 1.6 ␮s Conversion Time

Eight Single-Ended Analog Input Channels

Overvoltage Protection on Each Channel

Selection of Input Ranges:

؎5 V, ؎10 V for AD7891-1

0 to +2.5 V, 0 to +5 V, ؎2.5 V for AD7891-2

Parallel and Serial Interface

REF OUT/

REF IN

V

DD

REF GND

DD

V

IN1A

+2.5V

REFERENCE

V

IN1B

V

STANDBY

IN2A

AD7891

V

IN2B

V

IN3A

V

IN3B

On-Chip Track/Hold Amplifier

On-Chip Reference

Single Supply, Low Power Operation (85 mW max)

Power-Down Mode (75 ␮W typ)

V

12-BIT

ADC

IN4A

M

U

X

V

IN4B

V

IN5A

V

IN5B

TRACK/HOLD

V

IN6A

V

IN6B

DATA/

CONTROL

LINES

APPLICATIONS

Data Acquisition Systems

Motor Control

Mobile Communication Base Stations

Instrumentation

V

ADDRESS

DECODE

IN7A

V

IN7B

V

IN8A

V

IN8B

CLOCK

CONTROL LOGIC

WR CS RD EOC CONVST MODE

AGND AGND DGND

PRODUCT HIGHLIGHTS

GENERAL DESCRIPTION

1. The AD7891 is a complete monolithic 12-bit data acquisition

system combining an eight-channel multiplexer, 12-bit ADC,

+2.5 V reference and track/hold amplifier on a single chip.

The AD7891 is an eight-channel 12-bit data acquisition system

with a choice of either parallel or serial interface structure. The

part contains an input multiplexer, an on-chip track/hold ampli-

fier, a high speed 12-bit ADC, a +2.5 V reference and a high

speed interface. The part operates from a single +5 V supply

and accepts a variety of analog input ranges across two models,

the AD7891-1 (±5 V and ±10 V) and the AD7891-2 (0 V to

+2.5 V, 0 V to +5 V and ±2.5 V).

2. The AD7891-2 features a conversion time of 1.6 µs and an

acquisition time of 0.4 µs. This allows a sample rate of

500 kSPS when sampling one channel and 62.5 kSPS when

channel hopping. These sample rates can be achieved using

either a software or hardware convert start. The AD7891-1

has an acquisition time of 0.6 µs when using a hardware

convert start and an acquisition time of 0.7 µs when using a

software convert start. These acquisition times allow sample

rates of 454.5 kSPS and 435 kSPS respectively for hardware

and software convert start.

The AD7891 provides the option of either a parallel interface or

serial interface structure determined by the MODE pin. The

part has standard control inputs and fast data access times for

both the serial and parallel interfaces which ensures easy inter-

facing to modern microprocessors, microcontrollers and digital

signal processors.

3. Each channel on the AD7891 has overvoltage protection.

This means that an overvoltage on an unselected channel

does not affect the conversion on a selected channel. The

AD7891-1 can withstand overvoltages of ±17 V.

In addition to the traditional dc accuracy specifications such as

linearity, full-scale and offset errors, the part is also specified for

dynamic performance parameters including harmonic distortion

and signal-to-noise ratio.

Power dissipation in normal mode is 90 mW typical while in

the standby mode this is reduced to 75 µW typ. The part is

available in a 44-terminal plastic quad flatpack (PQFP) and a

44-lead plastic leaded chip carrier (PLCC).

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_DD= +5 V ؎ 5%, AGND = DGND = 0 V, REF IN = +2.5 V. All Specifications T_MINto

T

_MAXunless otherwise noted.)

AD7891–SPECIFICATIONS

A

B

Y

Parameter

Version¹

Version

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE²

Sample Rate = 454.5 kSPS³(AD7891-1),

500 kSPS³(AD7891-2). Any Channel

Signal to (Noise + Distortion) Ratio⁴

@ +25°C

70

–78

–80

70

–78

–80

70

–78

–80

dB min

dB max

T_MINto T_MAX

Total Harmonic Distortion⁴

Peak Harmonic or Spurious Noise⁴

Intermodulation Distortion⁴

2nd Order Terms

fa = 9 kHz, fb = 9.5 kHz

Any Channel

–80

dB typ

dB max

3rd Order Terms

Channel-to-Channel Isolation⁴

DC ACCURACY

Resolution

12

Bits

Minimum Resolution for Which

No Missing Codes are Guaranteed 12

12

±0.75

±1

±3

0.6

±3

0.1

±3

0.6

±4

12

Bits

Relative Accuracy⁴

±1

±3

0.6

±3

0.1

±3

0.6

±4

0.2

±1

±3

0.6

±3

0.1

±3

0.6

±4

0.2

LSB max

LSB typ

LSB max

LSB typ

LSB max

LSB typ

LSB max

LSB typ

Differential Nonlinearity⁴

Positive Full-Scale Error⁴

Positive Full-Scale Error Match^{4, 5}

Unipolar Offset Error

1.5 LSB max

Input Ranges of 0 V to +2.5 V, 0 V to +5 V

1 LSB max

Input Ranges of ±2.5 V, ±5 V, ±10 V

1.5 LSB max

Input Ranges of ±2.5 V, ±5 V, ±10 V

1.5 LSB max

Unipolar Offset Error Match⁵

Negative Full-Scale Error⁴

Negative Full-Scale Error Match^{4, 5}

Bipolar Zero Error

Bipolar Zero Error Match⁵

0.2

ANALOG INPUTS

AD7891-1 Input Voltage Range

±5

Volts

kΩ min

Input Applied to Both V_INXAand V_INXB

Input Applied to V_INXA, V_INXB= AGND

Input Range of ±5 V

±10

7.5

15

±10

7.5

15

±10

7.5

15

AD7891-1 V_INXAInput Resistance

AD7891-2 Input Voltage Range

Input Range of ±10 V

0 to +2.5

0 to +5

±2.5

1.5

±50

0 to +2.5

0 to +5

±2.5

1.5

±50

0 to +2.5

0 to +5

±2.5

1.5

±50

Volts

kΩ min

nA max

Input Applied to Both V_INXAand V_INXB

Input Applied to V_INXA, V_INXB= AGND

Input Applied to V_INXA, V_INXB= REF IN⁶

Input Ranges of ±2.5 V and 0 to +5 V

Input Range of 0 V to +2.5 V

AD7891-2 V_INXAInput Resistance

AD7891-2 V_INXAInput Current

REFERENCE INPUT/OUTPUT

REF IN Input Voltage Range

Input Impedance

2.375/2.625 2.375/2.625 2.375/2.625 V min/V max

2.5 V ± 5%

1.6

10

2.5

±10

±20

25

1.6

10

2.5

±10

±20

25

1.6

10

2.5

±10

±20

25

kΩ min

pF max

V nom

mV max

ppm/°C typ

kΩ nom

Resistor Connected to Internal Reference Node

Input Capacitance⁵

REF OUT Output Voltage

REF OUT Error @ +25°C

T_MINto T_MAX

REF OUT Temperature Coefficient

REF OUT Output Impedance

5

See REF IN Input Impedance

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH

2.4

0.8

±10

10

2.4

0.8

±10

10

2.4

0.8

±10

10

V min

V_DD= 5 V ± 5%

V max

µA max

pF max

Input Capacitance,⁵C_IN

–2–

REV. A

AD7891

A

B

Y

Parameter

Version¹

Version

Units

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

DB11–DB0

4.0

0.4

4.0

0.4

4.0

0.4

V min

V max

I_SOURCE= 200 µA

I_SINK= 1.6 mA

Floating-State Leakage Current

Floating-State Capacitance⁵

Output Coding

±10

15

±10

15

±10

15

µA max

pF max

Straight (Natural) Binary

2s Complement

Data Format Bit of Control Register = 0

Data Format Bit of Control Register = 1

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time

1.6

0.6

0.7

0.4

1.6

0.6

0.7

0.4

µs max

0.6

0.7

0.4

AD7891-1 Hardware Conversion

AD7891-1 Software Conversion

AD7891-2

POWER REQUIREMENTS

V_DD

+5

V nom

±5% for Specified Performance

I_DD

Normal Mode

Standby Mode

Power Dissipation

Normal Mode

Standby Mode

17

80

17

80

18

80

mA max

µA max

Logic Inputs = 0 V or V_DD

V_DD= 5 V

Typically 70 mW

Typically 75 µW

85

400

85

400

90

400

mW max

µW max

NOTES

¹Temperature Ranges for the A and B Versions: –40°C to +85°C. Temperature Range for the Y Version: –55°C to +105°C.

²The AD7891-1’s dynamic performance (THD and SNR) and the AD7891-2’s THD are measured with an input frequency of 10 kHz. The AD7891-2’s SNR is

evaluated with an input frequency of 100 kHz.

³This throughput rate can only be achieved when the part is operated in the parallel interface mode. Maximum achievable throughput rate in the serial interface mode

is 357 kSPS.

⁴See Terminology.

⁵Sample tested during initial release and after any redesign or process change that may affect this parameter.

⁶REF IN must be buffered before being applied to V_INXB

Specifications subject to change without notice.

.

ABSOLUTE MAXIMUM RATINGS*

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

(T_A= +25°C unless otherwise noted)

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND

AD7891-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V

AD7891-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to AGND . . . . –0.3 V to V_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Output Voltage to DGND . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C

Automotive (Y Version) . . . . . . . . . . . . . . –55°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7891 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

AD7891

TIMING CHARACTERISTICS^{1, 2}

Parameter

A, B, Y Versions

Units

Test Conditions/Comments

t_CONV

1.6

µs max

Conversion Time

Parallel Interface

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈₃

t₉

0

ns min

ns max

CS to RD/WR Setup Time

Write Pulsewidth

Data Valid to Write Setup Time

Data Valid to Write Hold Time

CS to RD/WR Hold Time

CONVST Pulsewidth

EOC Pulsewidth

Read Pulsewidth

Data Access Time after Falling Edge of RD

Bus Relinquish Time after Rising Edge of RD

35

25

5

0

35

55

35

25

5

4

t₁₀

30

Serial Interface

t₁₁

t₁₂

30

20

25

5

15

20

0

30

0

30

20

15

10

30

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

ns min

RFS Low to SCLK Falling Edge Setup Time

RFS Low to Data Valid Delay

SCLK High Pulsewidth

3

t₁₃

t₁₄

SCLK Low Pulsewidth

3

t₁₅

SCLK Rising Edge to Data Valid Hold Time

SCLK Rising Edge to Data Valid Delay

RFS to SCLK Falling Edge Hold Time

Bus Relinquish Time after Rising Edge of RFS

3

t₁₆

t₁₇

t₁₈

4

t_18A

Bus Relinquish Time after Rising Edge of SCLK

t₁₉

t₂₀

t₂₁

t₂₂

TFS Low to SCLK Falling Edge Setup Time

Data Valid to SCLK Falling Edge Setup Time

Data Valid to SCLK Falling Edge Hold Time

TFS Low to SCLK Falling Edge Hold Time

NOTES

¹Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to

90% of +5 V) and timed from a voltage level of +1.6 V.

²See Figures 2, 3 and 4.

³Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

⁴These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

1.6mA

TO

OUTPUT

+1.6V

50pF

200␮A

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

–4–

REV. A

AD7891

ORDERING GUIDE

Model

Input Ranges

Sample Rate Relative Accuracy Temperature Range

Package Options*

AD7891AS-1 ±5 V or ±10 V

AD7891AP-1 ±5 V or ±10 V

AD7891BS-1 ±5 V or ±10 V

AD7891BP-1 ±5 V or ±10 V

AD7891YS-1 ±5 V or ±10 V

AD7891YP-1 ±5 V or ±10 V

AD7891AS-2 0 V to +5 V, 0 V to +2.5 V

or ±2.5 V

AD7891AP-2 0 V to +5 V, 0 V to +2.5 V

or ±2.5 V

AD7891BS-2 0 V to +5 V, 0 V to +2.5 V

or ±2.5 V

454 kSPS

500 kSPS

±1 LSB

±0.75 LSB

±1 LSB

–40°C to +85°C

–55°C to +105°C

–40°C to +85°C

S-44

P-44A

S-44

P-44A

S-44

P-44A

S-44

500 kSPS

±1 LSB

–40°C to +85°C

–55°C to +105°C

P-44A

S-44

±0.75 LSB

±1 LSB

AD7891BP-2 0 V to +5 V, 0 V to +2.5 V

or ±2.5 V

AD7891YS-2 0 V to +5 V, 0 V to +2.5 V

or ±2.5 V

P-44A

S-44

*S = Plastic Quad Flatpack (PQFP); P = Plastic Leaded Chip Carrier (PLCC).

PIN CONFIGURATIONS

PLCC

PQFP

44 43 42 41 40 39 38 37 36 35 34

6

5

4

3

2

1

44 43 42 41 40

PIN 1

1

2

33

32

31

30

29

28

27

26

25

24

23

REF GND

7

8

39

38

37

36

35

34

V

REF GND

NC

V

IDENTIFIER

IN6A

IN6B

IN7A

IN7B

IN8A

IN8B

IN6A

IN6B

IN7A

IN7B

IN8A

IN8B

PIN 1

NC

V

IDENTIFIER

3

9

REF OUT/REF IN

V

4

10

V

DD

5

AGND

MODE

AGND 11

AD7891 PLCC

TOP VIEW

(Not to Scale)

AD7891 PQFP

6

12

13

MODE

TOP VIEW

7

33 AGND

DB11/TEST

DB10/TEST

DB9/TFS

(Not to Scale)

AGND

DB11/TEST

8

DB10/TEST 14

32

31

30

29

EOC

9

15

16

17

NC

DB9/TFS

DB8/RFS

DB7/DATA IN

10

11

DB8/RFS

CONVST

CS

CONVST

CS

DB7/DATA IN

12 13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

NC = NO CONNECT

REV. A

–5–

AD7891

Channel-to-Channel Isolation

TERMINOLOGY

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 20 kHz (AD7891-1) or 100 kHz (AD7891-2) sine wave

signal to one input channel and determining how much that

signal is attenuated in each of the other channels. The figure

given is the worst case across all eight channels.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. The theoretical signal to (noise +distortion) ratio

for an ideal N-bit converter with a sine wave input is given by:

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Differential Nonlinearity

Thus for a 12-bit converter, this is 74 dB.

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7891 it is defined as:

Positive Full-Scale Error (AD7891-1, ±10 V and ± 5 V,

AD7891-2, ±2.5 V)

V₂²+V₃²+V₄²+V₅²+V₆²

THD dB = 20log

This is the deviation of the last code transition (01. . .110 to

01. . .111) from the ideal 4 × REF IN – 3/2 LSB (AD7891-1

±10 V range), 2 × REF IN – 3/2 LSB (AD7891-1 ± 5 V range)

or REF IN – 3/2 LSB (AD7891-2, ±2.5 V range), after the

Bipolar Zero Error has been adjusted out.

(

)

V₁

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to

2.5 V)

This is the deviation of the last code transition (11. . .110 to

11. . .111) from the ideal 2 × REF IN – 3/2 LSB (0 V to 5 V

range) or REF IN – 3/2 LSB (0 V to 2.5 V range), after the

unipolar offset error has been adjusted out.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Bipolar Zero Error (AD7891-1, ±10 V and ± 5 V, AD7891-2 ,

±2.5 V)

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal AGND – 1/2 LSB.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which

neither m nor n are equal to zero. For example, the second

order terms include (fa + fb) and (fa – fb), while the third order

terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the first code transition (00. . .000 to

00. . .001) from the ideal AGND + 1/2 LSB.

Negative Full-Scale Error (AD7891-1, ± 10 V and ±5 V,

AD7891-2, ±2.5 V)

This is the deviation of the first code transition (10. . .000 to

10. . .001) from the ideal –4 × REF IN + 1/2 LSB (AD7891-1

±10 V range), –2 × REF IN + 1/2 LSB (AD7891-1 ± 5 V range)

or –REF IN + 1/2 LSB (AD7891-2, ±2.5 V range), after Bipolar

Zero Error has been adjusted out.

The AD7891 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second and third order terms are of differ-

ent significance. The second order terms are usually distanced

in frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. The calculation of the intermodulation distortion is as

per the THD specification where it is the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

fundamental expressed in dBs.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output

of the track/hold amplifier to reach its final value, within

±1/2 LSB, after the end of conversion (the point at which the

track/hold returns to track mode). It also applies to situations

where a change in the selected input channel takes place or

where there is a step input change on the input voltage applied

to the selected V_INinput of the AD7891. It means that the user

must wait for the duration of the track/hold acquisition time

after the end of conversion or after a channel change/step input

change to V_INbefore starting another conversion, to ensure that

the part operates to specification.

–6–

REV. A

AD7891

PIN FUNCTION DESCRIPTIONS

Mnemonic

Description

V_INXA, V_INXB

Analog Input Channels. The AD7891 contains eight pairs of analog input channels. Each channel con-

tains two input pins to allow a number of different input ranges to be used with the AD7891. There are

two possible input voltage ranges on the AD7891-1. The ±5 V input range is selected by connecting the

input voltage to both V_INXAand V_INXB, while the ±10 V input range is selected by applying the input

voltage to V_INXAand connecting V_INXBto AGND. The AD7891-2 has three possible input ranges. The

0 V to +2.5 V input range is selected by connecting the analog input voltage to both V_INXAand V_INXB; the

0 V to +5 V input range is selected by applying the input voltage to V_INXAand connecting V_INXBto AGND

while the ±2.5 V input range is selected by connecting the analog input voltage to V_INXAand connecting

V_INXBto REF IN (provided this REF IN voltage comes from a low impedance source). The channel to be

converted is selected by the A2, A1 and A0 bits of the control register. In the parallel interface mode,

these bits are available as three data input lines (DB3 to DB5) in a parallel write operation while in the

serial interface mode, these three bits are accessed via the DATA IN line in a serial write operation. The

multiplexer has guaranteed break-before-make operation.

V_DD

Positive supply voltage, +5 V ± 5%.

AGND

DGND

STANDBY

Analog Ground. Ground reference for track/hold, comparator and DAC.

Digital Ground. Ground reference for digital circuitry.

Standby Mode Input. TTL-compatible input which is used to put the device into the power save or

standby mode. The STANDBY input is high for normal operation and low for standby operation.

REF OUT/REF IN

Voltage Reference Output/Input. The part can either be used with its own internal reference or with an

external reference source. The on-chip +2.5 V reference voltage is provided at this pin. When using this

internal reference as the reference source for the part, REF OUT should be decoupled to REF GND with

a 0.1 µF disc ceramic capacitor. The output impedance of the reference source is typically 2 kΩ. When

using an external reference source as the reference voltage for the part, the reference source should be

connected to this pin. This overdrives the internal reference and provides the reference source for the

part. The reference pin is buffered on-chip but must be able to sink or source current through this 2 kΩ

resistor to the output of the on-chip reference. The nominal reference voltage for correct operation of the

AD7891 is +2.5 V.

REF GND

Reference Ground. Ground reference for the part’s on-chip reference buffer. The REF OUT pin of the

part should be decoupled with a 0.1 µF capacitor to this REF GND pin. If the AD7891 is used with an

external reference, the external reference should also be decoupled to this pin. The REF GND pin should

be connected to the AGND pin or the system’s AGND plane.

CONVST

Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold into

hold and initiates conversion. When changing channels on the part, sufficient time should be given for

multiplexer settling and track/hold acquisition between the channel change and the rising edge of CONVST.

EOC

End-of-Conversion. Active low logic output indicating converter status. The end of conversion is signified

by a low-going pulse on this line. The duration of this EOC pulse is nominally 80 ns.

MODE

Interface Mode. Control input which determines the interface mode for the part. With this pin at a logic

low, the AD7891 is in its serial interface mode; with this pin at a logic high, the device is in its parallel

interface mode.

NC

No Connect. The two NC pins on the device can be left unconnected. If they are to be connected to a

voltage it should be to ground potential. To ensure correct operation of the AD7891, neither of the NC

pins should be connected to a logic high potential.

REV. A

–7–

AD7891

PARALLEL INTERFACE MODE FUNCTIONS

Description

Mnemonic

CS

Chip Select Input. Active low logic input which is used in conjunction with RD to enable the data

outputs and with WR to allow input data to be written to the part.

RD

WR

Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs.

Write Input. Active low, logic input used in conjunction with CS to latch the multiplexer address and

software control information. The rising edge of this input also initiates an internal pulse. When using

the software start facility, this pulse delays the point at which the track/hold goes into hold and con-

version is initiated. This allows the multiplexer to settle and acquisition time of the track/hold to

elapse when a channel address is changed. If the SWCON bit of the control register is set to 1, when

this pulse times out, the track/hold then goes into hold and conversion is initiated. If the SWCON bit

of the control register is set to 0 the track/hold and conversion sequence are unaffected by the WR

operation.

Data I/O Lines

There are 12 data input/output lines on the AD7891. When the part is configured for parallel mode (MODE = 1), the output data

from the part is provided at these 12 pins during a read operation. For a write operation in parallel mode, these lines provide access

to the part’s Control Register.

Parallel Read Operation

During a parallel read operation the 12 lines become the 12 data bits containing the conversion result from the AD7891. These data

bits are labelled Data Bit 0 (LSB) to Data Bit 11 (MSB). They are three-state TTL-compatible outputs. Output data coding is twos

complement when the data FORMAT Bit of the control register is 1 and straight binary when the data FORMAT Bit of the control

register is 0.

Mnemonic

Description

DB0–DB11

Data Bit 0 (LSB) to Data Bit 11 (MSB). Three-state TTL-compatible outputs which are controlled

by the CS and RD inputs.

Parallel Write Operation

During a parallel write operation the following functions can be written to the control register via the 12 data input/output pins.

Mnemonic

Description

A0

Address Input. The status of this input during a parallel write operation is latched to the A0 bit of the

control register (see Control Register section).

A1

Address Input. The status of this input during a parallel write operation is latched to the A1 bit of the

control register (see Control Register section).

A2

Address Input. The status of this input during a parallel write operation is latched to the A2 bit of the

control register (see Control Register section).

SWCON

SWSTBY

FORMAT

Software Conversion Start. The status of this input during a parallel write operation is latched to the

SWCONV bit of the control register (see Control Register section).

Software Standby Control. The status of this input during a parallel write operation is latched to the

SWSTBY bit of the control register (see Control Register section).

Data Format Selection. The status of this input during a parallel write operation is latched to the

FORMAT bit of the control register (see Control Register section).

–8–

REV. A

AD7891

SERIAL INTERFACE MODE FUNCTIONS

When the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions.

These functions are outlined below.

Mnemonic

Description

SCLK

Serial Clock Input. This is an externally applied serial clock which is used to load serial data to the control

register and to access data from the output register.

TFS

RFS

Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling

edge of this signal.

Receive Frame Synchronization Pulse. This is an active low logic input with RFS provided externally as a

strobe or framing pulse to access serial data from the output register. For applications that require that

data be transmitted and received at the same time, RFS and TFS should be connected together.

DATA OUT

Serial Data Output. Sixteen bits of serial data are provided with the data FORMAT bit and the three

address bits of the control register preceding the 12 bits of conversion data. Serial data is valid on the

falling edge of SCLK for sixteen edges after RFS goes low. Output conversion data coding is twos comple-

ment when the FORMAT Bit of the control register is 1 and straight binary when the FORMAT Bit of the

control register is 0.

DATA IN

TEST

Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first six bits

of serial data are loaded to the control register on the first six falling edges of SCLK after TFS goes low.

Serial data on subsequent SCLK edges is ignored while TFS remains low.

Test Pin. When the device is configured for serial mode of operation, two of the pins which had been data

inputs become test inputs. To ensure correct operation of the device, both TEST inputs should be tied to

a logic low potential.

CONTROL REGISTER

The control register for the AD7891 contains 6 bits of information as described below. These 6 bits can be written to the control

register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in

the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If TFS re-

turns high before six serial clock cycles then no data transfer takes place to the control register and the write cycle will have to be

restarted to write data to the control register. However, if the SWCONV bit of the register was previously set to a logic 1 and TFS is

brought high before six serial clock cycles, then another conversion will be initiated.

MSB

A2 A1 A0 SWCONV SWSTBY FORMAT

A2

A1

A0

Address Input. This input is the most significant address input for multiplexer channel selection.

Address Input. This is the second most significant address input for multiplexer channel selection.

Address Input. Least significant address input for multiplexer channel selection. When the address is written to

the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi-

tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the

track/hold goes into hold and conversion is initiated. The selected channel is given by the formula:

A2 × 4 + A1 × 2 + A0 + 1

SWCONV

Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Con-

tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver-

sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e.,

the CONVST input, is disabled. Writing a 0 to this bit enables the hardware CONVST input.

SWSTBY

FORMAT

Standby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to

this bit places the device in its normal operating mode.

Data Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This

data format is generally be used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output

format to twos complement. This output data format is generally used for bipolar input ranges.

REV. A

–9–

AD7891

CONVERTER DETAILS

INTERFACE INFORMATION

The AD7891 is an eight-channel, high speed, 12-bit data acqui-

sition system. It provides the user with signal scaling, multi-

plexer, track/hold, reference, A/D converter and high speed

parallel and serial interface logic functions on a single chip. The

signal conditioning on the AD7891-1 allows the part to accept

analog input ranges of ±5 V or ±10 V when operating from a

single supply. The input circuitry on the AD7891-2 allows the

part to handle input signal ranges of 0 V to +2.5 V, 0 V to +5 V

and ±2.5 V again while operating from a single +5 V supply.

The part requires a +2.5 V reference which can be provided

from the part’s own internal reference or from an external refer-

ence source.

The AD7891 provides two interface options, a 12-bit parallel

interface and a high speed serial interface. The required inter-

face mode is selected via the MODE pin. The two interface

modes are discussed in the following sections.

Parallel Interface Mode

The parallel interface mode is selected by tying the MODE

input to a logic high. Figure 2 shows a timing diagram illustrating

the operational sequence of the AD7891 in parallel mode for a

hardware conversion start. The multiplexer address is written to

the AD7891 on the rising edge of the WR input. The on-chip

track/hold goes into hold mode on the rising edge of CONVST

and conversion is also initiated at this point. When the conversion

is complete, the end of conversion line (EOC) pulses low to

indicate that new data is available in the AD7891’s output regis-

ter. This EOC line can be used to drive an edge-triggered inter-

rupt of a microprocessor. CS and RD going low accesses the

12-bit conversion result. In systems where the part is interfaced

to a gate array or ASIC, this EOC pulse can be applied to the

CS and RD inputs to latch data out of the AD7891 and into the

gate array or ASIC. This means that the gate array or ASIC does

not need any conversion status recognition logic and it also elimi-

nates the logic required in the gate array or ASIC to generate

the read signal for the AD7891.

Conversion is initiated on the AD7891 either by pulsing the

CONVST input or by writing a logic 1 to the SWCONV bit of

the control register. When using the hardware CONVST input,

the on-chip track/hold goes from track to hold mode and the

conversion sequence is started on the rising edge of the CONVST

signal. When a software conversion start is initiated, an internal

pulse is generated which delays the track/hold acquisition point

and the conversion start sequence until the pulse is timed out.

This internal pulse is initiated (goes from low to high) whenever

a write to the AD7891 control register takes place with a 1 in

the SWCONV bit. It then starts to discharge and the track/hold

cannot go into hold and conversion cannot be initiated until the

pulse signal goes low.

CONVST (I)

The conversion clock for the part is internally generated and

conversion time for the AD7891 is 1.6 µs from the rising edge of

the hardware CONVST signal. The track/hold acquisition time

for the AD7891-1 is 600 ns while the track/hold acquisition time

for the AD7891-2 is 400 ns. To obtain optimum performance

from the part, the data read operation should not occur during

the conversion or during 100 ns prior to the next conversion.

This allows the AD7891-1 to operate at throughput rates up to

454.5 kSPS and the AD7891-2 at throughput rates up to

500 kSPS in the parallel mode and achieve data sheet specifi-

cations. In the serial mode, the maximum achievable through-

put rate for both the AD7891-1 and the AD7891-2 is 357 kSPS

(assuming a 20 MHz serial clock).

t₆

t₇

EOC (O)

CS (O)

t_CONV

t₁

t₅

t₁

t₅

t₂

t₈

WR (I)

RD (I)

t₃

t₉

t₄

t₁₀

VALID DATA

OUTPUT

VALID DATA

OUTPUT

DB0 - DB11

(I/O)

NOTE

All unused analog inputs should be tied to a voltage within the

nominal analog input range to avoid noise pickup. For mini-

mum power consumption, the unused analog inputs should be

tied to AGND.

I - INPUT

O = OUTPUT

Figure 2. Parallel Mode Timing Diagram

–10–

REV. A

AD7891

Serial Interface Mode

remain low for the duration of the data transfer operation. Six-

teen bits of data are transmitted in serial mode with the data

FORMAT bit first, followed by the three address bits in the

control register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the

rising edge of SCLK and is valid on the falling edge of SCLK.

At the end of the read operation, the DATA OUT line is three-

stated by a rising edge on either the SCLK or RFS inputs, which-

ever occurs first.

The serial interface mode is selected by tying the MODE input

to a logic low. In this case, five of the data/control inputs of the

parallel mode assume serial interface functions.

The serial interface on the AD7891 is a five-wire interface with

read and write capabilities, with data being read from the output

register via the DATA OUT line and data being written to the

control register via the DATA IN line. The part operates in a

slave or external clocking mode and requires an externally ap-

plied serial clock to the SCLK input to access data from the

data register or write data to the control register. There are

separate framing signals for the read (RFS) and write (TFS)

operations. The serial interface on the AD7891 is designed to

allow the part to be interfaced to systems that provide a serial

clock that is synchronized to the serial data, such as the 80C51,

87C51, 68HC11 and 68HC05 and most digital signal processors.

Write Operation

Figure 4 shows a write operation to the control register of the

AD7891. The TFS input goes low to indicate to the part that a

serial write is about to occur. The AD7891 Control Register

requires only six bits of data. These are loaded on the first six

clock cycles of the serial clock with data on all subsequent clock

cycles being ignored. Serial data to be written to the AD7891

must be valid on the falling edge of SCLK.

When using the AD7891 in serial mode, the data lines DB11–

DB10 should be tied to logic low, and the CS, WR and RD

inputs should be tied to logic high. Pins DB4–DB0 can be tied

to either logic high or logic low, but must not be left floating as

this condition could cause the AD7891 to draw large amounts

of current.

Simplifying the Serial Interface

To minimize the number of interconnect lines to the AD7891 in

serial mode, the user can connect the RFS and TFS lines of the

AD7891 together and read and write from the part simulta-

neously. In this case, new control register data line selecting the

input channel and providing a conversion start command should

be provided on the DATA IN line, while the part provides the

result from the conversion just completed on the DATA OUT

line.

Read Operation

Figure 3 shows the timing diagram for reading from the AD7891

in serial mode. RFS goes low to access data from the AD7891.

The serial clock input does not have to be continuous. The serial

data can be accessed in a number of bytes. However, RFS must

RFS (I)

t₁₁

t₁₃

t₁₇

SCLK (I)

t₁₈

t_18A

t₁₄

t₁₂

t₁₅

A0

t₁₆

3-STATE

DATA OUT (O)

FORMAT

A2

A1

DB11

DB10

DB0

NOTE

I = INPUT

O = OUTPUT

Figure 3. Serial Mode Read Operation

TFS (I)

t₁₉

t₂₂

SCLK (I)

t₂₁

t₂₀

A0

DONT

CARE

DONT

CARE

DATA IN (I)

A1

A0

CONV

STBY

FORMAT

NOTE

I = INPUT

Figure 4. Serial Mode Write Operation

REV. A

–11–

AD7891

CIRCUIT DESCRIPTION

Reference

The input resistance for the ±5 V range is typically 20 kΩ. For

the ±10 V input range the input resistance is typically 34.3 kΩ.

The resistor input stage is followed by the multiplexer and this

is followed by the high input impedance stage of the track/hold

amplifier.

The AD7891 contains a single reference pin labelled REF OUT/

REF IN, which either provides access to the part’s own +2.5 V

internal reference or to which an external +2.5 V reference can

be connected to provide the reference source for the part. The

part is specified with a +2.5 V reference voltage. Errors in the

reference source will result in gain errors in the transfer function

of the AD7891 and will add to the specified full scale errors on

the part. They will also result in an offset error injected into the

attenuator stage.

The designed code transitions take place midway between suc-

cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs,

etc.). LSB size is given by the formula, 1 LSB = FS/4096. Thus

for the ±5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the

±10 V range, 1 LSB = 20 V/4096 = 4.88 mV. Output coding is

determined by the FORMAT bit of the control register. The

ideal input/output code transitions are shown in Table I.

The AD7891 contains an on-chip +2.5 V reference. To use this

reference as a reference source for the AD7891, simply connect

a 0.1 µF disc ceramic capacitor from the REF OUT/REF IN pin

to REFGND. REFGND should be connected to AGND or the

analog ground plane. The voltage that appears at the REF OUT/

REF IN pin is internally buffered before being applied to the

ADC. If this reference is required for use external to the AD7891,

it should be buffered as the part has a FET switch in series with

the reference, resulting in a source impedance for this output of

2 kΩ nominal. The tolerance of the internal reference is ±10 mV

at +25°C with a typical temperature coefficient of 25 ppm/°C

and a maximum error over temperature of ±20 mV.

AD7891-2

Figure 6 shows the analog input section of the AD7891-2. Each

input can be configured for input ranges of 0 V to +5 V, 0 V to

+2.5 V or ±2.5 V. For the 0 V to +5 V input range, the V_INXB

input is tied to AGND and the input voltage is applied to the

V_INXAinput. For the 0 V to +2.5 V input range, the V_INXAand

V_INXBinputs are tied together and the input voltage is applied to

both. For the ±2.5 V input range, the V_INXBinput is tied to

+2.5 V and the input voltage is applied to the V_INXAinput. The

+2.5 V source must have a low output impedance. If the inter-

nal reference on the AD7891 is used, then it must be buffered

before being applied to V_INXB. The V_INXAand V_INXBinputs are

symmetrical and fully interchangeable. Thus for ease of PCB

layout on the 0 V to +5 V range or the ±2.5 V range, the input

voltage may be applied to the V_INXBinput while the V_INXAinput

is tied to AGND or +2.5 V.

If the application requires a reference with a tighter tolerance or

if the AD7891 needs to be used with a system reference, then an

external reference can be connected to the REF OUT/REF IN

pin. The external reference will overdrive the internal reference

and thus provide the reference source for the ADC. The refer-

ence input is buffered before being applied to the ADC and the

maximum input current is ±100 µA. Suitable reference for the

AD7891 include the AD580, the AD680, the AD780 and the

REF43 precision +2.5 V references.

REF OUT/REF IN

TO ADC

REFERENCE

CIRCUITRY

2k⍀

Analog Input Section

1.8k⍀

V

INXA

The AD7891 is offered as two part types, the AD7891-1 where

each input can be configured to have a ±10 V or a ±5 V input

range and the AD7891-2 where each input can be configured to

have a 0 V to 2.5 V, 0 V to 5 V and ±2.5 V input range.

1.8k⍀

2.5V

REFERENCE

TO

V

INXB

MULTIPLEXER

AD7891-2

AGND

AD7891-1

Figure 5 shows the analog input section of the AD7891-1. Each

input can be configured for ±5 V or ±10 V operation. For +5 V

operation, the V_INXAand V_INXBinputs are tied together and the

input voltage is applied to both. For ±10 V operation, the V_INXB

input is tied to AGND and the input voltage is applied to the

V_INXAinput. The V_INXAand V_INXBinputs are symmetrical and

fully interchangeable. Thus for ease of PCB layout on the ±10 V

range, the input voltage may be applied to the V_INXBinput while

the V_INXAinput is tied to AGND.

Figure 6. AD7891-2 Analog Input Structure

The input resistance for both the 0 V to +5 V and ±2.5 V ranges

is typically 3.6 kΩ. When an input is configured for 0 V to 2.5 V

operation, the input is fed into the high impedance stage of the

track/hold amplifier via the multiplexer and the two 1.8 kΩ

resistors in parallel.

The designed code transitions occur midway between successive

integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.).

LSB size is given by the formula 1 LSB = FS/4096. Thus for the

0 V to +5 V range, 1 LSB = 5 V/4096 = 1.22 mV, for the 0 V

to +2.5 V range, 1 LSB = 2.5 V/4096 = 0.61 mV and for the

±2.5 V range, 1 LSB = 5 V/4096 = 1.22 mV. Output coding is

determined by the FORMAT bit in the control register. The

ideal input/output code transitions for the ±2.5 V range are

shown in Table I. The ideal input/output code transitions for

the 0 V to +5 V range and the 0 V to +2.5 V range are shown in

Table II.

REF OUT/REF IN

TO ADC

REFERENCE CIRCUITRY

30k⍀

7.5k⍀

V

INXA

2k⍀

30k⍀

15k⍀

TO

V

INXB

MULTIPLEXER

2.5V

REFERENCE

AD7891-1

AGND

Figure 5. AD7891-1 Analog Input Structure

–12–

REV. A

AD7891

Table I. Ideal Code Transition Table for the AD7891-1, ؎10 V and ؎5 V Ranges and the AD7891-2, ؎2.5 V Range

Digital Output Code Transition¹

Analog Input

Input Voltage

Twos Complement

Straight Binary

+FSR²/2 – 3/2 LSBs³

+FSR/2 – 5/2 LSBs

+FSR/2 – 7/2 LSBs

(9.99268 V, 4.99634 V or 2.49817 V)⁴

(9.98779 V, 4.99390 V or 2.49695 V)

(9.99145 V, 4.99146 V or 2.49573 V)

011...110 to 011...111

011...101 to 011...110

011...100 to 011...101

111...110 to 111...111

111...101 to 111...110

111...100 to 111...101

AGND + 3/2 LSBs

AGND + 1/2 LSB

AGND – 1/2 LSB

AGND – 3/2 LSBs

(7.3242 mV, 3.6621 mV or 1.8310 mV)

(2.4414 mV, 1.2207 mV or 0.6103 mV)

(–2.4414 mV, –1.2207 mV or –0.6103 mV)

(–7.3242 mV, –3.6621 mV or –1.8310 mV)

000...001 to 000...010

000...000 to 000...001

111...111 to 000...000

111...110 to 111...111

100...001 to 100...010

100...000 to 100...001

011...111 to 100...000

011...110 to 011...111

–FSR/2 + 5/2 LSBs

–FSR/2 + 3/2 LSBs

–FSR/2 + 1/2 LSB

(–9.98779 V, –4.99390 V or –2.49695 V)

(–9.99268 V, –4.99634 V or –2.49817 V)

(–9.99756 V, –4.99878 V or –2.49939 V)

100...010 to 100...011

100...001 to 100...010

100...000 to 100...001

000...010 to 000...011

000...001 to 000...010

000...000 to 000...001

NOTES

¹Output Code format is determined by the FORMAT bit in the control register

²FSR is full-scale range and is 20 V for the ±10 V range, 10 V for the ±5 V range and 5 V for the ± 2.5 V range, with REFIN = +2.5 V .

³1 LSB = FSR/4096 = 4.88 mV (±10 V range), 2.44 mV (± 5 V range) and 1.22 mV (±2.5 V range), with REF IN = +2.5 V.

⁴± 10 V range, ± 5 V range or ± 2.5 V range.

Table II. Ideal Code Transition Table for the AD7891-2, 0 V to +5 V and 0 V to +2.5 V Ranges

Digital Output Code Transition¹

Analog Input

Input Voltage

Twos Complement

Straight Binary

+FSR²– 3/2 LSBs³

+FSR – 5/2 LSBs

+FSR – 7/2 LSBs

(4.99817 V or 2.49908 V)⁴

(4.99695 V or 2.49847 V)

(4.99573 V or 2.49786 V)

011...110 to 011...111

011...101 to 011...110

011...100 to 011...101

111...110 to 111...111

111...101 to 111...110

111...100 to 111...101

AGND + 5/2 LSBs

AGND + 3/2 LSBs

AGND + 1/2 LSB

(3.0518 mV or 1.52588 mV)

(1.83105 mV or 0.9155 mV)

(0.6103 mV or 0.3052 mV)

100...010 to 000...011

100...001 to 000...010

100...000 to 000...001

000...010 to 000...011

000...001 to 000...010

000...000 to 000...001

NOTES

¹Output Code format is determined by the FORMAT bit in the control register

²FSR is full-scale range and is 5 V for the 0 to 5 V range and 2.5 V for the 0 to 2.5 V range with REF IN = +2.5 V.

³1 LSB = FS/4096 = 1.22 mV (0 to 5 V range) or 610 µV (0 to 2.5 V range), with REF IN = 2.5 V.

⁴0 V to +5 V range or 0 V to + 2.5 V range.

Transfer Function of the AD7891-1 and AD7891-2

The transfer function of the AD7891-1 and AD7891-2 can be

expressed as follows:

Table III. Transfer Function M and N Values

Range

Output Data Format

M

N

AD7891-1

±10 V

Input Voltage = (M × REFIN × D/4096) + (N × REFIN)

Straight Binary

Twos Complement

Straight Binary

8

4

–4

0

–2

0

D is the output data from the AD7891 and is in the range 0 to

4095 for straight binary encoding and from –2048 to 2047 for

twos complement encoding. Values for M depend upon the

input voltage range. Values for N depend upon the input volt-

age range and the output data format. These values are given in

Table III. REFIN is the reference voltage applied to the AD7891.

±10 V

±5 V

Twos Complement

AD7891-2

0 V to +5 V

0 V to +2.5 V

±2.5 V

Straight Binary

Twos Complement

Straight Binary

Twos Complement

Straight Binary

Twos Complement

2

1

2

0

1

0

0.5

–1

0

±2.5 V

REV. A

–13–

AD7891

Track/Hold Amplifier section

P3.4

P3.3

TXD

RFS

The track/hold amplifier on the AD7891 allows the ADC to

accurately convert an input sine wave of full-scale amplitude to

12-bit accuracy. The input bandwidth of the track/hold is

greater than the Nyquist rate of the ADC even when the ADC is

operated at its maximum throughput rate of 454 kHz (AD7891-

1) or 500 kHz (AD7891-2). In other words, the track/hold

amplifier can handle input frequencies in excess of 227 kHz

(AD7891-1) or 250 kHz (AD7891-2).

TFS

AD7891*

8X51*

SCLK

RXD

DATA IN

DATA OUT

*ADDITIONAL PINS OMITTED FOR CLARITY

The track/hold amplifier acquires an input signal in 600 ns

(AD7891-1) or 400 ns (AD7891-2). The operation of the track/

hold is essentially transparent to the user. The track/hold ampli-

fier goes from its tracking mode to its hold mode on the rising

edge of CONVST. The aperture time for the track/hold (i.e.,

the delay between the external CONVST signal and the track/

hold actually going into hold) is typically 15 ns. At the end of

conversion, the part returns to its tracking mode. The track/hold

starts acquiring the next signal at this point.

Figure 7. AD7891 to 8X51 Interface

The 8X51 provides the LSB of its SBUF register as the first bit

in the serial data stream. The AD7891 expects the MSB of the

6-bit write first. Therefore, the data in the SBUF register must

be arranged correctly so that this is taken into account. When

data is to be transmitted to the part, P3.3 is taken low. The

8XC51 transmits its data in 8-bit bytes with only 8 falling clock

edges occurring in the transmit cycle. One 8-bit transfer is

needed to write data to the control register of the AD7891.

After the data has been transferred, the P3.3 line is taken high

to complete the transmission.

STANDBY Operation

The AD7891 can be put into power save or standby mode by

use of the STANDBY pin or the SWSTBY bit of the control

register. Normal operation of the AD7891 takes place when the

STANDBY input is at a logic one and the SWSTBY bit is at a

logic zero. When the STANDBY pin is brought low or a one is

written to the SWSTBY bit, then the part goes into its standby

mode of operation, which reduces its power consumption to

typically 75 µW.

When reading data from the AD7891, P3.4 of the 8X51 is taken

low. Two 8-bit serial reads are performed by the 8X51 and P3.4

is taken high to complete the transfer. Again, the 8X51 expects

the LSB first, while the AD7891 transmits MSB first, so this

must be taken into account in the 8X51 software.

No provision has been made in the given interface to determine

when a conversion has ended. If the conversions are initiated by

software, then the 8X51 can wait a predetermined amount of

time before reading back valid data. Alternately the falling edge

of the EOC signal can be used to initiate an interrupt service

routine which reads the conversion result from part to part.

The AD7891 is returned to normal operation when the

STANDBY input is at a logic 1 and the SWSTBY bit is a logic

zero. The wake-up time of the AD7891 is normally determined

by the amount of time required to charge the 0.1 µF capacitor

between the REF OUT/REF IN pin and REFGND. If the inter-

nal reference is being used as the reference source, then this

capacitor is charged via a nominal 2 kΩ resistor. Assuming 10

time constants to charge the capacitor to 12-bit accuracy, this

implies a wake-up time of 2 ms.

AD7891 to 68HC11 Serial Interface

Figure 8 shows a serial interface between the AD7891 and the

68HC11 microcontroller. SCK of the 68HC11 drives SCLK of

the AD7891, the MOSI output drives DATA IN of the AD7891

and the MISO input receives data from DATA OUT of the

AD7891. Ports PC6 and PC7 of the 68HC11 drive the TFS

and RFS lines of the AD7891 respectively.

If an external reference is used, then this will have to be taken

into account when working out how long it will take to charge

the capacitor. If the external reference has remained at 2.5 V

during the time the AD7891 was in standby mode, then the

capacitor will already be charged when the part is taken out of

standby mode. Thus the wake-up time is now the time required

for the internal circuitry of the AD7891 to settle to 12-bit accu-

racy. This typically takes 5 µs. If the external reference was also

put into standby then the wake-up time of the reference, com-

bined with the amount of time taken to recharge the reference

capacitor from the external reference, determines how much

time must elapse before conversions can begin again.

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 1 and its CPHA bit is a 0.

When data is to be transferred to the AD7891, PC7 is taken

low. When data is to be received from the AD7891, PC6 is

taken low. The 68HC11 transmits and receives its serial data in

8-bit bytes, MSB first. The AD7891 transmits and receives data

MSB first also. Eight falling clock edges occur in a read or write

cycle from the 68HC11. A single 8-bit write with PC7 low is

required to write to the control register. When data has been

written, PC7 is taken high. When reading from the AD7891,

PC6 is left low after the first eight bits have been read. A second

byte of data is then transmitted serially from the AD7891. When

this transfer is complete, the PC6 line is taken high.

MICROPROCESSOR INTERFACING

AD7891 to 8X51 Serial Interface

A serial interface between the AD7891 and the 8X51 micro-

controller is shown in Figure 7. TXD of the 8X51 drives SCLK

of the AD7891 while RXD transmits data to and receives data

from the part. The serial clock speed of the 8X51 is slow com-

pared to the maximum serial clock speed of the AD7891, so

maximum throughput of the AD7891 is not achieved with this

interface.

–14–

REV. A

AD7891

As in the 8X51 circuit above, the way that the 68HC11 is in-

formed that a conversion is completed is not shown in the dia-

gram. The EOC line can be used to inform the 68HC11 that a

conversion is complete by using it as an interrupt signal. The

interrupt service routine reads in the result of the conversion. If

a software conversion start is used, the 68HC11 can wait for

2.0 µs (AD7891-2) or 2.2 µs (AD7891-1) before reading from

the AD7891.

AD7891 to DSP5600x Serial Interface

Figure 10 shows a serial interface between the AD7891 and the

DSP5600x series of DSPs. When reading from the AD7891, the

DSP5600x should be set up for 16-bit data transfers, MSB first,

normal mode synchronous operation, internally generated word

frame sync and gated clock. When writing to the AD7891, 8-bit

or 16-bit data transfers can be used. The frame sync signal from

the DSP5600x must be inverted before being applied to the

RFS and TFS inputs of the AD7891 as shown in Figure 10.

To monitor the conversion time of the AD7891, a scheme such

as outlined in previous interfaces with EOC can be used. This

can be implemented by connecting the EOC line directly to the

IRQA input of the DSP5600x.

PC7

PC6

SCK

RFS

TFS

68HC11*

AD7891*

SCLK

MOSI

DATA IN

DSP56000/

DSP56002*

MOSO

DATA OUT

RFS

FST (SC2)

TFS

*ADDITIONAL PINS OMITTED FOR CLARITY

AD7891*

SCK

SCLK

Figure 8. AD7891 to 68HC11 Interface

STD

SRD

DATA IN

AD7891 to ADSP-21xx Serial Interface

DATA OUT

An interface between the AD7891 and the ADSP-21xx is shown

in Figure 9. In the interface shown either SPORT0 or SPORT1

can be used to transfer data to the AD7891. When reading from

the part, the SPORT must be set up with a serial word length of

16 bits. When writing to the AD7891, a serial word length of 6

bits or more can be used. Other setups for the serial interface on

the ADSP-21xx internal SCLK, alternate framing mode and

active low framing signal. Normally the EOC line from the

AD7891 would be connected to the IRQ2 line of the ADSP-

21xx to interrupt the DSP at the end of a conversion (not shown

in diagram).

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 10. AD7891 to DSP5600x Serial Interface

AD7891 to TMS320xxx Serial Interface

The AD7891 can be interfaced to the serial port of TMS320xxx

DSPs as shown in Figure 11. External timing generation cir-

cuitry is necessary to generate the serial clock and syncs neces-

sary for the interface.

TIMING

GENERATION

CIRCUITRY

RFS

TFS

RFS

TFS

FSR

FSX

TMS32020/

TMS320C25/

TMS320C5X/

TMS320C3X*

TFS

ADSP-21xx*

AD7891*

SCLK

AD7891*

CLKR

SCLK

DT

DR

DATA IN

CLKX

DX

DATA OUT

DATA IN

DR

DATA OUT

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 9. AD7891 to ADSP-2101 Serial Interface

Figure 11. AD7891 to TMSxxx Serial Interface

REV. A

–15–

AD7891

PARALLEL INTERFACING

The parallel interface on the AD7891 is fast enough to interface

to the TMS32020 with no extra wait states. If high speed glue

logic such as 74AS devices are used to drive the WR and RD

lines when interfacing to the TMS320C25, then again no wait

states are necessary. However, if slower logic is used, data ac-

cesses may be slowed sufficiently when reading from and writing

to the part to require the insertion of one wait state. In such a

case, this wait state can be generated using the single OR gate to

combine the CS and MSC signals to drive the READY line of

the TMS320C25, as shown in Figure 13. Extra wait states will

be necessary when using the TMS320C5x at their fastest clock

speeds. Wait states can be programmed via the IOWSR and

CWSR registers (please see TMS320C5x User Guide for details).

The parallel port on the AD7891 allows the device to be inter-

faced to microprocessors or DSP processors as a memory

mapped or I/O mapped device. The CS and RD inputs are

common to all memory peripheral interfacing. Typical interfaces

to different processors are shown in Figures 12 to 15. In all the

interfaces shown, an external timer controls the CONVST input

of the AD7891 and the EOC output interrupts the host DSP.

AD7891 to ADSP-21xx

Figure 12 shows the AD7891 interfaced to the ADSP-21xx

series of DSPs as a memory mapped device. A single wait state

may be necessary to interface the AD7891 to the ADSP-21xx

depending on the clock speed of the DSP. This wait state can be

programmed via the Data Memory Waitstate Control Register

of the ADSP-21xx (please see ADSP-2100 family Users manual

for details). The following instruction reads data from the

AD7891:

Data is read from the ADC using the following instruction:

IN D,ADC

where D is the memory location where the data is to be stored

and ADC is the I/O address of the AD7891.

MR = DM(ADC)

AD7891 to TMS320C30

where ADC is the address of the AD7891.

Figure 14 shows a parallel interface between the AD7891 and

the TMS320C3x family of DSPs. The AD7891 is interfaced to

the Expansion Bus of the TMS320C3x. A single wait state is

required in this interface. This can be programmed using the

WTCNT bits of the Expansion Bus Control register (see

TMS320C3x Users guide for details). Data from the AD7891

can be read using the following instruction:

ADDRESS BUS

A13–A0

ADDR

DECODE

ADSP-21xx*

CS

EN

DMS

WR

RD

WR

RD

AD7891*

LDI *ARn,Rx

where ARn is an auxiliary register containing the lower 16 bits

of the address of the AD7891 in the TMS320C3x memory

space and Rx is the register into which the ADC data is loaded.

EOC

IRQ2

DATA BUS

D23–D8

DB11–DB0

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

XA15–XA0

Figure 12. AD7891 to ADSP-21xx Parallel Interface

AD7891 to TMS32020, TMS320C25 and TMS320C5x

Parallel interfaces between the AD7891 and the TMS32020,

TMS320C25 and TMS320C5x family of DSPs are shown in

Figure 13. The memory mapped address chosen for the

AD7891 should be chosen to fall in the I/O memory space of

the DSPs.

ADDR

DECODE

TMS320C30*

CS

AD7891*

IOSTRB

XR/W

WR

RD

EOC

INTx

EXPANSION DATA BUS

XD23–XD0

DB11–DB0

ADDRESS BUS

ADDR

A15–A0

*ADDITIONAL PINS OMITTED FOR CLARITY

TMS32020/

TMS320C25/

TMS320C50*

CS

EN

IS

DECODE

Figure 14. AD7891 to TMS320C30 Parallel Interface

READY

TMS320C25

ONLY

AD7891*

MSC

STRB

R/W

WR

RD

EOC

INTx

D23–D0

DATA BUS

DB11–DB0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. AD7891 to TMS32020/C25/C5x Parallel Interface

–16–

REV. A

AD7891

AD7891 to DSP5600x

Digital lines running under the device should be avoided as

these will couple noise onto the die. The analog ground plane

should be allowed to run under the AD7891 to avoid noise

coupling. The power supply lines of the AD7891 should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board and

should never be run near the analog inputs. Avoid crossover of

digital and analog signals. Traces on opposite sides of the board

should run at right angles to each other. This reduces the effects

of feedthrough through the board. A microstrip technique is by

far the best but not always possible with a double sided board.

In this technique, the component side of the board is dedicated

to ground plane while signal traces are placed on the solder side.

Figure 15 shows a parallel interface between the AD7891 and

the DSP5600x series of DSPs. The AD7891 should be mapped

into the top 64 locations of Y data memory. If extra wait states

are needed in this interface, they can be programmed using

the Port A Bus Control Register (please see DSP5600x users

manual for details). Data can be read from the AD7891 using

the following instruction:

MOVEO Y:ADC,X0

where ADC is the address in the DSP5600x address space to

which the AD7891 has been mapped.

ADDRESS BUS

A15–A0

DSP56000/

DSP56002*

X/Y

ADDR

DECODE

CS

The AD7891 should have ample supply bypassing located as

close to the package as possible, ideally right up against the

device. One of the V_DDpins (Pin 10 of the PQFP package, Pin 4

on the PLCC package) drives mainly the analog circuitry on the

chip. This pin should be decoupled to the analog ground plane

with a 10 µF tantalum bead capacitor in parallel with a 0.1 µF

capacitor. The other V_DDpin (Pin 19 on the PQFP package,

Pin 13 on the PLCC package) drives mainly digital circuitry on

the chip. This pin should be decoupled to the digital ground

plane with a 0.1 µF capacitor. The 0.1 µF capacitors should

have low Effective Series Resistance (ESR) and Effective Series

Inductance (ESI), such as the common ceramic types or surface

mount types, which provide a low impedance path to ground at

high frequencies to handle transient currents due to internal

logic switching. Figure 16 shows the recommended decoupling

scheme.

DS

WR

RD

WR

RD

AD7891*

IRQ

EOC

DATA BUS

D23–D0

DB11–DB0

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. AD7891 to DSP5600x Parallel Interface

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the specified performance. The printed circuit board on which

the AD7891 is mounted should be designed such that the ana-

log and digital sections are separated and confined to certain

areas of the board. This facilitates the use of ground planes that

can be separated easily. A minimum etch technique is generally

best for ground planes as it gives the best shielding. Digital and

analog ground planes should be joined at only one place. If the

AD7891 is the only device requiring an AGND to DGND con-

nection then the ground planes should be connected at the

AGND and DGND pins of the AD7891. If the AD7891 is in a

system where multiple devices require an AGND to DGND

connection, the connection should still be made at one point

only, a star ground point which should be established as close as

possible to the AD7891.

AD7891

V

(PIN 10, PQFP

PIN 4, PLCC)

DD

0.1␮F

10␮F

AGND

V

(PIN 19, PQFP

PIN 13, PLCC)

DD

DGND

Figure 16. Recommended Decoupling Scheme for the

AD7891

REV. A

–17–

AD7891

AD7891 PERFORMANCE

Linearity

Dynamic Performance

The AD7891 contains an on-chip track/hold amplifier, allowing

the part to sample input signals of up to 250 kHz on any of its

input channels. Many of the AD7891’s applications will simply

require it to sequence through low frequency input signals

across its eight channels. There may be some applications, how-

ever, for which the dynamic performance of the converter on

signals of up to 250 kHz input frequency is of interest. It is

recommended for these wider bandwidth signals that hardware

conversion start method of sampling is used.

The Linearity of the AD7891 is primarily determined by the on-

chip 12-bit D/A converter. This is a segmented DAC which is

laser trimmed for 12-bit integral linearity and differential linear-

ity. Typical INL for the AD7891 is ±0.25 LSB while typical

DNL is ±0.5 LSB.

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT for example)

in ac applications. In a sampling A/D such as the AD7891, all

information about the analog input appears in the baseband

from dc to half the sampling frequency. The input bandwidth of

the track/hold amplifier exceeds the Nyquist bandwidth and,

therefore, an antialiasing filter should be used to remove un-

wanted signals above f_S/2 in the input signal in applications

where such signals exist.

These applications require information on the spectral content

of the input signal. Signal to (noise + distortion), total harmonic

distortion, peak harmonic or spurious tone and intermodulation

distortion are all specified. Figure 18 shows a typical FFT plot

of a 10 kHz, ±10 V input after being digitized by the AD7891-1

operating at 500 kHz, with the input connected for ±10 V opera-

tion. The signal to (noise + distortion) ratio is 72.2 dB and the

total harmonic distortion is –87 dB. Figure 19 shows a typical

FFT plot of a 100 kHz, 0 V to +5 V input after being digitized

by the AD7891-2 operating at 500 kHz, with the input connected

for 0 V to +5 V operation. The signal to (noise + distortion)

ratio is 71.17 dB and the total harmonic distortion is –82.3 dB.

It should be noted that reading from the part during conversion

does have a significant impact on dynamic performance. There-

fore, for sampling applications, it is recommended not to read

during conversion.

Figure 17 shows a histogram plot for 16384 conversions of a dc

input signal using the AD7891-1. The analog input was set at

the center of a code transition in the following way. An initial dc

input level was selected and a number of conversions were

made. The resulting histogram was noted and the applied level

was adjusted so that only two codes were generated with an

equal number of occurrences. This indicated that the transition

point between the two codes had been found. The voltage level

at which this occurred was recorded. The other edge of one of

these two codes was then found in a similar manner. The dc

level for the center of code could then be calculated as the aver-

age of the two transition levels. The AD7891-1 inputs were

configured for ±5 V input range and the data was read from the

part in parallel mode, after conversion. Similar results have been

found with the AD7891-1 on the ±10 V range and on all input

ranges of the AD7891-2. The same performance is achieved in

serial mode, again with the data read from the AD7891-1 after

conversion. All the codes, except for 3, appear in one output

bin, indicating excellent noise performance from the ADC.

2048 POINT FFT

0

–30

SNR = 72.2dB

–60

–90

–120

–150

18000

16381 Codes

16000

F

/2

S

14000

12000

Figure 18. Typical AD7891-1 FFT Plot

10000

8000

6000

2048 POINT FFT

0

–30

4000

2000

SNR = 71.17dB

–60

1 Code

2148

2 Codes

2150

0

2149

OUTPUT CODE

–90

Figure 17. Typical Histogram Plot (AD7891-1)

–120

–150

F

/2

S

Figure 19. Typical AD7891-2 FFT Plot

–18–

REV. A

AD7891

Effective Number of Bits

12.0

The formula for signal to (noise + distortion) Ratio (see termi-

nology) is related to the resolution, or number of bits, of the

converter. Rewriting the formula, below, gives a measure of

performance expressed in effective number of bits (ENOB):

11.9

11.8

11.7

11.6

11.5

11.4

11.3

11.2

11.1

ENOB = (SNR - 1.76)/6.02

AD7891-2 ENOB

where SNR is the signal to (noise + distortion) ratio.

The effective number of bits for a device can be calculated from

its measured SNR. Figure 20 shows a typical plot of effective

number of bits versus frequency for the AD7891-1 and the

AD7891-2 from dc to 200 kHz. The sampling frequency is

500 kHz. The AD7891-1 inputs were configured for ±10 V

operation. The AD7891-2 inputs were configured for 0 to +5 V

operation. The AD7891-1 plot only goes to 100 kHz as a

±10 V sine wave of sufficient quality was unavailable at higher

frequencies.

AD7891-1 ENOB

11.0

0

20

40

60

80

100 120 140 160 180 200

FREQUENCY – kHz

Figure 20. Effective Number of Bits vs. Frequency

Figure 20 shows that the AD7891-1 converts an input sine wave

of 100 kHz to an effective number of bits of of 11 which equates

to a signal-to-(noise + distortion) level of 68.02 dBs. The

AD7891-2 converts an input sine wave of 200 kHz to an effec-

tive number of bits of 11.07 which equates to a signal-to-(noise

+ distortion) level of 68.4 dBs.

REV. A

–19–

AD7891

OUTLINE DIMENSIONS

Dimension shown in inches and (mm).

44-Lead PLCC

(P-44A)

0.180 (4.57)

0.165 (4.19)

0.056 (1.42)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

0.048 (1.21)

0.042 (1.07)

6

40

39

7

PIN 1

IDENTIFIER

0.050

(1.27)

BSC

0.63 (16.00)

0.59 (14.99)

0.021 (0.53)

0.013 (0.33)

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

17

29

28

18

0.040 (1.01)

0.025 (0.64)

0.020

(0.50)

R

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

44-Terminal PQFP

(S-44)

0.557 (14.15)

0.537 (13.65)

0.397 (10.1)

0.390 (9.9)

0.096 (2.45)

MAX

0.037 (0.95)

0.026 (0.65)

SEATING PLANE

8؇

0.8؇

33

23

34

22

0.398 (10.1)

0.390 (9.9)

TOP VIEW

(PINS DOWN)

44

12

1

11

0.040 (1.02)

0.032 (0.82)

0.040 (1.02)

0.032 (0.82)

0.033 (0.85)

0.029 (0.75)

0.016 (0.4)

0.012 (0.3)

0.083 (2.1)

0.077 (1.95)

–20–

REV. A


型号：	AD7891
厂家：	ADI
描述：	LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System LC2MOS 8通道， 12位高速数据采集系统
文件：	总20页 (文件大小：176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7891 [ADI]

相关型号：

AD7891ACHIPS-1

AD7891ACHIPS-2

AD7891AP

AD7891AP-1

AD7891AP-1REEL

AD7891AP-2

AD7891AP-2REEL

AD7891APZ-1

AD7891APZ-1REEL

AD7891APZ-2

AD7891APZ-2REEL

AD7891AS-1