AD7914BRU [ADI]
4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP; 4通道， 1 MSPS ， 8位/ 10位/ 12位ADC，定序器采用16引脚TSSOP
| 型号： | AD7914BRU |
| 厂家： | 
ADI |
| 描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 文件： | 总24页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs
with Sequencer in 16-Lead TSSOP
a
AD7904/AD7914/AD7924
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low Power:
6 mW max at 1 MSPS with 3 V Supplies
13.5 mW max at 1 MSPS with 5 V Supplies
4 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
V
DD
REF
IN
V
0
IN
T/H
•
•
•
•
•
•
•
•
•
•
•
•
•
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7924, 70 dB SNR at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
I/P
MUX
High Speed Serial Interface SPITM/QSPITM
/
MICROWIRETM/DSP Compatible
Shutdown Mode: 0.5 A Max
V
3
16-Lead TSSOP Package
IN
SCLK
DOUT
DIN
CONTROL LOGIC
SEQUENCER
GENERAL DESCRIPTION
The AD7904/AD7914/AD7924 are respectively, 8-bit, 10-bit,
and 12-bit, high speed, low power, 4-channel, successive-approxi-
mation ADCs. The parts operate from a single 2.7 V to 5.25 V
power supply and feature throughput rates up to 1 MSPS. The
parts contain a low noise, wide bandwidth track/hold amplifier that
can handle input frequencies in excess of 8 MHz.
CS
AD7904/AD7914/AD7924
V
DRIVE
GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and conversion is also
initiated at this point. There are no pipeline delays associated
with the part.
The AD7904/AD7914/AD7924 offer up to 1 MSPS through-
put rates. At the maximum throughput rate with 3 V sup`plies,
the AD7904/AD7914/AD7924 dissipate just 6 mW of
power maximum.
2. Four Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels can be selected, through
which the ADC will cycle and convert on.
The AD7904/AD7914/AD7924 use advanced design techniques to
achieve very low power dissipation at maximum throughput rates.
At maximum throughput rates, the AD7904/AD7914/AD7924
consume 2 mA maximum with 3 V supplies; with 5 V supplies, the
current consumption is 2.7 mA maximum.
3. Single-Supply Operation with VDRIVE Function.
The AD7904/AD7914/AD7924 operate from a single 2.7 V
to 5.25 V supply. The VDRIVE function allows the serial inter-
face to connect directly to either 3 V or 5 V processor systems
Through the configuration of the Control Register, the analog
input range for the part can be selected as 0 V to REFIN or 0 V
to 2 × REFIN, with either straight binary or twos complement
output coding. The AD7904/AD7914/AD7924 each feature four
single-ended analog inputs with a channel sequencer to allow a
preprogrammed selection of channels to be converted sequentially.
independent of VDD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock speed
increase. The parts also feature various shutdown modes to
maximize power efficiency at lower throughput rates. Current
consumption is 0.5 µA max when in full shutdown.
The conversion time for the AD7904/AD7914/AD7924 is deter-
mined by the SCLK frequency, as this is also used as the master
clock to control the conversion.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX
,
AD7904–SPECIFICATIONS
unless otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise
(SFDR)2
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
49
49
–66
dB min
dB min
dB max
–64
dB max
Intermodulation Distortion (IMD)2
Second Order Terms
fa = 40.1 kHz, fb = 41.5 kHz
–90
–90
10
dB typ
dB typ
ns typ
Third Order Terms
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
8
Bits
LSB max
LSB max
0.2
0.2
Guaranteed No Missed Codes to 8 Bits
Straight Binary Output Coding
0.5
0.05
0.2
LSB max
LSB max
LSB max
LSB max
Offset Error Match
Gain Error
Gain Error Match
0.05
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
0.2
0.05
0.5
0.1
0.2
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0.05
ANALOG INPUT
Input Voltage Range
0 to REFIN
0 to 2 × REFIN
1
V
V
RANGE Bit Set to 1
RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
µA max
pF typ
20
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1% Specified Performance
fSAMPLE = 1 MSPS
µA max
kΩ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V min
0.3 × VDRIVE
V max
µA max
pF max
1
10
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
V min
ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
MSPS max See Serial Interface Section
–2–
REV. 0
AD7904/AD7914/AD7924
Parameter
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
VDD = 2.7 V to 5.25 V, SCLK On or Off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
mA max
mA max
µA typ
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Using Auto Shutdown Mode
fSAMPLE = 250 kSPS
(Static)
SCLK On or Off (20 nA typ)
µA max
µA max
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
VDD = 5 V, fSCLK = 20 MHz
V
V
DD = 3 V, fSCLK = 20 MHz
DD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
VDD = 3 V
DD = 5 V
VDD = 3 V
V
NOTES
1Temperature ranges as follows: B Version: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power Versus Throughput Rate section.
Specifications subject to change without notice.
REV. 0
–3–
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX
,
AD7914–SPECIFICATIONS
unless otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise
(SFDR)2
61
61
dB min
dB min
dB max
–72
–74
dB max
Intermodulation Distortion (IMD)2
Second Order Terms
fa = 40.1 kHz, fb = 41.5 kHz
–90
–90
10
dB typ
dB typ
ns typ
Third Order Terms
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
10
0.5
0.5
Bits
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
Straight Binary Output Coding
2
LSB max
LSB max
LSB max
LSB max
Offset Error Match
Gain Error
Gain Error Match
0.2
0.5
0.2
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
0.5
0.2
2
0.2
0.5
0.2
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
ANALOG INPUT
Input Voltage Range
0 to REFIN
0 to 2 × REFIN
1
V
V
RANGE Bit Set to 1
RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
µA max
pF typ
20
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1% Specified Performance
fSAMPLE = 1 MSPS
µA max
kΩ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V min
0.3 × VDRIVE
V max
µA max
pF max
1
10
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
V min
ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
MSPS max See Serial Interface Section
–4–
REV. 0
AD7904/AD7914/AD7924
Parameter
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
VDD = 2.7 V to 5.25 V, SCLK On or Off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
mA max
mA max
µA typ
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Using Auto Shutdown Mode
fSAMPLE = 250 kSPS
(Static)
SCLK On or Off (20 nA typ)
µA max
µA max
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
VDD = 5 V, fSCLK = 20 MHz
V
V
DD = 3 V, fSCLK = 20 MHz
DD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
VDD = 3 V
DD = 5 V
VDD = 3 V
V
NOTES
1Temperature ranges as follows: B Version: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power Versus Throughput Rate section.
Specifications subject to change without notice.
REV. 0
–5–
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX
,
AD7924–SPECIFICATIONS
unless otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
@ 5 V
@ 3 V Typically 69.5 dB
Signal to Noise + Distortion (SINAD)2
70
69
70
–77
–73
–78
–76
dB min
dB min
dB min
dB max
dB max
dB max
dB max
Signal to Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
@ 5 V Typically –84 dB
@ 3 V Typically –77 dB
@ 5 V Typically –86 dB
@ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz
Peak Harmonic or Spurious Noise
(SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
–90
–90
10
dB typ
dB typ
ns typ
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
12
Bits
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
1
LSB max
LSB max
–0.9/+1.5
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Typically 0.5 LSB
8
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Gain Error Match
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
1.5
0.5
8
0.5
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Typically 0.8 LSB
0.5
ANALOG INPUT
Input Voltage Range
0 to REFIN
V
RANGE Bit Set to 1
0 to 2 × REFIN
V
RANGE Bit Set to 0, VDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
1
µA max
pF typ
20
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1% Specified Performance
fSAMPLE = 1 MSPS
µA max
kΩ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V min
0.3 × VDRIVE
V max
µA max
pF max
1
10
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
10
Straight (Natural) Binary
Twos Complement
V min
ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
Coding Bit Set to 1
Coding Bit Set to 0
–6–
REV. 0
AD7904/AD7914/AD7924
Parameter
B Version1
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
MSPS max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
See Serial Interface Section
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
Normal Mode(Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
VDD = 2.7 V to 5.25 V, SCLK On or Off
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
mA max
mA max
µA typ
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Using Auto Shutdown Mode
fSAMPLE = 250 kSPS
(Static)
SCLK On or Off (20 nA typ)
µA max
µA max
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
VDD = 5 V, fSCLK = 20 MHz
V
V
DD = 3 V, fSCLK = 20 MHz
DD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
VDD = 3 V
DD = 5 V
VDD = 3 V
V
NOTES
1Temperature ranges as follows: B Versions: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power Versus Throughput Rate section.
Specifications subject to change without notice.
REV. 0
–7–
AD7904/AD7914/AD7924
TIMING SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, VDRIVE Յ VDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX AD7904/AD7914/AD7924
Parameter
VDD = 3 V
VDD = 5 V
Unit
Description
2
fSCLK
10
10
kHz min
20
20
MHz max
tCONVERT
tQUIET
16 × tSCLK
50
16 × tSCLK
50
ns min
Minimum Quiet Time Required Between CS Rising Edge
and Start of Next Conversion
t23
t33
t4
t5
t6
10
35
40
10
30
40
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs max
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
0.4 × tSCLK
0.4 × tSCLK
10
15/45
10
5
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
SCLK High Pulsewidth
t74
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto
Shutdown Modes
t8
t9
t10
t11
t12
20
1
20
1
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE
.
4t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
–8–
REV. 0
AD7904/AD7914/AD7924
TSSOP Package, Power Dissipation ........................... 450 mW
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted.)
θ
θ
JA Thermal Impedance ......................... 150.4°C/W (TSSOP)
AVDD to AGND ............................................... –0.3 V to +7 V
JC Thermal Impedance........................... 27.6°C/W (TSSOP)
V
DRIVE to AGND................................ –0.3 V to AVDD + 0.3 V
Lead Temperature, Soldering
Analog Input Voltage to AGND ......... –0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND........................ –0.3 V to +7 V
Digital Output Voltage to AGND ........... –0.3 V to AVDD + 0.3 V
REFIN to AGND ................................ –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 ................. 10 mA
Operating Temperature Range
Commercial (B Version) ............................. –40°C to +85°C
Storage Temperature Range ...................... –65°C to +150°C
Junction Temperature ................................................... 150°C
Vapor Phase (60 secs) ................................................ 215°C
Infrared (15 secs) ....................................................... 220°C
ESD ................................................................................. 2 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
I
200A
OL
TO
OUTPUT
PIN
1.6V
C
50pF
L
I
200A
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option
Package
Description
Model
Error (LSB)1
AD7904BRU
AD7914BRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Controller Board
0.2
0.5
1
RU-16
RU-16
RU-16
TSSOP
TSSOP
TSSOP
AD7924BRU
EVAL-AD79x4CB2
EVAL-CONTROL BRD23
NOTES
1Linearity error here refers to integral linearity error.
2This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.
The board comes with one chip of each the AD7904, AD7914, and AD7924.
3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To
order a complete evaluation kit you will need to order the particular ADC evaluation board, e.g., EVAL-AD79x4CB, the EVAL-CONTROL BRD2,
and a 12 V ac transformer. See relevant Evaluation Board Technical Note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7904/AD7914/AD7924 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–9–
AD7904/AD7914/AD7924
PIN CONFIGURATION
16-Lead TSSOP
SCLK
DIN
1
2
3
4
5
6
7
8
16 AGND
15
V
DRIVE
AD7904/
AD7914/
AD7924
14 DOUT
13 AGND
CS
AGND
AV
AV
12
11
10
9
V 0
IN
DD
DD
TOP VIEW
(Not to Scale)
V
1
IN
REF
V 2
IN
IN
AGND
V 3
IN
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7904/AD7914/AD7924’s conversion process.
2
3
DIN
Data In. Logic Input. Data to be written to the AD7904/AD7914/AD7924’s Control Register is
provided on this input and is clocked into the register on the falling edge of SCLK (see Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7904/AD7914/AD7924 and also frames the serial data transfer.
CS
4, 8, 13, 16 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All
analog input signals and any external reference signal should be referred to this AGND voltage. All
AGND pins should be connected together.
5, 6
7
AVDD
Analog Power Supply Input. The AVDD range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V.
For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V.
Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this
input. The voltage range for the external reference is 2.5 V 1% for specified performance.
REFIN
12–9
VIN0–VIN3
Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed
into the on-chip track/hold. The analog input channel to be converted is selected by using the address
bits ADD1 and ADD0 of the control register. The address bits, in conjunction with the SEQ1 and
SEQ0 bits, allow the Sequencer to be programmed. The input range for all input channels can extend
from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any
unused input channels should be connected to AGND to avoid noise pickup.
14
DOUT
Data Out. Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input.
The data stream from the AD7904 consists of two leading zeros, two address bits indicating which channel
the conversion result corresponds to, followed by the eight bits of conversion data, followed by four
trailing zeros, provided MSB first; the data stream from the AD7914 consists of two leading zeros, two
address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of
conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7924
consists of two leading zeros, two address bits indicating which channel the conversion result corresponds
to, followed by the 12 bits of conversion data provided MSB first. The output coding may be selected
as straight binary or twos complement via the CODING bit in the control register.
15
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the serial interface of
the AD7904/AD7914/AD7924 will operate at.
–10–
REV. 0
AD7904/AD7914/AD7924
TERMINOLOGY
Negative Gain Error Match
Integral Nonlinearity
This is the difference in Negative Gain Error between any two
channels.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Channel-to-Channel Isolation
Channel-to-Channel Isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 400 kHz
sine wave signal to all three nonselected input channels and deter-
mining how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure is given worst case across all
four channels for the AD7904/AD7914/AD7924.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
PSR (Power Supply Rejection)
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Variations in power supply will affect the full scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power-supply voltage from the nominal value. See Typical
Performance Curves.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
Track/Hold Acquisition Time
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the
offset error has been adjusted out.
The track/hold amplifier returns into track mode at the end
of conversion. Track/Hold acquisition time is the time required
for the output of the track/hold amplifier to reach its final
value, within 1 LSB, after the end of conversion.
Gain Error Match
This is the difference in Gain error between any two channels.
Signal to (Noise + Distortion) Ratio
Zero Code Error
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the midscale transition (all 0s to all 1s) from the ideal VIN volt-
age, i.e., REFIN – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two
channels.
Signal to(Noise + Distortion) = (6.02N +1.76)dB
Positive Gain Error
Thus for a 12-bit converter, this is 74 dB, for a 10-bit converter
this is 62 dB, and for an 8-bit converter this is 50 dB.
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the last code transition (011. . .110) to (011 . . . 111) from the
ideal (i.e., +REFIN – 1 LSB) after the Zero Code Error has been
adjusted out.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7904/AD7914/AD7924, it
is defined as:
Positive Gain Error Match
This is the difference in Positive Gain Error between any two
channels.
V22 +V32 +V42 +V52 +V62
THD(dB) = 20log
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × REFIN input range with –REF IN
to +REFIN biased about the REFIN point. It is the deviation of
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has
been adjusted out.
REV. 0
–11–
AD7904/AD7914/AD7924–Typical Performance Characteristics
PERFORMANCE CURVES
TPC 4 shows a graph of total harmonic distortion versus analog
TPC 1 shows a typical FFT plot for the AD7924 at 1MSPS
sample rate and 50 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 1 MSPS
with an SCLK of 20 MHz.
input frequency for various supply voltages, while TPC 5 shows
a graph of total harmonic distortion versus analog input frequency
for various source impedances. See the Analog Input section.
TPC 6 and TPC 7 show typical INL and DNL plots for the
AD7924.
TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7924 when no decoupling is used.
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency f, to the power
of a 200 mV p-p sine wave applied to the ADC AVDD supply of
frequency fS:
0
V
= 5V,
DD
200mV p-p SINEWAVE ONV
REF = 2.5V, 1F CAPACITOR
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
IN
= 25؇C
T
A
PSRR(dB) = 10log(Pf / Pfs)
Pf is equal to the power at frequency f in ADC output; PfS is
equal to the power at frequency fS coupled onto the ADC
AVDD supply. Here a 200 mV p-p sine wave is coupled onto
the AVDD supply.
4096 POINT FFT
–10
V
= 5V
DD
f
= 1MSPS
SAMPLE
f
= 50kHz
IN
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY – kHz
–30
–50
SINAD = 71.147
THD = –87.229
SFDR = –90.744
TPC 3. AD7924 PSRR vs. Supply Ripple Frequency
–50
f
= 1MSPS
SAMPLE
–70
T
= 25؇C
A
–55
–60
–65
–70
–75
–80
–85
–90
RANGE = 0TO REF
IN
V
=V
= 2.7V
DRIVE
DD
–90
V
=V
= 3.6V
DRIVE
DD
–110
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – kHz
TPC 1. AD7924 Dynamic Performance at 1 MSPS
V
=V
= 4.75V
DRIVE
DD
75
V
=V
=V
= 5.25V
= 4.75V
DD
DRIVE
DRIVE
V
=V
= 5.25V
DRIVE
DD
V
DD
10
100
INPUT FREQUENCY – kHz
1000
70
65
60
55
TPC 4. AD7924 THD vs. Analog Input Frequency for
Various Supply Voltages at 1 MSPS
V
=V
= 3.6V
DRIVE
DD
–50
fSAMPLE = 1MSPS
T
= 25؇C
A
–55
–60
–65
–70
–75
–80
–85
–90
RANGE = 0TO REF
IN
V
= 5.25V
DD
f
T
= 1MSPS
= 25؇C
SAMPLE
V
=V
= 2.7V
DRIVE
DD
A
R
= 1000⍀
IN
RANGE = 0TO REF
IN
10
100
INPUT FREQUENCY – kHz
1000
R
= 100⍀
IN
R
= 50⍀
IN
TPC 2. AD7924 SINAD vs. Analog Input Frequency for
Various Supply Voltages at 1 MSPS
R
= 10⍀
IN
10
100
1000
INPUT FREQUENCY – kHz
TPC 5. AD7924 THD vs. Analog Input Frequency for
Various Source Impedances
–12–
REV. 0
AD7904/AD7914/AD7924
1.0
0.8
1.0
0.8
V
=V
= 5V
DRIVE
DD
V
=V
= 5V
DRIVE
TEMP = 25؇C
DD
TEMP = 25؇C
0.6
0.4
0.6
0.4
0.2
0
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
CODE
TPC 6. AD7924 Typical INL
TPC 7. AD7924 Typical DNL
CONTROL REGISTER
The Control Register on the AD7904/AD7914/AD7924 is a 12-bit, write-only register. Data is loaded from the DIN pin of the
AD7904/AD7914/AD7924 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conver-
sion result is read from the part. The data transferred on the DIN line corresponds to the AD7904/AD7914/AD7924 configuration
for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling
clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions
are outlined in Table I.
Table I. Control Register Bit Functions
MSB
WRITE
LSB
CODING
SEQ1 DONTC DONTC ADD1 ADD0
PM1
PM0 SEQ0
DONTC RANGE
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded
to the control register or not. If this bit is a 1 then the following 11 bits will be written to the control register; if it
is a 0 then the remaining 11 bits are not loaded to the control register and so it remains unchanged.
10
SEQ1
The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the use of the
sequencer function. (See Table IV.)
9–8
7–6
DONTCARE
ADD1, ADD0 These two address bits are loaded at the end of the present conversion sequence and select which analog
input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive
sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The
address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data,
see the Serial Interface section. The next channel to be converted on will be selected by the mux on the
fourteenth SCLK falling edge.
5, 4
3
PM1, PM0
Power Management Bits. These two bits decode the mode of operation of the AD7904/AD7914/AD7924
as shown in Table III.
SEQ0
The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the use of the
sequencer function. (See Table IV.)
2
1
DONTCARE
RANGE
This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0 then the
analog input range will extend from 0 V to 2 × REFIN. If it is set to 1 then the analog input range will extend
from 0 V to REFIN (for the next conversion). For 0 V to 2 × REFIN, VDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding the AD7904/AD7914/AD7924 will use for the conversion result.
If this bit is set to 0 the output coding for the part will be twos complement. If this bit is set to 1 then the
output coding from the part will be straight binary (for the next conversion).
REV. 0
–13–
AD7904/AD7914/AD7924
Table II. Channel Selection
Analog Input Channel
IN0
SEQUENCER OPERATION
The configuration of the SEQ1 and SEQ0 bits in the control
register allows the user to select a particular mode of operation
of the sequencer function. Table IV outlines the three modes of
operation of the Sequencer.
ADD1
ADD0
0
0
1
1
0
1
0
1
V
VIN
IN2
VIN
1
V
Figure 2 reflects the traditional operation of a multichannel ADC,
where each serial transfer selects the next channel for conversion.
In this mode of operation the Sequencer function is not used.
3
Table III. Power Mode Selection
PM1 PM0 Mode
Figure 3 shows how to program the AD7904/AD7914/AD7924
to continuously convert on a sequence of consecutive channels
from Channel 0 to a selected final channel. To exit this mode of
operation and revert back to the traditional mode of operation of a
multichannel ADC (as outlined in Figure 2), ensure that the
WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer.
1
1
1
Normal Operation. In this mode, the AD7904/
AD7914/AD7924 remain in full power mode
regardless of the status of any of the logicinputs.
This mode allows the fastest possible throughput
rate from the AD7904/AD7914/AD7924.
Table IV. Sequence Selection
SEQ1 SEQ0 Sequence Type
0
Full Shutdown. In this mode, the AD7904/
AD7914/AD7924 is in full shutdown mode with all
circuitry on the AD7904/AD7914/AD7924
powering down. The AD7904/AD7914/AD7924
retains the information in the Control Register
while in full shutdown. The part remains in full
shutdown until these bits are changed.
0
X
This configuration means that the sequence
function is not used. The analog input channel
selected for each individual conversion is
determined by the contents of the channel
address bits ADD1, ADD0 in each prior write
operation. This mode of operation reflects the
traditional operation of a multichannel ADC,
without the Sequencer function being used, where
each write to the AD7904/AD7914/AD7924
selects the next channel for conversion
(see Figure 2).
0
0
1
0
Auto Shutdown. In this mode, the AD7904/
AD7914/AD7924/ automatically enters full
shutdown mode at the end of each conversion
when the control register is updated. Wake-up
time from full shutdown is 1 µs and the user
should ensure that 1µs has elapsed before
attempting to perform a valid conversion on the
part in this mode.
1
1
0
1
If the SEQ1 and SEQ0 bits are set in this way
then the sequence function will not be interrupted
upon completion of the WRITE operation. This
allows other bits in the Control Register to be
altered between conversions while in a sequence
without terminating the cycle.
Invalid Selection. This configuration is not allowed.
This configuration is used in conjunction with
the channel address bits ADD1, ADD0 to
program continuous conversions on a consecutive
sequence of channels from Channel 0 to a selected
final channel as determined by the channel
address bits in the Control Register (see Figure 3).
–14–
REV. 0
AD7904/AD7914/AD7924
CIRCUIT INFORMATION
POWER ON
The AD7904/AD7914/AD7924 are high speed, 4-channel, 8-bit,
10-bit, and 12-bit, single supply, A/D converters, respectively.
The parts can be operated from a 2.7 V to 5.25 V supply. When
operated from either a 5 V or 3 V supply, the AD7904/AD7914/
AD7924 are capable of throughput rates of 1 MSPS when pro-
vided with a 20 MHz clock.
DUMMY CONVERSION
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
CS
The AD7904/AD7914/AD7924 provide the user with an on-chip
track/hold, A/D converter, and a serial interface housed in a
16-lead TSSOP package. The AD7904/AD7914/AD7924 each
have four single-ended input channels with a channel sequencer,
allowing the user to select a channel sequence through which the
ADC can cycle with each consecutive CS falling edge. The serial
clock input accesses data from the part, controls the transfer of
data written to the ADC, and provides the clock source for the
successive-approximation A/D converter. The analog input
range for the AD7904/AD7914/AD7924 is 0 V to REFIN or 0 V
to 2 × REFIN, depending on the status of Bit 1 in the Control
Register. For the 0 to 2 × REFIN range, the part must be operated
from a 4.75 V to 5.25 V supply.
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A1, A0
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
CS
WRITE BIT = 1,
SEQ1 = 0, SEQ0 = x
Figure 2. SEQ1 Bit = 0, SEQ0 Bit = x Flowchart
POWER ON
DUMMY CONVERSION
The AD7904/AD7914/AD7924 provide flexible power
management options to allow the user to achieve the best power
performance for a given throughput rate. These options are
selected by programming the Power Management bits, PM1
and PM0, in the Control Register.
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 1, SEQ0 = 1
CS
CONVERTER OPERATION
The AD7904/AD7914/AD7924 are 8-, 10-, and 12-bit successive
approximation analog-to-digital converters based around a
capacitive DAC, respectively. The AD7904/AD7914/AD7924
can convert analog input signals in the range 0 V to REFIN or 0 V
to 2 × REFIN. Figures 4 and 5 show simplified schematics of
the ADC. The ADC is comprised of Control Logic, SAR, and a
Capacitive DAC, which are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. Figure 4 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in position A.
The comparator is held in a balanced condition and the sampling
capacitor acquires the signal on the selected VIN channel.
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A1, A0 IN THE CONTROL REGISTER
CS
WRITE BIT = 0
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING, AND SO FORTH, TO CHANGE IN
THE CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ1 = 1, SEQ0 = 0
CS
WRITE BIT = 1,
SEQ1 = 1,
SEQ0 = 0
CAPACITIVE
DAC
Figure 3. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
A
4k⍀
V
0
IN
CONTROL
LOGIC
SW1
B
SW2
V
3
IN
COMPARATOR
AGND
Figure 4. ADC Acquisition Phase
REV. 0
–15–
AD7904/AD7914/AD7924
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to position B, causing the comparator
to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 7 and 8 show the ADC transfer functions.
ADC TRANSFER FUNCTION
The output coding of the AD7904/AD7914/AD7924 is either
straight binary or twos complement, depending on the status of
the LSB in the Control Register. The designed code transitions
occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on).
The LSB size is REFIN/256 for the AD7904 , REFIN/1024 for the
AD7914, and REFIN/4096 for the AD7924. The ideal transfer
characteristic for the AD7904/AD7914/AD7924 when straight
binary coding is selected is shown in Figure 7, and the ideal
transfer characteristic for the AD7904/AD7914/AD7924 when
twos complement coding is selected is shown in Figure 8.
CAPACITIVE
DAC
A
4k⍀
V
0
IN
CONTROL
LOGIC
SW1
.
•
3
•
B
111…111
111…110
SW2
.
V
IN
•
•
COMPARATOR
AGND
111…000
•
011…111
1LSB =V
1LSB =V
1LSB = V
/256 AD7904
/1024 AD7914
/4096 AD7924
REF
REF
REF
Figure 5. ADC Conversion Phase
•
•
Analog Input
000…010
000…001
000…000
Figure 6 shows an equivalent circuit of the analog input structure
of the AD7904/AD7914/AD7924. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 200 mV. This will cause these diodes
to become forward biased and start conducting current into the
substrate. 10 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. The
capacitor C1 in Figure 6 is typically about 4 pF and can primarily
be attributed to pin capacitance. The resistor R1 is a lumped com-
ponent made up of the on resistance of a switch (track and hold
switch) and also includes the on resistance of the input multiplexer.
The total resistance is typically about 400 Ω. The capacitor C2 is
the ADC sampling capacitor and has a capacitance of 30 pF
typically. For ac applications, removing high frequency compo-
nents from the analog input signal is recommended by use of an
RC low-pass filter on the relevant analog input pin. In applica-
tions where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances will significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a
function of the particular application.
1 LSB
+V
؊ 1 LSB
REF
0V
ANALOG INPUT
NOTE:V
IS EITHER REF OR 2
؋
REF IN
IN
REF
Figure 7. Straight Binary Transfer Characteristic
011…111
011…110
•
•
000…001
000…000
111…111
•
•
1LSB = 2
؋
V 1LSB = 2
؋
V 1LSB = 2
؋
V ր256 AD7904
ր1024 AD7914
ր4096 AD7924
REF
REF
REF
100…010
100…001
100…000
–V
؉ 1LSB
+V
REF
؊ 1LSB
REF
V
REF
؊ 1LSB
ANALOG INPUT
Figure 8. Twos Complement Transfer Characteristic with
REFIN REFIN Input Range
Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2 × REFIN
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal is
biased about REFIN and twos complement output coding is
selected, then REFIN becomes the zero code point, –REFIN is
negative full scale and +REFIN becomes positive full scale, with
a dynamic range of 2 × REFIN.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade
(see TPC 5).
V
DD
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7904/
AD7914/AD7924. In this setup the GND pin is connected to
the analog ground plane of the system. In Figure 10, REFIN is
connected to a decoupled 2.5 V supply from a reference source,
the AD780, to provide an analog input range of 0 V to 2.5 V (if
RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although
the AD7904/AD7914/AD7924 is connected to a VDD of 5 V, the
serial interface is connected to a 3 V microprocessor. The VDRIVE
pin of the AD7904/AD7914/AD7924 is connected to the same 3 V
supply of the microprocessor to allow a 3 V logic interface (see
the Digital Inputs section). The conversion result is output in a
C2
D1
30pF
R1
V
IN
C1
4pF
D2
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
Figure 6. Equivalent Analog Input Circuit
–16–
REV. 0
AD7904/AD7914/AD7924
V
DD
V
REF
0.1F
V
DD
REF
IN
V
DD
V
DRIVE
AD7904/
AD7914/
AD7924
R4
R1
DSP/P
V
R3
R2
TWOS
COMPLEMENT
V
0
DOUT
IN
V
0V
011…111
000…000
100…000
(= 2
؋
REF )
IN
+REF
IN
V
3
IN
R1
؍
R2 ؍
R3 ؍
R4 REF
IN
(= 0V)
–REF
IN
Figure 9. Handling Bipolar Signals
16-bit word. This 16-bit data stream consists of two leading
zeros, two address bits indicating which channel the conversion
result corresponds to, followed by the 12 bits of conversion data
for the AD7924 (10 bits of data for the AD7914 and 8 bits of data
for the AD7904, each followed by 2 and 4 trailing zeros, respec-
tively). For applications where power consumption is of concern,
the power-down modes should be used between conversions or
bursts of several conversions to improve power performance.
See the Modes of Operation section of the data sheet.
It is not necessary to write to the Control Register again once a
sequencer operation has been initiated. The WRITE bit must be
set to zero or the DIN line tied low to ensure the Control Regis-
ter is not accidently overwritten, or the sequence operation
interrupted. If the Control Register is written to at any time
during the sequence then it must be ensured that the SEQ1 and
SEQ0 bits are set to 1,0 to avoid interrupting the automatic
conversion sequence. This pattern will continue until such time
as the AD7904/AD7914/AD7924 is written to and the SEQ1
and SEQ0 bits are configured with any bit combination except
1,0 resulting in the termination of the sequence. If uninter-
rupted, however (WRITE bit = 0, or WRITE bit = 1 and SEQ1
and SEQ0 bits are set to 1,0), then upon completion of the
sequence, the AD7904/AD7914/AD7924 sequencer will return
to the Channel 0 and commence the sequence again.
5V
SUPPLY
0.1F
10F
SERIAL
INTERFACE
V
DD
V
0
SCLK
DOUT
CS
IN
AD7904/
AD7914/
AD7924
0VTO REF
IN
C/P
Regardless of which channel selection method is used, the 16-bit
word output from the AD7924 during each conversion will always
contain two leading zeros, two channel address bits that the con-
version result corresponds to, followed by the 12-bit conversion
result; the AD7914 will output two leading zeros, two channel
address bits that the conversion result corresponds to, followed by
the 10-bit conversion result and two trailing zeros; the AD7904 will
output two leading zeros, two channel address bits that the conver-
sion result corresponds to, followed by the 8-bit conversion result
and four trailing zeros. See the Serial Interface section.
V
3
IN
AGND
DIN
REF
V
IN
DRIVE
0.1F
10F
0.1F
2.5V
AD780
3V
SUPPLY
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTEDTO AGND
Figure 10. Typical Connection Diagram
Analog Input Selection
Digital Inputs
Any one of four analog input channels may be selected for con-
version by programming the multiplexer with the address bits
ADD1 and ADD0 in the Control Register. The channel con-
figurations are shown in Table II.
The digital inputs applied to the AD7904/AD7914/AD7924 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog inputs.
The AD7904/AD7914/AD7924 may also be configured to auto-
matically cycle through a number of channels as selected. The
sequencer feature is accessed via the SEQ1 and SEQ0 bits in the
Control Register, see Table IV. The AD7904/AD7914/AD7924
can be programmed to continuously convert on a number of
consecutive channels in ascending order from Channel 0 to a
selected final channel as determined by the channel address bits
ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 bits
are set to 1,1. The next serial transfer will then act on the sequence
programmed by executing a conversion on Channel 0. The next
serial transfer will result in a conversion on Channel 1, and so
on, until the channel selected via the address bits ADD1, ADD0
is reached.
Another advantage of SCLK, DIN, and CS not being restricted
by the VDD + 0.3 V limit is the fact that power supply sequenc-
ing issues are avoided. If CS, DIN, or SCLK are applied before
VDD there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to VDD
.
VDRIVE
The AD7904/AD7914/AD7924 also have the VDRIVE feature.
VDRIVE controls the voltage at which the serial interface oper-
ates. VDRIVE allows the ADC to easily interface to both 3 V and
5 V processors. For example, if the AD7904/AD7914/AD7924
were operated with a VDD of 5 V, the VDRIVE pin could be pow-
ered from a 3 V supply. The AD7904/AD7914/AD7924 have
REV. 0
–17–
AD7904/AD7914/AD7924
better dynamic performance with a VDD of 5 V while still being
able to interface to 3 V processors. Care should be taken to
ensure VDRIVE does not exceed VDD by more than 0.3 V. (See
the Absolute Maximum Ratings section).
CS
SCLK
DOUT
1
16
12
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7904/AD7914/AD7924. Errors in the refer-
ence source will result in gain errors in the AD7904/AD7914/
AD7924 transfer function and will add to the specified full-scale
errors of the part. A capacitor of at least 0.1 µF should be placed
on the REFIN pin. Suitable reference sources for the AD7904/
AD7914/AD7924 include the AD780, REF 193, and the AD1582.
DIN
DATA INTO CONTROL REGISTER
NOTE: CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
Figure 11. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7904/AD7914/
AD7924 is powered down. The part retains information in the
Control Register during full shutdown. The AD7904/AD7914/
AD7924 remains in full shutdown until the power management
bits in the Control Register, PM1 and PM0, are changed.
If 2.5 V is applied to the REFIN pin, the analog input range can
either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.
MODES OF OPERATION
If a write to the Control Register occurs while the part is in Full
Shutdown, with the power management bits changed to PM0 =
PM1 = 1, Normal mode, the part will begin to power up on the
CS rising edge. The track and hold that was in hold while the
part was in Full Shutdown will return to track on the fourteenth
SCLK falling edge.
The AD7904/AD7914/AD7924 have a number of different
modes of operation. These modes are designed to provide flex-
ible power management options. These options can be chosen
to optimize the power dissipation/throughput rate ratio for dif-
fering application requirements. The mode of operation of the
AD7904/AD7914/AD7924 is controlled by the power manage-
ment bits, PM1 and PM0, in the Control Register, as detailed in
Table III. When power supplies are first applied to the AD7904/
AD7914/AD7924, care should be taken to ensure that the part
is placed in the required mode of operation (see the Powering
Up the AD7904/AD7914/AD7924 section).
To ensure that the part is fully powered up, tPOWER UP (t12) should
have elapsed before the next CS falling edge. Figure 12 shows
the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7904/AD7914/AD7924 automatically enters
shutdown at the end of each conversion when the control register
is updated. When the part is in shutdown, the track and hold is in
hold mode. Figure 13 shows the general diagram of the operation
of the AD7904/AD7914/AD7924 in this mode. In shutdown mode
all internal circuitry on the AD7904/AD7914/AD7924 is
powered down. The part retains information in the Control
Register during shutdown. The AD7904/AD7914/AD7924
remains in shutdown until the next CS falling edge it receives.
On this CS falling edge the track and hold that was in hold while
the part was in shutdown will return to track. Wake-up time
from auto shutdown is 1 µs maximum, and the user should
ensure that 1 µs has elapsed before attempting a valid conver-
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate performance
as the user does not have to worry about any power-up times
with the AD7904/AD7914/AD7924 remaining fully powered at
all times. Figure 11 shows the general diagram of the operation
of the AD7904/AD7914/AD7924 in this mode.
The conversion is initiated on the falling edge of CS and the track
and hold will enter hold mode as described in the Serial Interface
section. The data presented to the AD7904/AD7914/AD7924 on
the DIN line during the first 12 clock cycles of the data transfer
are loaded into the Control Register (provided WRITE bit is set
to 1). The part will remain fully powered up in normal mode at
the end of the conversion as long as PM1 and PM0 are set to 1
in the write transfer during that same conversion. To ensure
continued operation in Normal Mode, PM1 and PM0 must both
be loaded with 1 on every data transfer, assuming a write opera-
tion is taking place. If the WRITE bit is set to 0, then the power
management bits will be left unchanged and the part will remain
in Normal Mode.
sion. When running the AD7904/AD7914/AD7924 with
a
20 MHz clock, one 16 SCLK dummy cycle should be sufficient
to ensure the part is fully powered up. During this dummy cycle
the contents of the Control Register should remain unchanged,
therefore the WRITE bit should be 0 on the DIN line. This
dummy cycle effectively halves the throughput rate of the part,
with every other conversion result being valid. In this mode the
power consumption of the part is greatly reduced with the part
entering shutdown at the end of each conversion. When the
Control Register is programmed to move into auto shutdown, it
does so at the end of the conversion. The user can move the ADC
in and out of the low power state by controlling the CS signal.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. The track and hold will go
back into track on the fourteenth SCLK falling edge. CS may
then idle high until the next conversion or may idle low until
sometime prior to the next conversion, (effectively idling CS low).
Once a data transfer is complete (DOUT has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET, has elapsed by bringing CS low again.
–18–
REV. 0
AD7904/AD7914/AD7924
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
PART IS IN FULL
SHUTDOWN
PART BEGINSTO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
t12
CS
1
14
16
1
14
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 12. Full Shutdown Mode Operation
PART ENTERS
PART ENTERS
SHUTDOWN ON CS TO POWER
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 PART BEGINS
SHUTDOWN ON CS
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 PART IS FULLY
POWERED UP
UP ON CS
FALLING EDGE
CS
DUMMY CONVERSION
12
1
12
16
1
16
1
12
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS, PM1
؍
0, PM0 ؍
1 CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE,WRITE BIT
؍
0 TO KEEP PART INTHIS MODE, LOAD PM1
؍
0, PM0 ؍
1 IN CONTROL REGISTER OR SETWRITE BIT = 0
Figure 13. Auto Shutdown Mode Operation
Powering Up the AD7904/AD7914/AD7924
If the desired mode of operation is Auto Shutdown after sup-
plies are applied, then two dummy cycles will be required, the
first with DIN tied high and the second dummy cycle to set the
power management bits PM1 and PM0 = 0,1. On the second
CS rising edge after the supplies are applied, the Control Regis-
ter will contain the correct information and the part will enter
Auto Shutdown mode as programmed. If power consumption is
of critical concern, then in the first dummy cycle the user may
set PM1, PM0 = 1,0, i.e., Full Shutdown, and then place the
part into Auto Shutdown in the second dummy cycle. For illus-
tration purposes, Figure 14c is shown with DIN tied high on the
first dummy cycle in this case.
When supplies are first applied to the AD7904/AD7914/AD7924,
the ADC may power up in any of the operating modes of the
part. To ensure the part is placed into the required operating
mode the user should perform a dummy cycle operation as
outlined in Figures 14a through 14c.
The dummy conversion operation must be performed to place the
part into the desired mode of operation. To ensure the part is in
normal mode, this dummy cycle operation can be performed with
the DIN line tied HIGH, i.e., PM1, PM0 = 1,1 (depending on
other required settings in the control register) but the minimum
power-up time of 1 µs must be allowed from the rising edge
of CS, where the control register is updated, before attempting
the first valid conversion. This is to allow for the possibility that
the part initially powered up in shutdown. If the desired mode
of operation is Full Shutdown, then again only one dummy cycle
is required after supplies are applied. In this dummy cycle the
user simply sets the power management bits, PM1, PM0 = 1,0
and upon the rising edge of CS at the end of that serial transfer
the part will enter full shutdown.
Figures 14a, 14b, and 14c each show the required dummy cycle(s)
after supplies are applied in the case of Normal mode, Full
Shutdown mode, or Auto Shutdown mode, respectively, being
the desired mode of operation.
REV. 0
–19–
AD7904/AD7914/AD7924
PART IS IN
IF IN SHUTDOWN AT POWER-ON,
PART BEGINSTO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
UNKNOWN MODE
AFTER POWER-ON
ALLOW tPOWER TO ELAPSE
t12
CS
1
14
16
1
14
16
SCLK
DOUT
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 14a. To Place AD7904/AD7914/AD7924 into Normal Mode after Supplies are First Applied
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = PM0 = 0
CS
1
14
16
SCLK
DOUT
DIN
INVALID DATA
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON
THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
Figure 14b. To Place AD7904/AD7914/AD7924 into Full Shutdown Mode after Supplies are First Applied
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
PART ENTERS AUTO SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
CS
1
14
16
1
14
16
SCLK
DOUT
DIN
INVALID DATA
INVALID DATA
DATA INTO CONTROL REGISTER
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
Figure 14c. To Place AD7904/AD7914/AD7924 into Auto Shutdown Mode after Supplies are First Applied
POWER VERSUS THROUGHPUT RATE
The maximum power dissipation during normal operation is
13.5 mW (VDD = 5 V). If the power-up time from Auto Shutdown
is one dummy cycle, i.e., 1 µs, and the remaining conversion time is
another cycle, i.e., 1 µs, then the AD7924 can be said to dissipate
13.5 mW for 2 µs during each conversion cycle. For the remainder
of the conversion cycle, 8 µs, the part remains in shutdown.
The AD7924 can be said to dissipate 2.5 µW for the remaining 8 µs of
the conversion cycle. If the throughput rate is 100 kSPS, the cycle
time is 10 µs and the average power dissipated during each cycle is
(2/10) × (13.5 mW) + (8/10) ×(2.5 µW) = 2.702 mW.
By operating in Auto Shutdown mode on the AD7904/AD7914/
AD7924, the average power consumption of the ADC decreases
at lower throughput rates. Figure 15 shows how as the through-
put rate is reduced, the part remains in its shutdown state longer
and the average power consumption over time drops accordingly.
For example, if the AD7924 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and an SCLK
of 20 MHz (VDD = 5 V), and the device is placed in Auto Shut-
down mode, i.e., if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
–20–
REV. 0
AD7904/AD7914/AD7924
Figure 15 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 5 V and 3 V supplies.
SERIAL INTERFACE
Figures 16, 17, and 18 show the detailed timing diagrams for
serial interfacing to the AD7904, AD7914, and AD7924,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7904/AD7914/AD7924 during each conversion.
10
V
= 5V
DD
V
= 3V
DD
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track and hold
will go back into track on the fourteenth SCLK falling edge as
shown in Figures 16, 17, and 18 at Point B. On the sixteenth
SCLK falling edge, the DOUT line will go back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion will be terminated, the DOUT line will go back
into three-state, and the Control Register will not be updated;
otherwise DOUT returns to three-state on the sixteenth SCLK
falling edge as shown in Figures 16, 17, and 18.
1
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT – kSPS
Figure 15. AD7924 Power vs. Throughput Rate
CS
tCONVERT
t2
t3
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
SCLK
t11
t7
t4
t8
tQUIET
ZERO
t9
ADD1
ADD0
DB7
DB6
DB0
ZERO
ZERO
ZERO
ZERO
DOUT
DIN
THREE-
STATE
THREE-
STATE
2 IDENTIFICATION
BITS
4TRAILING ZEROS
ZERO
t10
WRITE SEQ1
DONTC DONTC
ADD1
ADD0
CODING DONTC DONTC
DONTC
DONTC
Figure 16. AD7904 Serial Interface Timing Diagram
CS
tCONVERT
t2
t3
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
SCLK
t11
t7
t4
t8
tQUIET
ZERO
t9
ADD1
ADD0
DB9
DB8
DB2
DB1
DB0
ZERO
ZERO
DOUT
DIN
THREE-
STATE
THREE-
STATE
2 IDENTIFICATION
BITS
2TRAILING ZEROS
ZERO
t10
WRITE SEQ1
DONTC DONTC
ADD1
ADD0
CODING DONTC DONTC
DONTC
DONTC
Figure 17. AD7914 Serial Interface Timing Diagram
CS
tCONVERT
t2
t3
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
SCLK
t11
t7
t4
t8
tQUIET
ZERO
t9
ADD1
ADD0
DB11
DB10
DB4
DB3
DB2
DB1
DB0
DOUT
DIN
THREE-
STATE
THREE-
STATE
2 IDENTIFICATION
BITS
ZERO
t10
WRITE SEQ1
DONTC DONTC
ADD1
ADD0
CODING DONTC DONTC
DONTC
DONTC
Figure 18. AD7924 Serial Interface Timing Diagram
–21–
REV. 0
AD7904/AD7914/AD7924
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7904/AD7914/AD7924.
For the AD7904/AD7914/AD7924 the 8/10/12 bits of data are
preceded by two leading zeros and two channel address bits ADD1
and ADD0, identifying which channel the result corresponds to.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP on the first falling edge of SCLK.
The first falling edge of SCLK will also clock out the second
leading zero to be read in by the microcontroller or DSP on the
second SCLK falling edge, and so on. The remaining two address
bits and 8/10/12 data bits are then clocked out by subsequent
SCLK falling edges beginning with the first address bit ADD1;
thus the second falling clock edge on the serial clock has the
second leading zero provided and also clocks out address bit
ADD1. The final bit in the data transfer is valid on the sixteenth falling
edge, having been clocked out on the previous (fifteenth) falling edge.
TMS320C541*
AD7904/
AD7914/
AD7924
*
CLKX
SCLK
CLKR
DR
DOUT
DIN
DT
FSX
FSR
CS
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
V
DD
Figure 19. Interfacing to the TMS320C541
AD7904/AD7914/AD7924 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7904/AD7914/AD7924 without any glue logic required. The
DRIVE pin of the AD7904/AD7914/AD7924 takes the same
supply voltage as that of the ADSP-218x. This allows the
ADC to operate at a higher voltage than the serial interface,
i.e., ADSP-218x, if necessary.
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, i.e., the WRITE bit, has been set to 1.
V
The AD7904 will output two leading zeros, two channel address
bits that the conversion result corresponds to, followed by the 8-bit
conversion result, and four trailing zeros. The AD7914 will
output two leading zeros, two channel address bits that the
conversion result corresponds to, followed by the 10-bit conver-
sion result, and two trailing zeros. The 16-bit word read from
the AD7924 will always contain two leading zeros, two channel
address bits that the conversion result corresponds to, followed
by the 12-bit conversion result.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
MICROPROCESSOR INTERFACING
ITFS = 1
The serial interface on the AD7904/AD7914/AD7924 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7904/AD7914/AD7924 with some of the more common
microcontroller and DSP serial interface protocols.
The connection diagram is shown in Figure 20. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
Alternate Framing Mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC, and under certain conditions equidistant sampling may
not be achieved.
AD7904/AD7914/AD7924 to TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7904/AD7914/AD7924. The CS input allows easy inter-
facing between the TMS320C541 and the AD7904/AD7914/
AD7924 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode with
internal CLKX0 (TX serial clock on serial port 0) and FSX0
(TX frame sync from serial port 0). The serial port control
register (SPC) must have the following setup: FO = 0, FSM
= 1, MCM = 1, and TXM = 1. The connection diagram is
shown in Figure 19. It should be noted that for signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provides equidistant sampling.
The VDRIVE pin of the AD7904/AD7914/AD7924 takes the
same supply voltage as that of the TMS320C541. This allows
the ADC to operate at a higher voltage than the serial inter-
face, i.e., TMS320C541, if necessary.
The Timer register, and so on, are loaded with a value that
will provide an interrupt at the required sample interval. When
an interrupt is received, a value is transmitted with TFS/DT
(ADC control word). The TFS is used to control the RFS and
thus the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low, and
High before transmission will start. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master
cycle time would be 25 ns. If the SCLKDIV register is loaded with
the value 3, then a SCLK of 5 MHz is obtained and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the timer register was loaded
with the value, say 803 (803 + 1 = 804), then 100.5 SCLKs will
occur between interrupts and subsequently between transmit
–22–
REV. 0
AD7904/AD7914/AD7924
instructions. This situation will result in nonequidistant sam-
pling as the transmit instruction is occurring on a SCLK edge. If
the number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
The printed circuit board that houses the AD7904/AD7914/
AD7924 should be designed such that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be
separated easily. A minimum etch technique is generally best
for ground planes as it gives the best shielding. All three
AGND pins of the AD7904/AD7914/AD7924 should be sunk
in the AGND plane. Digital and analog ground planes should
be joined at only one place. If the AD7904/AD7914/AD7924
is in a system where multiple devices require an AGND to
DGND connection, the connection should still be made at
one point only, a star ground point that should be established
as close as possible to the AD7904/AD7914/AD7924.
ADSP-218x*
AD7904/
AD7914/
AD7924*
SCLK
SCLK
DOUT
DR
CS
RFS
TFS
DT
DIN
V
DRIVE
Avoid running digital lines under the device as these will
couple noise onto the die. The analog ground plane should
be allowed to run under the AD7904/AD7914/AD7924 to
avoid noise coupling. The power supply lines to the AD7904/
AD7914/AD7924 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, like clocks,
should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digi-
tal and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique is
by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes while signals are placed on the
solder side.
*ADDITIONAL PINS REMOVED FOR CLARITY
V
DD
Figure 20. Interfacing to the ADSP-218x
AD7904/AD7914/AD7924 to DSP563xx
The connection diagram in Figure 21 shows how the
AD7904/AD7914/AD7924 can be connected to the ESSI
(Synchronous Serial Interface) of the DSP563xx family of DSPs
from Motorola. Each ESSI (two on board) is operated in
Synchronous Mode (SYN bit in CRB = 1) with internally
generated 1-bit clock period frame sync for both Tx and Rx (bits
FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI
is selected by making MOD = 0 in the CRB. Set the word length
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit
in the CRB should be set to 1 so the frame sync is negative. It
should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the DSP563xx
provides equidistant sampling.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum in parallel with 0.1 µF
capacitors to AGND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device, ideally right up against the device. The 0.1 µF capacitors
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types or
surface mount types, which provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
In the example shown in Figure 21 below, the serial clock is
taken from the ESSI so the SCK0 pin must be set as an output,
SCKD = 1. The VDRIVE pin of the AD7904/AD7914/AD7924
takes the same supply voltage as that of the DSP563xx. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., DSP563xx, if necessary.
DSP563xx*
AD7904/
AD7914/
Evaluating the AD7904/AD7914/AD7924 Performance
The recommended layout for the AD7904/AD7914/AD7924 is
outlined in the evaluation board for the AD7904/AD7914/AD7924.
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-BOARD
CONTROLLER. The EVAL-BOARD CONTROLLER can be
used in conjunction with the AD7904/AD7914/AD7924
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7904/AD7914/AD7924.
AD7924
*
SCK
SCLK
SRD
DOUT
STD
SC2
CS
DIN
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
V
DD
Figure 21. Interfacing to the DSP563xx
APPLICATION HINTS
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7904/AD7914/
AD7924. The software and documentation are on a CD shipped
with the evaluation board.
Grounding and Layout
The AD7904/AD7914/AD7924 have very good immunity to
noise on the power supplies as can be seen by the PSRR vs.
Supply Ripple Frequency plot, TPC 3. However, care should
still be taken with regard to grounding and layout.
REV. 0
–23–
AD7904/AD7914/AD7924
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8؇
0؇
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
–24–
REV. 0
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