AD7928BRU-REEL7 [ADI]
8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP; 8通道， 1 MSPS ， 8位/ 10位/ 12位ADC，定序器采用20引脚TSSOP
| 型号： | AD7928BRU-REEL7 |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
| 文件： | 总24页 (文件大小：574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs
with Sequencer in 20-Lead TSSOP
AD7908/AD7918/AD7928
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 1 MSPS
Specified for AVDD of 2.7 V to 5.25 V
Low Power:
6.0 mW Max at 1 MSPS with 3 V Supply
13.5 mW Max at 1 MSPS with 5 V Supply
8 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
AV
DD
REF
IN
V
0
IN
T/H
•
•
•
•
•
•
•
•
•
•
•
•
•
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7928, 70 dB Min SINAD at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
I/P
MUX
High Speed Serial Interface SPI®/QSPI™/
MICROWIRE™/DSP Compatible
Shutdown Mode: 0.5 A Max
V
7
20-Lead TSSOP Package
IN
SCLK
DOUT
DIN
CONTROL LOGIC
SEQUENCER
GENERAL DESCRIPTION
The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit,
and 12-bit, high speed, low power, 8-channel, successive
approximation ADCs. The parts operate from a single 2.7 V
to 5.25 V power supply and feature throughput rates up to
1 MSPS. The parts contain a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 8 MHz.
CS
AD7908/AD7918/AD7928
V
DRIVE
GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The conversion process and data acquisition are controlled using
CS and the serial clock signal, allowing the device to easily inter-
face with microprocessors or DSPs. The input signal is sampled
on the falling edge of CS and conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7908/AD7918/AD7928 offer up to 1 MSPS throughput
rates. At the maximum throughput rate with 3 V supplies, the
AD7908/AD7918/AD7928 dissipate just 6 mW of power
maximum.
The AD7908/AD7918/AD7928 use advanced design techniques to
achieve very low power dissipation at maximum throughput rates.
At maximum throughput rates, the AD7908/AD7918/AD7928
consume 2 mA maximum with 3 V supplies; with 5 V supplies, the
current consumption is 2.7 mA maximum.
2. Eight Single-Ended Inputs with a Channel Sequencer.
A sequence of channels can be selected, through which the
ADC will cycle and convert on.
3. Single-Supply Operation with VDRIVE Function.
The AD7908/AD7918/AD7928 operate from a single 2.7 V to
5.25 V supply. The VDRIVE function allows the serial interface
to connect directly to either 3 V or 5 V processor systems
Through the configuration of the Control Register, the analog
input range for the part can be selected as 0 V to REFIN or 0 V to
2 ϫ REFIN, with either straight binary or twos complement out-
put coding. The AD7908/AD7918/AD7928 each feature eight
single-ended analog inputs with a channel sequencer to allow a
preprogrammed selection of channels to be converted sequentially.
independent of AVDD
.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The parts also feature various shutdown
modes to maximize power efficiency at lower throughput rates.
Current consumption is 0.5 µA max when in full shutdown.
The conversion time for the AD7908/AD7918/AD7928 is deter-
mined by the SCLK frequency, which is also used as the master
clock to control the conversion.
5. No Pipeline Delay.
The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD7908/AD7918/AD7928
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
AD7908–SPECIFICATIONS otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise
(SFDR)2
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
49
49
–66
dB min
dB min
dB max
–64
dB max
Intermodulation Distortion (IMD)2
Second Order Terms
fa = 40.1 kHz, fb = 41.5 kHz
–90
–90
10
dB typ
dB typ
ns typ
Third Order Terms
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
8
Bits
LSB max
LSB max
0.2
0.2
Guaranteed No Missed Codes to 8 Bits
Straight Binary Output Coding
0.5
0.05
0.2
LSB max
LSB max
LSB max
LSB max
Offset Error Match
Gain Error
Gain Error Match
0.05
0 V to 2 ϫ REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
0.2
0.05
0.5
0.1
0.2
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
0.05
ANALOG INPUT
Input Voltage Ranges
0 to REFIN
V
RANGE Bit Set to 1
0 to 2 ϫ REFIN
1
20
V
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
µA max
pF typ
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1ꢀ Specified Performance
fSAMPLE = 1 MSPS
µA max
k⍀ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 ϫ VDRIVE
0.3 ϫ VDRIVE
1
10
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
V min
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
MSPS max See Serial Interface Section
–2–
REV. A
AD7908/AD7918/AD7928
Parameter
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
AVDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK On or Off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Normal Mode (Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
mA max
mA max
µA typ
µA max
µA max
Using Auto Shutdown Mode
(Static)
SCLK On or Off (20 nA typ)
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
AVDD = 3 V
NOTES
1Temperature ranges as follows: B Version: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–3–
AD7908/AD7918/AD7928
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
otherwise noted.)
AD7918–SPECIFICATIONS
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 50 kHz Sine Wave, fSCLK = 20 MHz
Signal-to-(Noise + Distortion) (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise
(SFDR)2
61
61
–72
dB min
dB min
dB max
–74
dB max
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
fa = 40.1 kHz, fb = 41.5 kHz
–90
–90
10
dB typ
dB typ
ns typ
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
10
0.5
0.5
Bits
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
Straight Binary Output Coding
2
LSB max
LSB max
LSB max
LSB max
Offset Error Match
Gain Error
Gain Error Match
0.2
0.5
0.2
0 V to 2 ϫ REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
0.5
0.2
2
0.2
0.5
0.2
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to REFIN
V
RANGE Bit Set to 1
0 to 2 ϫ REFIN
1
20
V
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
µA max
pF typ
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1ꢀ Specified Performance
fSAMPLE = 1 MSPS
µA max
k⍀ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 ϫ VDRIVE
0.3 ϫ VDRIVE
1
10
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
V min
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
MSPS max See Serial Interface Section
–4–
REV. A
AD7908/AD7918/AD7928
Parameter
B Version1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
AVDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK On or Off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Normal Mode (Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
mA max
mA max
µA typ
µA max
µA max
Using Auto Shutdown Mode
(Static)
SCLK On or Off (20 nA typ)
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
AVDD = 3 V
NOTES
1Temperature ranges as follows: B Version: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–5–
REV. A
AD7908/AD7918/AD7928
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
AD7928–SPECIFICATIONS otherwise noted.)
Parameter
B Version2
Unit
Test Conditions/Comments
IN = 50 kHz Sine Wave, fSCLK = 20 MHz
@ 5 V
DYNAMIC PERFORMANCE
f
Signal-to-(Noise + Distortion) (SINAD)2
70
69
70
–77
–73
–78
–76
dB min
dB min
dB min
dB max
dB max
dB max
dB max
@ 3 V Typically 70 dB
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
@ 5 V Typically –84 dB
@ 3 V Typically –77 dB
@ 5 V Typically –86 dB
@ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz
Peak Harmonic or Spurious Noise
(SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
–90
–90
10
dB typ
dB typ
ns typ
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–85
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
12
Bits
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
1
LSB max
LSB max
–0.9/+1.5
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Typically 0.5 LSB
8
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Gain Error Match
0 V to 2 ϫ REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
1.5
0.5
8
0.5
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Typically 0.8 LSB
0.5
ANALOG INPUT
Input Voltage Ranges
0 to REFIN
0 to 2 ϫ REFIN
V
V
RANGE Bit Set to 1
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
1
20
µA max
pF typ
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
1
36
V
1ꢀ Specified Performance
fSAMPLE = 1 MSPS
µA max
k⍀ typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 ϫ VDRIVE
0.3 ϫ VDRIVE
1
10
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
0.4
1
V min
ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
–6–
REV. A
AD7908/AD7918/AD7928
Parameter
B Version1
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
300
1
ns max
ns max
ns max
MSPS max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
See Serial Interface Section
POWER REQUIREMENTS
AVDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK On or Off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
(Static)
SCLK On or Off (20 nA typ)
Normal Mode (Static)
Normal Mode (Operational)
600
2.7
2
960
0.5
0.5
µA typ
mA max
mA max
µA typ
µA max
µA max
Using Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational)
13.5
6
2.5
1.5
2.5
1.5
mW max
mW max
µW max
µW max
µW max
µW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
Auto Shutdown Mode (Static)
Full Shutdown Mode
AVDD = 3 V
NOTES
1Temperature ranges as follows: B Version: –40°C to +85°C.
2See Terminology section.
3Sample tested @ 25°C to ensure compliance.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
REV. A
–7–
AD7908/AD7918/AD7928
TIMING SPECIFICATIONS1 (AVDD = 2.7 V to 5.25 V, VDRIVE < AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX AD7908/AD7918/AD7928
Parameter
AVDD = 3 V
AVDD = 5 V
Unit
Description
2
fSCLK
10
10
kHz min
20
20
MHz max
tCONVERT
tQUIET
16 ϫ tSCLK
50
16 ϫ tSCLK
50
ns min
Minimum Quiet Time Required between CS Rising Edge
and Start of Next Conversion
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto Shutdown Mode
t23
t33
t4
t5
t6
10
35
40
10
30
40
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs max
0.4 ϫ tSCLK
0.4 ϫ tSCLK
0.4 ϫ tSCLK
0.4 ϫ tSCLK
t74
10
15/45
10
5
20
1
10
15/35
10
5
20
1
t8
t9
t10
t11
t12
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of AVDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ϫ VDRIVE
.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
I
200A
OL
TO
OUTPUT
PIN
1.6V
C
50pF
L
I
200A
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. A
–8–
AD7908/AD7918/AD7928
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
JA Thermal Impedance . . . . . . . . . . . . . 143°C/W (TSSOP)
JC Thermal Impedance . . . . . . . . . . . . . . 45°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
q
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
q
NOTES
Input Current to Any Pin Except Supplies2 . . . . . . . .
Operating Temperature Range
10 mA
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option
Package
Description
Model
Error (LSB)1
AD7908BRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Ϯ0.2
Ϯ0.2
Ϯ0.2
Ϯ0.5
Ϯ0.5
Ϯ0.5
Ϯ1
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
AD7908BRU-REEL
AD7908BRU-REEL7
AD7918BRU
AD7918BRU-REEL
AD7918BRU-REEL7
AD7928BRU
AD7928BRU-REEL
AD7928BRU-REEL7
EVAL-AD79x8CB2
EVAL-CONTROL BRD3
Ϯ1
Ϯ1
TSSOP
Evaluation Board
Controller Board
NOTES
1Linearity error here refers to integral linearity error.
2This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.
The board comes with one chip of each the AD7908, AD7918, and AD7928.
3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
To order a complete evaluation kit, order the particular ADC evaluation board, e.g., EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a
12 V ac transformer. See relevant Evaluation Board Technical Note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7908/AD7918/AD7928 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. A
–9–
AD7908/AD7918/AD7928
PIN CONFIGURATION
20-Lead TSSOP
SCLK
DIN
1
2
20 AGND
19
V
DRIVE
3
18 DOUT
17 AGND
CS
AD7908/
AD7918/
AD7928
AGND
4
AV
AV
5
16
15
14
13
12
11
V 0
IN
DD
DD
TOP VIEW
(Not to Scale)
6
V 1
IN
REF
IN
7
V 2
IN
AGND
8
V 3
IN
V
7
9
V 4
IN
IN
V
6
10
V 5
IN
IN
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7908/AD7918/AD7928’s conversion process.
2
3
DIN
Data In. Logic input. Data to be written to the AD7908/AD7918/AD7928’s Control Register is provided on
this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7908/AD7918/AD7928, and also frames the serial data transfer.
CS
4, 8, 17, 20 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7908/AD7918/AD7928.
All analog input signals and any external reference signal should be referred to this AGND voltage.
All AGND pins should be connected together.
5, 6
7
AVDD
Analog Power Supply Input. The AVDD range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V.
For the 0 V to 2 ϫ REFIN range, AVDD should be from 4.75 V to 5.25 V.
Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input.
The voltage range for the external reference is 2.5 V 1ꢀ for specified performance.
REFIN
16–9
V
IN0–VIN
7
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the
address bits ADD2 through ADD0 of the Control Register. The address bits, in conjunction with the SEQ
and SHADOW bits, allow the Sequencer to be programmed. The input range for all input channels
can extend from 0 V to REFIN or 0 V to 2 ϫ REFIN as selected via the RANGE bit in the Control
Register. Any unused input channels must be connected to AGND to avoid noise pickup.
18
DOUT
Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The
data stream from the AD7908 consists of one leading zero, three address bits indicating which channel
the conversion result corresponds to, followed by the eight bits of conversion data, followed by four
trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero,
three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits
of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the
AD7928 consists of one leading zero, three address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding
may be selected as straight binary or twos complement via the CODING bit in the Control Register.
19
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial
interface of the AD7908/AD7918/AD7928 will operate.
–10–
REV. A
AD7908/AD7918/AD7928
TERMINOLOGY
Negative Gain Error Match
Integral Nonlinearity
This is the difference in Negative Gain Error between any two
channels.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 400 kHz
sine wave signal to all seven nonselected input channels and deter-
mining how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure is given worst case across all
eight channels for the AD7908/AD7918/AD7928.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
PSR (Power Supply Rejection)
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Variations in power supply will affect the full scale transition, but
not the converter’s linearity. Power supply rejection is the maxi-
mum change in full-scale transition point due to a change in
power-supply voltage from the nominal value. See Typical
Performance Curves.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
Track-and-Hold Acquisition Time
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the
offset error has been adjusted out.
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 1 LSB, after the end of conversion.
Gain Error Match
This is the difference in Gain Error between any two channels.
Signal-to-(Noise + Distortion) Ratio
Zero Code Error
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
This applies when using the twos complement output coding
option, in particular to the 2 ϫ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the midscale transition (all 0s to all 1s) from the ideal VIN voltage,
i.e., REFIN – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two channels.
Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 ϫ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the last code transition (011. . .110) to (011 . . . 111) from the
ideal (i.e., +REFIN – 1 LSB) after the Zero Code Error has been
adjusted out.
Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter,
this is 62 dB; and for an 8-bit converter, this is 50 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7908/AD7918/
AD7928, it is defined as:
Positive Gain Error Match
This is the difference in Positive Gain Error between any two
channels.
V22 +V32 +V42 +V52 +V62
THD(dB) = 20log
V
1
Negative Gain Error
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
This applies when using the twos complement output coding
option, in particular to the 2 ϫ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has
been adjusted out.
–11–
REV. A
AD7908/AD7918/AD7928–Typical Performance Characteristics
PERFORMANCE CURVES
TPC 4 shows a graph of total harmonic distortion versus analog
TPC 1 shows a typical FFT plot for the AD7928 at 1 MSPS
sample rate and 50 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 1 MSPS
with an SCLK of 20 MHz.
input frequency for various supply voltages, while TPC 5 shows
a graph of total harmonic distortion versus analog input frequency
for various source impedances. See the Analog Input section.
TPC 6 and TPC 7 show typical INL and DNL plots for the
AD7928.
TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7928 when no decoupling is used.
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency f, to the power
of a 200 mV p-p sine wave applied to the ADC AVDD supply of
frequency fS:
0
AV = 5V
DD
200mV p-p SINEWAVE ON AV
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
REF = 2.5V, 1F CAPACITOR
IN
T
= 25؇C
A
PSRR(dB) =10log(Pf / Pfs)
Pf is equal to the power at frequency f in ADC output; PfS is
equal to the power at frequency fS coupled onto the ADC AVDD
supply. Here a 200 mV p-p sine wave is coupled onto the AVDD
supply.
4096 POINT FFT
–10
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
AV = 5V
DD
fSAMPLE = 1MSPS
fIN = 50kHz
SINAD = 71.147dB
THD = –87.229dB
SFDR = –90.744dB
–30
–50
TPC 3. AD7928 PSRR vs. Supply Ripple Frequency
–50
fSAMPLE = 1MSPS
T
= 25؇C
A
–55
–60
–65
–70
–75
–80
–85
–90
RANGE = 0TO REF
IN
AV =V
DD
= 2.7V
–70
DRIVE
–90
AV =V
DD
= 3.6V
DRIVE
–110
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
TPC 1. AD7928 Dynamic Performance at 1 MSPS
AV =V
DD
= 4.75V
DRIVE
AV =V
DD
= 5.25V
DRIVE
75
10
100
INPUT FREQUENCY (kHz)
1000
AV =V
= 5.25V
= 4.75V
DD
DRIVE
DRIVE
AV =V
DD
TPC 4. AD7928 THD vs. Analog Input Frequency for
Various Supply Voltages at 1 MSPS
70
65
60
55
AV =V
= 3.6V
DRIVE
–50
DD
fSAMPLE = 1MSPS
T
= 25؇C
A
–55
–60
–65
–70
–75
–80
–85
–90
RANGE = 0TO REF
IN
AV = 5.25V
DD
fSAMPLE = 1MSPS
= 25؇C
RANGE = 0TO REF
R
= 1000⍀
IN
AV =V
= 2.7V
DRIVE
DD
T
A
IN
R
= 100⍀
IN
R
= 50⍀
IN
10
100
INPUT FREQUENCY (kHz)
1000
TPC 2. AD7928 SINAD vs. Analog Input Frequency for
Various Supply Voltages at 1 MSPS
R
= 10⍀
IN
10
100
INPUT FREQUENCY (kHz)
1000
TPC 5. AD7928 THD vs. Analog Input Frequency for
Various Source Impedances
REV. A
–12–
AD7908/AD7918/AD7928
1.0
0.8
1.0
0.8
AV =V
DD
= 5V
AV =V
DD
= 5V
DRIVE
TEMP = 25؇C
DRIVE
TEMP = 25؇C
0.6
0.4
0.6
0.4
0.2
0
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
CODE
TPC 6. AD7928 Typical INL
TPC 7. AD7928 Typical DNL
CONTROL REGISTER
The Control Register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the
AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conver-
sion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration
for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling
clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions
are outlined in Table I.
Table I. Control Register Bit Functions
MSB
LSB
WRITE SEQ DONTC ADD2 ADD1 ADD0 PM1 PM0 SHADOW
DONTC
RANGE
CODING
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the Control Register determines whether or not the following 11 bits will be
loaded to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register; if it is a
0, the remaining 11 bits are not loaded to the Control Register, and it remains unchanged.
10
SEQ
The SEQ bit in the Control Register is used in conjunction with the SHADOW bit to control the use of the
sequencer function and access the SHADOW Register. (See Table IV.)
9
DONTCARE
8–6
ADD2–ADD0 These three address bits are loaded at the end of the present conversion sequence and select which analog
input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive
sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The
address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data,
see the Serial Interface section. The next channel to be converted on will be selected by the mux on the
14th SCLK falling edge.
5, 4
3
PM1, PM0
Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928
as shown in Table III.
SHADOW
The SHADOW bit in the Control Register is used in conjunction with the SEQ bit to control the use of the
sequencer function and access the SHADOW Register. (See Table IV.)
2
1
DONTCARE
RANGE
This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the
analog input range will extend from 0 V to 2 ϫ REFIN. If it is set to 1, the analog input range will extend from
0 V to REFIN (for the next conversion). For 0 V to 2 ϫ REFIN, AVDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding the AD7908/AD7918/AD7928 will use for the conversion result.
If this bit is set to 0, the output coding for the part will be twos complement. If this bit is set to 1, the output
coding from the part will be straight binary (for the next conversion).
–13–
REV. A
AD7908/AD7918/AD7928
Table II. Channel Selection
ADD0 Analog Input Channel
IN0
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the
Control Register allows the user to select a particular mode of
operation of the sequencer function. Table IV outlines the four
modes of operation of the Sequencer.
ADD2
ADD1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
V
1
0
1
0
1
0
1
VIN1
VIN
VIN
VIN
VIN
VIN
VIN
2
3
4
5
6
7
Table IV. Sequence Selection
SEQ SHADOW Sequence Type
0
0
This configuration means that the sequence
function is not used. The analog input
channel selected for each individual
conversion is determined by the contents of
the channel address bits ADD0 through
ADD2 in each prior write operation. This
mode of operation reflects the traditional
operation of a multichannel ADC, without
the Sequencer function being used, where
each write to the AD7908/AD7918/
AD7928 selects the next channel for
conversion. (See Figure 2.)
Table III. Power Mode Selection
PM1 PM0 Mode
1
1
Normal Operation. In this mode, the AD7908/
AD7918/AD7928 remain in full power mode
regardless of the status of any of the logic inputs.
This mode allows the fastest possible throughput
rate from the AD7908/AD7918/AD7928.
1
0
Full Shutdown. In this mode, the AD7908/
AD7918/AD7928 is in full shutdown mode with
all circuitry powering down. The AD7908/AD7918/
AD7928 retains the information in the Control
Register while in full shutdown. The part remains in
full shutdown until these bits are changed.
0
1
This configuration selects the SHADOW
Register for programming. The following
write operation will load the contents of the
SHADOW Register. This will program the
sequence of channels to be converted on
continuously with each successive valid CS
falling edge. (See SHADOW Register
section, Table V, and Figure 3.) The
channels selected need not be consecutive.
0
0
1
0
Auto Shutdown. In this mode, the AD7908/
AD7918/AD7928 automatically enters full
shutdown mode at the end of each conversion
when the control register is updated. Wake-up
time from full shutdown is 1 µs and the user
should ensure that 1 µs has elapsed before
attempting to perform a valid conversion on the
part in this mode.
1
1
0
1
If the SEQ and SHADOW bits are set in
this way, then the sequence function will
not be interrupted upon completion of the
WRITE operation. This allows other bits in
the Control Register to be altered between
conversions while in a sequence, without
terminating the cycle.
Invalid Selection. This configuration is not allowed.
This configuration is used in conjunction
with the channel address bits ADD2 to
ADD0 to program continuous conversions
on a consecutive sequence of channels from
Channel 0 to a selected final channel as
determined by the channel address bits in
the Control Register. (See Figure 4.)
–14–
REV. A
AD7908/AD7918/AD7928
SHADOW REGISTER
in ascending order beginning with the lowest channel, until a
write operation occurs (i.e., the WRITE bit is set to 1) with the
SEQ and SHADOW bits configured in any way except 1,0.
(See Table IV.) The bit functions are outlined in Table V.
The SHADOW Register on the AD7908/AD7918/AD7928 is a
16-bit, write-only register. Data is loaded from the DIN pin of
the AD7908/AD7918/AD7928 on the falling edge of SCLK.
The data is transferred on the DIN line at the same time that a
conversion result is read from the part. This requires 16 serial
clock falling edges for the data transfer. The information is
clocked into the SHADOW Register, provided that the SEQ
and SHADOW bits were set to 0,1, respectively, in the previous
write to the Control Register. MSB denotes the first bit in the
data stream. Each bit represents an analog input from Channel
0 to Channel 7. Through programming the SHADOW Register,
two sequences of channels may be selected, through which the
AD7908/AD7918/AD7928 will cycle with each consecutive
conversion after the write to the SHADOW Register. Sequence
One will be performed first and then Sequence Two. If the user
does not wish to perform a second sequence option, then all 0s
must be written to the last 8 LSBs of the SHADOW Register.
To select a sequence of channels, the associated channel bit
must be set for each analog input. The AD7908/AD7918/
AD7928 will continuously cycle through the selected channels
Figure 2 reflects the traditional operation of a multichannel
ADC, where each serial transfer selects the next channel for
conversion. In this mode of operation the Sequencer function is
not used.
Figure 3 shows how to program the AD7908/AD7918/AD7928
to continuously convert on a particular sequence of channels. To
exit this mode of operation and revert back to the traditional
mode of operation of a multichannel ADC (as outlined in
Figure 2), ensure that the WRITE bit = 1 and the SEQ =
SHADOW = 0 on the next serial transfer. Figure 4 shows how a
sequence of consecutive channels can be converted on without
having to program the SHADOW Register or write to the part
on each serial transfer. Again to exit this mode of operation and
revert back to the traditional mode of operation of a multichannel
ADC (as outlined in Figure 2), ensure the WRITE bit = 1 and
the SEQ = SHADOW = 0 on the next serial transfer.
Table V. SHADOW Register Bit Functions
MSB
LSB
VIN
------------------SEQUENCE ONE-------------------------------------------------------SEQUENCE TWO-----------------------
VIN
0
VIN
1
VIN
2
VIN
3
VIN
4
VIN
5
VIN
6
VIN
7
VIN
0
VIN
1
VIN
2
VIN
3
VIN
4
VIN
5
VIN
6
7
POWER-ON
POWER-ON
DUMMY CONVERSION
DIN = ALL 1s
DUMMY CONVERSION
DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
CS
CS
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 0 SHADOW = 1
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2–A0.
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2–A0.
CS
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
CS
WRITE BIT = 1,
DIN: WRITE TO SHADOW REGISTER, SELECTING
WHICH CHANNELS TO CONVERT ON; CHANNELS
SELECTED NEED NOT BE CONSECUTIVE CHANNELS
SEQ = SHADOW = 0
SELECT CODING, RANGE, AND POWER MODE.
SELECT A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0
WRITE BIT = 0
WRITE BIT = 1
SEQ = 1 SHADOW = 0
Figure 2. SEQ Bit = 0, SHADOW Bit = 0 Flowchart
CONTINUOUSLY
CONVERTS ON
THE SELECTED
SEQUENCE OF
CHANNELS
CONTINUOUSLY
CONVERTS ON THE
CS
SELECTED SEQUENCE
OF CHANNELS BUT WILL
ALLOW RANGE, CODING,
AND SO ON, TO CHANGE
IN THE CONTROL
REGISTER WITHOUT
INTERRUPTING THE
WRITE BIT = 0
SEQUENCE, PROVIDED
SEQ = 1 SHADOW = 0
WRITE BIT = 0
WRITE BIT = 1,
SEQ = 1,
SHADOW = 0
Figure 3. SEQ Bit = 0, SHADOW Bit = 1 Flowchart
–15–
REV. A
AD7908/AD7918/AD7928
a capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 5 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on the selected VIN
channel.
POWER-ON
DUMMY CONVERSION
DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
CS
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 1 SHADOW = 1
CAPACITIVE
DAC
A
4k⍀
V
0
7
IN
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTROL
LOGIC
SW1
B
SW2
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A2–A0 IN THE CONTROL REGISTER
CS
V
WRITE BIT = 0
IN
COMPARATOR
AGND
Figure 5. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 6), SW2 will
open and SW1 will move to position B, causing the comparator
to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 8 and 9 show the ADC transfer functions.
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING, AND SO ON, TO CHANGE IN THE
CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ = 1
SHADOW = 0
CS
WRITE BIT = 1,
SEQ = 1,
SHADOW = 0
Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart
CIRCUIT INFORMATION
The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit,
10-bit, and 12-bit, single supply, A/D converters, respectively.
The parts can be operated from a 2.7 V to 5.25 V supply. When
operated from either a 5 V or 3 V supply, the AD7908/AD7918/
AD7928 are capable of throughput rates of 1 MSPS when provided
with a 20 MHz clock.
CAPACITIVE
DAC
A
4k⍀
V
0
.
.
IN
CONTROL
LOGIC
SW1
B
SW2
V
7
IN
COMPARATOR
The AD7908/AD7918/AD7928 provide the user with an on-chip
track-and-hold, A/D converter, and a serial interface housed in
a 20-lead TSSOP package. The AD7908/AD7918/AD7928 each
have eight single-ended input channels with a channel sequencer,
allowing the user to select a channel sequence through which the
ADC can cycle with each consecutive CS falling edge. The serial
clock input accesses data from the part, controls the transfer of
data written to the ADC, and provides the clock source for the
successive approximation A/D converter. The analog input
range for the AD7908/AD7918/AD7928 is 0 V to REFIN or 0 V
to 2 ϫ REFIN, depending on the status of Bit 1 in the Control
Register. For the 0 to 2 ϫ REFIN range, the part must be oper-
ated from a 4.75 V to 5.25 V supply.
AGND
Figure 6. ADC Conversion Phase
Analog Input
Figure 7 shows an equivalent circuit of the analog input structure
of the AD7908/AD7918/AD7928. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be taken
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. This will cause these diodes to
become forward biased and start conducting current into the
substrate. 10 mA is the maximum current these diodes can conduct
without causing irreversible damage to the part. The capacitor
C1 in Figure 7 is typically about 4 pF and can primarily be attrib-
uted to pin capacitance. The resistor R1 is a lumped component
made up of the on resistance of the track-and-hold switch and
also includes the on resistance of the input multiplexer. The
total resistance is typically about 400 ⍀. The capacitor C2 is the
ADC sampling capacitor and has a capacitance of 30 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the relevant analog input pin. In applications where
harmonic distortion and signal-to-noise ratio are critical, the analog
input should be driven from a low impedance source. Large
source impedances will significantly affect the ac performance of
the ADC. This may necessitate the use of an input buffer ampli-
fier. The choice of the op amp will be a function of the particular
application.
The AD7908/AD7918/AD7928 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by pro-
gramming the power management bits, PM1 and PM0, in the
Control Register.
CONVERTER OPERATION
The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit succes-
sive approximation analog-to-digital converters based around a
capacitive DAC, respectively. The AD7908/AD7918/AD7928
can convert analog input signals in the range 0 V to REFIN or 0 V
to 2 ϫ REFIN. Figures 5 and 6 show simplified schematics of
the ADC. The ADC is comprised of control logic, SAR, and
REV. A
–16–
AD7908/AD7918/AD7928
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases, and performance will degrade. (See TPC 5.)
011…111
011…110
•
•
000…001
000…000
111…111
•
•
1LSB
؍
2 ؋
V 1LSB
؍
2 ؋
V 1LSB
؍
2 ؋
V ր256 AD7908
ր1024 AD7918
ր4096 AD7928
AV
DD
REF
REF
REF
100…010
100…001
100…000
C2
30pF
D1
R1
–V
REF
؉ 1 LSB
+V
؊ 1 LSB
V
REF
IN
V
؊ 1LSB
REF
C1
4pF
D2
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
ANALOG INPUT
Figure 9. Twos Complement Transfer Characteristic with
REFIN REFIN Input Range
Handling Bipolar Input Signals
Figure 7. Equivalent Analog Input Circuit
Figure 10 shows how useful the combination of the 2 ϫ REFIN
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal is
biased about REFIN and twos complement output coding is
selected, then REFIN becomes the zero code point, –REFIN is
negative full scale and +REFIN becomes positive full scale, with
ADC TRANSFER FUNCTION
The output coding of the AD7908/AD7918/AD7928 is either
straight binary or twos complement, depending on the status of
the LSB in the Control Register. The designed code transitions
occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on).
The LSB size is REFIN/256 for the AD7908, REFIN/1024 for the
AD7918, and REFIN/4096 for the AD7928. The ideal transfer
characteristic for the AD7908/AD7918/AD7928 when straight
binary coding is selected is shown in Figure 8, and the ideal
transfer characteristic for the AD7908/AD7918/AD7928 when
twos complement coding is selected is shown in Figure 9.
a dynamic range of 2 ϫ REFIN
.
TYPICAL CONNECTION DIAGRAM
Figure 11 shows a typical connection diagram for the AD7908/
AD7918/AD7928. In this setup, the AGND pin is connected to
the analog ground plane of the system. In Figure 11, REFIN is
connected to a decoupled 2.5 V supply from a reference source,
the AD780, to provide an analog input range of 0 V to 2.5 V
(if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although
the AD7908/AD7918/AD7928 is connected to a VDD of 5 V, the
serial interface is connected to a 3 V microprocessor. The VDRIVE
pin of the AD7908/AD7918/AD7928 is connected to the same 3 V
supply of the microprocessor to allow a 3 V logic interface (see
the Digital Inputs section). The conversion result is output in a
16-bit word. This 16-bit data stream consists of a leading zero,
three address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data for
the AD7928 (10 bits of data for the AD7918 and 8 bits of data for
the AD7908, each followed by two and four trailing zeros, respec-
tively). For applications where power consumption is of
111…111
111…110
•
•
111…000
•
011…111
1LSB
؍
V 1LSB
؍
V 1LSB
؍
V /256 AD7908
/1024 AD7918
/4096 AD7928
REF
REF
REF
•
•
000…010
000…001
000…000
1 LSB
+V
؊ 1 LSB
REF
0V
ANALOG INPUT
NOTE:V
IS EITHER REF OR 2
؋
REF IN
IN
REF
Figure 8. Straight Binary Transfer Characteristic
V
DD
V
REF
0.1F
AV
DD
REF
IN
V
DD
V
DRIVE
AD7908/
AD7918/
AD7928
R4
R1
DSP/P
V
R3
R2
TWOS
COMPLEMENT
V
0
DOUT
IN
•
•
V
0V
011…111
000…000
100…000
(= 2
؋
REF )
IN
+REF
IN
V
7
IN
R1
؍
R2 ؍
R3 ؍
R4 REF
IN
(= 0V)
–REF
IN
Figure 10. Handling Bipolar Signals
–17–
REV. A
AD7908/AD7918/AD7928
concern, the power-down modes should be used between
conversions or bursts of several conversions to improve power
performance. (See the Modes of Operation section.)
Regardless of which channel selection method is used, the 16-bit
word output from the AD7928 during each conversion will
always contain a leading zero, three channel address bits that
the conversion result corresponds to, followed by the 12-bit
conversion result; the AD7918 will output a leading zero, three
channel address bits that the conversion result corresponds to,
followed by the 10-bit conversion result and two trailing zeros; the
AD7908 will output a leading zero, three channel address bits that
the conversion result corresponds to, followed by the 8-bit conver-
sion result and four trailing zeros. (See the Serial Interface section.)
5V
SERIAL
SUPPLY
0.1F
10F
INTERFACE
AV
0
•
•
DD
SCLK
DOUT
CS
V
IN
AD7908/
AD7918/
AD7928
0VTO REF
IN
C/P
V
7
IN
DIN
DRIVE
REF
V
Digital Inputs
AGND
IN
The digital inputs applied to the AD7908/AD7918/AD7928 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the AVDD + 0.3 V limit as on the analog inputs.
2.5V
AD780
0.1F
10F
0.1F
3V
SUPPLY
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTEDTO AGND
Another advantage of SCLK, DIN, and CS not being restricted
by the AVDD + 0.3 V limit is the fact that power supply sequenc-
ing issues are avoided. If CS, DIN, or SCLK are applied before
AVDD, there is no risk of latch-up as there would be on the analog
Figure 11. Typical Connection Diagram
Analog Input Selection
Any one of eight analog input channels may be selected for
conversion by programming the multiplexer with the address bits
ADD2–ADD0 in the Control Register. The channel configurations
are shown in Table II. The AD7908/AD7918/AD7928 may also be
configured to automatically cycle through a number of channels
as selected. The sequencer feature is accessed via the SEQ and
SHADOW bits in the Control Register. (See Table IV.)
inputs if a signal greater than 0.3 V was applied prior to AVDD
.
VDRIVE
The AD7908/AD7918/AD7928 also have the VDRIVE feature.
V
DRIVE controls the voltage at which the serial interface operates.
VDRIVE allows the ADC to easily interface to both 3 V and 5 V
processors. For example, if the AD7908/AD7918/AD7928 were
operated with an AVDD of 5 V, the VDRIVE pin could be powered
from a 3 V supply. The AD7908/AD7918/AD7928 have better
dynamic performance with an AVDD of 5 V while still being able
to interface to 3 V processors. Care should be taken to ensure
VDRIVE does not exceed AVDD by more than 0.3 V. (See the
Absolute Maximum Ratings.)
The AD7908/AD7918/AD7928 can be programmed to continu-
ously convert on a selection of channels in ascending order. The
analog input channels to be converted on are selected through
programming the relevant bits in the SHADOW Register (see
Table V). The next serial transfer will then act on the sequence
programmed by executing a conversion on the lowest channel in
the selection. The next serial transfer will result in a conversion
on the next highest channel in the sequence, and so on.
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7908/AD7918/AD7928. Errors in the refer-
ence source will result in gain errors in the AD7908/AD7918/
AD7928 transfer function and will add to the specified full-scale
errors of the part. A capacitor of at least 0.1 µF should be placed
on the REFIN pin. Suitable reference sources for the AD7908/
AD7918/AD7928 include the AD780, REF193, AD1582,
ADR03, ADR381, ADR391, and ADR421.
It is not necessary to write to the Control Register once a
sequencer operation has been initiated. The WRITE bit must be
set to zero or the DIN line tied low to ensure the Control Register
is not accidently overwritten, or the sequence operation inter-
rupted. If the Control Register is written to at any time during
the sequence, then it must be ensured that the SEQ and SHADOW
bits are set to 1,0 to avoid interrupting the automatic conversion
sequence. This pattern will continue until such time as the
AD7908/AD7918/AD7928 is written to and the SEQ and
SHADOW bits are configured with any bit combination except
1,0. On completion of the sequence, the AD7908/AD7918/
AD7928 sequencer will return to the first selected channel in
the SHADOW Register and commence the sequence again.
If 2.5 V is applied to the REFIN pin, the analog input range can
either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.
MODES OF OPERATION
The AD7908/AD7918/AD7928 have a number of different
modes of operation. These modes are designed to provide flex-
ible power management options. These options can be chosen
to optimize the power dissipation/throughput rate ratio for dif-
fering application requirements. The mode of operation of the
AD7908/AD7918/AD7928 is controlled by the power manage-
ment bits, PM1 and PM0, in the Control Register, as detailed in
Table III. When power supplies are first applied to the AD7908/
AD7918/AD7928, care should be taken to ensure that the part is
placed in the required mode of operation. (See the Powering Up
the AD7908/AD7918/AD7928 section.)
Rather than selecting a particular sequence of channels, a num-
ber of consecutive channels beginning with Channel 0 may also
be programmed via the Control Register alone, without needing
to write to the SHADOW Register. This is possible if the SEQ
and SHADOW bits are set to 1,1. The channel address bits
ADD2 through ADD0 will then determine the final channel in
the consecutive sequence. The next conversion will be on Chan-
nel 0, then Channel 1, and so on until the channel selected via
the address bits ADD2 through ADD0 is reached. The cycle
will begin again on the next serial transfer, provided the WRITE
bit is set to low, or if high, that the SEQ and SHADOW bits are
set to 1,0; then the ADC will continue its preprogrammed auto-
matic sequence uninterrupted.
REV. A
–18–
AD7908/AD7918/AD7928
Normal Mode (PM1 = PM0 = 1)
Auto Shutdown (PM1 = 0, PM0 = 1)
This mode is intended for the fastest throughput rate performance
as the user does not have to worry about any power-up times
with the AD7908/AD7918/AD7928 remaining fully powered at
all times. Figure 12 shows the general diagram of the operation
of the AD7908/AD7918/AD7928 in this mode.
In this mode, the AD7908/AD7918/AD7928 automatically
enters shutdown at the end of each conversion when the control
register is updated. When the part is in shutdown, the track and
hold is in hold mode. Figure 14 shows the general diagram of
the operation of the AD7908/AD7918/AD7928 in this mode. In
shutdown mode, all internal circuitry on the AD7908/AD7918/
AD7928 is powered down. The part retains information in the
Control Register during shutdown. The AD7908/AD7918/
AD7928 remains in shutdown until the next CS falling edge it
receives. On this CS falling edge, the track-and-hold that was in
hold while the part was in shutdown will return to track. Wake-
up time from auto shutdown is 1 µs, and the user should ensure
that 1 µs has elapsed before attempting a valid conversion.
When running the AD7908/AD7918/AD7928 with a 20 MHz
clock, one dummy cycle should be sufficient to ensure the part
is fully powered up. During this dummy cycle the contents of
the Control Register should remain unchanged; therefore the
WRITE bit should be 0 on the DIN line. This dummy cycle
effectively halves the throughput rate of the part, with every
other conversion result being valid. In this mode, the power
consumption of the part is greatly reduced with the part enter-
ing shutdown at the end of each conversion. When the Control
Register is programmed to move into Auto Shutdown, it does so
at the end of the conversion. The user can move the ADC in
and out of the low power state by controlling the CS signal.
The conversion is initiated on the falling edge of CS and the
track-and-hold will enter hold mode as described in the Serial
Interface section. The data presented to the AD7908/AD7918/
AD7928 on the DIN line during the first 12 clock cycles of the
data transfer are loaded into the Control Register (provided
WRITE bit is set to 1). If data is to be written to the SHADOW
Register (SEQ = 0, SHADOW = 1 on previous write), data pre-
sented on the DIN line during the first 16 SCLK cycles is loaded
into the SHADOW Register. The part will remain fully powered
up in Normal mode at the end of the conversion as long as PM1
and PM0 are both loaded with 1 on every data transfer.
Sixteen serial clock cycles are required to complete the conversion
and access the conversion result. The track-and-hold will go back
into track on the 14th SCLK falling edge. CS may then idle high
until the next conversion or may idle low until sometime prior to
the next conversion, (effectively idling CS low).
Once a data transfer is complete (DOUT has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET, has elapsed by bringing CS low again.
Powering Up the AD7908/AD7918/AD7928
CS
When supplies are first applied to the AD7908/AD7918/AD7928,
the ADC may power up in any of the operating modes of the
part. To ensure the part is placed into the required operating
mode, the user should perform a dummy cycle operation as out-
lined in Figure 15.
1
16
12
SCLK
DOUT
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
The three dummy conversion operation outlined in Figure 15
must be performed to place the part into the Auto Shutdown
mode. The first two conversions of this dummy cycle operation
are performed with the DIN line tied high; for the third conver-
sion of the dummy cycle operation, the user should write the
desired Control Register configuration to the AD7908/AD7918/
AD7928 in order to place the part into the Auto Shutdown
mode. On the third CS rising edge after the supplies are applied,
the Control Register will contain the correct information and
valid data will result from the next conversion.
DATA INTO CONTROL/SHADOW REGISTER
DIN
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES
Figure 12. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7908/AD7918/
AD7928 is powered down. The part retains information in the
Control Register during full shutdown. The AD7908/AD7918/
AD7928 remains in full shutdown until the power management
bits in the Control Register, PM1 and PM0, are changed.
Therefore, to ensure the part is placed into the correct operating
mode, when supplies are first applied to the AD7908/AD7918/
AD7928, the user must first issue two serial write operations
with the DIN line tied high, and on the third conversion cycle the
user can then write to the Control Register to place the part into
any of the operating modes. The user should not write to the
SHADOW Register until the fourth conversion cycle after the
supplies are applied to the ADC, in order to guarantee the
Control Register contains the correct data.
If a write to the Control Register occurs while the part is in Full
Shutdown, with the power management bits changed to PM0 =
PM1 = 1, Normal mode, the part will begin to power up on the
CS rising edge. The track-and-hold that was in hold while the
part was in Full Shutdown will return to track on the 14th SCLK
falling edge.
To ensure that the part is fully powered up, tPOWER UP, should have
elapsed before the next CS falling edge. Figure 13 shows the
general diagram for this sequence.
If the user wants to place the part into either the Normal mode
or Full Shutdown mode, the second dummy cycle with DIN tied
high can be omitted from the three dummy conversion operation
outlined in Figure 15.
–19–
REV. A
AD7908/AD7918/AD7928
PART IS IN FULL
PART BEGINSTO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
SHUTDOWN
t12
CS
1
14
16
1
14
16
SCLK
DOUT
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
DATA INTO CONTROL REGISTER
DIN
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 13. Full Shutdown Mode Operation
PART ENTERS
PART ENTERS
PART BEGINSTO
SHUTDOWN ON CS
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 SHUTDOWN ON CS
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 POWER
PART IS FULLY
POWERED UP
UP ON CS
FALLING EDGE
CS
DUMMY CONVERSION
12
1
12
16
1
16
1
12
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS, PM1
؍
0, PM0 ؍
1 CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE,WRITE BIT
؍
0 TO KEEP PART INTHIS MODE, LOAD PM1
؍
0, PM0 ؍
1 IN CONTROL REGISTER OR SETWRITE BIT = 0
Figure 14. Auto Shutdown Mode Operation
CORRECTVALUE IN CONTROL
REGISTER,VALID DATA FROM
NEXT CONVERSION, USER CAN
WRITETO SHADOW REGISTER
IN NEXT CONVERSION
CS
SCLK
DOUT
DUMMY CONVERSION
DUMMY CONVERSION
1
12
16
1
12
16
1
12
16
INVALID DATA
INVALID DATA
INVALID DATA
DATA INTO CONTROL REGISTER
DIN
KEEP DIN LINETIED HIGH FOR FIRSTTWO DUMMY CONVERSIONS
CONTROL REGISTER IS LOADED ONTHE FIRST
12 CLOCK EDGES
Figure 15. Placing AD7928 into the Required Operating Mode after Supplies are Applied
is one dummy cycle, i.e., 1 µs, and the remaining conversion
time is another cycle, i.e., 1 µs, then the AD7928 can be said
to dissipate 13.5 mW for 2 µs during each conversion cycle.
For the remainder of the conversion cycle, 8 µs, the part
remains in Auto Shutdown mode. The AD7928 can be said
to dissipate 2.5 µW for the remaining 8 µs of the conversion
cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs
and the average power dissipated during each cycle is
(2/10) ϫ (13.5 mW) + (8/10) ϫ (2.5 µW) = 2.702 mW.
POWER VS. THROUGHPUT RATE
By operating in Auto Shutdown mode on the AD7908/AD7918/
AD7928, the average power consumption of the ADC decreases
at lower throughput rates. Figure 16 shows how as the through-
put rate is reduced, the part remains in its shutdown state longer
and the average power consumption over time drops accordingly.
For example if the AD7928 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and an SCLK
of 20 MHz (AVDD = 5 V), and the device is placed in Auto
Shutdown mode, i.e., if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
Figure 16 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 3 V and 5 V supplies.
The maximum power dissipation during normal operation is
13.5 mW (AVDD = 5 V). If the power-up time from Auto Shutdown
REV. A
–20–
AD7908/AD7918/AD7928
10
Writing of information to the Control Register takes place on
the first 12 falling edges of SCLK in a data transfer, assuming
the MSB, i.e., the WRITE bit, has been set to 1. If the Control
Register is programmed to use the SHADOW Register, then
writing of information to the SHADOW Register will take place
on all 16 SCLK falling edges in the next serial transfer as shown
for example on the AD7928 in Figure 20. Two sequence options
can be programmed in the SHADOW Register. If the user does
not want to program a second sequence, then the eight LSBs
should be filled with zeros. The SHADOW Register will be
updated upon the rising edge of CS and the track-and-hold will
begin to track the first channel selected in the sequence.
AV = 5V
DD
AV = 3V
DD
1
0.1
The AD7908 will output a leading zero, three channel address
bits that the conversion result corresponds to, followed by the
8-bit conversion result, and four trailing zeros. The AD7918 will
output a leading zero, three channel address bits that the con-
version result corresponds to, followed by the 10-bit conversion
result, and two trailing zeros. The 16-bit word read from the
AD7928 will always contain a leading zero, three channel address
bits that the conversion result corresponds to, followed by the
12-bit conversion result.
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 16. AD7928 Power vs. Throughput Rate
SERIAL INTERFACE
Figures 17, 18, and 19 show the detailed timing diagrams
for serial interfacing to the AD7908, AD7918, and AD7928,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7908/AD7918/AD7928 during each conversion.
MICROPROCESSOR INTERFACING
The serial interface on the AD7908/AD7918/AD7928 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7908/AD7918/AD7928 with some of the more common
microcontroller and DSP serial interface protocols.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state; the analog input is sampled at this
point. The conversion is also initiated at this point and will require
16 SCLK cycles to complete. The track-and-hold will go back into
track on the 14th SCLK falling edge as shown in Figures 17, 18,
and 19 at point B, except when the write is to the SHADOW
Register, in which case the track-and-hold will not return to track
until the rising edge of CS, i.e., point C in Figure 20. On the 16th
SCLK falling edge, the DOUT line will go back into three-
state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated, the DOUT line
will go back into three-state, and the Control Register will not
be updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge as shown in Figures 17, 18, and 19. Sixteen
serial clock cycles are required to perform the conversion process
and to access data from the AD7908/AD7918/AD7928. For
the AD7908/AD7918/AD7928 the 8/10/12 bits of data are
preceded by a leading zero and the three channel address
bits, ADD2 to ADD0, identify which channel the result corre-
sponds to. CS going low provides the leading zero to be
read in by the microcontroller or DSP. The three remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges beginning with the first address bit ADD2, thus
the first falling clock edge on the serial clock has a leading zero
provided and also clocks out address bit ADD2. The final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
AD7908/AD7918/AD7928 to TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7908/AD7918/AD7928. The CS input allows easy interfacing
between the TMS320C541 and the AD7908/AD7918/AD7928
without any glue logic required. The serial port of the TMS320C541
is set up to operate in burst mode with internal CLKX0 (Tx serial
clock on serial port 0) and FSX0 (Tx frame sync from serial
port 0). The serial port control register (SPC) must have the
following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1.
The connection diagram is shown in Figure 21. It should be
noted that for signal processing applications, it is imperative that
the frame synchronization signal from the TMS320C541 provides
equidistant sampling. The VDRIVE pin of the AD7908/AD7918/
AD7928 takes the same supply voltage as that of the TMS320C541.
This allows the ADC to operate at a higher voltage than the
serial interface, i.e., TMS320C541, if necessary.
REV. A
–21–
AD7908/AD7918/AD7928
CS
tCONVERT
t2
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
SCLK
t11
t3
t7
t4
t8
tQUIET
ADD2
t9
ADD1
ADD0
DB7
DB6
DB0
ZERO
ZERO
ZERO
ZERO
DOUT
DIN
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION
BITS
4TRAILING ZEROS
ZERO
WRITE
t10
SEQ1
DONTC
ADD2
ADD1
ADD0
CODING DONTC DONTC
DONTC
DONTC
Figure 17. AD7908 Serial Interface Timing Diagram
CS
tCONVERT
t2
t3
t6
B
1
2
3
4
5
6
11
12
13
14
t5
15
16
SCLK
t11
t7
t4
tQUIET
t8
ADD2
t9
ADD1
ADD0
DB9
DB8
DB2
DB1
DB0
ZERO
ZERO
DOUT
DIN
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION
BITS
2TRAILING ZEROS
ZERO
t10
WRITE
SEQ
DONTC
ADD2
ADD1
ADD0
CODING DONTC DONTC
DONTC
DONTC
Figure 18. AD7918 Serial Interface Timing Diagram
CS
tCONVERT
t6
tQUIET
B
t2
1
2
3
4
5
13
14
t5
15
16
t11
SCLK
t7
t3
t8
DB0
t4
DB11
DOUT
DIN
ADD2
ADD1
ADD0
DB10
DB2
DB1
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
WRITE
ADD2
DONTC
SEQ
DONTC
ADD1
ADD0
DONTC DONTC
Figure 19. AD7928 Serial Interface Timing Diagram
C
CS
tCONVERT
t6
t2
SCLK
1
2
3
4
5
13
14
t5
15
16
t11
t7
t3
t8
t4
DOUT
DIN
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
V
0
V
1
V
2
V
3
V
4
V
5
V
5
V
6
V 7
IN
IN
IN
IN
IN
IN
IN
IN
IN
SEQUENCE 1
SEQUENCE 2
Figure 20. AD7928 Writing to SHADOW Register Timing Diagram
–22–
REV. A
AD7908/AD7918/AD7928
The Timer Register, for example, is loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (i.e., AX0 = TX0), the state of the SCLK is checked. The
DSP will wait until the SCLK has gone High, Low, and High
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
TMS320C541*
AD7908/
AD7918/
AD7928
*
CLKX
SCLK
CLKR
DR
DOUT
DIN
DT
FSX
FSR
CS
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
V
DD
Figure 21. Interfacing to the TMS320C541
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV register was loaded with
the value 3, then an SCLK of 5 MHz is obtained, and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the timer register is loaded
with the value, say 803 (803 + 1 = 804), 100.5 SCLKs will occur
between interrupts and subsequently between transmit instruc-
tions. This situation will result in nonequidistant sampling as the
transmit instruction is occurring on a SCLK edge. If the number
of SCLKs between interrupts is a whole integer figure of N,
then equidistant sampling will be implemented by the DSP.
AD7908/AD7918/AD7928 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7908/AD7918/AD7928 without any glue logic required. The
VDRIVE pin of the AD7908/AD7918/AD7928 takes the same supply
voltage as that of the ADSP-218x. This allows the ADC to operate
at a higher voltage than the serial interface, i.e., ADSP-218x,
if necessary.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
AD7908/AD7918/AD7928 to DSP563xx
The connection diagram in Figure 23 shows how the AD7908/
AD7918/AD7928 can be connected to the ESSI (Synchronous
Serial Interface) of the DSP563xx family of DSPs from Motorola.
Each ESSI (two on board) is operated in Synchronous mode
(SYN bit in CRB = 1) with internally generated word length
frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0
in CRB). Normal operation of the ESSI is selected by making
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should
be set to 1 so the frame sync is negative. It should be noted that
for signal processing applications, it is imperative that the frame
synchronization signal from the DSP563xx provides equidis-
tant sampling.
ITFS = 1
The connection diagram is shown in Figure 22. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set as
an output and RFS set as an input. The DSP operates in Alternate
Framing mode and the SPORT control register is set up as
described. The frame synchronization signal generated on the TFS
is tied to CS and as with all signal processing applications equi-
distant sampling is necessary. However, in this example the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling may not be achieved.
In the example shown in Figure 23, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output, SCKD = 1.
The VDRIVE pin of the AD7908/AD7918/AD7928 takes the same
supply voltage as that of the DSP563xx. This allows the
ADC to operate at a higher voltage than the serial interface, i.e.,
DSP563xx, if necessary.
ADSP-218x*
AD7908/
AD7918/
AD7928*
SCLK
SCLK
DOUT
DR
CS
RFS
TFS
DT
DSP563xx*
AD7908/
AD7918/
DIN
V
DRIVE
AD7928
*
SCK
SCLK
SRD
*ADDITIONAL PINS REMOVED FOR CLARITY
DOUT
DIN
V
DD
STD
SC2
Figure 22. Interfacing to the ADSP-218x
CS
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
V
DD
Figure 23. Interfacing to the DSP563xx
REV. A
–23–
AD7908/AD7918/AD7928
APPLICATION HINTS
Grounding and Layout
The AD7908/AD7918/AD7928 have very good immunity to
noise on the power supplies as can be seen by the PSRR versus
Supply Ripple Frequency plot, TPC 3. However, care should
still be taken with regard to grounding and layout.
reduce the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should be
The printed circuit board that houses the AD7908/AD7918/AD7928 decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to
should be designed such that the analog and digital sections are AGND. To achieve the best from these decoupling components, they
separated and confined to certain areas of the board. This facili- must be placed as close as possible to the device, ideally right up
tates the use of ground planes that can be separated easily. A against the device. The 0.1 µF capacitors should have low Effective
minimum etch technique is generally best for ground planes as Series Resistance (ESR) and Effective Series Inductance (ESI),
it gives the best shielding. All three AGND pins of the AD7908/ such as the common ceramic types or surface mount types, which
AD7918/AD7928 should be sunk in the AGND plane. Digital
and analog ground planes should be joined at only one place.
If the AD7908/AD7918/AD7928 is in a system where multiple
devices require an AGND to DGND connection, the connec-
tion should still be made at one point only, a star ground point
that should be established as close as possible to the AD7908/
AD7918/AD7928.
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
Evaluating the AD7908/AD7918/AD7928 Performance
The recommended layout for the AD7908/AD7918/AD7928 is
outlined in the AD7908/AD7918/AD7928 evaluation board.
The evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling the
board from the PC via the Eval-Board Controller.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed to
run under the AD7908/AD7918/AD7928 to avoid noise coupling.
The power supply lines to the AD7908/AD7918/AD7928 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals, like clocks, should be shielded with digital ground
The Eval-Board Controller can be used in conjunction with the
AD7908/AD7918/AD7928 evaluation board, as well as many other
Analog Devices evaluation boards ending in the CB designator,
to demonstrate/evaluate the ac and dc performance of the
AD7908/AD7918/AD7928.
to avoid radiating noise to other sections of the board, and clock The software allows the user to perform ac (fast Fourier transform)
signals should never be run near the analog inputs. Avoid cross- and dc (histogram of codes) tests on the AD7908/AD7918/
over of digital and analog signals. Traces on opposite sides of
the board should run at right angles to each other. This will
AD7928. The software and documentation are on a CD shipped
with the evaluation board.
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8؇
0؇
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AC
Revision History
Location
Page
9/03—Data Sheet changed from REV. 0 to REV. A.
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REV. A
–24–
相关型号：
AD7933BRU
4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28
ROCHESTER
AD7933BRU-REEL7
4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28
ROCHESTER
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