AD7938BCPZ-6REEL7 [ADI]
8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer; 8通道， 625 kSPS时，用音序器，12位并行ADC
| 型号： | AD7938BCPZ-6REEL7 |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer |
| 文件： | 总32页 (文件大小：928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 625 kSPS, 12-Bit
Parallel ADCs with a Sequencer
AD7938-6
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast throughput rate: 625 kSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 625 kSPS with 3 V supplies
7.5 mW max at 625 kSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs
8-channel single-ended inputs
V
AGND
DD
AD7938-6
V
REFIN/
V
REFOUT
2.5V
VREF
V
0
7
IN
IN
CLKIN
12-BIT
SAR ADC
AND
CONTROL
I/P
MUX
CONVST
T/H
BUSY
V
4-channel fully differential inputs
4-channel pseudo-differential inputs
7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
0.2ꢀ max @ 25°C, 25 ppm/°C max
70 dB SINAD at 50 kHz input frequency
No pipeline delays
SEQUENCER
V
PARALLEL INTERFACE/CONTROL REGISTER
DRIVE
DB0 DB11
CS RD WR W/B
DGND
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA max
32-lead LFCSP and TQFP package
Figure 1.
The AD7938-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
features flexible power management options. An on-chip
control register allows the user to set up different operating
conditions, including analog input range and configuration,
output coding, power management, and channel sequencing.
GENERAL DESCRIPTION
The AD7938-6 is a 12-bit high speed, low power, successive
approximation (SAR) ADC. The part operates from a single
2.7 V to 5.25 V power supply and features throughput rates up
to 625 kSPS. The part contains a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Software configurable analog inputs. Single-ended, pseudo-
differential, or fully differential analog inputs that are
software selectable.
The AD7938-6 features eight analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. The part can operate
with either single-ended, fully differential, or pseudo-
differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of VDD
6. No pipeline delay.
.
falling edge of
and the conversion is also initiated at
CONVST
7. Accurate control of the sampling instant via a
CONVST
this point.
input and once off conversion control.
The AD7938-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD7938-6
TABLE OF CONTENTS
AD7938-6—Specifications .............................................................. 3
Analog Input Structure.............................................................. 16
Analog Inputs.............................................................................. 17
Analog Input Selection .............................................................. 19
Reference Section ....................................................................... 20
Parallel Interface......................................................................... 22
Power Modes of Operation....................................................... 25
Power vs. Throughput Rate....................................................... 26
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 28
Grounding and Layout .............................................................. 28
PCB Design Guidelines for Chip Scale Package .................... 28
Evaluating the AD7938-6 Performance................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 30
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Function Description................................................................ 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
On-Chip Registers.......................................................................... 13
Control Register.......................................................................... 13
Sequencer Operation ................................................................. 14
Shadow Register.......................................................................... 14
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
ADC Transfer Function............................................................. 15
Typical Connection Diagram ................................................... 16
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7938-6
SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, FCLKIN = 10 MHz, FSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
70
dB min
dB min
dB min
dB min
dB max
dB max
dB max
68
71
Signal-to-Noise Ratio (SNR)2
69
Single-ended mode
Total Harmonic Distortion (THD)2
−73
−70
−73
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−85
5
72
50
dB typ
dB typ
dB typ
ns typ
FIN = 50 kHz, FNOISE = 300 kHz
Aperture Jitter2
Full Power Bandwidth2
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
Integral Nonlinearity2
12
1
1.5
Bits
LSB max
LSB max
Differential mode
Single-ended mode
Differential Nonlinearity2
Differential Mode
0.95
−0.95/+1.5
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
Single-Ended Mode
Single-Ended and Pseudo-Differential Input
Offset Error2
6
1
3
1
LSB max
LSB max
LSB max
LSB max
Offset Error Match2
Gain Error2
Gain Error Match2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Twos complement output coding
3
1
6
1
3
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Single-Ended Input Range
Pseudo-Differential Input Range: VIN+
VIN−
0 to VREF or 0 to 2 × VREF
0 to VREF or 2 × VREF
V
V
V typ
V typ
V
RANGE bit = 0, or RANGE bit = 1, respectively
RANGE bit = 0, or RANGE bit = 1, respectively
VDD = 3 V
−0.3 to +0.7
−0.3 to +1.8
VCM VREF/2
VCM VREF
1
VDD = 3 V
Fully Differential Input Range: VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current4
VCM = common-mode voltage3 = VREF/2
V
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
µA max
pF typ
pF typ
Input Capacitance
45
10
When in track
When in hold
Rev. 0 | Page 3 of 32
AD7938-6
Parameter
B Version1
Unit
Test Conditions/Comments
1ꢀ for specified performance
0.2ꢀ max @ 25ꢁC
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Current
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
VREF Noise
2.5
1
V
µA max
V
ppm/ꢁC max 5 ppm/ꢁC typ
µV typ
µV typ
Ω typ
pF typ
pF typ
2.5
25
10
130
10
15
25
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
When in track
When in hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
Twos Complement
CODING bit = 0
CODING bit = 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
t2 + 13 tCLK
125
625
ns
ns max
kSPS max
Full-scale step input
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital I/PS = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 100 kSPS, VDD = 5 V
(Static)
Normal Mode (Static)
Normal Mode (Operational)
0.8
1.5
1.2
0.3
160
2
mA typ
mA max
mA max
mA typ
µA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
µA max
SCLK on or off
Normal Mode (Operational)
7.5
3.6
800
480
10/6
mW max
mW max
µW typ
µW typ
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V/3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode (Static)
1 Temperature ranges as follows: B Versions: −40ꢁC to +85ꢁC.
2 See the Terminology section.
3 For full common-mode range, see Figure 25 and Figure 26.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.
6 Measured with a midscale dc analog input.
Rev. 0 | Page 4 of 32
AD7938-6
TIMING SPECIFICATIONS1
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; FCLKIN = 10MHz, FSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Parameter
AD7938-6
Unit
Description
fCLKIN
50
10
30
kHz min
MHz max
ns min
tQUIET
Minimum time between end of read and start of next conversion, i.e., time from
when the data bus goes into three-state until the next falling edge of CONVST.
t1
10
15
50
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
CONVST Pulse Width.
t2
CONVST Falling Edge to CLKIN Falling Edge Setup Time.
CLKIN Falling Edge to BUSY Rising Edge.
CS to WR Setup Time.
t3
t4
t5
0
CS to WR Hold Time.
t6
10
10
10
10
0
WR Pulse Width.
t7
Data Setup Time before WR.
Data Hold after WR.
t8
t9
New Data Valid before Falling Edge of BUSY.
CS to RD Setup Time.
t10
t11
t12
0
CS to RD Hold Time.
30
30
3
RD Pulse Width.
2
t13
Data Access Time after RD.
Bus Relinquish Time after RD.
Bus Relinquish Time after RD.
HBEN to RD Setup Time.
3
t14
50
0
t15
t16
t17
t18
t19
t20
t21
t22
0
HBEN to RD Hold Time.
10
0
Minimum Time between Reads/Writes.
HBEN to WR Setup Time.
10
40
15.7
7.8
HBEN to WR Hold Time.
CLKIN Falling Edge to BUSY Falling Edge.
CLKIN Low Pulse Width.
CLKIN High Pulse Width.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance (see Figure 35, Figure 36, Figure 37, and Figure 38).
2 The time required for the output to cross 0.4 V or 2.4 V.
3 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. 0 | Page 5 of 32
AD7938-6
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to AGND/DGND
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to DGND
VREFIN to AGND
AGND to DGND
−0.3 V to +7 V
−0.3 V to VDD +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to + 0.3 V
10 mA
Input Current to Any
Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
−40ꢁC to +85ꢁC
−65ꢁC to +150ꢁC
150ꢁC
θJA Thermal Impedance
108.2ꢁC/W (LFCSP)
121ꢁC/W (TQFP)
32.71ꢁC/W (LFCSP)
45ꢁC/W (TQFP)
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature
(10 sec to 30 sec)
ESD
255ꢁC
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 32
AD7938-6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
PIN 1
IDENTIFIER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
2
3
4
5
6
7
8
24
23
22
V
V
V
1
0
IN
IN
/V
REFIN REFOUT
AD7938-6
21 AGND
20 CS
TOP VIEW
(Not to Scale)
19 RD
18 WR
17 CONVST
9
10 11 12 13 14 15 16
Figure 2. Pin Configuration
Table 4. Pin Function Description
Pin No
Mnemonic
Function
1 to 8
DB0 to DB7
Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control
and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the VDRIVE input.
9
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that
at VDD but should never exceed VDD by more than 0.3 V.
10
11
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte
of data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of
the data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4
to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the
channel address bits in Table 8). When writing to the device, DB4 to DB7 of the high byte must be all 0s.
DB8/HBEN
12 to 14 DB9 to DB11
Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR.
The logic high/low voltage levels for these pins are determined by the VDRIVE input.
15
BUSY
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and
the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY on the 13th rising edge of SCLK, see Figure 35.
16
17
CLKIN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for
the AD7938-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from
track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following
power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to
power-up the device.
CONVST
18
19
WR
RD
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
20
CS
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data
to the internal registers.
Rev. 0 | Page 7 of 32
AD7938-6
Pin No
Mnemonic
Function
21
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7938-6. All analog
input signals and any external reference signal should be referred to this AGND voltage. The AGND and
DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
22
VREFIN/VREFOUT
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the
ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by
an external reference. The input voltage range for the external reference is 0.1 V to VDD; however, care must be
taken to ensure that the analog input range does not exceed VDD + 0.3 V. See the Reference Section.
23 to 30 VIN0 to VIN7
Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and-
hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo-differential pairs, or seven pseudo-differential inputs by setting the MODE bits in the control register
appropriately (see Table 8). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be
used. The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow
register to be programmed. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and
the coding can be binary or twos complement, depending on the states of the RANGE and CODING bits in the
control register. Any unused input channels should be connected to AGND to avoid noise pickup.
31
32
VDD
Power Supply Input. The VDD range for the AD7938-6 is 2.7 V to 5.25 V. The supply should be decoupled to
AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938-6 in 12-bit words on
Pins DB0 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are
transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when
operating in byte transfer mode should be tied off to DGND.
W/B
Rev. 0 | Page 8 of 32
AD7938-6
TERMINOLOGY
Integral Nonlinearity
Negative Gain Error
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., −VREFIN + 1 LSB) after the zero-code error has been
adjusted out.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Offset Error
This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 ×
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match
VREF, while the signal amplitude is at 1 × VREF
.
This is the difference in gain error between any two channels.
Power Supply Rejection Ratio (PSRR)
Zero-Code Error
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the noise varies from 1 kHz to 1 MHz.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
mid scale transition (all 0s to all 1s) from the ideal VIN voltage,
PSRR (dB) = 10log(Pf/PfS)
i.e., VREF
.
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,
+VREF − 1 LSB) after the zero-code error has been adjusted out.
CMRR (dB) = 10log (Pf/PfS)
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 1/2 LSB, after the end of conversion.
Rev. 0 | Page 9 of 32
AD7938-6
Signal-to-(Noise + Distortion) Ratio (SINAD)
Peak Harmonic or Spurious Noise
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb)
and (fa − 2fb).
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938-6, it is defined as
2
V22 +V32 +V42 +V52 +V6
The AD7938-6 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
THD dB = −20log
( )
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Rev. 0 | Page 10 of 32
AD7938-6
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–60
100mV p-p SINE WAVE ON V AND/OR V
DD
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
4096 POINT FFT
V = 5V
DD
DRIVE
F
= 625kSPS
SAMPLE
–70
–80
F
= 49.62kHz
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
INT REF
–90
EXT REF
–100
–110
–120
–100
–110
10
210
410
610
810
1010
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Figure 6. AD7938-6 FFT @ VDD = 5 V
1.0
0.8
0.6
–70
INTERNAL/EXTERNAL REFERENCE
V
= 5V
DD
V
= 5V
DIFFERENTIAL MODE
DD
–75
0.4
0.2
–80
–85
0
–0.2
–0.4
–0.6
–0.8
–1.0
–90
–195
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
100
200
300
400
500
600
700
800
NOISE FREQUENCY (kHz)
Figure 4. AD7938-6 Channel-to-Channel Isolation
Figure 7. AD7938-6 Typical DNL @ VDD = 5 V
1.0
0.8
0.6
80
70
60
50
40
30
20
V
= 5V
V
= 5V
DD
DD
DIFFERENTIAL MODE
V
= 3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
F
= 625kSPS
SAMPLE
RANGE = 0 TO V
DIFFERENTIAL MODE
REF
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
Figure 5. AD7938-6 SINAD vs. Analog Input
Frequency for Various Supply Voltages
Figure 8. AD7938-6 Typical INL @ VDD = 5 V
Rev. 0 | Page 11 of 32
AD7938-6
6
5
4
3
2
1
10000
9000
8000
7000
6000
5000
4000
3000
9997
CODES
INTERNAL
REF
DIFFERENTIAL MODE
SINGLE-ENDED MODE
POSITIVE DNL
NEGATIVE DNL
2000
1000
0
0
3 CODES
2049 2050
–1
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
2046
2047
2048
V
(V)
CODE
REF
Figure 12. AD7938-6 Histogram of Codes for
10k Samples @ VDD = 5 V with the Internal Reference
Figure 9. AD7938-6 DNL vs. VREF for VDD = 3 V
12
11
10
–60
–70
–80
DIFFERENTIAL MODE
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
SINGLE-ENDED MODE
9
8
–90
V
= 3V
DD
SINGLE-ENDED MODE
–100
V
= 3V
DD
DIFFERENTIAL MODE
7
6
–110
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
200
400
600
800
1000
1200
V
(V)
RIPPLE FREQUENCY (kHz)
REF
Figure 13. CMRR vs. Input Frequency with VDD = 5 V and 3 V
Figure 10. AD7938-6 ENOB vs. VREF
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 5V
DD
V
= 3V
DD
–4.0
–4.5
–5.0
SINGLE-ENDED MODE
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
REF
Figure 11. AD7938-6 Offset vs. VREF
Rev. 0 | Page 12 of 32
AD7938-6
ON-CHIP REGISTERS
The AD7938-6 has two on-chip registers that are necessary for the operation of the device. These are the control register, which is used to
set up different operating conditions, and the shadow register, which is used to program the analog input channels to be converted.
CONTROL REGISTER
The control register on the AD7938-6 is a 12-bit, write-only register. Data is written to this register using the
and
pins. The control
WR
CS
register is shown below and the functions of the bits are described in Table 6. At power up, the default bit settings in the control register
are all 0s.
Table 5. Control Register Bits
MSB
DB11
PM1
LSB
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PM0
CODING
REF
ADD2
ADD1
ADD0
MODE1
MODE0
SHDW
SEQ
RANGE
Table 6. Control Register Bit Function Description
Bit No. Mnemonic Description
11, 10
PM1, PM0
CODING
REF
Power Management Bits. These two bits are used to select the power mode of operation. The user can
choose between either normal mode or various power-down modes of operation as shown in Table 7.
This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight
(natural) binary. If this bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0,
an external reference should be applied to the VREF pin, and if this bit is Logic 1, the internal reference is selected
(see the Reference Section).
9
8
7 to 5
4, 3
ADD2 to
ADD0
These three address bits are used to either select which analog input channel is converted in the next conversion
if the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used
as described in Table 9. The selected input channel is decoded as shown in Table 8.
The two mode pins select the type of analog input on the eight VIN pins. The AD7938-6 can have either eight
single-ended inputs, four fully differential inputs, four pseudo-differential inputs, or seven pseudo-differential
inputs (see Table 8).
MODE1,
MODE0
2
1
0
SHDW
SEQ
The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and
access the SHDW register (see Table 9).
The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and
access the SHDW register (see Table 9).
This bit selects the analog input range of the AD7938-6. If it is set to 0, then the analog input range extends from
0 V to VREF. If it is set to 1, then the analog input range extends from 0 V to 2 × VREF. When this range is selected,
AVDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog
input remains within the supply rails. See Analog Inputs section for more information.
RANGE
Table 7. Power Mode Selection using the Power Management Bits in the Control Register
PM1 PM0 Mode
Description
0
0
0
1
Normal Mode
When operating in normal mode, all circuitry is fully powered up at all times.
Autoshutdown When operating in autoshutdown mode, the AD7938-6 enters full shutdown mode at the end of each
conversion. In this mode, all circuitry is powered down.
1
1
0
1
Autostandby
When the AD7938-6 enters this mode, all circuitry is powered down except for the reference and reference
buffer. This mode is similar to autoshutdown mode, but it allows the part to power-up in 7 µs (or 600 ns if
an external reference is used). See the Power Modes of Operation section for more information.
Full Shutdown When the AD7938-6 enters this mode, all circuitry is powered down. The information in the control
register is retained.
Rev. 0 | Page 13 of 32
AD7938-6
Table 8. Analog Input Type Selection
Channel Address
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
MODE0 = 1, MODE1 = 1
Eight Single-Ended
I/P Channels
Four Fully Differential
I/P Channels
Four Pseudo-Differential I/P
Channels (Pseudo Mode 1)
Seven Pseudo-Differential I/P
Channels (Pseudo Mode 2)
ADD2 ADD1 ADD0 VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
Not Allowed
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 9 outlines the four modes of operation of the sequencer.
Table 9. Sequence Selection
SEQ SHDW Sequence Type
0
0
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer
function being used, where each write to the AD7938-6 selects the next channel for conversion.
0
1
1
1
0
1
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge (see the shadow register description and Table 10).
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
SHADOW REGISTER
The shadow register on the AD7938-6 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of
. The eight
WR
LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits in the
control register were set to 0 and 1, respectively, in the previous write to the control register. Each bit represents an analog input from
Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938-6 cycles with each consecutive
conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in single-ended mode or
Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When operating in
differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required in the
sequence. With each consecutive
pulse after the sequencer has been set up, the AD7938-6 progresses through the selected
CONVST
channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and SHDW
bits configured in any way except 1, 0 (see Table 9). When a sequence is set up in differential or Pseudo Mode 1, the ADC does not convert
on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in Table 10. See the Analog Input Selection
section for further information on using the sequencer.
Table 10. Shadow Register Bit Functions
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Rev. 0 | Page 14 of 32
AD7938-6
CIRCUIT INFORMATION
The AD7938-6 is a fast, 8-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter. The
part can operate from a 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS.
When the ADC starts a conversion (Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once
the conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to
bring the comparator back into a balanced condition. When
the comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and the VIN− pins
must match; otherwise, the two inputs have different settling
times, which result in errors.
The AD7938-6 provides the user with an on-chip track-and-
hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP
or TQFP package.
The AD7938-6 has eight analog input channels that can
be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo-differential pairs, or seven
pseudo-differential inputs with respect to one common
input. There is an on-chip user-programmable channel
sequencer that allows the user to select a sequence of channels
through which the ADC can progress and cycle with each
CAPACITIVE
DAC
C
B
A
S
V
V
IN+
SW1
CONTROL
LOGIC
SW3
consecutive falling edge of
.
CONVST
SW2
A
B
IN–
C
S
The analog input range for the AD7938-6 is 0 to VREF or 0 to
2 × VREF depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
V
REF
COMPARATOR
CAPACITIVE
DAC
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
The AD7938-6 provides flexible power management options
to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0,
in the control register.
The output coding for the AD7938-6 is either straight binary
or twos complement, depending on the status of the CODING
bit in the control register. The designed code transitions occur
at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on) and the
LSB size is VREF/4096 . The ideal transfer characteristics of the
AD7938-6 for both straight binary and twos complement
output coding are shown in Figure 16 and Figure 17,
respectively.
CONVERTER OPERATION
The AD7938-6 is a successive approximation ADC based
around two capacitive DACs. Figure 14 and Figure 15 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises of control logic, a SAR,
and two capacitive DACs. Both figures show the operation of
the ADC in differential/pseudo-differential mode. Single-ended
mode operation is similar but VIN− is internally tied to AGND.
In acquisition phase, SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
111...111
111...110
111...000
011...111
1 LSB = V
/4096
REF
000...010
000...001
000...000
CAPACITIVE
DAC
1 LSB
+V
–1 LSB
REF
0V
C
B
A
S
ANALOG INPUT
V
V
IN+
SW1
CONTROL
LOGIC
NOTE: V
IS EITHER V
OR 2 × V
REF REF
SW3
REF
SW2
A
B
IN–
Figure 16. AD7938-6 Ideal Transfer Characteristic
with Straight Binary Output Coding
C
S
V
REF
COMPARATOR
CAPACITIVE
DAC
Figure 14. ADC Acquisition Phase
Rev. 0 | Page 15 of 32
AD7938-6
ANALOG INPUT STRUCTURE
1 LSB = 2 × V
/4096
REF
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7938-6 in differential/pseudo differential
mode. In single-ended mode, VIN− is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–V
+ 1 LSB
V
+V
– 1 LSB
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors and have
a capacitance of 40 pF typically.
REF
REF
REF
Figure 17. AD7938-6 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7938-6. The AGND and DGND pins are connected together
at the device for good noise suppression. The VREFIN/VREFOUT
pin is decoupled to AGND with a 0.47 µF capacitor to avoid
noise pickup if the internal reference is used. Alternatively,
VREFIN/VREFOUT can be connected to an external reference
source, and in this case, the reference pin should be decoupled
with a 0.1 µF capacitor. In both cases, the analog input range
can either be 0 V to VREF (RANGE bit = 0) or 0 V to 2 × VREF
(RANGE bit = 1). The analog input configuration can be either
eight single-ended inputs, four differential pairs, four pseudo-
differential pairs, or seven pseudo-differential inputs (see
Table 8). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface and here, it is connected to the
same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section).
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp is a function of the
particular application.
V
DD
D
R1
C2
V
+
IN
D
C1
V
DD
3V/5V
SUPPLY
D
D
0.1µF
10µF
R1
C2
V
–
IN
C1
V
V
DD
AD7938-6
W/B
CLKIN
CS
0
IN
Figure 19. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
0 TO V
/
REF
RD
0 TO 2 × V
REF
µC/µP
WR
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and
differential mode, respectively.
V
7
BUSY
CONVST
IN
DB0
AGND
DGND
DB11/DB9
V
/V
REFIN REFOUT
V
DRIVE
0.1µF
10µF
3V
2.5V
SUPPLY
V
REF
0.1µF EXTERNAL V
REF
0.47µF INTERNAL V
REF
Figure 18. Typical Connection Diagram
Rev. 0 | Page 16 of 32
AD7938-6
–40
ANALOG INPUTS
F
= 50kHz
IN
V
= 3V
DD
–45
–50
–55
–60
–65
–70
–75
–80
The AD7938-6 has software selectable analog input
configurations. The user can choose either eight single-ended
inputs, four fully differential pairs, four pseudo-differential
pairs, or seven pseudo-differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits
in the internal control register (see Table 8).
V
= 5V
DD
Single-Ended Mode
The AD7938-6 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the
control register to 0. In applications where the signal source has
a high impedance, it is recommended to buffer the analog input
before applying it to the ADC. The analog input range can be
–85
–90
10
100
1k
10k
R
(Ω)
SOURCE
programmed to be either 0 to VREF or 0 to 2 × VREF
.
Figure 20. THD vs. Source Impedance in Single-Ended Mode
–60
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
F
= 50kHz
IN
–65
–70
–75
–80
–85
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode.
+2.5V
R
V
= 3V
+1.25V
0V
DD
R
0V
V
IN
V
–1.25V
IN0
IN7
3R
–90
–95
V
= 5V
DD
AD7938-6*
V
–100
V
REFOUT
10
100
1k
10k
R
(Ω)
SOURCE
0.47µF
Figure 21. THD vs. Source Impedance in Differential Mode
Figure 22 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 625 kHz with
an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Single-Ended Mode Connection Diagram
Differential Mode
–50
V
= 3V
The AD7938-6 can have four differential analog input pairs by
setting the MODE0 and MODE1 bits in the control register
to 0 and 1, respectively.
DD
SINGLE-ENDED MODE
–60
–70
V
= 5V
DD
SINGLE-ENDED MODE
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7938-6.
–80
–90
V
= 5V/3V
DD
DIFFERENTIAL MODE
–100
–110
–120
F
= 625kSPS
SAMPLE
RANGE = 0 TO V
V
REF
REF
200
INPUT FREQUENCY (kHz)
V
IN+
p-p
0
100
300
400
500
600
700
AD7938-6*
V
REF
V
IN–
p-p
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
COMMON-MODE
VOLTAGE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Differential Input Definition
Rev. 0 | Page 17 of 32
AD7938-6
4.5
4.0
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (i.e., VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals each of amplitude VREF
(or 2 × VREF depending on the range chosen) that are 180° out of
phase (assuming the 0 to VREF range is selected). The amplitude
of the differential signal is therefore −VREF to +VREF peak-to-
peak (i.e., 2 × VREF). This is regardless of the common mode
(CM). The common mode is the average of the two signals, i.e.
(VIN+ + VIN−)/2 and is therefore the voltage on which the two
inputs are centered. This results in the span of each input being
CM VREF/2. This voltage has to be set up externally and its
range varies with the reference value VREF. As the value of VREF
increases, the common-mode range decreases. When driving
the inputs with an amplifier, the actual common-mode range
is determined by the amplifier’s output voltage swing.
T
= 25°C
A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
V
(V)
REF
Figure 26. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Figure 25 and Figure 26 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 to
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180°
out of phase. The common mode must be set up externally
and has a range that is determined by VREF, the power supply,
and the particular amplifier used to drive the analog inputs.
Differential modes of operation with either an ac or dc input
provide the best THD performance over a wide frequency
range. Since not all applications have a signal preconditioned
for differential operation, there is often a need to perform
single-ended-to-differential conversion.
VREF range or 2 × VREF range, respectively. The common mode
must be in this range to guarantee the functionality of the
AD7938-6.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 4096. If the 2 ×
VREF range is used then the input signal amplitude would extend
from −2VREF to +2VREF after conversion.
Using an Op Amp Pair
3.5
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7938-6. The
circuit configurations shown in Figure 27 and Figure 28 show
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
T
= 25°C
A
3.0
2.5
2.0
1.5
1.0
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
that could be used in this configuration to provide differential
drive to the AD7938-6 is the AD8022.
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
REF
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 27 and Figure 28 are optimized for
dc coupling applications requiring best distortion performance.
Figure 25. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
The circuit configuration shown in Figure 27 converts a
unipolar, single-ended signal into a differential signal.
The differential op amp driver circuit in Figure 28 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
Rev. 0 | Page 18 of 32
AD7938-6
220Ω
V+
V
p-p
REF
2
×
V
p-p
REF
V
V
IN+
390Ω
3.75V
V
27Ω
REF
GND
AD7938-6*
2.5V
1.25V
V–
IN–
V
IN+
220Ω
220Ω
220Ω
V+
V
REF
AD7938-6
DC INPUT
VOLTAGE
0.47µF
V
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
*ADDITIONAL PINS OMITTED FOR CLARITY
V–
Figure 29. Pseudo-Differential Mode Connection Diagram
0.47µF
10kΩ
20kΩ
ANALOG INPUT SELECTION
As shown in Table 8, the user can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended
Unipolar Signal into a Differential Signal
220Ω
2
×
V
p-p
REF
V+
390Ω
3.75V
V
27Ω
REF
2.5V
GND
1.25V
V–
V
IN+
Traditional Multichannel Operation (SEQ = SHDW = 0)
220Ω
220Ω
AD7938-6
Any one of eight analog input channels or four pairs of channels
may be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 30 shows a flow chart of this
mode of operation. The channel configurations are shown in
Table 8.
V
V+
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
V–
0.47µF
10kΩ
20kΩ
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
Pseudo-Differential Mode
POWER ON
The AD7938-6 can have four pseudo-differential pairs (Pseudo
Mode 1) or seven pseudo differential inputs (Pseudo Mode 2)
by setting the MODE0 and MODE1 bits in the control register
to 1, 0 and 1, 1, respectively. In the case of the four pseudo-
differential pairs, VIN+ is connected to the signal source which
must have an amplitude of VREF (or 2 × VREF depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to the VIN− pin. The voltage applied to this
input provides an offset from ground or a pseudo ground for
the VIN+ input. In the case of the seven pseudo-differential
inputs, the seven analog input signals inputs are referred to
a dc voltage applied to VIN7. The benefit of pseudo-differential
inputs is that they separate the analog input signal ground from
the ADC’s ground allowing dc common-mode voltages to be
cancelled. The specified voltage range for the VIN− pin while in
pseudo-differential mode is −0.1 V to +0.4 V; however, typically
this range can extend to −0.3 V to +0.7 V when VDD = 3 V or
−0.3 V to +1.8 V when VDD = 5 V. Figure 29 shows a connection
diagram for pseudo-differential mode.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Programmable Sequence (SEQ = 0,
SHDW = 1 )
The AD7938-6 may be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1
in the control register. The analog input channels to be
converted are selected by setting the relevant bits in the
shadow register to 1, see Table 10.
Rev. 0 | Page 19 of 32
AD7938-6
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The
next conversion executed is on the next highest channel
in the sequence and so on. When the last channel in the
sequence is converted, the internal multiplexer returns to
the first channel selected in the shadow register and commences
the sequence again.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ = 1 SHDW = 1.
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
It is not necessary to write to the control register again once a
SEQ BIT = 1
SHDW BIT = 0
sequencer operation has been initiated. The
input must be
WR
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted.
If the control register is written to at any time during the
sequence, then ensure that the SEQ and SHDW bits are set
to 1, 0 to avoid interrupting the conversion sequence. The
sequence program remains in force until such time as the
AD7938-6 is written to and the SEQ and SHDW bits are
configured with any bit combination except 1, 0. Figure 31
shows a flow chart of the programmable sequence operation.
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC BITS IN THE
CONTROL REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
Figure 32. Consecutive Sequence Mode Flow Chart
REFERENCE SECTION
The AD7938-6 can operate with either the on-chip or external
reference. The internal reference is selected by setting the REF
bit in the internal control register to 1. A block diagram of the
internal reference circuitry is shown in Figure 33. The internal
reference circuitry includes an on-chip 2.5 V band gap reference
and a reference buffer. When using the internal reference, the
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ = 0 SHDW = 1.
V
REFIN/VREFOUT pin should be decoupled to AGND with a
INITIATE A WRITE CYCLE.
THIS WRITE CYCLE IS TO THE SHADOW REGISTER.
SET RELEVANT BITS TO SELECT
0.47 µF capacitor. This internal reference not only provides
the reference for the analog-to-digital conversion, but it can
also be used externally in the system. It is recommended that
the reference output is buffered using an external precision
op amp before applying it anywhere in the system.
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
IN THE SHADOW REGISTER
WITH EACH CONVST PULSE.
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
WITH EACH CONVST PULSE
BUT ALLOWS THE RANGE,
CODING, ANALOG INPUT TYPE,
ETC BITS IN THE CONTROL
REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
BUFFER
REFERENCE
V
/
REFIN
V
REFOUT
ADC
AD7938-6
Figure 31. Programmable Sequence Flow Chart
Consecutive Sequence (SEQ = 1, SHDW = 1)
Figure 33. Internal Reference Circuit Block Diagram
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register.
This is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. Once the control register
is written to, to set this mode up, the next conversion is on
Channel 0, then Channel 1, and so on until the channel selected
by the address bits (ADD2 to ADD0) is reached. The cycle
Alternatively, an external reference can be applied to the
VREFIN/VREFOUT pin of the AD7938-6. An external reference input
is selected by setting the REF bit in the internal control register
to 0. The external reference input range is 0.1 V to VDD. It is
important to ensure that, when choosing the reference value, the
maximum analog input range (VIN MAX) is never greater than
VDD + 0.3 V to comply with the maximum ratings of the device.
For example, if operating in differential mode and the reference
is sourced from VDD, then the 0 to 2 × VREF range cannot be
used. This is because the analog input signal range would now
extend to 2 × VDD, which would exceed maximum rating
conditions. In the pseudo-differential modes, the user must
begins again provided the
input is tied high. If low, the
WR
SEQ and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 32
shows the flow chart of the consecutive sequence mode.
Rev. 0 | Page 20 of 32
AD7938-6
Digital Inputs
ensure that VREF + (VIN−) ≤ VDD when using the 0 to VREF range,
or when using the 2 × VREF range that 2 × VREF +(VIN−) ≤ VDD.
The digital inputs applied to the AD7938-6 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
AVDD + 0.3 V limit as on the analog inputs.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 9 to Figure 11. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7938-6 transfer function and add to specified full-scale
errors on the part.
Another advantage of the digital inputs not being restricted by
the AVDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before
AVDD, then there is no risk of latch-up as there would be on
the analog inputs if a signal greater than 0.3 V was applied
prior to AVDD.
Table 11 lists examples of suitable voltage references that could
be used that are available from Analog Devices and Figure 34
shows a typical connection diagram for an external reference.
VDRIVE Input
The AD7938-6 has a VDRIVE feature. VDRIVE controls the voltage at
which the parallel interface operates. VDRIVE allows the ADC to
easily interface to 3 V and 5 V processors.
Table 11. Examples of Suitable Voltage References
Output
Initial Accuracy Operating
Reference Voltage
(ꢀ Max)
Current (µA)
For example, if the AD7938-6 is operated with an AVDD of 5 V
and the VDRIVE pin is powered from a 3 V supply, the AD7938-6
has better dynamic performance with an AVDD of 5 V while still
being able to interface directly to 3 V processors. Care should be
taken to ensure VDRIVE does not exceed AVDD by more than 0.3 V
(see the Absolute Maximum Ratings section).
AD780
ADR421
ADR420
2.5/3
2.5
0.04
0.04
0.05
1000
500
500
2.048
AD7938-6*
AD780
V
NC
1
2
3
4
O/PSELECT
8
7
6
5
NC
NC
REF
V
+V
IN
DD
2.5V
TEMP
GND
V
OUT
0.1µF
10nF
0.1µF
0.1µF
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 34. Typical VREF Connection Diagram
Rev. 0 | Page 21 of 32
AD7938-6
otherwise, the conversion is aborted and the track-and-hold
goes back into track. At the end of the conversion, BUSY goes
low and can be used to activate an interrupt service routine. The
PARALLEL INTERFACE
The AD7938-6 has a flexible, high speed, parallel interface.
This interface is 12-bits wide and is capable of operating in
and
lines are then activated in parallel to read the 12 bits
CS
of conversion data. When power supplies are first applied to the
device, a rising edge on is necessary to put the track-
RD
either word (W/ tied high) or byte (W/ tied low) mode.
B
B
The
signal is used to initiate conversions and when
CONVST
CONVST
and-hold into track. The acquisition time of 125 ns minimum
must be allowed before is brought low to initiate a
operating in autoshutdown or autostandby mode, it is used to
initiate power up.
CONVST
conversion. The ADC then goes into hold on the falling edge
of
and back into track on the 13th rising edge of
A falling edge on the
signal is used to initiate
CONVST
conversions and it also puts the ADC track-and-hold into track.
Once the signal goes low, the BUSY signal goes high
CONVST
CLKIN after this (see Figure 35). When operating the device
in autoshutdown or autostandby mode, where the ADC
powers down at the end of each conversion, a rising edge
CONVST
for the duration of the conversion. In between conversions,
must be brought high for a minimum time of t1.
CONVST
on the
signal is used to power up the device.
CONVST
This must happen after the 14th falling edge of CLKIN;
B
t1
A
CONVST
tCONVERT
1
2
3
4
5
12
13
14
t2
CLKIN
BUSY
t20
t3
t9
INTERNAL
TRACK/HOLD
tAQUISITION
CS
RD
t10
t11
t12
t13
t14
THREE-STATE
tQUIET
DB0 TO DB11
DB0 TO DB11
DATA
THREE-STATE
WITH CS AND RD TIED LOW
OLD DATA
DATA
B
Figure 35. AD7938-6 Parallel Interface—Conversion and Read Cycle in Word Mode (W/ = 1)
Rev. 0 | Page 22 of 32
AD7938-6
The
and
signals are gated internally and level triggered
RD
Reading Data from the AD7938-6
CS
active low. In either word mode or byte mode,
and
may
RD
CS
With the W/ pin tied logic high, the AD7938-6 interface
B
be tied together as the timing specifications for t10 and t11 are
0 ns minimum. This would mean the bus would be constantly
driven by the AD7938-6.
operates in word mode. In this case, a single read operation
from the device accesses the conversion data-word on Pins DB0
to DB11. The DB8/HBEN pin assumes its DB8 function. With
the W/ pin tied to logic low, the AD7938-6 interface operates
B
The data is placed onto the data bus a time, t13, after both
CS
in byte mode. In this case, the DB8/HBEN pin assumes its
HBEN function. Conversion data from the AD7938-6 must be
accessed in two read operations with eight bits of data provided
on DB0 to DB7 for each of the read operations. The HBEN pin
determines whether the read operation accesses the high byte or
the low byte of the12-bit word. For a low byte read, DB0 to DB7
provide the eight LSBs of the 12-bit word. For a high byte read,
DB0 to DB3 provide the four MSBs of the 12-bit word. DB5 to
DB7 of the high byte provide the Channel ID. Figure 35 shows
the read cycle timing diagram for a 12-bit transfer. When
operated in word mode, the HBEN input does not exist, and
only the first read operation is required to access data from the
device. When operated in byte mode, the two read cycles shown
in Figure 36 are required to access the full data-word from the
device.
and
go low. The
RD
rising edge can be used to latch data
RD
out of the device. After a time, t14, the data lines become
three-stated.
Alternatively,
and
can be tied permanently low and the
RD
CS
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if
is pulsed during the conversion time then this
RD
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion by way of tying and
CS
low does not cause any degradation.
RD
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
RD
t13
t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 36. AD7938-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. 0 | Page 23 of 32
AD7938-6
Figure 37 shows the write cycle timing diagram of the
Writing Data to the AD7938-6
AD7938-6. When operated in word mode, the HBEN input does
not exist and only one write operation is required to write the
word of data to the device. Data should be provided on DB0 to
DB11. When operated in byte mode, the two write cycles shown
in Figure 38 are required to write the full data-word to the
AD7938-6. In Figure 38, the first write transfers the lower eight
bits of the data-word from DB0 to DB7, and the second write
transfers the upper four bits of the data-word. When writing to
the AD7938-6, the top four bits in the high byte must be 0s.
With W/ tied logic high, a single write operation transfers the
B
full data-word on DB0 to DB11 to the control register on the
AD7938-6. The DB8/HBEN pin assumes its DB8 function. Data
written to the AD7938-6 should be provided on the DB0 to
DB11 inputs with DB0 being the LSB of the data-word. With
W/ tied logic low, the AD7938-6 requires two write operations
B
to transfer a full 12-bit word. DB8/HBEN assumes its HBEN
function. Data written to the AD7938-6 should be provided on
the DB0 to DB7 inputs. HBEN determines whether the byte
written is high byte or low byte data. The low byte of the data-
word should be written first with DB0 being the LSB of the full
data-word. For the high byte write, HBEN should be high and
the data on the DB0 input should be data Bit 8 of the 12-bit
word. In both word and byte mode, a single write operation to
the shadow register is always sufficient since it is only 8-bits
wide.
The data is latched into the device on the rising edge of
.
WR
The data needs to be setup a time, t7, before the
rising edge
WR
and held for a time, t8, after the
rising edge. The
and
WR
WR
and
CS
may be tied together as
WR
signals are gated internally.
CS
the timing specifications for t4 and t5 are 0 ns minimum
(assuming
and
have not already been tied together).
CS
RD
CS
t4
t5
WR
t6
t8
t7
DATA
DB0 TO DB11
B
Figure 37. AD7938-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
t7
WR
t8
DB0 TO DB11
LOW BYTE
HIGH BYTE
B
Figure 38. AD7938-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. 0 | Page 24 of 32
AD7938-6
Autostandby (PM1 = 1; PM0 = 0)
POWER MODES OF OPERATION
In this mode of operation, the AD7938-6 automatically enters
standby mode at the end of each conversion, which is shown as
Point A in Figure 35. When this mode is entered, all circuitry on
the AD7938-6 is powered down except for the reference and
reference buffer. The track-and-hold goes into hold at this point
also and remains in hold as long as the device is in standby. The
The AD7938-6 have four different power modes of
operation. These modes are designed to provide flexible
power management options. Different options can be chosen
to optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 7. When power is first applied to the
AD7938-6 an on-chip, power-on reset circuit ensures that the
default power-up condition is normal mode.
part remains in standby until the next rising edge of
CONVST
powers up the device. The power-up time required depends on
whether the internal or external reference is used. With an
external reference, the power-up time required is a minimum of
600 ns, while when using the internal reference, the power-up
time required is a minimum of 7 µs. The user should ensure this
power-up time has elapsed before initiating another conversion
Note that, after power-on, the track-and-hold is in hold mode
and the first rising edge of
places the track-and-hold
CONVST
into track mode.
as shown in Figure 39. This rising edge of
the track-and-hold back into track mode.
also places
CONVST
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate
performance because the user does not have to worry about
any power-up times associated with the AD7938-6 because it
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the AD7938-6
is powered down upon completion of the write operation, i.e.,
on rising edge of
. The track-and-hold enters hold mode at
WR
this point. The part retains the information in the control
register while the part is in shutdown. The AD7938-6 remains
in full shutdown mode and the track-and-hold in hold mode,
until the power management bits (PM1 and PM0) in the control
register are changed. If a write to the control register occurs
while the part is in full shutdown mode, and the power
management bits are changed to PM0 = PM1 = 0, i.e., normal
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7938-6 automatically enters
full shutdown at the end of each conversion, which is shown at
Point A in Figure 35 and Figure 39. In shutdown mode, all
internal circuitry on the device is powered down. The part
retains information in the control register during shutdown.
The track-and-hold also goes into hold at this point and
remains in hold as long as the device is in shutdown. The
AD7938-6 remains in shutdown mode until the next rising edge
mode, the part begins to power-up on the
rising edge and
WR
the track-and-hold returns to track. To ensure the part is fully
powered up before a conversion is initiated, the power-up time
of
(see Point B in Figure 35 or Figure 39). In order to
CONVST
of 10 ms minimum should be allowed before the next
CONVST
keep the device in shutdown for as long as possible,
CONVST
falling edge; otherwise, invalid data is read.
should idle low between conversions as shown in Figure 39. On
this rising edge, the part begins to power-up and the track-and-
hold returns to track mode. The power-up time required is
10 ms minimum regardless of whether the user is operating
with the internal or external reference. The user should ensure
that the power-up time has elapsed before initiating a
conversion.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
CLKIN
BUSY
Figure 39. Autoshutdown/Autostandby Mode
Rev. 0 | Page 25 of 32
AD7938-6
7
6
5
4
3
2
1
0
POWER VS. THROUGHPUT RATE
T
= 25°C
A
A big advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using
the different power modes, the AD7938-6 is only powered up
for the duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 40 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example,
if the maximum CLKIN frequency of 10 MHz is used to
minimize the conversion time, this accounts for only 1.315 µs
of the overall cycle time while the AD7938-6 remains in
standby mode for the remainder of the cycle. If the device
runs at a throughput rate of 10 kSPS, for example, then the
overall cycle time would be 100 µs.
V
= 5V
DD
V
= 3V
DD
0
100
200
300
400
500
600
700
THROUGHPUT (kSPS)
Figure 41. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7938-6 to ADSP-21xx Interface
Figure 41 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and
3 V. In both plots, the figures apply when using the internal
reference. If an external reference is used, the power-up time
reduces to 600 ns; therefore, the AD7938-6 remains in standby
for a greater time in every cycle. Additionally, the current
consumption, when converting, should be lower than the
specified maximum of 1.5 mA or 1.2 mA with VDD = 5 V
or 3 V, respectively.
Figure 42 shows the AD7938-6 interfaced to the ADSP-21xx
series of DSPs as a memory mapped device. A single wait state
may be necessary to interface the AD7938-6 to the ADSP-21xx
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family User’s Manual for
details). The following instruction reads from the AD7938-6:
MR = DM (ADC)
2.0
T
= 25°C
A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
where ADC is the address of the AD7938-6.
OPTIONAL
V
= 5V
DD
CONVST
A0 TO A15
ADDRESS BUS
AD7938-6*
ADSP-21xx*
DMS
ADDRESS
DECODER
CS
V
= 3V
DD
IRQ2
WR
BUSY
WR
0.4
0.2
0
RD
RD
DB0 TO DB11
0
20
40
60
80
100
120
THROUGHPUT (kSPS)
D0 TO D23
DATA BUS
Figure 40. Power vs. Throughput in Autostandby
Mode Using Internal Reference
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. Interfacing to the ADSP-21xx
Rev. 0 | Page 26 of 32
AD7938-6
OPTIONAL
AD7938-6 to ADSP-21065L Interface
Figure 43 shows a typical interface between the AD7938-6 and
the ADSP-21065L SHARC® processor. This interface is an
CONVST
A0 TO A15
ADDRESS BUS
ADDRESS
TMS32020/
TMS320C25/
TMS320C50*
AD7938-6*
example of one of three DMA handshake modes. The
MSx
control line is actually three memory select lines. Internal
ADDR25-24 are decoded into , these lines are then asserted
IS
EN
CS
DECODER
MS3-0
(DMA request 1) is used in this
READY
as chip selects. The
DMAR1
TMS320C25
ONLY
MSC
setup as the interrupt to signal the end of conversion. The rest
of the interface is standard handshaking operation.
STRB
WR
RD
R/W
OPTIONAL
INT
X
BUSY
CONVST
ADDR TO ADDR
23
ADDRESS BUS
0
DMD0 TO DMD15
DB11 TO DB0
DATA BUS
ADDRESS
LATCH
*ADDITIONAL PINS OMITTED FOR CLARITY
MS
AD7938-6*
X
ADDRESS BUS
Figure 44. Interfacing to the TMS32020/C25/C5x
ADDRESS
DECODER
ADSP-21065L*
DMAR
AD7938-6 to 80C186 Interface
CS
Figure 45 shows the AD7938-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next
conversion.
BUSY
RD
1
RD
WR
WR
DB0 TO DB11
D0 TO D31
DATA BUS
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 43. Interfacing to the ADSP-21065L
AD7938-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7938-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 44. The memory mapped address chosen for the
OPTIONAL
AD7938-6 should be chosen to fall in the I/O memory space of
the DSPs. The parallel interface on the AD7938-6 is fast enough
to interface to the TMS32020 with no extra wait states. If high
CONVST
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
ADDRESS
LATCH
AD7938-6*
ALE
speed glue logic, such as 74AS devices, are used to drive the
RD
ADDRESS BUS
and the
lines when interfacing to the TMS320C25, then
WR
ADDRESS
DECODER
80C186*
DRQ1
CS
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
User’s Guide for details).
Q
R
S
BUSY
RD
RD
WR
WR
DATA BUS
DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY
Data is read from the ADC using the following instruction
IN D, ADC
Figure 45. Interfacing to the 80C186
where D is the data memory address and ADC is the AD7938-6
address.
Rev. 0 | Page 27 of 32
AD7938-6
APPLICATION HINTS
GROUNDING AND LAYOUT
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The printed circuit board that houses the AD7938-6 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the ground pins on the
AD7938-6 as possible. Avoid running digital lines under the
device as this couples noise onto the die. The analog ground
plane should be allowed to run under the AD7938-6 to avoid
noise coupling. The power supply lines to the AD7938-6 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line.
The lands on the chip scale package (CP-32) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized. The bottom
of the chip scale package has a thermal pad. The thermal pad on
the printed circuit board should be at least as large as this
exposed pad. On the printed circuit board, there should be a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern. This ensures that shorting is
avoided. Thermal vias may be used on the printed circuit board
thermal pad to improve thermal performance of the package. If
vias are used, they should be incorporated in the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via. The user should connect the printed
circuit board thermal pad to AGND.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not always
possible with a double-sided board.
EVALUATING THE AD7938-6 PERFORMANCE
The recommended layout for the AD7938-6 is outlined in the
evaluation board documentation. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from
the PC via the evaluation board controller. The evaluation
board controller can be used in conjunction with the AD7938-6
evaluation board, as well as many other ADI evaluation boards
ending in the CB designator, to demonstrate/evaluate the ac and
dc performance of the AD7938-6.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7938-6.
The software and documentation are on the CD that ships with
the evaluation board.
Rev. 0 | Page 28 of 32
AD7938-6
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
4.75
BSC SQ
TOP
BOTTOM
VIEW
VIEW
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32-2)
Dimensions shown in millimeters
1.20
MAX
9.00 SQ
0.75
0.60
0.45
25
32
1
24
PIN 1
7.00
SQ
TOP VIEW
(PINS DOWN)
VIEW A
0° MIN
1.05
1.00
0.95
0.20
0.09
8
17
9
16
7°
3.5°
0°
0.08 MAX
COPLANARITY
0.80
BSC
0.45
0.37
0.30
0.15
0.05
SEATING
PLANE
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 47. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
Rev. 0 | Page 29 of 32
AD7938-6
ORDERING GUIDE
Model
AD7938BCP-6
AD7938BCP-6REEL7
AD7938BCPZ-62
AD7938BCPZ-6REEL72
Temperature Range
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
Linearity Error (LSB)1
Package Descriptions
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
Package Option
CP-32-2
CP-32-2
CP-32-2
CP-32-2
SU-32-2
SU-32-2
SU-32-2
SU-32-2
1
1
1
1
1
1
1
1
1
AD7938BSU-6
AD7938BSU-6REEL
AD7938BSU-6REEL7
AD7938BSUZ-62
AD7938BSUZ-6REEL72
EVAL-AD7938-6CB3
EVAL-CONTROL BRD24
SU-32-2
Evaluation Board
Controller Board
1 Linearity error here refers to integral linearity error.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
4 Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB
designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (e.g. EVAL-AD7938-6CB), the EVAL-CONTROL BRD2 and
a 12 V ac transformer. See relevant evaluation board technical note for more details.
Rev. 0 | Page 30 of 32
AD7938-6
NOTES
Rev. 0 | Page 31 of 32
AD7938-6
NOTES
©2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04751–0–10/04(0)
Rev. 0 | Page 32 of 32
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