AD7951_技术文档

16-Bit, 250 kSPS, Unipolar/Bipolar

Programmable Input PulSAR^®ADC

AD7610

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Multiple pins/software programmable input ranges:

TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND

5 V, 10 V, 5 V, 10 V

Pins or serial SPI®-compatible input ranges/mode selection

Throughput: 250 kSPS

16-bit resolution with no missing codes

INL: 0.75 LSB typ, 1.5 LSB max ( 23 ppm of FSR)

SNR: 94 dB @ 2 kHz

iCMOS® process technology

5 V internal reference: typical drift 3 ppm/°C;

On-chip temperature sensor

No pipeline delay (SAR architecture)

Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface

SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

Power dissipation

OVDD

AGND

AD7610

REF

AMP

OGND

AVDD

PDREF

PDBUF

IN+

SERIAL

DATAPORT

REF

SERIAL

CONFIGURATION

PORT

16

SWITCHED

CAP DAC

D[15:0]

IN–

SER/PAR

BYTESWAP

OB/2C

PARALLEL

INTERFACE

CLOCK

CNVST

PD

BUSY

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

RD

CS

RESET

BIPOLAR TEN

Figure 1.

90 mW @ 250 kSPS

10 mW @ 1 kSPS

48-lead LQFP and LFCSP (7 mm × 7 mm) packages

APPLICATIONS

Process control

Medical instruments

High speed data acquisition

Digital signal processing

Instrumentation

Spectrum analysis

ATE

GENERAL DESCRIPTION

Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection

The AD7610 is a 16-bit charge redistribution successive approxi-

mation register (SAR), architecture analog-to-digital converter

(ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage

process. The device is configured through hardware or via a

dedicated write only serial configuration port for input range

and operating mode. The AD7610 contains a high speed 16-bit

sampling ADC, an internal conversion clock, an internal reference

(and buffer), error correction circuits, and both serial and parallel

100 kSPS to

250 kSPS

500 kSPS to

570 kSPS

800 kSPS to

1000 kSPS

>1000

kSPS

Type

Pseudo

Differential

AD7651

AD7660

AD7661

AD7650

AD7652

AD7664

AD7666

AD7653

AD7667

True Bipolar

AD7610

AD7663

AD7665

AD7676

AD7679

AD7612

AD7671

AD7951

True

Differential

AD7675

AD7678

AD7677

AD7621

AD7622

AD7623

CNVST

system interface ports. A falling edge on

samples the

analog input on IN+ with respect to a ground sense, IN−. The

AD7610 features four different analog input ranges: 0 V to 5 V, 0 V

t o 1 0 V, 5 V, a nd 1 0 V. Po w e r c o n s u m p t i o n i s s c a l e d l i n e a r l y

with throughput. The device is available in Pb-free 48-lead, low-

profile quad flat package (LQFP) and a lead frame chip-scale

(LFCSP_VQ) package. Operation is specified from −40°C to

+85°C.

18-Bit, True

Differential

AD7674

AD7641

AD7643

Multichannel/

Simultaneous

AD7654

AD7655

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7610

TABLE OF CONTENTS

Features .............................................................................................. 1

Driver Amplifier Choice ........................................................... 20

Voltage Reference Input/Output .............................................. 20

Power Supplies............................................................................ 21

Conversion Control ................................................................... 22

Interfaces.......................................................................................... 23

Digital Interface.......................................................................... 23

Parallel Interface......................................................................... 23

Serial Interface............................................................................ 24

Master Serial Interface............................................................... 24

Slave Serial Interface .................................................................. 26

Hardware Configuration........................................................... 28

Software Configuration............................................................. 28

Microprocessor Interfacing....................................................... 29

Application Information................................................................ 30

Layout Guidelines....................................................................... 30

Evaluating Performance ............................................................ 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

Overview...................................................................................... 16

Converter Operation.................................................................. 16

Transfer Functions...................................................................... 17

Typical Connection Diagram ................................................... 18

Analog Inputs.............................................................................. 19

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7610

SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V_REF= 5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

16

Bits

ANALOG INPUT

Voltage Range, V_IN

V_IN+− V_IN−= 0 V to 5 V

V_IN+− V_IN−= 0 V to 10 V

−0.1

−5.1

−10.1

−0.1

+5.1

+10.1

+5.1

+10.1

+0.1

V

dB

μA

V_IN+− V_IN−

=

5 V

10 V

V_IN−to AGND

f_IN= 100 kHz

V_IN= 5 V, 10 V @ 250 kSPS

See Analog Inputs section

Analog Input CMRR

Input Current

Input Impedance

75

100¹

THROUGHPUT SPEED

Complete Cycle

4

ꢀs

Throughput Rate

250

kSPS

DC ACCURACY

Integral Linearity Error²

No Missing Codes²

−1.5

16

−1

0.75

+1.5

+35

LSB³

Bits

LSB

ppm/°C

LSB

ppm/°C

LSB

Differential Linearity Error²

Transition Noise

0.55

1

Zero Error (Unipolar or Bipolar)

Zero Error Temperature Drift

Bipolar Full-Scale Error

Unipolar Full-Scale Error

Full-Scale Error Temperature Drift

Power Supply Sensitivity

AC ACCURACY

−35

−50

−70

+50

+70

1

3

AVDD = 5 V 5ꢁ

Dynamic Range

V_IN= 0 V to 5 V, f_IN= 2 kHz, −60 dB

V_IN= 0 V to 10 V, 5 V, f_IN= 2 kHz, −60 dB

V_IN= 10 V, f_IN= 2 kHz, −60 dB

V_IN= 0 V to 5 V, 0 V to 10 V, f_IN= 2 kHz

V_IN= 5 V, 10 V, f_IN= 2 kHz

V_IN= 0 V to 5 V, f_IN= 20 kHz

V_IN= 5 V, f_IN= 2 kHz

V_IN= 0 V to 10 V, 5 V, f_IN= 2 kHz

V_IN= 10 V, f_IN= 2 kHz

f_IN= 2 kHz

92.5

92

93.5

94

94.5

93

dB⁴

dB

kHz

ns

Signal-to-Noise Ratio

94

93.5

92.5

93

93.5

−107

107

650

2

Signal-to-(Noise + Distortion) (SINAD)

Total Harmonic Distortion

Spurious-Free Dynamic Range

–3 dB Input Bandwidth

Aperture Delay

f_IN= 2 kHz

V_IN= 0 V to 5 V

Aperture Jitter

5

ps rms

ns

Transient Response

INTERNAL REFERENCE

Output Voltage

Temperature Drift

Line Regulation

Full-scale step

PDREF = PDBUF = low

REF @ 25°C

–40°C to +85°C

AVDD = 5 V 5ꢁ

1000 hours

500

4.965

5.000

3

5.035

V

ppm/°C

ppm/V

ppm

ms

15

Long-Term Drift

50

10

Turn-On Settling Time

REFERENCE BUFFER

REFBUFIN Input Voltage Range

C_REF= 22 μF

PDREF = high

2.4

2.5

2.6

V

Rev. 0 | Page 3 of 32

AD7610

Parameter

EXTERNAL REFERENCE

Voltage Range

Conditions/Comments

PDREF = PDBUF = high

REF

Min

Typ

Max

Unit

4.75

5

AVDD + 0.1

V

Current Drain

250 kSPS throughput

30

μA

TEMPERATURE PIN

Voltage Output

Temperature Sensitivity

Output Resistance

@ 25°C

311

1

4.33

mV

mV/°C

kΩ

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

I_IH

−0.3

2.1

−1

+0.6

OVDD + 0.3

+1

V

μA

−1

DIGITAL OUTPUTS

Data Format

Pipeline Delay⁵

Parallel or serial 16-bit

V_OL

V_OH

I_SINK= 500 μA

I_SOURCE= –500 μA

0.4

V

OVDD − 0.6

POWER SUPPLIES

Specified Performance

AVDD

DVDD

OVDD

4.75⁶

4.75

2.7

5

5.25

15.75

0

V

VCC

7

15

−15

VEE

−15.75

Operating Current^{7, 8}

@ 250 kSPS throughput

AVDD

With Internal Reference

With Internal Reference Disabled

DVDD

OVDD

VCC

8

mA

6.3

3.3

0.3

1.4

0.8

0.7

VCC = 15 V, with internal reference buffer

VCC = 15 V

VEE = −15 V

VEE

Power Dissipation

@ 250 kSPS throughput

PDREF = PDBUF = low

PDREF = PDBUF = high

PD = high

With Internal Reference

With Internal Reference Disabled

In Power-Down Mode⁹

TEMPERATURE RANGE¹⁰

Specified Performance

90

70

10

110

90

mW

μW

T_MINto T_MAX

−40

+85

°C

¹With V_IN= 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 ꢀA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.

²Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.

³LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.

⁴All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

⁵Conversion results are available immediately after completed conversion.

⁶4.75 V or V_REF– 0.1 V, whichever is larger.

⁷Tested in parallel reading mode.

⁸With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.

⁹With all digital inputs forced to OVDD.

¹⁰Consult sales for extended temperature range.

Rev. 0 | Page 4 of 32

AD7610

TIMING SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V_REF= 5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION AND RESET (See Figure 33 and Figure 34)

Convert Pulse Width

Time Between Conversions

CNVST Low to BUSY High Delay

BUSY High (Except Master Serial Read After Convert)

Aperture Delay

End of Conversion to BUSY Low Delay

Conversion Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

10

4

ns

μs

ns

μs

ns

μs

ns

35

1.45

2

10

1.45

Acquisition Time

RESET Pulse Width

380

10

PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)

CNVST Low to DATA Valid Delay

DATA Valid to BUSY Low Delay

Bus Access Request to DATA Valid

Bus Relinquish Time

t₁₀

t₁₁

t₁₂

t₁₃

1.41

μs

ns

20

2

40

15

MASTER SERIAL INTERFACE MODES¹(See Figure 39 and Figure 40)

CS Low to SYNC Valid Delay

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

t₃₀

10

ns

CS Low to Internal SDCLK Valid Delay¹

CS Low to SDOUT Delay

CNVST Low to SYNC Delay, Read During Convert

SYNC Asserted to SDCLK First Edge Delay

Internal SDCLK Period²

560

3

30

15

10

4

5

45

Internal SDCLK High²

Internal SDCLK Low²

SDOUT Valid Setup Time²

SDOUT Valid Hold Time²

SDCLK Last Edge to SYNC Delay²

CS High to SYNC HI-Z

10

CS High to Internal SDCLK HI-Z

CS High to SDOUT HI-Z

BUSY High in Master Serial Read After Convert²

CNVST Low to SYNC Delay, Read After Convert

SYNC Deasserted to BUSY Low Delay

See Table 4

1.31

μs

ns

25

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES¹(See Figure 42,

Figure 43, and Figure 45)

External SDCLK, SCCLK Setup Time

External SDCLK Active Edge to SDOUT Delay

SDIN/SCIN Setup Time

t₃₁

t₃₂

t₃₃

t₃₄

t₃₅

t₃₆

t₃₇

5

2

5

25

10

ns

18

SDIN/SCIN Hold Time

External SDCLK/SCCLK Period

External SDCLK/SCCLK High

External SDCLK/SCCLK Low

¹In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C_Lof 10 pF; otherwise, the load is 60 pF maximum.

²In serial master read during convert mode. See Table 4 for serial mode read after convert mode.

Rev. 0 | Page 5 of 32

AD7610

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

0

1

DIVSCLK[0]

Symbol

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

0

1

0

1

Unit

ns

SYNC to SDCLK First Edge Delay Minimum

Internal SDCLK Period Minimum

Internal SDCLK Period Maximum

Internal SDCLK High Minimum

Internal SDCLK Low Minimum

SDOUT Valid Setup Time Minimum

SDOUT Valid Hold Time Minimum

SDCLK Last Edge to SYNC Delay Minimum

BUSY High Width Maximum

3

20

60

90

30

25

20

8

20

120

180

60

55

20

35

4.40

20

30

45

15

10

4

5

2.25

240

360

120

115

20

90

7.30

7

3.00

t₂₈

μs

1.6mA

I

OL

TO OUTPUT

1.4V

C

L

60pF

2V

500µA

I

OH

0.8V

t_DELAY

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT ARE DEFINED WITH A MAXIMUM LOAD

2V

0.8V

2V

0.8V

C

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

L

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C_L= 10 pF

Figure 3. Voltage Reference Levels for Timing

Rev. 0 | Page 6 of 32

AD7610

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

Analog Inputs/Outputs

IN+, IN−¹to AGND

REF, REFBUFIN, TEMP,

REFGND to AGND

Ground Voltage Differences

AGND, DGND, OGND

Supply Voltages

VEE − 0.3 V to VCC + 0.3 V

AVDD + 0.3 V to

AGND − 0.3 V

0.3 V

ESD CAUTION

AVDD, DVDD, OVDD

AVDD to DVDD, AVDD to OVDD

DVDD to OVDD

−0.3 V to +7 V

7 V

VCC to AGND, DGND

VEE to GND

Digital Inputs

PDREF, PDBUF²

–0.3 V to +16.5 V

+0.3 V to −16.5 V

−0.3 V to OVDD +0.3 V

20 mA

Internal Power Dissipation³

Internal Power Dissipation⁴

Junction Temperature

Storage Temperature Range

700 mW

2.5 W

125°C

−65°C to +125°C

¹See the Analog Inputs section.

²See the Voltage Reference Input section.

³Specification is for the device in free air: 48-Lead LQFP; θ_JA= 91°C/W,

θ_JC= 30°C/W.

⁴Specification is for the device in free air: 48-Lead LFCSP; θ_JA= 26°C/W.

Rev. 0 | Page 7 of 32

AD7610

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

AGND

AVDD

BIPOLAR

CNVST

PD

PIN 1

AGND

3

BYTESWAP

OB/2C

4

RESET

CS

5

AD7610

TOP VIEW

(Not to Scale)

OGND

6

RD

OGND

7

TEN

8

SER/PAR

BUSY

9

D15/SCCS

D14/SCCLK

D13/SCIN

D12/HW/SW

D0

D1

10

11

12

D2/DIVSCLK[0]

D3/DIVSCLK[1]

13 14 15 16 17 18 19 20 21 22 23 24

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

Description

1, 3, 42

AGND

P

Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to

AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and

OGND voltages should be at the same potential.

2, 44

4

AVDD

BYTESWAP

P

DI

Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 ꢀF and 100 nF capacitors.

Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on

D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

5

2C

DI²

P

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low,

the MSB is inverted resulting in a twos complement output from its internal shift register.

Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be

connected to the system digital ground ideally at the same potential as AGND and DGND.

OB/

6, 7, 17

8

OGND

PAR

SER/

DI

Serial/Parallel Selection Input.

PAR

When SER/

= low, the parallel mode is selected.

PAR

When SER/

= high, the serial modes are selected. Some bits of the data bus are used as a serial port and

the remaining data bits are high impedance outputs.

9, 10

D[0:1]

DO

Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of

PAR

SER/

.

11, 12

D[2:3] or

DI/O

In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

DIVSCLK[0:1]

PAR

Serial Data Division Clock Selection. In serial master read after convert mode (SER/

= high,

INT

EXT/

= low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data

clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

13

D4 or

INT

EXT/

DI/O

In parallel mode, this output is used as Bit 4 of the parallel port data output bus.

Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or

external (slave) serial data clock for the AD7610 output data.

INT

When EXT/

= low, master mode; the internal serial data clock is selected on SDCLK output.

INT

When EXT/

CS

)

= high, slave mode; the output data is synchronized to an external clock signal (gated by

connected to the SDCLK input.

Rev. 0 | Page 8 of 32

AD7610

Pin No.

Mnemonic

D5 or

Type¹

Description

14

DI/O

In parallel mode, this output is used as Bit 5 of the parallel port data output bus.

INVSYNC

PAR

INT

= high, EXT/

Serial Data Invert Sync Select. In serial master mode (SER/

= low). This input is used to

select the active state of the SYNC signal.

When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

15

16

D6 or

INVSCLK

DI/O

In parallel mode, this output is used as Bit 6 of the parallel port data output bus.

In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.

When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.

When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

In parallel mode, this output is used as Bit 7 of the parallel port data output bus.

D7 or

RDC or

PAR

INT

= high, EXT/

Serial Data Read During Convert. In serial master mode (SER/

= low) RDC is used to select

the read mode. See the Master Serial Interface section.

When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable

in this mode.

When RDC = high, the previous conversion result is read during the current conversion.

SDIN

PAR

INT

= high EXT/ = high) SDIN can be used as a data input to daisy-

Serial Data In. In serial slave mode (SER/

chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is

output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.

18

19

20

21

OVDD

DVDD

DGND

P

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3

V, or 5 V and decoupled with 10 μF and 100 nF capacitors.

Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied

from AVDD.

Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital

ground ideally at the same potential as AGND and OGND.

In parallel mode, this output is used as Bit 8 of the parallel port data output bus.

P

D8 or

DO

SDOUT

Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.

Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first,

2C

from its internal shift register. The data format is determined by the logic level of OB/

.

INT

When EXT/

= low, (master mode) SDOUT is valid on both edges of SDCLK.

= high (slave mode).

When INVSCLK = low, SDOUT is updated on SDCLK rising edge.

When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

22

23

D9 or

SDCLK

DI/O

DO

In parallel mode, this output is used as Bit 9 of the parallel port data output bus.

Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the

INT

logic state of the EXT/

pin. The active edge where the data SDOUT is updated depends on the logic state of

the INVSCLK pin.

D10 or

SYNC

In parallel mode, this output is used as Bit 10 of the parallel port data output bus.

PAR INT

Serial Data Frame Synchronization. In serial master mode (SER/

= high, EXT/ = low), this output is used

as a digital output frame synchronization for use with the internal data clock.

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT

output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT

output is valid.

24

25

D11 or

RDERROR

DO

In parallel mode, this output is used as Bit 11 of the parallel port data output bus.

PAR

Serial Data Read Error. In serial slave mode (SER/

INT

= high, EXT/

= high), this output is used as an

incomplete data read error flag. If a data read is started and not completed when the current conversion is

complete, the current data is lost and RDERROR is pulsed high.

In parallel mode, this output is used as Bit 12 of the parallel port data output bus.

D12 or

DI/O

SW

HW/

Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by

hardware or software. See the Hardware Configuration section and Software Configuration section.

SW

When HW/ = low, the AD7610 is configured through software using the serial configuration register.

SW

When HW/

= high, the AD7610 is configured through dedicated hardware input pins.

26

D13 or

SCIN

DI/O

In parallel mode, this output is used as Bit 13 of the parallel port data output bus.

PAR

SW

= high, HW/

Serial Configuration Data Input. In serial software configuration mode (SER/

= low) this

input is used to serially write in, MSB first, the configuration data into the serial configuration register. The

data on this input is latched with SCCLK. See the Software Configuration section.

Rev. 0 | Page 9 of 32

AD7610

Pin No.

Mnemonic

Type¹

Description

27

D14 or

SCCLK

DI/O

In parallel mode, this output is used as Bit 14 of the parallel port data output bus.

PAR

SW

= high, HW/

Serial Configuration Clock. In serial software configuration mode (SER/

= low) this input is

used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state

of the INVSCLK pin. See the Software Configuration section.

28

29

D15 or

SCCS

DI/O

DO

In parallel mode, this output is used as Bit 15 of the parallel port data output bus.

PAR

SW

= high, HW/

Serial Configuration Chip Select. In serial software configuration mode (SER/

= low) this

input enables the serial configuration port. See the Software Configuration section.

Busy Output. Transitions high when a conversion is started, and remains high until the conversion

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be

BUSY

PAR

INT

= high, EXT/

used as a data ready clock signal. Note that in master read after convert mode (SER/

= low,

RDC = low) the busy time changes according to Table 4.

Input Range Select. Used in conjunction with BIPOLAR per the following:

30

TEN

DI²

Input Range

0 V to 5 V

0 V to 10 V

5 V

BIPOLAR

Low

High

TEN

Low

High

Low

High

10 V

31

32

RD

CS

DI

CS RD

Read Data. When and

are both low, the interface parallel or serial output bus is enabled.

CS

Chip Select. When and

RD

CS

are both low, the interface parallel or serial output bus is enabled. is also

used to gate the external clock in slave serial mode (not used for serial programmable port).

33

RESET

DI

Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET

2C

resets the data outputs to all zero’s (with OB/ = high) and clears the configuration register. See the Digital

Interface section. If not used, this pin can be tied to OGND.

Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions

are inhibited after the current one is completed. The digital interface remains active during power down.

34

35

PD

DI²

DI

CNVST

puts the internal sample-and-hold into the hold state and initiates

Conversion Start. A falling edge on

a conversion.

36

37

BIPOLAR

REF

DI²

Input Range Select. See description for Pin 30.

AI/O

Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V

on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally

supplied voltage reference up to AVDD volts. Decoupling with at least a 22 ꢀF is required with or without the

internal reference and buffer. See the Reference Decoupling section.

38

39

40

41

43

45

REFGND

IN−

VCC

VEE

IN+

AI

P

AI

AO

Reference Input Analog Ground. Connected to analog ground plane.

Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.

High Voltage Positive Supply. Normally +7 V to +15 V.

High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).

Analog Input. Referenced to IN−.

TEMP

Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF =

low). See the Temperature Sensor section.

46

47

REFBUFIN

PDREF

AI

DI

Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,

PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section.

Internal Reference Power-Down Input.

When low, the internal reference is enabled.

When high, the internal reference is powered down, and an external reference must be used.

48

PDBUF

DI

Internal Reference Buffer Power-Down Input.

When low, the buffer is enabled (must be low when using internal reference).

When high, the buffer is powered-down.

¹AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

2

PAR

In serial configuration mode (SER/

SW

= high, HW/

= low), this input is programmed with the serial configuration register and this pin is a don’t care. See the

Hardware Configuration section and Software Configuration section.

Rev. 0 | Page 10 of 32

AD7610

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; V_REF= 5 V; T_A= 25°C.

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

0

16384

32768

CODE

49152

65536

0

16384

32768

CODE

49152

65536

Figure 5. Integral Nonlinearity vs. Code

Figure 8. Differential Nonlinearity vs. Code

250

200

150

100

50

180

NEGATIVE INL

POSITIVE INL

NEGATIVE DNL

POSITIVE DNL

160

140

120

100

80

60

40

20

0

–1.0 –0.8 –0.6 –0.4 –0.2

0

0.2

0.4

0.6

0.8

1.0

–1.0 –0.8 –0.6 –0.4 –0.2

0

0.2

0.4

0.6

0.8

1.0

INL DISTRIBUTION (LSB)

DNL DISTRIBUTION (LSB)

Figure 6. Integral Nonlinearity Distribution (296 Devices)

Figure 9. Differential Nonlinearity Distribution (296 Devices)

250000

140000

132700

σ = 0.44

σ = 0.51

127179

211404

120000

100000

80000

60000

40000

20000

0

200000

150000

100000

50000

0

27510

8002

22202

8004

1072

8002

0

4

0

169

8000

8001

8003

8004

8005

8006

8007

7FFF 8000

8001

8003

8005

8006

CODE IN HEX

Figure 7. Histogram of 261,120 Conversions of a DC Input

at the Code Center

Figure 10. Histogram of 261,120 Conversions of a DC Input

at the Code Transition

Rev. 0 | Page 11 of 32

AD7610

95.0

94.5

94.0

93.5

93.0

0

f_S= 250kSPS

f_IN= 19.95kHz

SNR = 93.4dB

THD = –107dB

SFDR = 114dB

SINAD = 93dB

SNR

SINAD

–20

±10V

±5V

–40

–60

–80

0V TO 10V

0V TO 5V

–100

–120

–140

–160

0

–60

–50

–40

–30

–20

–10

0

25

50

75

100

125

FREQUENCY (kHz)

INPUT LEVEL (dB)

Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)

Figure 11. FFT 20 kHz

–70

120

110

100

90

96

94

92

90

88

86

84

82

16.0

15.8

15.6

15.4

15.2

15.0

14.8

14.6

14.4

SNR

–80

–90

SINAD

SFDR

THD

ENOB

–100

–110

–120

–130

THIRD

HARMONIC

80

SECOND

HARMONIC

70

60

100

80

1

10

100

1

10

FREQUENCY (kHz)

Figure 15. THD, Harmonics, and SFDR vs. Frequency

Figure 12. SNR, SINAD, and ENOB vs. Frequency

96

95

94

93

92

91

90

96

95

94

93

92

91

VIN = 0V TO 5V

VIN = 0V TO 10V

VIN = ±5V

VIN = 0V TO 5V

VIN = 0V TO 10V

VIN = ±5V

VIN = ±10V

90

–55

–35

–15

5

25

45

65

85

105

125

–35

–15

5

25

45

65

85

105

125

TEMPERATURE (°C)

Figure 16. SINAD vs. Temperature

Figure 13. SNR vs. Temperature

Rev. 0 | Page 12 of 32

AD7610

–96

–100

–104

–108

–112

–116

–120

–124

126

124

122

120

118

116

114

112

110

108

VIN = 0V TO 5V

VIN = 0V TO 10V

VIN = ±5V

VIN = 0V TO 5V

VIN = 0V TO 10V

VIN = ±5V

VIN = ±10V

–55

–35

–15

5

25

45

65

85

105

125

–55

–35

–15

5

25

45

65

85

105

125

TEMPERATURE (°C)

Figure 17. THD vs. Temperature

Figure 20. SFDR vs. Temperature (Excludes Harmonics)

5

4

5.012

ZERO ERROR

POSITIVE FS ERROR

NEGATIVE FS ERROR

5.010

5.008

5.006

5.004

5.002

5.000

4.998

4.996

3

2

1

0

–1

–2

–3

–4

–5

–55

–35

–15

5

25

45

65

85

105

125

–55

–35

–15

5

25

45

65

85

105

125

TEMPERATURE (°C)

Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature

Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)

100000

60

10000

DVDD

50

40

30

20

10

0

1000

100

AVDD

10

1

VCC +15V

VEE –15V

ALL MODES

0.1

OVDD

0.01

PDREF = PDBUF = HIGH

0.001

10

100

1000

10000

100000

1000000

0

1

2

3

4

5

6

7

8

SAMPLING RATE (SPS)

REFERENCE DRIFT (ppm/°C)

Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)

Figure 22. Operating Currents vs. Sample Rate

Rev. 0 | Page 13 of 32

AD7610

50

45

40

35

30

25

20

15

10

5

700

PD = PDBUF = PDREF = HIGH

OVDD = 2.7V @ 85°C

OVDD = 2.7V @ 25°C

VEE = –15V

VCC = +15V

DVDD

OVDD

AVDD

600

500

400

300

200

100

0

OVDD = 5V @ 85°C

OVDD = 5V @ 25°C

0

50

100

(pF)

150

200

–55

–35

–15

5

25

45

65

85

105

TEMPERATURE (°C)

C

L

Figure 23. Power-Down Operating Currents vs. Temperature

Figure 24. Typical Delay vs. Load Capacitance C_L

Rev. 0 | Page 14 of 32

AD7610

TERMINOLOGY

Least Significant Bit (LSB)

Total Harmonic Distortion (THD)

The least significant bit, or LSB, is the smallest increment that

can be represented by a converter. For an analog-to-digital con-

verter with N bits of resolution, the LSB expressed in volts is

THD is the ratio of the rms sum of the first five harmonic

components to the rms value of a full-scale input signal and

is expressed in decibels.

V

_INp-p(max)

Signal-to-(Noise + Distortion) Ratio (SINAD)

LSB(V) =

2^N

SINAD is the ratio of the rms value of the actual input signal to

the rms sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code

from a line drawn from negative full-scale through positive full-

scale. The point used as negative full-scale occurs a ½ LSB before

the first code transition. Positive full-scale is defined as a level

1½ LSBs beyond the last code transition. The deviation is meas-

ured from the middle of each code to the true straight line.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of

the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave

input. It is related to SINAD and is expressed in bits by

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential

nonlinearity is the maximum deviation from this ideal value. It

is often specified in terms of resolution for which no missing

codes are guaranteed.

ENOB = [(SINAD_dB− 1.76)/6.02]

Aperture Delay

Aperture delay is a measure of the acquisition performance

Bipolar Zero Error

The difference between the ideal midscale input voltage (0 V)

and the actual voltage producing the midscale output code.

CNVST

measured from the falling edge of the

input to when

the input signal is held for a conversion.

Transient Response

The time required for the AD7610 to achieve its rated accuracy

after a full-scale step function is applied to its input.

Unipolar Offset Error

The first transition should occur at a level ½ LSB above analog

ground. The unipolar offset error is the deviation of the actual

transition from that point.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the

typical shift of output voltage at 25°C on a sample of parts at the

maximum and minimum reference output voltage (V_REF) meas-

ured at T_MIN, T(25°C), and T_MAX. It is expressed in ppm/°C as

Full-Scale Error

The last transition (from 111…10 to 111…11) should occur for

an analog voltage 1½ LSB below the nominal full-scale. The full-

scale error is the deviation in LSB (or % of full-scale range) of

the actual level of the last transition from the ideal level and

includes the effect of the offset error. Closely related is the gain

error (also in LSB or % of full-scale range), which does not

include the effects of the offset error.

V_REF(Max)–V_REF(Min)

TCV_REF(ppm/°C) =

×10⁶

V_REF(25°C) × (T_MAX–T_MIN

)

where:

V

_REF(Max) = maximum V_REFat T_MIN, T(25°C), or T_MAX.

Dynamic Range

_REF(Min) = minimum V_REFat T_MIN, T(25°C), or T_MAX

.

Dynamic range is the ratio of the rms value of the full-scale to

the rms noise measured for an input typically at −60 dB. The

value for dynamic range is expressed in decibels.

_REF(25°C) = V_REFat 25°C.

T

_MAX= +85°C.

_MIN= –40°C.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Rev. 0 | Page 15 of 32

AD7610

THEORY OF OPERATION

IN+

REF

REFGND

SWITCHES

CONTROL

SW

MSB

32,768C 16,384C

LSB

A

4C

2C

C

BUSY

CONTROL

LOGIC

COMP

OUTPUT

CODE

IN–

65,536C

SW

B

CNVST

Figure 25. ADC Simplified Schematic

OVERVIEW

CONVERTER OPERATION

The AD7610 is a very fast, low power, precise, 16-bit analog-to-

digital converter (ADC) using successive approximation capacitive

digital-to-analog converter (CDAC) architecture.

The AD7610 is a successive approximation ADC based on a

charge redistribution DAC. Figure 25 shows the simplified

schematic of the ADC. The CDAC consists of two identical

arrays of 16 binary weighted capacitors, which are connected

to the two comparator inputs.

The AD7610 can be configured at any time for one of four input

ranges with inputs in parallel and serial hardware modes or by a

dedicated write only, SPI-compatible interface via a configure-

tion register in serial software mode. The AD7610 uses Analog

Device’s patented iCMOS high voltage process to accommodate

0 to 5 V, 0 to 10 V, 5 V, and 10 V input ranges without the use

of conventional thin films. Only one acquisition cycle, t₈, is required

for the inputs to latch to the correct configuration. Resetting or

power cycling is not required for reconfiguring the ADC.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on IN+ and IN− inputs. A conversion

phase is initiated once the acquisition phase is complete and the

CNVST

input goes low. When the conversion phase begins, SW+

and SW− are opened first. The two capacitor arrays are then

disconnected from the inputs and connected to the REFGND

input. Therefore, the differential voltage between the inputs (IN+

and IN−) captured at the end of the acquisition phase is applied

to the comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between REFGND and REF, the comparator input varies by

binary weighted voltage steps (V_REF/2, V_REF/4 through V_REF/65536).

The control logic toggles these switches, starting with the MSB

first, in order to bring the comparator back into a balanced

condition.

The AD7610 is capable of converting 250,000 samples per

second (250 kSPS) and power consumption scales linearly with

throughput making it useful for battery powered systems.

The AD7610 provides the user with an on-chip track-and-hold,

successive approximation ADC that does not exhibit any pipe-

line or latency, making it ideal for multiple multiplexed channel

applications.

For unipolar input ranges, the AD7610 typically requires three

supplies; VCC, AVDD (which can supply DVDD), and OVDD

which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic.

For bipolar input ranges, the AD7610 requires the use of the

additional VEE supply.

After the completion of this process, the control logic generates

the ADC output code and brings the BUSY output low.

The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP

7 mm × 7 mm packages that combine space savings with flexi-

bility. In addition, the AD7610 can be configured as either a

parallel or serial SPI-compatible interface.

Rev. 0 | Page 16 of 32

AD7610

TRANSFER FUNCTIONS

111...111

111...110

111...101

2C

Using the OB/ digital input or via the configuration register,

the AD7610 offers two output codings: straight binary and twos

complement. See Figure 26 and Table 7 for the ideal transfer char-

acteristic and digital output codes for the different analog input

ranges, V_IN. Note that when using the configuration register, the

2C

OB/ input is a don’t care and should be tied to either high or low.

000...010

000...001

000...000

–FSR + 1 LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

ANALOG INPUT

–FSR

–FSR + 0.5 LSB

Figure 26. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

V_REF= 5 V

Digital Output Code

Straight Binary Twos Complement

Description

FSR −1 LSB

FSR − 2 LSB

Midscale + 1 LSB

Midscale

Midscale − 1 LSB

−FSR + 1 LSB

−FSR

V_IN= 5 V

4.999924 V

4.999847 V

2.500076 V

2.5 V

2.499924 V

76.3 μV

0 V

V_IN= 10 V

9.999847 V

9.999695 V

5.000153 V

5.000000 V

4.999847 V

152.6 μV

V_IN

=

5 V

V_IN= 10 V

+4.999847 V

+4.999695 V

+152.6 μV

0 V

−152.6 μV

−4.999847 V

−5 V

+9.999695 V

+9.999390 V

+305.2 μV

0 V

−305.2 μV

−9.999695 V

−10 V

0xFFFF¹

0xFFFE

0x8001

0x8000

0x7FFF

0x0001

0x0000²

0x7FFF¹

0x7FFE

0x0001

0x0000

0xFFFF

0x8001

0x8000²

0 V

¹This is also the code for overrange analog input (V_IN+− V_IN−above V_REF− V_REFGND).

²This is also the code for overrange analog input (V_IN+− V_IN−below V_REF− V_REFGND).

Rev. 0 | Page 17 of 32

AD7610

TYPICAL CONNECTION DIAGRAM

Figure 27 shows a typical connection diagram for the AD7610 using the internal reference, serial data and serial configuration interfaces.

Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.

DIGITAL

SUPPLY (+5V)

NOTE 5

DIGITAL

10Ω

INTERFACE

SUPPLY

ANALOG

SUPPLY (+5V)

(+2.5V, +3.3V, OR +5V)

100nF

10µF

100nF

10µF

AVDD AGND DGND

VCC

DVDD

OVDD

OGND

+7V TO +15.75V

SUPPLY

MICROCONVERTER/

BUSY

100nF

MICROPROCESSOR/

DSP

10µF

SDCLK

SDOUT

SERIAL

PORT 1

100nF

SCCLK

–7V TO –15.75V

SUPPLY

SERIAL

PORT 2

VEE

SCIN

NOTE 6

NOTE 3

REF

SCCS

C

REF

22µF

REFBUFIN

REFGND

NOTE 7

NOTE 4

50Ω

100nF

D

CNVST

AD7610

OB/2C

NOTE 2

U1

OVDD

SER/PAR

15Ω

IN+

HW/SW

ANALOG

INPUT +

BIPOLAR

C

2.7nF

C

TEN

CLOCK

ANALOG

INPUT–

IN–

NOTE 3

PDREF PDBUF

NOTE 1

PD

RD

CS RESET

NOTES

1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V.

2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.

4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).

SEE VOLTAGE REFERENCE INPUT SECTION.

5. OPTION, SEE POWER SUPPLY SECTION.

6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES.

FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION.

7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.

Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port

Rev. 0 | Page 18 of 32

AD7610

For instance, by using IN− to sense a remote signal ground,

ground potential differences between the sensor and the local

ADC ground are eliminated.

ANALOG INPUTS

Input Range Selection

In parallel mode and serial hardware mode, the input range is

selected by using the BIPOLAR (bipolar) and TEN (10 Volt range)

inputs. See Table 6 for pin details and the Hardware

Configuration section and Software Configuration section for

programming the mode selection with either pins or configuration

register. Note that when using the configuration register, the

BIPOLAR and TEN inputs are don’t cares and should be tied to

either high or low.

100

90

80

70

60

50

40

30

20

10

0

Input Structure

Figure 28 shows an equivalent circuit for the input structure of

the AD7610.

0 TO 5V

RANGE ONLY

1

10

100

1000

10000

AVDD

VCC

D1

FREQUENCY (kHz)

Figure 29. Analog Input CMRR vs. Frequency

D3

C

R

IN

IN+ OR IN–

VEE

During the acquisition phase for ac signals, the impedance of

the analog inputs, IN+ and IN−, can be modeled as a parallel

combination of Capacitor C_PINand the network formed by

the series connection of R_INand C_IN. C_PINis primarily the pin

capacitance. R_INis typically 5 kΩ and is a lumped component

comprised of serial resistors and the on resistance of the switches.

C

D2

D4

AGND

Figure 28. AD7610 Simplified Analog Input

The four diodes, D1 to D4, provide ESD protection for the analog

inputs, IN+ and IN−. Care must be taken to ensure that the analog

input signal never exceeds the supply rails by more than 0.3 V,

because this causes the diodes to become forward-biased and to

start conducting current. These diodes can handle a forward-

biased current of 120 mA maximum. For instance, these conditions

could eventually occur when the input buffer’s U1 supplies are

different from AVDD, VCC, and VEE. In such a case, an input

buffer with a short-circuit current limitation can be used to protect

the part although most op amps’ short circuit current is <100 mA.

Note that D3 and D4 are only used in the 0 V to 5 V range to

allow for additional protection in applications that are switching

from the higher voltage ranges.

C_INis primarily the ADC sampling capacitor and depending on

the input range selected is typically 48 pF in the 0 V to 5 V range,

typically 24 pF in the 0 V to 10 V and 5 V ranges and typically

12 pF in the 10 V range. During the conversion phase, when

the switches are opened, the input impedance is limited to C_PIN

.

Since the input impedance of the AD7610 is very high, it can be

directly driven by a low impedance source without gain error.

To further improve the noise filtering achieved by the AD7610

analog input circuit, an external, one-pole RC filter between the

amplifier’s outputs and the ADC analog inputs can be used, as

shown in Figure 27. However, large source impedances signifi-

antly affect the ac performance, especially total harmonic

distortion (THD). The maximum source impedance depends

on the amount of THD that can be tolerated. The THD degrades

as a function of the source impedance and the maximum input

frequency.

This analog input structure allows the sampling of the differential

signal between IN+ and IN−. By using this differential input,

small signals common to both inputs are rejected as shown in

Figure 29, which represents the typical CMRR over frequency.

Rev. 0 | Page 19 of 32

AD7610

The AD8021 meets these requirements and is appropriate for

almost all applications. The AD8021 needs a 10 pF external

compensation capacitor that should have good linearity as an

NPO ceramic or mica type. Moreover, the use of a noninverting

+1 gain arrangement is recommended and helps to obtain the

best signal-to-noise ratio.

DRIVER AMPLIFIER CHOICE

Although the AD7610 is easy to drive, the driver amplifier must

meet the following requirements:

•

For multichannel, multiplexed applications, the driver

amplifier and the AD7610 analog input circuit must be

able to settle for a full-scale step of the capacitor array at a

16-bit level (0.0015%). For the amplifier, settling at 0.1% to

0.01% is more commonly specified. This differs significantly

from the settling time at a 16-bit level and should be verified

prior to driver selection. The AD8021 op amp combines ultra-

low noise and high gain bandwidth and meets this settling

time requirement even when used with gains of up to 13.

The AD8022 can also be used when a dual version is needed

and a gain of 1 is present. The AD829 is an alternative in appli-

cations where high frequency (above 100 kHz) performance is not

required. In applications with a gain of 1, an 82 pF compensation

capacitor is required. The AD8610 is an option when low bias

current is needed in low frequency applications.

Since the AD7610 uses a large geometry, high voltage input

switch, the best linearity performance is obtained when using

the amplifier at its maximum full power bandwidth. Gaining

the amplifier to make use of the more dynamic range of the

ADC results in increased linearity errors. For applications

requiring more resolution, the use of an additional amplifier

with gain should precede a unity follower driving the AD7610.

See Table 8 for a list of recommended op amps.

•

The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition

noise performance of the AD7610. The noise coming from

the driver is filtered by the external 1-pole low-pass filter

as shown in Figure 27. The SNR degradation due to the

amplifier is

⎛

⎜

⎞

⎟

V_NADC

⎜

⎟

SNR_LOSS= 20log

Table 8. Recommended Driver Amplifiers

π

2

⎜

⎟

V_NADC

+

f_−3dB

(

Ne_N

)

Amplifier

Typical Application

2

⎝

⎠

ADA4841-x

12 V supply, very low noise, low distortion,

low power, low frequency

where:

V

_NADCis the noise of the ADC, which is:

AD829

AD8021

AD8022

15 V supplies, very low noise, low frequency

12 V supplies, very low noise, high frequency

12 V supplies, very low noise, high

frequency, dual

13 V supplies, low bias current, low

frequency, single/dual

V_INp-p

2 2

V_NADC

=

SNR

20

AD8610/AD8620

10

f

_–3dBis the cutoff frequency of the input filter (3.9 MHz).

N is the noise factor of the amplifier (+1 in buffer

configuration).

e_Nis the equivalent input voltage noise density of the op

amp, in nV/√Hz.

VOLTAGE REFERENCE INPUT/OUTPUT

The AD7610 allows the choice of either a very low temperature

drift internal voltage reference, an external reference or an external

buffered reference.

•

The driver needs to have a THD performance suitable to

that of the AD7610. Figure 15 shows the THD vs. frequency

that the driver should exceed.

The internal reference of the AD7610 provides excellent perfor-

mance and can be used in almost all applications. However, the

linearity performance is guaranteed only with an external reference.

Rev. 0 | Page 20 of 32

AD7610

Temperature Sensor

Internal Reference (REF = 5 V)

(PDREF = Low, PDBUF = Low)

When the internal reference is enabled (PDREF = PDBUF =

low), the on-chip temperature sensor output (TEMP) is enabled

and can be use to measure the temperature of the AD7610. To

improve the calibration accuracy over the temperature range, the

output of the TEMP pin is applied to one of the inputs of the

analog switch (such as ADG779), and the ADC itself is used to

measure its own temperature. This configuration is shown in

Figure 30.

To use the internal reference, the PDREF and PDBUF inputs

must be low. This enables the on-chip band gap reference, buffer,

and TEMP sensor resulting in a 5.00 V reference on the REF pin.

The internal reference is temperature-compensated to 5.000 V

35 mV. The reference is trimmed to provide a typical drift of

3 ppm/°C. This typical drift characteristic is shown in Figure 19.

External 2.5 V Reference and Internal Buffer (REF = 5 V)

(PDREF = High, PDBUF = Low)

TEMP

ADG779

To use an external reference with the internal buffer, PDREF

should be high and PDBUF should be low. This powers down

the internal reference and allows the 2.5 V reference to be applied

to REFBUFIN producing 5 V on the REF pin. The internal ref-

erence buffer is useful in multiconverter applications since a

buffer is typically required in these applications.

TEMPERATURE

IN+

SENSOR

ANALOG INPUT

AD7610

C

Figure 30. Use of the Temperature Sensor

POWER SUPPLIES

The AD7610 uses five sets of power supply pins:

External 5 V Reference (PDREF = High, PDBUF = High)

To use an external reference directly on the REF pin, PDREF

and PDBUF should both be high. PDREF and PDBUF power

down the internal reference and the internal reference buffer,

respectively. For improved drift performance, an external ref-

erence such as the ADR445 or ADR435 is recommended.

•

AVDD: analog 5 V core supply

VCC: analog high voltage positive supply

VEE: high voltage negative supply

DVDD: digital 5 V core supply

Reference Decoupling

OVDD: digital input/output interface supply

Whether using an internal or external reference, the AD7610

voltage reference input (REF) has a dynamic input impedance;

therefore, it should be driven by a low impedance source with

efficient decoupling between the REF and REFGND inputs. This

decoupling depends on the choice of the voltage reference, but

usually consists of a low ESR capacitor connected to REF and

REFGND with minimum parasitic inductance. A 22 μF (X5R,

1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor)

is appropriate when using either the internal reference or the

ADR445/ADR435 external reference.

Core Supplies

The AVDD and DVDD supply the AD7610 analog and digital

cores respectively. Sufficient decoupling of these supplies is

required consisting of at least a 10 ꢀF capacitor and 100 nF on

each supply. The 100 nF capacitors should be placed as close as

possible to the AD7610. To reduce the number of supplies needed,

the DVDD can be supplied through a simple RC filter from the

analog supply, as shown in Figure 27.

High Voltage Supplies

The high voltage bipolar supplies, VCC and VEE are required

and must be at least 2 V larger than the maximum input, V_IN.

For example, if using the bipolar 10 V range, the supplies should

be 12 V minimum. Sufficient decoupling of these supplies is

also required consisting of at least a 10 ꢀF capacitor and 100 nF

on each supply. For unipolar operation, the VEE supply can be

grounded with some slight THD performance degradation.

The placement of the reference decoupling is also important to

the performance of the AD7610. The decoupling capacitor should

be mounted on the same side as the ADC right at the REF pin

with a thick PCB trace. The REFGND should also connect to

the reference decoupling capacitor with the shortest distance

and to the analog ground plane with several vias.

For applications that use multiple AD7610 or other PulSAR

devices, it is more effective to use the internal reference buffer

to buffer the external 2.5 V reference voltage.

Digital Output Supply

The OVDD supplies the digital outputs and allows direct interface

with any logic working between 2.3 V and 5.25 V. OVDD should

be set to the same level as the system interface. Sufficient decou-

pling is required consisting of at least a 10 ꢀF capacitor and 100 nF

with the 100 nF placed as close as possible to the AD7610.

The voltage reference temperature coefficient (TC) directly

impacts full scale; therefore, in applications where full-scale

accuracy matters, care must be taken with the TC. For instance, a

15 ppm/°C TC of the reference changes full-scale by 1 LSB/°C.

Rev. 0 | Page 21 of 32

AD7610

Power Down

Power Sequencing

Setting PD = high powers down the AD7610, thus reducing

supply currents to their minimums as shown in Figure 23. When

the ADC is in power down, the current conversion (if any) is

completed and the digital bus remains active. To further reduce

the digital supply currents, drive the inputs to OVDD or OGND.

The AD7610 is independent of power supply sequencing and is

very insensitive to power supply variations on AVDD over a wide

frequency range as shown in Figure 31.

80

EXT REF

75

Power down can also be programmed with the configuration

register. See the Software Configuration section for details. Note

that when using the configuration register, the PD input is a

don’t care and should be tied to either high or low.

70

65

60

55

50

45

40

35

30

INT REF

CONVERSION CONTROL

CNVST

The AD7610 is controlled by the

input. A falling edge

is all that is necessary to initiate a conversion. Detailed

CNVST

on

timing diagrams of the conversion process are shown in Figure 33.

Once initiated, it cannot be restarted or aborted, even by the

power-down input, PD, until the conversion is complete. The

1

10

100

1000

10000

CNVST

CS

RD

signal operates independently of

and signals.

FREQUENCY (kHz)

Figure 31. AVDD PSRR vs. Frequency

t₂

t₁

Power Dissipation vs. Throughput

CNVST

BUSY

The AD7610 automatically reduces its power consumption at

the end of each conversion phase. During the acquisition phase,

the operating currents are very low, which allows a significant

power savings when the conversion rate is reduced (see Figure 32).

This feature makes the AD7610 ideal for very low power, battery-

operated applications.

t₄

t₃

t₆

t₅

MODE

ACQUIRE

CONVERT

t₇

ACQUIRE

t₈

CONVERT

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital supply

currents even further, drive the digital inputs close to the power

rails (that is, OVDD and OGND).

Figure 33. Basic Conversion Timing

CNVST

Although

is a digital signal, it should be designed with

1000

special care with fast, clean edges, and levels with minimum

overshoot, undershoot, or ringing.

CNVST

The

trace should be shielded with ground and a low value

(such as 50 Ω) serial resistor termination should be added close

to the output of the component that drives this line.

100

10

CNVST

For applications where SNR is critical, the

have very low jitter. This can be achieved by using a dedicated

CNVST CNVST

with a

signal should

oscillator for

generation, or by clocking

high frequency, low jitter clock, as shown in Figure 27.

PDREF = PDBUF = HIGH

1

10

100

1000

10000

100000 1000000

SAMPLING RATE (kSPS)

Figure 32. Power Dissipation vs. Sample Rate

Rev. 0 | Page 22 of 32

AD7610

INTERFACES

DIGITAL INTERFACE

CS = RD = 0

CNVST

t₁

The AD7610 has a versatile digital interface that can be set up

as either a serial or a parallel interface with the host system. The

serial interface is multiplexed on the parallel data bus. The AD7610

digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In

most applications, the OVDD supply pin is connected to the host

system interface 2.5 V to 5.25 V digital supply. Finally, by using

t₁₀

BUSY

t₄

t₃

t₁₁

DATA

BUS

PREVIOUS CONVERSION DATA

NEW DATA

2C

the OB/ input pin, both twos complement or straight binary

coding can be used.

Figure 35. Master Parallel Data Timing for Reading (Continuous Read)

CS

RD

, control the interface. When at least

Two signals,

one of these signals is high, the interface outputs are in high

CS

and

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after

each conversion, which is during the next acquisition phase, or

during the following conversion, as shown in Figure 36 and

Figure 37, respectively. When the data is read during the conver-

sion, it is recommended that it is read only during the first half

of the conversion phase. This avoids any potential feedthrough

between voltage transients on the digital interface and the most

critical analog conversion circuitry.

impedance. Usually,

in multicircuit applications and is held low in a single AD7610

RD

allows the selection of each AD7610

design.

the data bus.

is generally used to enable the conversion result on

RESET

The RESET input is used to reset the AD7610. A rising edge on

RESET aborts the current conversion (if any) and tristates the

data bus. The falling edge of RESET resets the AD7610 and clears

the data bus and configuration register. See Figure 34 for the

RESET timing details.

CS

t₉

RD

RESET

BUSY

DATA

BUS

DATA

BUS

t₈

CURRENT

CONVERSION

CNVST

t₁₂

t₁₃

Figure 36. Slave Parallel Data Timing for Reading (Read After Convert)

Figure 34. RESET Timing

PARALLEL INTERFACE

CS = 0

The AD7610 is configured to use the parallel interface when

CNVST,

t₁

RD

PAR

SER/

is held low.

Master Parallel Interface

CS

RD

low, thus

Data can be continuously read by tying

and

BUSY

t₄

requiring minimal microprocessor connections. However, in

this mode, the data bus is always driven and cannot be used in

shared bus applications (unless the device is held in RESET).

Figure 35 details the timing for this mode.

t₃

DATA

BUS

t₁₂

t₁₃

Figure 37. Slave Parallel Data Timing for Reading (Read During Convert)

Rev. 0 | Page 23 of 32

AD7610

8-Bit Interface (Master or Slave)

MASTER SERIAL INTERFACE

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 38, when BYTESWAP is low, the LSB byte

is output on D[7:0] and the MSB is output on D[15:8]. When

BYTESWAP is high, the LSB and MSB bytes are swapped; the

LSB is output on D[15:8] and the MSB is output on D[7:0]. By

connecting BYTESWAP to an address line, the 16-bit data can

be read in two bytes on either D[15:8] or D[7:0]. This interface

can be used in both master and slave parallel reading modes.

The pins multiplexed on D[10:2] and used for the master serial

INT

interface are: DIVSCLK[0], DIVSCLK[1], EXT/

INVSCLK, RDC, SDOUT, SDCLK and SYNC.

, INVSYNC,

PAR

INT

= High, EXT/

Internal Clock (SER/

= Low)

The AD7610 is configured to generate and provide the serial

INT

data clock, SDCLK, when the EXT/

pin is held low. The

AD7610 also generates a SYNC signal to indicate to the host

when the serial data is valid. The SDCLK, and the SYNC signals

can be inverted, if desired using the INVSCLK and INVSYNC

inputs, respectively. Depending on the input, RDC, the data can

be read during the following conversion or after each conver-

sion. Figure 39 and Figure 40 show detailed timing diagrams of

these two modes.

CS

RD

BYTESWAP

Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])

HI-Z

Setting RDC = low, allows the read after conversion mode.

Since the AD7610 is limited to 250kSPS and the time between

conversions, t2 = 4μs, this mode is the most recommended

serial mode. Unlike the other serial modes, the BUSY signal

returns low after the 16 data bits are pulsed out and not at the

end of the conversion phase, resulting in a longer BUSY width

(See Table 4 for BUSY timing specifications). The

DIVSCLK[1:0] inputs control the SDCLK period and SDOUT

data rate. As a result, the maximum throughput can only be

achieved in two of the DIVSCLK[1:0] settings. In this mode, the

AD7610 generates a discontinuous SDCLK however, a fixed

period and hosts supporting both SPI and serial ports can also

be used.

PINS D[15:8]

PINS D[7:0]

HIGH BYTE

LOW BYTE

t₁₂

LOW BYTE

t₁₂

t₁₃

HIGH BYTE

Figure 38. 8-Bit and 16-Bit Parallel Interface

SERIAL INTERFACE

The AD7610 has a serial interface (SPI-compatible) multiplexed

on the data pins D[15:2]. The AD7610 is configured to use the

PAR

serial interface when SER/

is held high.

Data Interface

The AD7610 outputs 16 bits of data, MSB first, on the SDOUT pin.

This data is synchronized with the 16 clock pulses provided on

the SDCLK pin. The output data is valid on both the rising and

falling edge of the data clock.

Read During Convert (RDC = High)

Setting RDC = high, allows the master read (previous conver-

sion result) during conversion mode. In this mode, the serial

clock and data toggle at appropriate instances, minimizing

potential feed through between digital activity and critical

conversion decisions. In this mode, the SDCLK period changes

since the LSBs require more time to settle and the SDCLK is

derived from the SAR conver-sion cycle. In this mode, the

AD7610 generates a discontinuous SDCLK of two different

periods and the host should use an SPI interface.

Serial Configuration Interface

The AD7610 can be configured through the serial configuration

register only in serial mode as the serial configuration pins are

also multiplexed on the data pins D[15:12]. See the Hardware

Configuration section and Software Configuration section for

more information.

Rev. 0 | Page 24 of 32

AD7610

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

EXT/INT = 0

CS, RD

CNVST

t₃

BUSY

SYNC

t₂₈

t₃₀

t₂₉

t₂₅

t₁₈

t₁₉

t₁₄

t₂₄

t₂₀

t₂₁

2

t₂₆

1

3

14

15

16

SDCLK

SDOUT

t₁₅

t₂₇

D15

D14

t₂₃

D2

D1

D0

X

t₁₆

t₂₂

Figure 39. Master Serial Data Timing for Reading (Read After Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t₁

CNVST

BUSY

t₃

t₁₇

t₂₅

SYNC

t₁₄

t₁₉

t₂₀t₂₁

t₂₄

t₂₆

t₁₅

SDCLK

SDOUT

1

2

3

14

15

16

t₁₈

t₂₇

X

D15

D14

t₂₃

D2

D1

D0

t₁₆

t₂₂

Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 25 of 32

AD7610

CNVST

signal. Note that the SDIN input is latched on the opposite

SLAVE SERIAL INTERFACE

edge of SDCLK used to shift out the data on SDOUT (SDCLK

falling edge when INVSCLK = low). Therefore, the MSB of the

upstream converter follows the LSB of the down-stream converter

on the next SDCLK cycle. In this mode, the 40 MHz SDCLK

rate cannot be used since the SDIN to SDCLK setup time, t₃₃, is

less than the minimum time specified. (SDCLK to SDOUT delay,

t₃₂, is the same for all converters when simultaneously sampled).

For proper operation, the SDCLK edge for latching SDIN (or ½

period of SDCLK) needs to be:

The pins multiplexed on D[11:4] used for slave serial interface are:

INT

EXT/

External Clock (SER/

INT

, INVSCLK, SDIN, SDOUT, SDCLK and RDERROR.

PAR INT

= High, EXT/

= High)

Setting the EXT/

= high allows the AD7610 to accept an

externally supplied serial data clock on the SDCLK pin. In this

mode, several methods can be used to read the data. The external

CS

RD

serial clock is gated by . When

and are both low, the

data can be read after each conversion or during the following

conversion. A clock can be either normally high or normally low

when inactive. For detailed timing diagrams, see Figure 42 and

Figure 43.

t_{1/ 2SDCLK}= t₃₂+t₃₃

Or the max SDCLK frequency needs to be:

1

f_SDCLK

=

While the AD7610 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins,

or degradation of the conversion result may occur. This is par-

ticularly important during the last 475 ns of the conversion phase

because the AD7610 provides error correction circuitry that can

correct for an improper bit decision made during the first part

of the conversion phase. For this reason, it is recommended that

any external clock provided, is a discontinuous clock that transi-

tions only when BUSY is low, or, more importantly, that it does

not transition during the last 475 ns of BUSY high.

2(t₃₂+t₃₃)

If not using the daisy-chain feature, the SDIN input should be

tied either high or low.

BUSY

OUT

BUSY

AD7610

#2

#1

(UPSTREAM)

(DOWNSTREAM)

DATA

OUT

RDC/SDIN SDOUT

External Discontinuous Clock Data Read After

Conversion

CNVST

CS

CNVST

CS

Since the AD7610 is limited to 250 kSPS, the time between con-

versions, t₄= 4 ꢀs, and the conversion time, t₇= 1.45 ꢀs. This

makes the read after conversion mode the most recommended

serial slave mode since the time to read the data is t₄− t₇. Figure 42

shows the detailed timing diagrams for this method. After a

conversion is complete, indicated by BUSY returning low, the

SCLK

SCLK IN

CS IN

CNVST IN

Figure 41. Two AD7610 Devices in a Daisy-Chain Configuration

External Clock Data Read During Previous Conversion

CS

RD

conversion result can be read while both

and

are low.

Data is shifted out MSB first with 16 clock pulses and, depending

on the SDCLK frequency, can be valid on the falling and rising

edges of the clock.

Figure 43 shows the detailed timing diagrams for this method.

CS

RD

During a conversion, while both

and

are low, the result

of the previous conversion can be read. The data is shifted out,

MSB first, with 16 clock pulses, and is valid on both the rising

and falling edge of the clock. The 16 bits have to be read before

the current conversion is complete; otherwise, RDERROR is

pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading.

One advantage of this method is that conversion performance is

not degraded because there are no voltage transients on the digital

interface during the conversion process. Another advantage is

the ability to read the data at any speed up to 40 MHz, which

accommodates both the slow digital host interface and the fastest

serial reading.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 40 MHz is recommended to ensure

that all the bits are read during the first half of the SAR

conversion phase.

Daisy-Chain Feature

Also in the read after convert mode, the AD7610 provides a daisy-

chain feature for cascading multiple converters together using the

serial data input, SDIN, pin. This feature is useful for reducing

component count and wiring connections when desired, for

instance, in isolated multiconverter applications. See Figure 42

for the timing details.

The daisy-chain feature should not be used in this mode since

digital activity occurs during the second half of the SAR

conversion phase likely resulting in performance degradation.

An example of the concatenation of two devices is shown in

Figure 41. Simultaneous sampling is possible by using a common

Rev. 0 | Page 26 of 32

AD7610

discontinuous SDCLK whenever possible to minimize potential

External Clock Data Read After/During Conversion

incorrect bit decisions. For the different modes, the use of a slower

SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode

and 13 MHz in impulse mode can be used.

It is also possible to begin to read data after conversion and

continue to read the last bits after a new conversion has been

initiated. This method allows the full throughput and the use of

a slower SDCLK frequency. Again, it is recommended to use a

SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0

CS

BUSY

t₃₁

t₃₅

t₃₆

t₃₁

SDCLK

X*

1

2

3

4

14

15

16

17

18

19

t₃₂

t₃₇

SDOUT

SDIN

D15

X15

D14

X14

X15

Y15

X14

Y14

D13

D2

X2

D1

X1

D0

X0

t₁₆

X13

t₃₃

*A DISCONTINUOUS SDCLK IS RECOMMENDED.

t₃₄

Figure 42. Slave Serial Data Timing for Reading (Read After Convert)

SER/PAR = 1 EXT/INT = 1 INVSCLK = 0

RD = 0

CS

CNVST

BUSY

t₃₅

t₃₆

16

t₃₁

SDCLK

X*

1

2

3

15

t₃₂

t₃₇

D1

DATA = SDIN

t₂₇

SDOUT

D15

D14

D0

t₁₆

*A DISCONTINUOUS SDCLK IS RECOMMENDED.

Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 27 of 32

AD7610

attainable because the time required for SCP access is (t₃₁+ 9 × 1/

SCCLK +t₈) minimum. If the full throughput is required, the

SCP can be written to during conversion, however it is not

recommended to write to the SCP during the last 475 ns of

conversion (BUSY = high) or performance degradation can

result. In addition, the SCP can be accessed in both serial

master and serial slave read during and read after convert modes.

HARDWARE CONFIGURATION

The AD7610 can be configured at any time with the dedicated

2C

hardware pins BIPOLAR, TEN, OB/ , and PD for parallel mode

PAR PAR

= high,

(SER/

SW

= low) or serial hardware mode (SER/

= high). Programming the AD7610 for input range

HW/

configuration can be done before or during conversion. Like

the RESET input, the ADC requires at least one acquisition

time to settle as indicated in Figure 44. See Table 6 for pin descrip-

tions. Note that these inputs are high impedance when using

the software configuration mode.

Note that at power up, the configuration register is undefined.

The RESET input clears the configuration register (sets all bits

to 0), thus placing the configuration to 0 V to 5 V input, normal

mode, and twos complemented output.

SOFTWARE CONFIGURATION

Table 9. Configuration Register Description

The pins multiplexed on D[15:12] used for software configu-

Bit Name

Description

SW

SCCS

ration are: HW/ , SCIN, SCCLK, and

. The AD7610 is

8

START

SCCS

START bit. With the SCP enabled ( = low),

programmed using the dedicated write-only serial configurable

port (SCP) for conversion mode, input range selection, output

coding, and power-down using the serial configuration register.

See Table 9 for details of each bit in the configuration register.

The SCP can only be used in serial software mode selected with

when START is high, the first rising edge of SCCLK

(INVSCLK = low) begins to load the register with

the new configuration.

7

BIPOLAR

Input Range Select. Used in conjunction with Bit 6,

TEN, per the following:

Input Range

0 V to 5 V

0 V to 10 V

5 V

BIPOLAR

Low

High

TEN

Low

High

Low

High

PAR

SER/

SW

= high and HW/

= low since the port is multiplexed

on the parallel interface.

SCCS

The SCP is accessed by asserting the port’s chip select,

,

10 V

and then writing SCIN synchronized with SCCLK, which (like

SDCLK) is edge sensitive depending on the state of INVSCLK.

See Figure 45 for timing details. SCIN is clocked into the con-

figuration register MSB first. The configuration register is an

internal shift register that begins with Bit 8, the start bit. The 9^th

SPPCLK edge updates the register and allows the new settings to be

used. As indicated in the timing diagram, at least one acquisition

time is required from the 9^thSCCLK edge. Bits [4:3] and [1:0] are

reserved bits and are not written to while the SCP is being

updated.

6

5

TEN

PD

Input Range Select. See Bit 7, BIPOLAR.

Power Down.

PD = Low, normal operation.

PD = High, power down the ADC. The SCP is

accessible while in power down. To power up the

ADC, write PD = low on the next configuration

setting.

4

3

2

RSV

Reserved.

Output Coding

2C

OB/

2C

OB/ = Low, use twos complement output.

The SCP can be written to at any time, up to 40 MHz, and it is

recommended to write to while the AD7610 is not busy convert-

ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not

2C

OB/ = High, use straight binary output.

1

0

RSV

Reserved.

HW/SW = 0

PD = 0

SER/PAR = 0, 1

t₈

CNVST

BUSY

BIPOLAR,

TEN

WARP,

IMPULSE

Figure 44. Hardware Configuration Timing

Rev. 0 | Page 28 of 32

AD7610

SER/PAR = 1 INVSCLK = 0

WARP = 0 OR 1

BIP = 0 OR 1

TEN = 0 OR 1

t₈

HW/SW = 0

PD = 0

IMPULSE = 0 OR 1

CNVST

BUSY

t₃₁

SCCS

t₃₁

t₃₅

t₃₆

5

SCCLK

1

2

3

4

6

7

8

9

t₃₇

SCIN

X

OB/2C

BIPOLAR

TEN

PD

X

START

X

t₃₃

t₃₄

Figure 45. Serial Configuration Port Timing

The reading process can be initiated in response to the end-of-

conversion signal (BUSY going low) using an interrupt line of

the DSP. The serial peripheral interface (SPI) on the ADSP-219x

is configured for master mode (MSTR) = 1, clock polarity bit

(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable

(TIMOD) = 0 by writing to the SPI control register (SPICLTx).

MICROPROCESSOR INTERFACING

The AD7610 is ideally suited for traditional dc measurement appli-

cations supporting a microprocessor, and ac signal processing

applications interfacing to a digital signal processor. The AD7610 is

designed to interface with a parallel 8-bit or 16-bit wide inter-

face, or with a general-purpose serial port or I/O ports on a micro-

controller. A variety of external buffers can be used with the

AD7610 to prevent digital noise from coupling into the ADC.

It should be noted that to meet all timing requirements, the SPI

clock should be limited to 17 Mbps allowing it to read an ADC

result in less than 1 μs. When a higher sampling rate is desired,

use one of the parallel interface modes.

SPI Interface

The AD7610 is compatible with SPI and QSPI digital hosts

and DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/

ADSP-219x. Figure 46 shows an interface diagram between the

AD7610 and the SPI-equipped ADSP-219x. To accommodate

the slower speed of the DSP, the AD7610 acts as a slave device, and

data must be read after conversion. This mode also allows the

daisy-chain feature. The convert command could be initiated

in response to an internal timer interrupt.

DVDD

AD7610*

ADSP-219x*

SER/PAR

BUSY

CS

PFx

EXT/INT

SPIxSEL (PFx)

MISOx

SDOUT

SCLK

CNVST

RD

SCKx

PFx OR TFSx

INVSCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Interfacing the AD7610 to SPI Interface

Rev. 0 | Page 29 of 32

AD7610

APPLICATION INFORMATION

The DVDD supply of the AD7610 can be either a separate supply

or come from the analog supply, AVDD, or from the digital

interface supply, OVDD. When the system digital supply is noisy,

or fast switching digital signals are present, and no separate supply

is available, it is recommended to connect the DVDD digital supply

to the analog supply AVDD through an RC filter, and to connect

the system supply to the interface digital supply OVDD and the

remaining digital circuitry. See Figure 27 for an example of this

configuration. When DVDD is powered from the system supply,

it is useful to insert a bead to further reduce high frequency spikes.

LAYOUT GUIDELINES

While the AD7610 has very good immunity to noise on the

power supplies, exercise care with the grounding layout. To facil-

itate the use of ground planes that can be easily separated, design

the printed circuit board that houses the AD7610 so that the

analog and digital sections are separated and confined to certain

areas of the board. Digital and analog ground planes should be

joined in only one place, preferably underneath the AD7610, or

as close as possible to the AD7610. If the AD7610 is in a system

where multiple devices require analog-to-digital ground connect-

ions, the connections should still be made at one point only, a

star ground point, established as close as possible to the AD7610.

The AD7610 has four different ground pins: REFGND, AGND,

DGND, and OGND.

To prevent coupling noise onto the die, avoid radiating noise,

and to reduce feedthrough:

•

REFGND senses the reference voltage and, because it carries

pulsed currents, should be a low impedance return to the

reference.

• Do not run digital lines under the device.

•

AGND is the ground to which most internal ADC analog

signals are referenced; it must be connected with the least

resistance to the analog ground plane.

• Do run the analog ground plane under the AD7610.

CNVST

• Do shield fast switching signals, like

or clocks, with

digital ground to avoid radiating noise to other sections of

the board, and never run them near analog signal paths.

•

DGND must be tied to the analog or digital ground plane

depending on the configuration.

• Avoid crossover of digital and analog signals.

OGND is connected to the digital system ground.

• Run traces on different but close layers of the board, at right

angles to each other, to reduce the effect of feedthrough through

the board.

The layout of the decoupling of the reference voltage is important.

To minimize parasitic inductances, place the decoupling capacitor

close to the ADC and connect it with short, thick traces.

The power supply lines to the AD7610 should use as large a trace as

possible to provide low impedance paths and reduce the effect of

glitches on the power supply lines. Good decoupling is also

important to lower the impedance of the supplies presented to

the AD7610, and to reduce the magnitude of the supply spikes.

Decoupled ceramic capacitors, typically 100 nF, should be placed

on each of the power supplies pins, AVDD, DVDD, and OVDD,

VCC, and VEE. The capacitors should be placed close to, and

ideally right up against, these pins and their corresponding ground

pins. Additionally, low ESR 10 μF capacitors should be located

in the vicinity of the ADC to further reduce low frequency ripple.

EVALUATING PERFORMANCE

A recommended layout for the AD7610 is outlined in the EVAL-

AD7610CB evaluation board documentation. The evaluation

board package includes a fully assembled and tested evaluation

board, documentation, and software for controlling the board

from a PC via the EVAL-CONTROL BRD3.

Rev. 0 | Page 30 of 32

AD7610

OUTLINE DIMENSIONS

9.20

9.00 SQ

8.80

0.75

0.60

0.45

1.60

MAX

37

48

36

1

PIN 1

7.20

TOP VIEW

(PINS DOWN)

7.00 SQ

6.80

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08

COPLANARITY

25

12

0.15

0.05

13

24

SEATING

PLANE

0.27

0.22

0.17

VIEW A

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

EXPOSED

5.25

5.10 SQ

4.95

TOP

VIEW

6.75

BSC SQ

(BOTTOM VIEW)

0.50

0.40

0.30

25

24

12

13

0.25 MIN

5.50

REF

PADDLE CONNECTED TO VEE.

THIS CONNECTION IS NOT

REQUIRED TO MEET THE

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

ELECTRICAL PERFORMANCES.

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-48-1

ST-48

AD7610BCPZ¹

48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

48-Lead Low Profile Quad Flat Package (LQFP)

Evaluation Board

AD7610BCPZ-RL¹

AD7610BSTZ¹

AD7610BSTZ-RL¹

EVAL-AD7610CB²

EVAL-CONTROL BRD3³

Controller Board

1

Z = Pb-free part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators.

3

Rev. 0 | Page 31 of 32

AD7610

NOTES

registered trademarks are the property of their respective owners.

D06395-0-10/06(0)

Rev. 0 | Page 32 of 32


型号：	AD7951
厂家：	ADI
描述：	16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC 16位250 kSPS时，单极/双极性可编程输入的PulSAR ADC
文件：	总32页 (文件大小：821K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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