AD797ANZ [ADI]
Ultralow Distortion, Ultralow Noise Op Amp; 超低失真，超低噪声运算放大器
| 型号： | AD797ANZ |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion, Ultralow Noise Op Amp |
| 文件： | 总20页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion,
Ultralow Noise Op Amp
AD797
FEATURES
Low noise
PIN CONFIGURATION
DECOMPENSATION
AND DISTORTION
NEUTRALIZATION
OFFSET NULL
1
2
3
4
8
7
6
5
AD797
0.9 nV/√Hz typical (1.2 nV/√Hz maximum) input voltage
noise at 1 kHz
50 nV p-p input voltage noise, 0.1 Hz to 10 Hz
Low distortion
–IN
+IN
+V
S
OUTPUT
–V
OFFSET NULL
S
TOP VIEW
Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] and
8-Lead Standard Small Outline Package [SOIC]
−120 dB total harmonic distortion at 20 kHz
Excellent ac characteristics
800 ns settling time to 16 bits (10 V step)
110 MHz gain bandwidth (G = 1000)
8 MHz bandwidth (G = 10)
280 kHz full power bandwidth at 20 V p-p
20 V/μs slew rate
Excellent dc precision
80 μV maximum input offset voltage
1.0 μV/°C VOS drift
GENERAL DESCRIPTION
The AD797 is a very low noise, low distortion operational
amplifier ideal for use as a preamplifier. The low noise of
0.9 nV/√Hz and low total harmonic distortion of −120 dB at
audio bandwidths give the AD797 the wide dynamic range
necessary for preamps in microphones and mixing consoles.
Furthermore, the AD797’s excellent slew rate of 20 V/μs and
110 MHz gain bandwidth make it highly suitable for low
frequency ultrasound applications.
Specified for 5 V and 15 V power supplies
High output drive current of 50 mA
The AD797 is also useful in infrared (IR) and sonar imaging
applications, where the widest dynamic range is necessary. The
low distortion and 16-bit settling time of the AD797 make it
ideal for buffering the inputs to Σ-Δ ADCs or the outputs of
high resolution DACs, especially when the device is used in
critical applications such as seismic detection or in spectrum
analyzers. Key features such as a 50 mA output current drive
and the specified power supply voltage range of 5 V to 15 V
make the AD797 an excellent general-purpose amplifier.
APPLICATIONS
Professional audio preamplifiers
IR, CCD, and sonar imaging systems
Spectrum analyzers
Ultrasound preamplifiers
Seismic detectors
Σ-Δ ADC/DAC buffers
–90
5
4
3
2
1
0
–100
–110
–120
0.001
0.0003
0.0001
MEASUREMENT
LIMIT
–130
100
300
1k
3k
10k
30k
100k
300k
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3. THD vs. Frequency
Figure 2. AD797 Voltage Noise Spectral Density
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD797
TABLE OF CONTENTS
Features .............................................................................................. 1
Low Frequency Noise ................................................................ 12
Wideband Noise ......................................................................... 12
Bypassing Considerations ......................................................... 12
The Noninverting Configuration............................................. 13
The Inverting Configuration .................................................... 14
Driving Capacitive Loads.......................................................... 14
Settling Time............................................................................... 14
Distortion Reduction................................................................. 15
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Noise and Source Impedance Considerations........................ 11
REVISION HISTORY
1/08—Rev. E to Rev. F
Changes to Absolute Maximum Ratings....................................... 5
Change to Equation 1..................................................................... 12
Changes to the Noninverting Configuration Section................ 13
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/05—Rev. D to Rev. E
Updated Figure 1 Caption ............................................................... 1
Deleted Metallization Photo ........................................................... 6
Changes to Equation 1 ................................................................... 12
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
10/02—Rev. C to Rev. D
Deleted 8-Lead CERDIP Package (Q-8)..........................Universal
Edits to Specifications ...................................................................... 2
Edits to Absolute Maximum Ratings ............................................. 3
Edits to Ordering Guide .................................................................. 3
Edits to Table I .................................................................................. 9
Deleted Operational Amplifiers Graphic .................................... 15
Updated Outline Dimensions....................................................... 15
Rev. F | Page 2 of 20
AD797
SPECIFICATIONS
TA = 25°C and VS = 15 V dc, unless otherwise noted.
Table 1.
Supply
AD797A
Typ
2±
AD797B
Typ
ꢀ0
Parameter
Conditions
Voltage (V)
±± V, ±ꢀ± V
Min
Max
80
Min
Max
40
Unit
μV
INPUT OFFSET VOLTAGE
TMIN to TMAX
±0
ꢀ2±/ꢀ80
ꢀ.0
30
60
μV
Offset Voltage Drift
±± V, ±ꢀ± V
±± V, ±ꢀ± V
0.2
0.2
0.6
0.9
2.0
200
300
μV/°C
μA
INPUT BIAS CURRENT
0.2±
0.±
ꢀ.±
0.2±
0.2±
80
TMIN to TMAX
3.0
μA
INPUT OFFSET CURRENT
OPEN-LOOP GAIN
±± V, ±ꢀ± V
±ꢀ± V
ꢀ00
ꢀ20
20
400
nA
TMIN to TMAX
VOUT = ±ꢀ0 V
RLOAD = 2 kΩ
TMIN to TMAX
RLOAD = 600 Ω
TMIN to TMAX
@ 20 kHzꢀ
600/700
ꢀ20
20
nA
ꢀ
ꢀ
ꢀ
ꢀ
2
2
2
2
V/μV
V/μV
V/μV
V/μV
V/V
6
ꢀ0
ꢀ±
ꢀ±
±
7
ꢀ4,000 20,000
ꢀ4,000 20,000
DYNAMIC PERFORMANCE
Gain Bandwidth Product
G = ꢀ000
±ꢀ± V
ꢀ± V
ꢀꢀ0
4±0
8
ꢀꢀ0
4±0
8
MHz
MHz
MHz
kHz
G = ꢀ0002
–3 dB Bandwidth
Full Power Bandwidthꢀ
G = ꢀ0
±ꢀ± V
±ꢀ± V
VOUT = 20 V p-p,
280
280
R
LOAD = ꢀ kΩ
Slew Rate
RLOAD = ꢀ kΩ
ꢀ0 V step
±ꢀ± V
ꢀ2.±
20
ꢀ2.±
20
V/μs
Settling Time to 0.00ꢀ±%
COMMON-MODE REJECTION
±ꢀ± V
800
ꢀ30
ꢀ20
ꢀ30
ꢀ20
±0
ꢀ200
800
ꢀ30
ꢀ20
ꢀꢀ4
ꢀ20
±0
ꢀ200 ns
VCM = CMVR
TMIN to TMAX
±± V, ±ꢀ± V
ꢀꢀ4
ꢀꢀ0
ꢀꢀ4
ꢀꢀ0
ꢀ20
ꢀꢀ4
ꢀ20
ꢀ30
dB
dB
dB
dB
POWER SUPPLY REJECTION
INPUT VOLTAGE NOISE
VS = ±± V to ±ꢀ8 V
TMIN to TMAX
f = 0.ꢀ Hz to ꢀ0 Hz
f = ꢀ0 Hz
±ꢀ± V
nV p-p
±ꢀ± V
ꢀ.7
0.9
ꢀ.0
2.0
±ꢀ2
±3
ꢀ.7
2.±
ꢀ.2
ꢀ.2
nV/√Hz
f = ꢀ kHz
±ꢀ± V
ꢀ.2
ꢀ.3
0.9
nV/√Hz
f = ꢀ0 Hz to ꢀ MHz
f = ꢀ kHz
±ꢀ± V
ꢀ.0
μV rms
INPUT CURRENT NOISE
±ꢀ± V
2.0
pA/√Hz
INPUT COMMON-MODE VOLTAGE RANGE
±ꢀ± V
±ꢀꢀ
±2.±
±ꢀ2
±ꢀꢀ
±2.±
±ꢀꢀ
±2.±
±ꢀ3
±ꢀ3
±3
±ꢀ2
±3
V
±± V
V
OUTPUT VOLTAGE SWING
RLOAD = 2 kΩ
RLOAD = 600 Ω
RLOAD = 600 Ω
±ꢀ± V
±ꢀ3
±ꢀ3
±3
±ꢀ2
±ꢀꢀ
±2.±
V
±ꢀ± V
V
±± V
V
Short-Circuit Current
Output Current3
±± V, ±ꢀ± V
±± V, ±ꢀ± V
±ꢀ± V
80
80
mA
mA
dB
30
±0
30
±0
TOTAL HARMONIC DISTORTION
RLOAD = ꢀ kΩ, CN = ±0 pF,
f = 2±0 kHz, 3 V rms
−98
−90
−98
−90
RLOAD = ꢀ kΩ,
±ꢀ± V
−ꢀ20
−ꢀꢀ0
−ꢀ20
−ꢀꢀ0 dB
f = 20 kHz, 3 V rms
INPUT CHARACTERISTICS
Input Resistance
Differential
7.±
7.±
kΩ
Common Mode
Input Capacitance
Differential4
ꢀ00
ꢀ00
MΩ
20
±
20
±
pF
pF
Common Mode
Rev. F | Page 3 of 20
AD797
Supply
AD797A
AD797B
Typ
Parameter
Conditions
Voltage (V)
Min
Typ
Max
Min
Max
Unit
OUTPUT RESISTANCE
POWER SUPPLY
Operating Range
Quiescent Current
AV = ꢀ, f = ꢀ kHz
3
3
mΩ
±±
±ꢀ8
ꢀ0.±
±±
±ꢀ8
ꢀ0.±
V
±± V, ±ꢀ± V
8.2
8.2
mA
ꢀ Full power bandwidth = slew rate/2π VPEAK
.
2 Specified using external decompensation capacitor.
3 Output current for |VS – VOUT| > 4 V, AOL > 200 kΩ.
4 Differential input capacitance consists of ꢀ.± pF package capacitance and ꢀ8.± pF from the input differential pair.
Rev. F | Page 4 of 20
AD797
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Ratings
Stresses above those listed under Absolute Maximum Ratings
Supply Voltage
±ꢀ8 V
Internal Power Dissipation @ 2±°Cꢀ
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PDIP
SOIC
ꢀ.3 W − (TA − 2±°C)/θJA
0.9 W (TA − 2±°C)/θJA
±VS
Input Voltage
Differential Input Voltage2
Output Short-Circuit Duration
±0.7 V
Indefinite within
maximum internal
power dissipation
ESD CAUTION
Storage Temperature Range
(N, R Suffix)
−6±°C to +ꢀ2±°C
Operating Temperature Range
Lead Temperature Range
(Soldering 60 sec)
−40°C to +8±°C
300°C
ꢀ θJA = 9±°C/W for the 8-lead PDIP; ꢀ±±°C/W for the 8-lead SOIC.
2 The AD797 inputs are protected by back-to-back diodes. To achieve low
noise, internal current-limiting resistors are not incorporated into the design
of this amplifier. If the differential input voltage exceeds ±0.7 V, the input
current should be limited to less than 2± mA by series protection resistors.
Note, however, that this degrades the low noise performance of the device.
Rev. F | Page ± of 20
AD797
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
0
0
5
10
15
20
HORIZONTAL SCALE (5sec/DIV)
SUPPLY VOLTAGE (±V)
Figure 7. 0.1 Hz to 10 Hz Noise
Figure 4. Input Common-Mode Voltage Range vs. Supply Voltage
0
20
15
10
–0.5
–1.0
+V
OUT
–V
OUT
5
0
–1.5
–2.0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 8. Input Bias Current vs. Temperature
30
20
10
0
140
120
100
80
V
= ±15V
S
SOURCE CURRENT
SINK CURRENT
V
= ±5
S
60
40
10
100
1k
10k
–60 –40 –20
0
20
40
60
100 120 140
80
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
Figure 9. Short-Circuit Current vs. Temperature
Figure 6. Output Voltage Swing vs. Load Resistance
Rev. F | Page 6 of 20
AD797
11
10
9
200
140
175
120
100
+125°C
PSR
+SUPPLY
PSR
–SUPPLY
150
125
100
75
80
60
+25°C
–55°C
8
CMR
7
40
20
6
50
1M
0
5
15
20
10
SUPPLY VOLTAGE (±V)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 10. Quiescent Supply Current vs. Supply Voltage
Figure 13. Power Supply and Common-Mode Rejection vs. Frequency
–60
f = 1kHz
R
= 600Ω
L
R
= 600Ω
L
G = +10
f = 10kHz
G = +10
NOISE BW = 100kHz
9
6
3
0
–80
–100
–120
V
= ±5V
S
V
= ±15V
S
0
±5
±10
±15
±20
0.01
0.1
OUTPUT LEVEL (V)
1
10
SUPPLY VOLTAGE (±V)
Figure 11. Output Voltage vs. Supply Voltage for 0.01% Distortion
Figure 14. Total Harmonic Distortion (THD) + Noise vs. Output Level
1.0
0.8
30
±15V SUPPLIES
R
= 600Ω
L
0.0015%
20
10
0
0.6
0.01%
0.4
±5V SUPPLIES
0.2
0
0
2
4
6
8
10
10k
100k
1M
10M
STEP SIZE (V)
FREQUENCY (Hz)
Figure 12. Settling Time vs. Step Size (
)
Figure 15. Large-Signal Frequency Response
Rev. F | Page 7 of 20
AD797
120
110
100
5
4
3
2
1
35
GAIN/BANDWIDTH PRODUCT
30
25
SLEW RATE
RISING EDGE
SLEW RATE
FALLING EDGE
20
15
90
80
0
–60 –40 –20
0
20
40
60
80
100 120 140
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Input Voltage Noise Spectral Density
Figure 19. Slew Rate and Gain/Bandwidth Product vs. Temperature
120
100
80
100
160
PHASE MARGIN
80
60
WITHOUT
R *
S
WITH R *
S
140
120
100
40
20
60
GAIN
40
*R = 100
S
WITHOUT
R *
20
0
S
*SEE FIGURE 25.
1k
WITH R *
S
0
100
10k
100k
1M
10M
100M
100
10k
1k
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
Figure 17. Open-Loop Gain and Phase Margin vs. Frequency
Figure 20. Open-Loop Gain vs. Load Resistance
100
10
300
OVERCOMPENSATED
150
0
1
WITHOUT C
*
N
–150
0.1
0.01
UNDER COMPENSATED
WITH C *
N
*SEE FIGURE 32.
100
–300
–60 –40 –20
0
20
40
60
80
100 120 140
10
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 21. Magnitude of Output Impedance vs. Frequency
Figure 18. Input Offset Current vs. Temperature
Rev. F | Page 8 of 20
AD797
20pF
100Ω
+V
S
1kΩ
**
**
+V
S
7
2
3
*
*
V
6
1kΩ
AD797
OUT
7
V
2
3
IN
R *
S
600Ω
V
IN
4
V
6
AD797
OUT
4
–V
S
*VALUE OF SOURCE RESISTANCE
SEE THE NOISE AND SOURCE IMPEDANCE
(
–V
S
CONSIDERATIONS SECTION).
**SEE FIGURE 35.
*SEE FIGURE 35.
Figure 22. Inverter Connection
Figure 25. Follower Connection
1µs
5V
1µs
100
90
100
90
10
10
0%
0%
5V
Figure 23. Inverter Large-Signal Pulse Response
Figure 26. Follower Large-Signal Pulse Response
50mV
100ns
50mV
100ns
100
90
100
90
10
10
0%
0%
Figure 27. Follower Small-Signal Pulse Response
Figure 24. Inverter Small-Signal Pulse Response
Rev. F | Page 9 of 20
AD797
50mV
500ns
50mV
500ns
100
90
100
90
10
10
0%
0%
Figure 28. 16-Bit Settling Time Positive Input Pulse
Figure 29. 16-Bit Settling Time Negative Input Pulse
Rev. F | Page ꢀ0 of 20
AD797
THEORY OF OPERATION
The architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous
precision amplifiers used three stages to ensure high open-loop
gain (see Figure 30) at the expense of additional frequency com-
pensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not adequate
beyond audio frequencies. As can be seen in Figure 30, the first
stage gain is rolled off at high frequencies by the compensation
network. Second stage noise and distortion then appears at the
input and degrade performance. The AD797, on the other hand,
uses a single ultrahigh gain stage to achieve dc as well as dynamic
precision. As shown in the simplified schematic (Figure 31),
Node A, Node B, and Node C track the input voltage, forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated on
the same IC chip, high open-loop gain, CMRR, PSRR, and low
benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
extend to beyond 1 MHz. This means new levels of perform-
ance for sampled data and imaging systems. All of this
performance as well as load drive in excess of 30 mA are made
possible by the Analog Devices, Inc., advanced complementary
bipolar (CB) process.
Another unique feature of this circuit is that the addition of a
single capacitor, CN (see Figure 31), enables cancellation of
distortion due to the output stage. This can best be explained by
referring to a simplified representation of the AD797 using
idealized blocks for the different circuit elements (Figure 32).
A single equation yields the open-loop transfer function of this
amplifier; solving it at Node B yields
VOUT
VIN
gm
=
CN
A
CC
A
jω − CN jω −
jω
VOS are guaranteed by pairwise device matching (that is, NPN
to NPN and PNP to PNP), not by an absolute parameter such as
beta and the early voltage.
where:
gm is the transconductance of Q1 and Q2.
A is the gain of the output stage (~1).
BUFFER
V
OUT
g
V
V
OUT is voltage at the output.
IN is differential input voltage.
m
R
R1
C1
L
When CN is equal to CC, the ideal single-pole op amp response
is attained:
6
GAIN = g × R1 × 5 × 10
m
a.
VOUT
VIN
gm
jωC
C2
=
BUFFER
V
g
A2
C1
A3
OUT
m
In Figure 32, the terms of Node A, which include the properties of
the output stage, such as output impedance and distortion, cancel
by simple subtraction. Therefore, the distortion cancellation does
not affect the stability or frequency response of the amplifier. With
only 500 μA of output stage bias, the AD797 delivers a 1 kHz
sine wave into 60 Ω at 7 V rms with only 1 ppm of distortion.
R1
R
L
R2
GAIN = g × R1 × A2 × A3
m
b.
Figure 30. Model of AD797 vs. That of a Typical Three-Stage Amplifier
V
CC
I1
I2
C
R2
R3
N
C
N
R1
I5
Q4
Q10
Q11
Q3
Q7
A
B
A
B
V
A
OUT
Q9
V
OUT
+IN
–IN
+IN
–IN
Q12 Q8
C
C
CURRENT
MIRROR
Q1 Q2
C
C
Q5
C
Q6
Q1
Q2
1
I6
I1
I7
I4
I3
C
I4
V
SS
Figure 31. AD797 Simplified Schematic
Figure 32. AD797 Block Diagram
This matching benefits not just dc precision, but, because it holds
up dynamically, both distortion and settling time are also reduced.
This single stage has a voltage gain of >5 × 106 and VOS < 80 μV,
while at the same time providing a THD + noise of less than
−120 dB and true 16-bit settling in less than 800 ns. The
elimination of second-stage noise effects has the additional
NOISE AND SOURCE IMPEDANCE
CONSIDERATIONS
The AD797 ultralow voltage noise of 0.9 nV/√Hz is achieved
with special input transistors running at nearly 1 mA of
collector current. Therefore, it is important to consider the total
input-referred noise (eNtotal), which includes contributions
Rev. F | Page ꢀꢀ of 20
AD797
from voltage noise (eN), current noise (iN), and resistor noise
(√4 kTRS).
The plot in Figure 7 uses a slightly different technique: an
FFT-based instrument (Figure 34) is used to generate a 10 Hz
“brickwall” filter. A low frequency pole at 0.1 Hz is generated
with an external ac coupling capacitor, which is also the
instrument being dc coupled.
eN total =[eN + 4 kTRS + (iN × RS )2 ]1/2
(1)
2
where RS is the total input source resistance.
Several precautions are necessary to attain optimum low
frequency noise performance:
This equation is plotted for the AD797 in Figure 33. Because
optimum dc performance is obtained with matched source
resistances, this case is considered even though it is clear from
Equation 1 that eliminating the balancing source resistance
lowers the total noise by reducing the total RS by a factor of 2.
•
Care must be used to account for the effects of RS. Even
a 10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9%
when root sum squared with 0.9 nV/√Hz).
At very low source resistance (RS < 50 Ω), the voltage noise of the
amplifier dominates. As source resistance increases, the Johnson
noise of RS dominates until a higher resistance of RS > 2 kΩ is
achieved; the current noise component is larger than the
resistor noise.
•
•
The test setup must be fully warmed up to prevent eOS drift
from erroneously contributing to input noise.
Circuitry must be shielded from air currents. Heat flow out
of the package through its leads creates the opportunity for
a thermoelectric potential at every junction of different
metals. Selective heating and cooling of these by random
air currents appears as 1/f noise and obscures the true
device noise.
100
TOTAL NOISE
•
The results must be interpreted using valid statistical
techniques.
10
100kΩ
+V
S
RESISTOR
NOISE
ONLY
*
1
1
Ω
2
3
7
HP 3465
1.5µF
DYNAMIC SIGNAL
ANALYZER
(10Hz)
AD797
6
*
V
OUT
4
0.1
10
100
1000
10000
SOURCE RESISTANCE (Ω)
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 33. Noise vs. Source Resistance
Figure 34. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
The AD797 is the optimum choice for low noise performance if
the source resistance is kept <1 kΩ. At higher values of source
resistance, optimum performance with respect to only noise is
obtained with other amplifiers from Analog Devices (Table 3).
WIDEBAND NOISE
Due to its single-stage design, the noise of the AD797 is flat
over frequencies from less than 10 Hz to beyond 1 MHz. This
is not true of most dc precision amplifiers, where second-stage
noise contributes to input-referred noise beyond the audio
frequency range. The AD797 offers new levels of performance in
wideband imaging applications. In sampled data systems, where
aliasing of out-of-band noise into the signal band is a problem,
the AD797 outperforms all previously available IC op amps.
Table 3. Recommended Amplifiers for Different Source
Impedances
RS (kΩ)
0 to <ꢀ
ꢀ to <ꢀ0
ꢀ0 to <ꢀ00
>ꢀ00
Recommended Amplifier
AD797
AD743/AD74±, OP27/OP37, OP07
AD743/AD74±, OP07
AD±48, AD±49, AD7ꢀꢀ, AD743/AD74±
BYPASSING CONSIDERATIONS
Taking full advantage of the very wide bandwidth and dynamic
range capabilities of the AD797 requires some precautions.
First, multiple bypassing is recommended in any precision
application. A 1.0 μF to 4.7 μF tantalum in parallel with 0.1 μF
ceramic bypass capacitors are sufficient in most applications.
When driving heavy loads, a larger demand is placed on the
supply bypassing. In this case, selective use of larger values of
tantalum capacitors and damping of their lead inductance with
small-value (1.1 Ω to 4.7 Ω) carbon resistors can achieve an
improvement. Figure 35 summarizes power supply bypassing
recommendations.
LOW FREQUENCY NOISE
Analog Devices specifies low frequency noise as a peak-to-peak
quantity in a 0.1 Hz to 10 Hz bandwidth. Several techniques can
be used to make this measurement. The usual technique involves
amplifying, filtering, and measuring the amplifier noise for a
predetermined test time. The noise bandwidth of the filter is
corrected for, and the test time is carefully controlled because
the measurement time acts as an additional low frequency roll-off.
Rev. F | Page ꢀ2 of 20
AD797
V
V
S
S
Low noise preamplification is usually performed in the non-
inverting mode (Figure 38). For lowest noise, the equivalent
resistance of the feedback network should be as low as possible.
The 30 mA minimum drive current of the AD797 makes it easier
to achieve this. The feedback resistors can be made as low as
possible, with consideration to load drive and power consumption.
0.1µF
4.7µF TO 22.0µF
OR
4.7µF
0.1µF
1.1Ω TO 4.7Ω
KELVIN RETURN
KELVIN RETURN
USE SHORT
LEAD LENGTHS
(<5mm)
USE SHORT
LEAD LENGTHS
(<5mm)
C
L
LOAD
LOAD
CURRENT
CURRENT
R2
Figure 35. Recommended Power Supply Bypassing
+V
S
THE NONINVERTING CONFIGURATION
*
Ultralow noise requires very low values of the internal parasitic
resistance (rBB) for the input transistors (≈6 Ω). This implies
very little damping of input and output reactive interactions.
With the AD797, additional input series damping is required
for stability with direct output to input feedback. A 100 Ω
resistor (R1) in the inverting input (Figure 36) is sufficient; the
100 Ω balancing resistor (R2) is recommended but is not
required for stability. The noise penalty is minimal (eNtotal ≈
2.1 nV/√Hz), which is usually insignificant.
R1
2
3
7
6
*
AD797
R
L
4
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 38. Low Noise Preamplifier
Table 4 provides some representative values for the AD797
when used as a low noise follower. Operation on 5 V supplies
allows the use of a 100 Ω or less feedback network (R1 + R2).
Because the AD797 shows no unusual behavior when operating
near its maximum rated current, it is suitable for driving the
AD600/AD602 (see Figure 50) while preserving low noise
performance.
R1
100Ω
+V
S
*
2
3
7
6
*
AD797
R2
100Ω
R
600Ω
L
4
Optimum flatness and stability at noise gains >1 sometimes
require a small capacitor (CL) connected across the feedback
resistor (R1 of Figure 38). Table 4 includes recommended values
of CL for several gains. In general, when R2 is greater than
100 Ω and CL is greater than 33 pF, a 100 Ω resistor should be
placed in series with CL. Source resistance matching is assumed,
and the AD797 should not be operated with unbalanced source
resistance >200 kΩ/G.
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 36. Voltage Follower Connection
Best response flatness is obtained with the addition of a small
capacitor (CL < 33 pF) in parallel with the 100 Ω resistor
(Figure 37). The input source resistance and capacitance also
affect the response slightly, and experimentation may be
necessary for best results.
Table 4. Values for Follower with Gain Circuit
Noise
C
L
Gain
2
2
ꢀ0
20
>3±
R1
R2
CL
(Excluding RS)
3.0 nV/√Hz
ꢀ.8 nV/√Hz
ꢀ.2 nV/√Hz
ꢀ.0 nV/√Hz
0.98 nV/√Hz
ꢀ kΩ
ꢀ kΩ
≈20 pF
≈ꢀ0 pF
≈± pF
100Ω
300 Ω
33.2 Ω
ꢀ6.± Ω
ꢀ0 Ω
300 Ω
300 Ω
3ꢀ6 Ω
(G − ꢀ) × ꢀ0 Ω
+V
S
*
2
3
7
AD797
6
*
R
S
The I-to-V converter is a special case of the follower configu-
ration. When the AD797 is used in an I-to-V converter, for
example as a DAC buffer, the circuit shown in Figure 39 should
be used. The value of CL depends on the DAC, and if CL is greater
than 33 pF, a 100 Ω series resistor is required. A bypassed balancing
resistor (RS and CS) can be included to minimize dc errors.
600Ω
4
C
S
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 37. Alternative Voltage Follower Connection
Rev. F | Page ꢀ3 of 20
AD797
20pF TO 120pF
100Ω
DRIVING CAPACITIVE LOADS
R
1
The capacitive load driving capabilities of the AD797 are
displayed in Figure 41. At gains greater than 10, usually no
special precautions are necessary. If more drive is desirable,
however, the circuit shown in Figure 42 should be used. For
example, this circuit allows a 5000 pF load to be driven cleanly
at a noise gain ≥2.
+V
S
*
I
IN
2
3
7
6
*
AD797
600Ω
4
100nF
C
R
S
S
–V
S
10nF
1nF
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 39. I-to-V Converter Connection
THE INVERTING CONFIGURATION
The inverting configuration (see Figure 40) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 makes
it the preferred choice in many inverting applications, and
with careful selection of feedback resistors, the noise penalties
are minimal. Some examples are presented in Table 5 and
Figure 40.
100pF
10pF
1pF
1
10
100
1k
CLOSED-LOOP GAIN
Figure 41. Capacitive Load Drive Capability vs. Closed-Loop Gain
C
L
20pF
R
2
1kΩ
+V
7
S
200pF
100Ω
*
R1
+V
S
2
3
*
6
*
AD797
1kΩ
2
3
7
R
L
4
33Ω
6
*
AD797
R
S
C1
4
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
–V
S
Figure 40. Inverting Amplifier Connection
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Table 5. Values for Inverting Circuit
Figure 42. Recommended Circuit for Driving a High Capacitance Load
Noise
SETTLING TIME
Gain
−ꢀ
−ꢀ
R1
R2
CL
(Excluding RS)
3.0 nV/√Hz
ꢀ.8 nV/√Hz
ꢀ.8 nV/√Hz
The AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 μV) in less than 800 ns. Measuring this
performance presents a challenge. A special test circuit (see
Figure 43) was developed for this purpose. The input signal was
obtained from a resonant reed switch pulse generator, available
from Tektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. The low repetition rate
signal was captured on a digital oscilloscope after being
ꢀ kΩ
300 Ω
ꢀ±0 Ω
ꢀ kΩ
300 Ω
ꢀ±00 Ω
≈20 pF
≈ꢀ0 pF
≈± pF
−ꢀ0
amplified and clamped twice. The selection of plug-in for the
oscilloscope was made for minimum overload recovery.
Rev. F | Page ꢀ4 of 20
AD797
The benefits of adding C1 are evident for closed-loop gains
of ≥100. A maximum value of ≈33 pF at gains of ≥1000 is
recommended. At a gain of 1000, the bandwidth is 450 kHz.
TO TEKTRONIX
7A26
OSCILLOSCOPE
PREAMP INPUT
SECTION
1MΩ
20pF
Table 6 and Figure 45 summarize the performance of the
226Ω
4.26kΩ
AD797 with distortion cancellation and decompensation.
(VIA LESS THAN 1FT
50Ω COAXIAL CABLE)
R1
2
3
–
A2
250Ω
6
AD829
+
50pF
7
2×
HP2835
4
R2
2×
HP2835
0.47µF
2
3
8
0.47µF
6
AD797
+V
S
–V
S
1kΩ
1kΩ
100Ω
1kΩ
TEKTRONIX
CALIBRATION
FIXTURE
R1
V
20pF
IN
1kΩ
C2
C1
2
3
–
A1
6
AD797
+
4
R2
7
2
3
8
51pF
6
AD797
0.1µF
1µF
+V
S
1µF
0.1µF
–V
C1, SEE TABLE
C2 = 50pF – C1
S
NOTES
Figure 44. Recommended Connections for Distortion Cancellation
and Bandwidth Enhancement
USE CIRCUIT BOARD WITH GROUND PLANE.
Figure 43. Settling Time Test Circuit
Table 6. Recommended External Compensation for
Distortion Cancellation and Bandwidth Enhancement
DISTORTION REDUCTION
The AD797 has distortion performance (THD < −120 dB,
@ 20 kHz, 3 V rms, RL = 600 Ω) unequaled by most voltage
feedback amplifiers.
A/B
R2
(Ω) (pF) (pF) BW
A
B
R1
C1
C2
3 dB
C1
C2
3 dB
Gain (Ω)
(pF) (pF) BW
ꢀ0
ꢀ00
909 ꢀ00
ꢀ k ꢀ0
0
0
0
±0
±0
±0
6 MHz
ꢀ MHz
ꢀꢀ0 kHz 33
0
ꢀ±
±0
33
ꢀ±
6 MHz
ꢀ.± MHz
4±0 kHz
At higher gains and higher frequencies, THD increases due to a
reduction in loop gain. However, in contrast to most conven-
tional voltage feedback amplifiers, the AD797 provides two
effective means of reducing distortion as gain and frequency
are increased: cancellation of the output stage’s distortion and
gain bandwidth enhancement by decompensation. By applying
these techniques, gain bandwidth can be increased to 450 MHz
at G = 1000, and distortion can be held to −100 dB at 20 kHz for
G = 100.
ꢀ000 ꢀ0 k ꢀ0
0.01
–80
G = +1000
R
= 600Ω
L
0.003
–90
NOISE LIMIT, G = +1000
NOISE LIMIT, G = +100
G = +1000
R
= 10kΩ
L
0.001
–100
–110
–120
The unique design of the AD797 provides cancellation of the
output stage’s distortion. To achieve this, a capacitance equal to
the effective compensation capacitance, usually 50 pF, is
connected between Pin 8 and the output (see C2 in Figure 44).
Use of this feature improves distortion performance when the
closed-loop gain is more than 10 or when frequencies of interest
are greater than 30 kHz.
G = +100
= 600Ω
R
L
0.0003
0.0001
G = +10
= 600Ω
R
L
100
300
1k
3k
10k
30k
100k
300k
Bandwidth enhancement via decompensation is achieved by
connecting a capacitor from Pin 8 to ground (see C1 in Figure 44).
Adding C1 results in subtracting from the value of the internal
compensation capacitance (50 pF), yielding a smaller effective
compensation capacitance and therefore a larger bandwidth.
FREQUENCY (Hz)
Figure 45. Total Harmonic Distortion (THD) vs. Frequency @ 3 V rms
for Figure 44b
Differential Line Receiver
The differential receiver circuit of Figure 46 is useful for many
applications, from audio to MRI imaging. The circuit allows
Rev. F | Page ꢀ± of 20
AD797
extraction of a low level signal in the presence of common-
mode noise. As shown in Figure 47, the AD797 provides this
function with only 9 nV/√Hz noise at the output. Figure 48
shows the AD797 20-bit THD performance over the audio band
and the 16-bit accuracy to 250 kHz.
A General-Purpose ATE/Instrumentation I/O Driver
The ultralow noise and distortion of the AD797 can be
combined with the wide bandwidth, slew rate, and load drive
of a current feedback amplifier to yield a very wide dynamic
range general-purpose driver. The circuit shown in Figure 49
combines the AD797 with the AD811 in just such an
application. Using the component values shown, this circuit is
capable of better than −90 dB THD with a 5 V, 500 kHz output
signal. The circuit is, therefore, suitable for driving a high
resolution ADC as an output driver in automatic test equipment
(ATE) systems. Using a 100 kHz sine wave, the circuit drives a
600 Ω load to a level of 7 V rms with less than −109 dB THD
and a 10 kΩ load at less than −117 dB THD.
20pF
1kΩ
1kΩ
+V
S
**
50pF*
7
DIFFERENTIAL
INPUT
2
3
8
4
AD797
6
22pF
**
–V
S
R2
1kΩ
1kΩ
2kΩ
+V
7
S
*
20pF
+V
7
S
2
3
*
*OPTIONAL
**USE THE POWER SUPPLY BYPASSING
SHOWN IN FIGURE 35.
3
AD797
6
*
1kΩ
Figure 46. Differential Line Receiver
V
IN
4
AD811
6
*
V
OUT
16
14
12
10
8
2
4
–V
S
–V
S
649Ω
649Ω
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 49. A General-Purpose ATE/Instrumentation I/O Driver
Ultrasound/Sonar Imaging Preamp
The AD600 variable gain amplifier provides the time-controlled
gain (TCG) function necessary for very wide dynamic range
sonar and low frequency ultrasound applications. Under some
circumstances, it is necessary to buffer the input of the AD600
to preserve its low noise performance. To optimize dynamic
range, this buffer should have a maximum of 6 dB of gain. The
combination of low noise and low gain is difficult to achieve.
The input buffer circuit shown in Figure 50 provides 1 nV/√Hz
noise performance at a gain of 2 (dc to 1 MHz) by using
26.1 Ω resistors in its feedback path. Distortion is only −50 dBc
at 1 MHz for a 2 V p-p output level and drops rapidly to better
than −70 dBc at an output level of 200 mV p-p.
6
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 47. Output Voltage Noise Spectral Density
for Differential Line Receiver
–90
–100
–110
–120
–130
0.003
WITHOUT
OPTIONAL
50pF C
0.001
N
MEASUREMENT
0.0003
0.0001
LIMIT
WITH
OPTIONAL
50pF C
N
100
300
1k
3k
10k
30k
100k
300k
FREQUENCY (Hz)
Figure 48. Total Harmonic Distortion (THD) vs. Frequency
for Differential Line Receiver
Rev. F | Page ꢀ6 of 20
AD797
26.1Ω
Professional Audio Signal Processing—DAC Buffers
The low noise and low distortion of the AD797 make it an ideal
choice for professional audio signal processing. An ideal I-to-V
converter for a current output DAC would simply be a resistor
to ground, were it not for the fact that most DACs do not operate
linearly with voltage on their output. Standard practice is to
operate an op amp as an I-to-V converter, creating a virtual
ground at its inverting input. Normally, clock energy and current
steps must be absorbed by the op amp output stage. However, in
the configuration shown in Figure 53, Capacitor CF shunts high
frequency energy to ground while correctly reproducing the
desired output with extremely low THD and IMD.
+V
7
S
*
*
26.1Ω
2
3
V
OUT
6
*
AD600
AD797
V
4
IN
*
–V
S
V
= ±6Vdc
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
Figure 50. An Ultrasound Preamplifier Circuit
Amorphous (Photodiode) Detector
C
F
Large area photodiodes (CS ≥ 500 pF) and certain image
detectors (amorphous Si) have optimum performance when used
in conjunction with amplifiers with very low voltage (rather than
very low current noise). Figure 51 shows the AD797 used with
an amorphous Si (CS = 1000 pF) detector. The response is adjusted
for flatness using capacitor CL, and the noise is dominated by
voltage noise amplified by the ac noise gain. The AD797’s excellent
input noise performance gives 27 μV rms total noise in a 1 MHz
bandwidth, as shown by Figure 52.
82pF
100Ω
3kΩ
+V
S
*
AD1862
DAC
2
3
7
C1
2000pF
V
6
*
AD797
OUT
4
C
L
100Ω 50pF
–V
S
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
10kΩ
Figure 53. A Professional Audio DAC Buffer
+V
7
S
+V
S
*
2
3
–IN
+IN
2
3
7
C
S
V
OUT
AD797
6
*
I
S
V
AD797
6
OUT
1000pF
5
4
1
4
20kΩ
–V
S
V
ADJUST
OS
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
–V
S
Figure 51. Amorphous Detector Preamp
Figure 54. Offset Null Configuration
–30
–40
–50
–60
–70
–80
100
80
60
40
20
0
V
OUT
NOISE
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 52. Total Integrated Voltage Noise and VOUT
of Amorphous Detector Preamp
Rev. F | Page ꢀ7 of 20
AD797
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 55. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Rev. F | Page ꢀ8 of 20
AD797
ORDERING GUIDE
Model
AD797AN
AD797ANZꢀ
Temperature Range
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
−40°C to +8±°C
Package Description
Package Option
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
AD797AR
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
AD797AR-REEL
AD797AR-REEL7
AD797ARZꢀ
AD797ARZ-REELꢀ
AD797ARZ-REEL7ꢀ
AD797BR
AD797BR-REEL
AD797BR-REEL7
AD797BRZꢀ
AD797BRZ-REELꢀ
AD797BRZ-REEL7ꢀ
ꢀ Z = RoHS Compliant Part.
Rev. F | Page ꢀ9 of 20
AD797
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00846-0-1/08(F)
Rev. F | Page 20 of 20
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