AD7986 [ADI]
1 nV/√Hz, Low Power; 1内华达州/ √Hz的低功耗
| 型号： | AD7986 |
| 厂家： | 
ADI |
| 描述： | 1 nV/√Hz, Low Power |
| 文件： | 总28页 (文件大小：624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 nV/√Hz, Low Power,
Rail-to-Rail Output Amplifiers
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low wideband noise
1 nV/√Hz
2.8 pA/√Hz
NC
–IN
+IN
1
2
3
4
8
7
6
5
DISABLE
+V
S
OUT
NC
Low 1/f noise: 2.4 nV/√Hz at 10 Hz
Low distortion: −115 dBc at 100 kHz, VOUT = 2 V p-p
Low power: 3 mA per amplifier
Low input offset voltage: 0.5 mV maximum
High speed
−3 dB bandwidth: 230 MHz (G = +1)
Slew rate: 120 V/μs
Settling time to 0.1%: 45 ns
Rail-to-rail output
–V
S
Figure 1. 8-Lead SOIC (ADA4897-1)
8
7
6
5
4
3
2
1
0
V
= ±5V
S
Wide supply range: 3 V to 10 V
Disable feature (ADA4897-1/ADA4897-2)
APPLICATIONS
Low noise preamplifier
Ultrasound amplifiers
PLL loop filters
High performance ADC drivers
DAC buffers
1
10
100
1k
10k
100k
1M
5M
FREQUENCY (Hz)
Figure 2. Voltage Noise vs. Frequency
GENERAL DESCRIPTION
The ADA4896-2/ADA4897-1/ADA4897-2 are unity-gain stable,
low noise, rail-to-rail output, high speed voltage feedback amplifiers
that have a quiescent current of 3 mA. With a 1/f noise of
2.4 nV/√Hz at 10 Hz and a spurious-free dynamic range of −80 dBc
at 2 MHz, the ADA4896-2/ADA4897-1/ADA4897-2 are ideal
solutions in a variety of applications, including ultrasound, low
noise preamplifiers, and drivers of high performance ADCs. The
Analog Devices, Inc., proprietary next-generation SiGe bipolar
process and innovative architecture enable such high performance
amplifiers.
Table 1. Other Low Noise Amplifiers
VN (nV/√Hz)
Supply
Part No.
AD797
AD8021
AD8099
AD8045
ADA4899-1
At 1 kHz
At 100 kHz BW (MHz) Voltage (V)
0.9
5
3
6
1.4
0.9
2.1
0.95
3
8
10 to 30
5 to 24
5 to 12
3.3 to 12
5 to 12
10 to 32
490
510
1000
600
65
1
ADA4898-1/ 0.9
ADA4898-2
0.9
The ADA4896-2/ADA4897-1/ADA4897-2 have 230 MHz
bandwidth, 120 V/μs slew rate, and settle to 0.1% in 45 ns.
With a wide supply voltage range of 3 V to 10 V, the ADA4896-2/
ADA4897-1/ADA4897-2 are ideal candidates for systems that
require high dynamic range, precision, low power, and high speed.
Table 2. Complementary ADCs
Part No.
AD7944
AD7985
AD7986
Bits
Speed (MSPS)
Power (mW)
14
16
18
2.5
2.5
2
15.5
15.5
15
The ADA4896-2 is available in 8-lead LFCSP and 8-lead MSOP
packages. The ADA4897-1 is available in 8-lead SOIC and 6-lead
SOT-23 packages. The ADA4897-2 is available in a 10-lead MSOP
package. The ADA4896-2/ADA4897-1/ADA4897-2 operate over
the extended industrial temperature range of −40°C to +125°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Amplifier Description................................................................ 17
Input Protection ......................................................................... 17
Disable Operation ...................................................................... 17
DC Errors .................................................................................... 18
Bias Current Cancellation ......................................................... 18
Noise Considerations................................................................. 19
Capacitance Drive ...................................................................... 19
Applications Information.............................................................. 20
Typical Performance ꢀalues...................................................... 20
Low Noise, Gain Selectable Amplifier..................................... 21
Medical Ultrasound Applications ............................................ 22
Layout Considerations............................................................... 24
Outline Dimensions....................................................................... 2±
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±± ꢀ Supply................................................................................... 3
+± ꢀ Supply................................................................................... 4
+3 ꢀ Supply................................................................................... 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Maximum Power Dissipation ..................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
REVISION HISTORY
4/12—Rev. A to Rev. B
Change to Figure 26; Moved Figure 26........................................ 13
Changes to Figure 37...................................................................... 1±
Changed 6-Lead Single SOT-23 (ADA4897-1) Thermal
Reistance from 306°C/W to 1±0°C/W........................................... 8
Changes to Figure 3.......................................................................... 8
Changes to Amplifier Description Section, Disable Operation
Section, Figure 44, and Figure 4±................................................. 17
Added Bias Current Cancellation Section, Figure 47,
10/11—Rev. 0 to Rev. A
Added ADA4897-2 and 10-Lead MSOP .........................Universal
Change to Table 1 ............................................................................. 1
Changes to Table 3............................................................................ 3
Changes to Table 4............................................................................ 4
Changes to Table ±............................................................................ 6
Changes to Table 7 and Figure 3..................................................... 8
Changes to Figure 4, Table 8, and Table 9 ..................................... 9
Added Figure 8 and Table 10; Renumbered Sequentially ......... 10
Changed Summary Statement for Typical Performance
Table 11, and Table 12.................................................................... 18
Changes to Table 13 ....................................................................... 20
Changes to Low Noise, Gain Selectable Amplifier Section
and Figure ±2................................................................................... 21
Deleted Figure ±1............................................................................ 22
Changes to Power Supply Bypassing Section ............................. 24
Moved Figure ±7............................................................................. 2±
Moved Figure ±8............................................................................. 26
Added Figure 60 ............................................................................. 27
Changes to Ordering Guide.......................................................... 27
Characteristics Section................................................................... 11
Changes to Figure 18...................................................................... 12
Change to Figure 20 ....................................................................... 12
7/11—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
SPECIFICATIONS
±±5 5ꢀSUUPL5
TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted.
Table 3.
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
230
30
90
7
120
45
90
MHz
MHz
MHz
MHz
V/μs
ns
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 6 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (SFDR)
ns
VOUT = 2 V p-p
fC = 100 kHz
fC = 1 MHz
fC = 2 MHz
fC = 5 MHz
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
−115
−93
−80
−61
2.4
1
11
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
G = +101, RF = 1 kΩ, RG = 10 Ω
−500
−17
−28
0.2
−11
3
−0.02
110
+500
−4
μV
μV/°C
μA
nA/°C
μA
dB
−0.6
100
+0.6
VOUT = −4 V to +4 V
INPUT CHARACTERISTICS
Input Resistance
Common-Mode
Differential
10
10
MΩ
kΩ
Input Capacitance
Common-Mode
Differential
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
(CMRR)
3
11
pF
pF
V
−4.9 to +4.1
−120
VCM = −2 V to +2 V
VIN = 5 V, G = +2
−92
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Positive
81
ns
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
RL = 100 Ω
SFDR = −45 dBc
Sinking/sourcing
30% overshoot, G = +2
4.85
4.5
−4.85
−4.5
4.96
4.73
−4.97
−4.84
80
V
V
V
V
mA
mA
pF
Negative
Output Current
Short-Circuit Current
Capacitive Load Drive
135
39
Rev.B | Page 3 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3 to 10
3.0
0.13
V
mA
mA
2.8
3.2
0.25
DISABLE = −5 V
Power Supply Rejection Ratio (PSRR)
Positive
Negative
+VS = 4 V to 6 V, −VS = −5 V
+VS = 5 V, −VS = −4 V to −6 V
−96
−96
−125
−121
dB
dB
DISABLE PIN (ADA4897-1/ADA4897-2)
DISABLE Voltage
Enabled
Disabled
>+VS − 0.5
<+VS − 2
V
V
Input Current
Enabled
DISABLE = +5 V
DISABLE = −5 V
−1.2
−40
μA
μA
Disabled
Switching Speed
Enabled
Disabled
0.25
12
μs
μs
+±5 5ꢀSUUPL5
TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 4.
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
230
30
90
7
100
45
95
MHz
MHz
MHz
MHz
V/μs
ns
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 3 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (SFDR)
ns
VOUT = 2 V p-p
fC = 100 kHz
fC = 1 MHz
fC = 2 MHz
fC = 5 MHz
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
−115
−93
−80
−61
2.4
1
11
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
G = +101, RF = 1 kΩ, RG = 10 Ω
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
−500
−17
−30
0.2
−11
3
−0.02
110
+500
−4
μV
μV/°C
μA
nA/°C
μA
dB
−0.6
97
+0.6
VOUT = 0.5 V to 4.5 V
Rev.B | Page 4 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
INPUT CHARACTERISTICS
Input Resistance
Common-Mode
Differential
10
10
MΩ
kΩ
Input Capacitance
Common-Mode
Differential
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
(CMRR)
3
11
0.1 to 4.1
−118
pF
pF
V
VCM = 1 V to 4 V
−91
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Positive
VIN = 0 V to 5 V, G = +2
96
ns
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
RL = 100 Ω
SFDR = −45 dBc
Sinking/sourcing
30% overshoot, G = +2
4.85
4.8
0.15
0.2
4.98
4.88
0.014
0.08
70
V
V
V
V
mA
mA
pF
Negative
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
125
39
Operating Range
Quiescent Current per Amplifier
3 to 10
2.8
0.05
V
mA
mA
2.6
2.9
0.18
DISABLE = 0 V
Power Supply Rejection Ratio (PSRR)
Positive
Negative
+VS = 4.5 V to 5.5 V, −VS = 0 V
+VS = 5 V, −VS = −0.5 V to +0.5 V
−96
−96
−123
−121
dB
dB
DISABLE PIN (ADA4897-1/ADA4897-2)
DISABLE Voltage
Enabled
Disabled
>+VS − 0.5
<+VS − 2
V
V
Input Current
Enabled
DISABLE = +5 V
DISABLE = 0 V
−1.2
−20
μA
μA
Disabled
Switching Speed
Enabled
Disabled
0.25
12
μs
μs
Rev.B | Page 5 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
+35 5ꢀSUUPL5
TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 5.
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = −1, VOUT = 1 V p-p
230
45
90
7
85
45
96
MHz
MHz
MHz
MHz
V/μs
ns
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 1 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (SFDR)
ns
fC = 100 kHz, VOUT = 2 V p-p, G = +2
fC = 1 MHz, VOUT = 1 V p-p, G = −1
fC = 2 MHz, VOUT = 1 V p-p, G = −1
fC = 5 MHz, VOUT = 1 V p-p, G = −1
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
G = +101, RF = 1 kΩ, RG = 10 Ω
−105
−84
−77
−60
2.3
1
11
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
−500
−17
−30
0.2
−11
3
−0.02
108
+500
−4
μV
μV/°C
μA
nA/°C
μA
dB
−0.6
95
+0.6
VOUT = 0.5 V to 2.5 V
INPUT CHARACTERISTICS
Input Resistance
Common-Mode
Differential
10
10
MΩ
kΩ
Input Capacitance
Common-Mode
Differential
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
(CMRR)
3
11
0.1 to 2.1
−124
pF
pF
V
VCM = 1.1 V to 1.9 V
−90
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Positive
VIN = 0 V to 3 V, G = +2
83
ns
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
RL = 100 Ω
SFDR = −45 dBc
Sinking/sourcing
30% overshoot, G = +2
2.85
2.8
0.15
0.2
2.97
2.92
0.01
0.05
60
V
V
V
V
mA
mA
pF
Negative
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
120
39
Operating Range
Quiescent Current per Amplifier
3 to 10
2.7
0.035
V
mA
mA
2.5
2.9
0.15
DISABLE = 0 V
Rev.B | Page 6 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
Power Supply Rejection Ratio (PSRR)
Positive
Negative
+VS = 2.7 V to 3.7 V, −VS = 0 V
+VS = 3 V, −VS = −0.3 V to +0.7 V
−96
−96
−121
−120
dB
dB
DISABLE PIN (ADA4897-1/ADA4897-2)
DISABLE Voltage
Enabled
Disabled
>+VS − 0.5
<−VS + 2
V
V
Input Current
Enabled
DISABLE = +3 V
DISABLE = 0 V
−1.2
−15
μA
μA
Disabled
Switching Speed
Enabled
Disabled
0.25
12
μs
μs
Rev.B | Page 7 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
The quiescent power dissipation is the voltage between the supply
pins ( VS) multiplied by the quiescent current (IS).
Table 6.
Parameter
Rating
PD = Quiescent Power + (Total Drive Power − Load Power)
Supply Voltage
11 V
Power Dissipation
See Figure 3
−VS − 0.7 V to +VS + 0.7 V
0.7 V
−65°C to +125°C
−40°C to +125°C
300°C
2
VS VOUT
VOUT
RL
PD
VS IS
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
2
RL
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the worst
case, when VOUT = VS/4 for RL to midsupply.
150°C
2
VS / 4
RL
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PD
VS IS
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
and exposed paddle from metal traces, through holes, ground,
and power planes reduces θJA.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for surface-
mount packages. Table 7 lists the θJA for the ADA4896-2/
ADA4897-1/ADA4897-2.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a JEDEC standard
4-layer board. θJA values are approximations.
3.5
T
= 150°C
J
Table 7. Thermal Resistance
Package Type
3.0
2.5
2.0
1.5
1.0
0.5
0
θJA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
8-Lead Dual MSOP (ADA4896-2)
8-Lead Dual LFCSP (ADA4896-2)
8-Lead Single SOIC (ADA4897-1)
6-Lead Single SOT-23 (ADA4897-1)
10-Lead Dual MSOP (ADA4897-2)
222
61
133
150
210
8-LEAD LFCSP
6-LEAD SOT-23
10-LEAD MSOP
8-LEAD SOIC
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4896-2/
ADA4897-1/ADA4897-2 is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150C,
which is the glass transition temperature, the properties of the
plastic change. Even temporarily exceeding this temperature
limit may change the stresses that the package exerts on the
die, permanently shifting the parametric performance of the
ADA4896-2/ADA4897-1/ADA4897-2. Exceeding a junction
temperature of 175C for an extended period of time can result
in changes in silicon devices, potentially causing degradation or
loss of functionality.
8-LEAD MSOP
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4896-2/ADA4897-1/ADA4897-2 drive at
the output.
Rev. B | Page 8 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADA4896-2
OUT1 1
–IN1 2
+IN1 3
8
7
6
5
+V
S
OUT2
–IN2
+IN2
ADA4896-2
OUT1
–IN1
+IN1
1
2
3
4
8
7
6
5
+V
S
OUT2
–IN2
–V
4
S
NOTES
–V
+IN2
S
1. THE EXPOSED PAD CAN BE
CONNECTED TO GND OR
POWER PLANES, OR IT CAN
BE LEFT FLOATING.
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead LFCSP Pin Configuration
Figure 5. 8-Lead MSOP Pin Configuration
Table 8. ADA4896-2 Pin Function Descriptions
Uin5No.5
Mnemonic5
OUT1
−IN1
+IN1
−VS
+IN2
−IN2
OUT2
+VS
Description5
1
2
3
4
5
6
7
8
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
EPAD
Exposed Pad (LFCSP Only). The exposed pad can be connected to GND or power planes, or it can
be left floating.
NC
–IN
+IN
1
2
3
8
7
6
5
DISABLE
OUT
1
2
3
6
5
4
+V
S
+V
S
OUT
NC
–V
DISABLE
–IN
S
–V
4
S
ADA4897-1
+IN
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
ADA4897-1
Figure 6. 8-Lead SOIC Pin Configuration
Figure 7. 6-Lead SOT-23 Pin Configuration
Table 9. ADA4897-1 Pin Function Descriptions
Uin5No.5
ꢀOIC5
ꢀOT-235 Mnemonic5Description5
1, 5
2
N/A
4
NC
−IN
No Connect. Do not connect to these pins.
Inverting Input.
3
4
6
7
3
2
1
6
+IN
−VS
OUT
+VS
Noninverting Input.
Negative Supply.
Output.
Positive Supply.
8
5
DISABLE
Disable.
Rev.B | Page 9 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
OUT1
1
2
3
4
5
10 +V
S
–IN1
+IN1
9
8
7
6
OUT2
–IN2
–V
+IN2
S
ADA4897-2
DISABLE1
DISABLE2
Figure 8. 10-Lead MSOP Pin Configuration
Table 10. ADA4897-2 Pin Function Descriptions
Uin5No.5
Mnemonic5
Description5
1
2
3
4
5
6
7
8
9
10
OUT1
−IN1
+IN1
−VS
DISABLE1
DISABLE2
+IN2
−IN2
OUT2
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Disable 1.
Disable 2.
Noninverting Input 2.
Inverting Input 2.
Output 2.
+VS
Positive Supply.
Rev.B | Page 10 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
TYPICAL PERFORMANCE CHARACTERISTICS
RL = 1 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω; otherwise, RF = 249 Ω.
2
2
V
V
= +5V
V = ±5V
S
G = +1
S
= 20mV p-p
OUT
G = +1
1
1
20mV p-p
0
0
G = –1 OR
G = +2
–1
–2
–3
–4
–5
–6
100mV p-p
400mV p-p
–1
–2
–3
–4
–5
G = +10
2V p-p
0.1
1
10
FREQUENCY (MHz)
100
300
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response vs. Gain
Figure 12. Frequency Response for Various Output Voltages
2
1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
G = +1
= 20mV p-p
V
V
= +5V
S
V
= +3V
V
= +5V
S
S
V
= 2V p-p
OUT
OUT
G = +2
R
= R = 249Ω
G
F
R
= 1kΩ
L
R
= R = 100Ω
G
F
0
V
= ±5V
S
R
= R = 49.9Ω
G
F
–1
–2
–3
–4
–5
–0.1
–0.2
–0.3
0.1
1
10
FREQUENCY (MHz)
100
500
0.1
1
10
50
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response vs. Supply Voltage
Figure 13. 0.1 dB Bandwidth at Selected RF Values
2
2
1
V
= +5V
S
V
OUT
= +5V
S
–40°C
G = –1
G = +1
G = +1
= 20mV p-p
V
= 2V p-p
V
OUT
1
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
+125°C
+25°C
G = +10
100k
1M
10M
100M
1G
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (Hz)
Figure 11. Small Signal Frequency Response vs. Temperature
Figure 14. Large Signal Frequency Response vs. Gain
Rev.B | Page 11 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
–30
4
V
V
= +5V
OUT
V
= +5V
S
S
= 2V p-p
G = +2
C
= 39pF
L
–40 G = +10
R
V
= 100Ω
L
3
2
= 20mV p-p
R
= 100ꢀ, SECOND
OUT
L
–50
–60
–70
–80
–90
1
0
C
= 20pF
L
R
= 100ꢀ, THIRD
L
–1
–2
–3
R
= 1kꢀ, THIRD
L
C
= 0pF
L
–100
R
= 1kꢀ, SECOND
L
–110
0.1
1
5
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response vs. Capacitive Load
Figure 18. Harmonic Distortion vs. Frequency, G = +10
–50
–50
V
= ±5V
V
V
= +5V
S
S
G = +1
= 1kꢀ
= 2V p-p
OUT
R
G = +1
–60
–70
–60
–70
L
R
= 100ꢀ, SECOND
L
–80
–80
R
= 100ꢀ, THIRD
L
8V p-p, THIRD
8V p-p, SECOND
–90
–90
2V p-p, SECOND
2V p-p, THIRD
R
= 1kꢀ, THIRD
L
–100
–110
–120
–100
–110
–120
4V p-p, SECOND
4V p-p, THIRD
R
= 1kꢀ, SECOND
L
1
5
0.1
1
0.1
5
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Harmonic Distortion vs. Frequency, G = +1
Figure 19. Harmonic Distortion vs. Frequency for Various Output Voltages
–40
–50
–50
V
V
= +5V
OUT
G = +5
G = +2
L
S
V
= +5V,
S
= 2V p-p
R
= 1kꢀ
SECOND
–60
–70
R
= 100ꢀ, SECOND
L
V
= +5V,
S
–60
THIRD
–80
–70
V
= +3V,
S
–90
SECOND
V
= ±5V,
S
SECOND
–80
–100
–110
–120
–130
R
= 100ꢀ, THIRD
L
–90
V
= ±5V,
THIRD
S
R
= 1kꢀ, THIRD
L
–100
V
= +3V,
THIRD
S
R
= 1kꢀ, SECOND
L
–110
0.1
1
5
0.1
1
5
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Harmonic Distortion vs. Frequency for Various Supplies
Figure 17. Harmonic Distortion vs. Frequency, G = +5
Rev.B | Page 12 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
18
16
14
12
10
8
90
80
70
60
50
40
30
20
10
0
–80
V
= ±5V
S
100 UNITS
σ = 309.2µV/°C
–100
–120
–140
–160
–180
–200
PHASE
GAIN
6
4
–220
–240
2
–10
–20
10k
0
–600
–400
–200
0
200
400
600
800
1000
100k
1M
10M
100M
1G
FREQUENCY (Hz)
OFFSET VOLTAGE DRIFT DISTRIBUTION (nV/°C)
Figure 21. Open-Loop Gain and Phase vs. Frequency
Figure 24. Input Offset Voltage Drift Distribution
8
7
6
5
4
3
2
1
0
G = +1
OUT
TIME = 100ns/DIV
V
V
= +3V
= +5V
V
= ±5V
S
S
S
V
= 20mV p-p
10
V
= ±5V
S
0
–10
1
10
100
1k
10k
100k
1M
5M
FREQUENCY (Hz)
Figure 22. Voltage Noise vs. Frequency
Figure 25. Small Signal Transient Response for Various Supplies, G = +1
100
10
1
V
V
= +3V
= +5V
G = +2
= 20mV p-p
S
S
V
= ±5V
S
V
OUT
TIME = 100ns/DIV
10
V
= ±5V
S
0
–10
1
10
100
1k
10k
100k
1M
5M
FREQUENCY (Hz)
Figure 23. Current Noise vs. Frequency
Figure 26. Small Signal Transient Response for Various Supplies, G = +2
Rev.B | Page 13 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
3
2
V
= ±5V
S
C
C
= 39pF
= 20pF
= 0pF
V
= +5V
L
2× V
S
IN
G = +2
G = +2
TIME = 100ns/DIV
L
L
TIME = 100ns/DIV
C
V
OUT
10
0
1
0
–1
–2
–3
–10
Figure 27. Small Signal Transient Response for Various Capacitive Loads
Figure 30. Output Overdrive Recovery Time
1.5
250
200
150
100
50
V
V
= ±5V
S
V
= +5V
S
= 2V p-p
G = +2
G = +1
OUT
G = +2
TIME = 100ns/DIV
1.0
0.5
0
–0.5
–1.0
–1.5
0
0
100
200
300
400
500
600
700
800
900
OVERLOAD DURATION (ns)
Figure 28. Large Signal Transient Response, G = +1 and G = +2
Figure 31. Average Output Overload Recovery Time vs. Overload Duration
4
105.0
V
V
= 3V p-p
= +5V
V
= +5V
OUT
S
G = +1
S
102.5
100.0
97.5
95.0
92.5
90.0
87.5
85.0
82.5
80.0
V
TIME = 100ns/DIV
3
2
IN
G = +2
RISING EDGE
1
V
OUT
FALLING EDGE
0
–1
–2
–3
–4
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 29. Input Overdrive Recovery Time
Figure 32. Slew Rate vs. Temperature
Rev.B | Page 14 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
0.3
100000
10000
1000
100
V
= +5V
V = +5V
S
G = +1
P = –30dBm
IN
S
G = +2
= 2V STEP
V
R
OUT
= 1kꢀ
0.2
L
PART DISABLED
TIME = 10ns/DIV
0.1
0
10
PART ENABLED
–0.1
–0.2
–0.3
1
0.1
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 33. Settling Time to 0.1%
Figure 36. Output Impedance vs. Frequency
–26.0
–28.5
–31.0
–33.5
–20
V
= +5V
S
–30 ΔV
= 2V p-p
CM
–40
V
= ±5V
S
–50
V
= +5V
S
–60
–70
V
= +3V
S
–80
–90
–100
–110
–120
–130
–40 –25 –10
5
20
35
50
65
80
95 110 125
1k
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 34. CMRR vs. Frequency
Figure 37. Input Offset Voltage vs. Temperature for Various Supplies
0
–10.50
V
= +5V
S
V
= ±5V
–10
–20
S
ΔV = 2V p-p
G = +1
S
–30
–10.75
–11.00
–11.25
–11.50
–40
V
= +5V
S
–50
–PSRR
–60
–70
+PSRR
–80
V
= +3V
S
–90
–100
–110
–120
–130
1k
10k
100k
1M
10M
100M
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 35. PSRR vs. Frequency
Figure 38. Input Bias Current vs. Temperature for Various Supplies
Rev.B | Page 15 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
3.2
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.875
TIME = 2µs/DIV
= +5V
DISABLE PIN
V
3.750
3.625
3.500
3.375
3.250
3.125
3.000
2.875
2.750
2.625
2.500
2.375
S
V
= ±5V
S
G = +1
= 1V
3.1
3.0
2.9
2.8
2.7
2.6
2.5
V
IN
+25°C
–40°C
V
= +5V
S
V
= +3V
S
+125°C
–0.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 39. Supply Current vs. Temperature for Various Supplies
Figure 42. Turn-Off Time vs. Temperature (ADA4897-1 and ADA4897-2)
–40
–30
V
= +5V
V = +5V
S
S
G = +2
= 2V p-p
G = +2
–40
–50
–50
–60
V
R
= 100ꢀ
= 2V p-p
OUT
L
V
OUT
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
0.01
0.1
1
10
100
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40. Crosstalk, OUT1 to OUT2 (ADA4896-2 and ADA4897-2)
Figure 43. Forward Isolation vs. Frequency
5.5
3.875
3.750
3.625
3.500
3.375
3.250
3.125
3.000
2.875
2.750
2.625
2.500
2.375
DISABLE PIN
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+125°C
+25°C
–40°C
TIME = 200ns/DIV
V
= +5V
S
G = +1
= 1V
V
IN
–0.5
Figure 41. Turn-On Time vs. Temperature (ADA4897-1 and ADA4897-2)
Rev.B | Page 16 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
THEORY OF OPERATION
The ESD clamps begin to conduct for input voltages that are
more than 0.7 V above the positive supply and input voltages
more than 0.7 V below the negative supply. If an overvoltage
condition is expected, it is recommended that the input current
be limited to less than 10 mA.
AMPLIFIER DESCRIPTION
The ADA4896-2/ADA4897-1/ADA4897-2 are 1 nV/√Hz input
noise amplifiers that consume 3 mA from supplies ranging from
3 V to 10 V. Fabricated on the Analog Devices SiGe bipolar process,
the ADA4896-2/ADA4897-1/ADA4897-2 have a bandwidth in
excess of 200 MHz. The amplifiers are unity-gain stable, and the
input structure results in an extremely low input 1/f noise for a
high speed amplifier.
DISABLE OPERATION
Figure 45 shows the ADA4897-1/ADA4897-2 power-down
DISABLE
circuitry. If the
pin is left unconnected, the base of
The rail-to-rail output stage is designed to drive the heavy feed-
back load required to achieve an overall low output referred noise.
To meet more demanding system requirements, the large signal
bandwidth of the ADA4896-2/ADA4897-1/ADA4897-2 was
increased beyond the typical fundamental limits of other low noise,
unity-gain stable amplifiers. The maximum offset voltage of 500 μV
and drift of 0.2 μV/°C make the ADA4896-2/ADA4897-1/
ADA4897-2 excellent amplifier choices even when the low noise
performance is not needed because there is minimal power
penalty in achieving the low input noise or the high bandwidth.
the input PNP transistor is pulled high through the internal
pull-up resistor to the positive supply and the part is turned
DISABLE
on. Pulling the
pin to ≥2 V below the positive supply
turns the part off, reducing the supply current to approximately
18 μA for a 5 V voltage supply.
+V
S
I
BIAS
ESD
ESD
DISABLE
TO
AMPLIFIER
BIAS
INPUT PROTECTION
The ADA4896-2/ADA4897-1/ADA4897-2 are fully protected
from ESD events, withstanding human body model ESD events
of 2.5 kV and charged-device model events of 1 kV with no mea-
sured performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 44.
–V
S
DISABLE
Figure 45.
Circuit
+V
S
DISABLE
The
Figure 45. Voltages beyond the power supplies cause these
DISABLE
pin is protected by ESD clamps, as shown in
BIAS
diodes to conduct. For protection of the
pin, the
ESD
+IN
ESD
ESD
ESD
voltage to this pin should not exceed 0.7 V above the positive
supply or 0.7 V below the negative supply. If an overvoltage
condition is expected, it is recommended that the input current
be limited with a series resistor to less than 10 mA.
–IN
–V
S
When the amplifier is disabled, its output goes to a high
impedance state. The output impedance decreases as frequency
increases; this effect can be observed in Figure 36. In disable
mode, a forward isolation of 50 dB can be achieved at 10 MHz.
Figure 43 shows the forward isolation vs. frequency data.
TO THE REST OF THE AMPLIFIER
Figure 44. Input Stage and Protection Diodes
For differential voltages above approximately 0.7 V, the diode
clamps begin to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages must be
sustained across the input terminals, it is recommended that the
current through the input clamps be limited to less than 10 mA.
Series input resistors that are sized appropriately for the expected
differential overvoltage provide the needed protection.
Rev.B | Page 17 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
The output error due to the input currents can be estimated as
DC5ERRORꢀ5
Figure 46 shows a typical connection diagram and the major
dc error sources.
⎛
⎞
⎟
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF
RG
⎜
⎜
(5)
× IB+
VOUT = (RF|| RG ) × 1+
× IB− − RS × 1 +
ERROR
⎜
⎝
R
F
BIAꢀ5CSRRENT5CANCEPPATION5
– V
+
+ V
–
IN
OS
R
G
S
To cancel the output voltage error due to unmatched bias
currents at the inputs, RBP and RBN can be used (see Figure 47).
+ V
–
OUT
I
–
B
– V
+
IP
R
R
R
G
F
I
+
B
Figure 46. Typical Connection Diagram and DC Error Sources
R
R
BN
The ideal transfer function (all error sources set to 0 and
infinite dc gain) can be written as
R
S
BP
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF
RG
⎜
(1)
VOUT = 1 +
× VIP
−
× VIN
Figure 47. Using RBP and RBN to Cancel Bias Current Error
To compensate for the unmatched bias currents at the two
inputs, set RBP and RBN as shown in Table 11.
This equation reduces to the familiar forms for noninverting
and inverting op amp gain expressions, as follows:
Table 11. Setting RBN and RBP to Cancel Bias Current Errors
For noninverting gain (VIN = 0 V)
alue5of5RF||RG5
Greater Than RS
Less Than RS
alue5of5RBU5(Ω)5
alue5of5RBN5(Ω)5
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
RF||RG − RS
0
0
⎜
(2)
(3)
VOUT = 1 +
× VIP
RS − RF||RG
For inverting gain (VIP = 0 V)
Table 12 shows sample values for RBP and RBN when RF||RG > RS
and when RF||RG < RS.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
− RF
RG
VOUT
=
×VIN
Table 12. Examples of RBN and RBP Settings
Gain5R
F5(Ω)5
249
249
RG5(Ω)5
Rꢀ5(Ω)5
RBU5(Ω)5
74.5
0
RBN5(Ω)5
0
25.3
The total output voltage error is the sum of errors due to the
amplifier offset voltage and input currents. The output error
due to the offset voltage can be estimated as
+2
+10
249
27.4
50
50
VOUT
=
ERROR
(4)
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VCM
CMRR
VP −VPNOM
VOUT
A
RF
RG
⎛
⎞
⎟
⎜
V
+
+
+
× 1 +
⎜
⎝
OFFSETNOM
PSRR
⎠
where:
VOFFSET
is the offset voltage at the specified supply voltage,
NOM
which is measured with the input and output at midsupply.
CM is the common-mode voltage.
VP is the power supply voltage.
PNOM is the specified power supply voltage.
V
V
CMRR is the common-mode rejection ratio.
PSRR is the power supply rejection ratio.
A is the dc open-loop gain.
Rev.B | Page 18 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
500
50
5
NOISE CONSIDERATIONS
Figure 48 illustrates the primary noise contributors for the
typical gain configurations. The total rms output noise is
the root-mean-square of all the contributions.
vn _ R
=
4kT × R
R
F
F
F
AMPLIFIER AND
RESISTOR NOISE
ven
R
vn _ R
=
G
S
4kT × R
G
G
+ vout_en –
ien
iep
SOURCE
RESISTANCE NOISE
R
vn _ R
=
4kT × R
S
S
TOTAL
AMPLIFIER NOISE
Figure 48. Noise Sources in Typical Connection
0.5
50
500
5k
50k
The output noise spectral density can be calculated by
SOURCE RESISTANCE (Ω)
Figure 49. RTI Noise vs. Source Resistance
vout _en =
2
2
CAPACITANCE DRIVE
4kTRs + iep2 RS 2 + ven2
]
+
4kTRG + ien2 RF
⎛
⎞
⎛
⎞
RF
RG
RF
RG
2
⎜
⎟
⎟
⎜
⎜
⎟
⎟
4kTRF + 1+
[
Capacitance at the output of an amplifier creates a delay within the
feedback path that, if within the bandwidth of the loop, can create
excessive ringing and oscillation. The ADA4896-2/ADA4897-1/
ADA4897-2 show the most peaking at a gain of +2 (see Figure 9).
⎜
⎝
⎠
⎝
⎠
(6)
where:
k is Boltzmann’s constant.
T is the absolute temperature (degrees Kelvin).
iep ien
Placing a small snub resistor (RSNUB) in series with the amplifier
output and the capacitive load mitigates the problem. Figure 50
shows the effect of using a snub resistor (RSNUB) on reducing the
peaking for the worst-case frequency response (gain of +2).
Using RSNUB = 100 ꢀ eliminates the peaking entirely, with the
trade-off that the closed-loop gain is reduced by 0.8 dB due to
attenuation at the output. RSNUB can be adjusted from 0 ꢀ to
100 ꢀ to maintain an acceptable level of peaking and closed-
loop gain (see Figure 50).
and
density (pA/√Hz).
ven
represent the amplifier input current noise spectral
is the amplifier input voltage noise spectral density (nV/√Hz).
RS is the source resistance, as shown in Figure 48.
RF and RG are the feedback network resistances, as shown in
Figure 48.
ven
Source resistance noise, amplifier voltage noise ( ), and the
voltage noise from the amplifier current noise ( × RS) are all
subject to the noise gain term (1 + RF/RG). Note that with a
1 nV/√Hz input voltage noise and 2.8 pA/√Hz input current
noise, the noise contributions of the amplifier are relatively
small for source resistances from approximately 50 Ω to 700 Ω.
iep
3
V
V
= +5V
OUT
S
= 200mV p-p
2
1
G = +2
R
= 0Ω
SNUB
R
= 50Ω
SNUB
R
= 100Ω
SNUB
0
Figure 49 shows the total RTI noise due to the amplifier vs. the
source resistance. In addition, the value of the feedback resistors
used affects the noise. It is recommended that the value of the
feedback resistors be maintained between 250 Ω and 1 kΩ to
keep the total noise low.
–1
–2
–3
–4
–5
R
249Ω
2
R
249Ω
1
R
SNUB
V
OUT
ADA4896-2
V
C
L
39pF
R
IN
L
1kΩ
0.1
1
10
FREQUENCY (MHz)
100
Figure 50. Using a Snub Resistor to Reduce Peaking
Due to Output Capacitive Load
Rev.B | Page 19 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
APPLICATIONS INFORMATION
2
1
TLUICAP5UERFORMANCE5 APSEꢀ5
V
V
R
R
= +5V
S
= 200mV p-p
OUT
= 249ꢀ
= 1kꢀ
To reduce design time and eliminate uncertainty, Table 13
provides a reference for typical gains, component values, and
performance parameters. The supply voltage used is 5 V. The band-
width is obtained with a small signal output of 200 mV p-p, and
the slew rate is obtained with a 2 V output step.
F
L
G = +5
G = +2
0
–1
–2
–3
–4
–5
–6
G = +10
G = +20
G = +1
Note that as the gain increases, the small signal bandwidth
decreases, as is expected from the gain bandwidth product
relationship. In addition, the phase margin improves with
higher gains, and the amplifier becomes more stable. As a
result, the peaking in the frequency response is reduced
(see Figure 51).
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 51. Small Signal Frequency Response at Various Gains
Table 13. Recommended Values and Typical Performance
Total5Output5Noise5Including5
Resistors5(n /√Hz)5
Gain5R
+1
+2
+5
+10
+20
F5(Ω)5
RG5(Ω)5
N/A
249
61.9
27.4
13.0
−35dB5BW5(MHz)5 ꢀlew5Rate,5tR/tF5( /μs)5 Ueaking5(dB)5
0
92
54
30
17
9
78/158
101/140
119/137
87/88
0.8
1.2
0
0
0
1.0
3.6
6.8
12.0
21.1
249
249
249
249
37/37
Rev.B | Page 20 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
POW5NOIꢀE,5GAIN5ꢀEPECTABPE5AMUPIFIER5
USING S3B IS OPTIONAL
R
F2
225ꢀ
S3B
D3 ADG633
R
75ꢀ
F1
+5V
8
6
5
+5V
8
R
G1
75ꢀ
2
3
7
ADA4896-2
S1B
S2B
S2A
V
02
V1
V2
R
L
D1
D2
1
ADA4896-2
V
4
01
S1A
R
V
BALANCE
IN
–5V
150ꢀ
4
ADG633
–5V
Figure 52. Using the ADA4896-2 and the ADG633 to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load
A gain selectable amplifier makes processing a wide range of
input signals possible. A traditional gain selectable amplifier
uses switches in the feedback loops connecting to the inverting
input. The switch resistances degrade the noise performance of
the amplifier, as well as adding significant capacitance on the
inverting input node. The noise and capacitance issues can be
especially bothersome when working with low noise amplifiers.
Also, the switch resistances contribute to nonlinear gain error,
which is undesirable.
to cancel out the varying offset. Placing a resistor equal to the
difference between RF2 and RF1 in series with Switch S2A results
in a more constant offset voltage.
The following derivation shows that sampling at V1 yields the
desired signal gain without gain error. RS denotes the switch
resistance. V2 can be derived using the same method.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
R
F1 + RS1
RG1
⎜
V01 =VIN × 1 +
(7)
(8)
Figure 52 presents an innovative switching technique used in
the gain selectable amplifier such that the 1 nV/Hz noise per-
formance of the ADA4896-2 is preserved while the nonlinear
gain error is much reduced. With this technique, the user can
also choose switches with minimal capacitance to optimize the
bandwidth of the circuit.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF1 + RG1
RF1 + RG1 + RS1
V1 = V01
×
Substituting Equation 1 into Equation 2, the following
derivation is obtained.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF1
RG1
⎜
V1=VIN × 1 +
In the circuit shown in Figure 52, the switches are implemented
with the ADG633 and are configured such that either S1A and
S2A are on, or S1B and S2B are on. In this example, when the
S1A and S2A switches are on, the first stage amplifier gain is +4.
When the S1B and S2B switches are on, the first stage amplifier
gain is +2. The first set of switches of the ADG633 is placed on
the output side of the feedback loop, and the second set of switches
is used to sample at a point (V1 or V2) where switch resistances
and nonlinear resistances do not matter. In this way, the gain
error can be reduced while preserving the noise performance
of the ADA4896-2.
(9)
Note that if V01 yields the desired signal gain without gain
error, the buffered output V02 will also be free from gain
error. Figure 53 shows the normalized frequency response of
the circuit at V02.
6
V
V
= ±5V
IN
S
= 100mV p-p
= 1kꢀ
3
0
R
L
–3
G = +2
G = +4
–6
–9
Note that the input bias current of the output buffer can cause
problems with the impedance of the S2A and S2B sampling
switches. Both sampling switches are not only nonlinear with
voltage but with temperature as well. If this is an issue, place the
unused switch of the ADG633 (S3B) in the feedback path of the
output buffer to balance the bias currents (see Figure 52).
–12
–15
–18
–21
–24
–27
–30
In addition, the bias current of the input amplifier causes
an offset at the output that varies based on the gain setting.
Because the input amplifier and the output buffer are mono-
lithic, the relative matching of their bias currents can be used
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 53. Frequency Response of V02/VIN
Rev.B | Page 21 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
MEDICAL ULTRASOUND APPLICATIONS
BEAMFORMER
CENTRAL CONTROL
Tx BEAMFORMER
AD9279
HV
Rx BEAMFORMER
(B AND F MODES)
MUX/
T/R
ADC
LNA
VGA
DEMUX
SWITCHES
AAF
TRANSDUCER
ARRAY
CW (ANALOG)
BEAMFORMER
IMAGE AND
SPECTRAL
DOPPLER
PROCESSING
MODE
COLOR
DOPPLER
PROCESSING
(F MODE)
MOTION
PROCESSING
(B MODE)
ADA4896-2/
ADA4897-1/
ADA4897-2
AUDIO
OUTPUT
DISPLAY
Figure 54. Simplified Ultrasound System Block Diagram
Overview of the Ultrasound System
The ultrasound system consists of two main operations: the
time gain control (TGC) operation and the continuous wave
(CW) Doppler operation. The AD9279 integrates the essential
components of these two operations into a single IC. It contains
eight channels of a variable gain amplifier (VGA) with a low
noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation. For detailed information
about how to use the AD9279 in an ultrasound system, see the
AD9279 data sheet.
Medical ultrasound systems are among the most sophisticated
signal processing systems in widespread use today. By transmit-
ting acoustic energy into the body and receiving and processing
the returning reflections, ultrasound systems can generate images
of internal organs and structures, map blood flow and tissue
motion, and provide highly accurate blood velocity information.
Figure 54 shows a simplified block diagram of an ultrasound
system.
Rev.B | Page 22 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
ADA4896-2/ADA4897-1/ADA4897-2 in the Ultrasound System
R
C
FILT
FILT
R
A
CWI+
Φ
AD7982
50ꢀ
1.5V
1.5V
2.5V
2.5V
ADA4896-2/
ADA4897-1/
ADA4897-2
ADA4896-2/
ADA4897-1/
ADA4897-2
LNA
CHANNEL A
I
18-BIT ADC
CWI–
Φ
50ꢀ
4nF
R
A
C
FILT
R
R
FILT
FILT
C
FILT
R
A
CWQ+
AD7982
50ꢀ
Φ
1.5V
1.5V
2.5V
2.5V
ADA4896-2/
ADA4897-1/
ADA4897-2
ADA4896-2/
ADA4897-1/
ADA4897-2
18-BIT ADC
Q
LNA
CHANNEL H
CWQ–
50ꢀ
4nF
R
A
C
R
FILT
Φ
FILT
4
LO
GENERATION
AD9279
Figure 55. Using the ADA4896-2/ADA4897-1/ADA4897-2 as Filters, I-to-V Converters, Current Summers, and ADC Drivers After the I/Q Outputs of the AD9279
The ADA4896-2/ADA4897-1/ADA4897-2 are used in the CW
Doppler path in the ultrasound application after the I/Q demod-
ulators of the AD9279. Doppler signals can be typically between
100 Hz to 100 kHz. The low noise floor and high dynamic range
of the ADA4896-2/ADA4897-1/ADA4897-2 make them excellent
choices for processing weak Doppler signals.
The output-referred noise of the CW signal path depends on
the LNA gain, the selection of the first stage summing amplifier,
and the value of RFILT. To determine the output-referred noise, it
is important to know the active low-pass filter (LPF) values RA,
RFILT, and CFILT, as shown as Figure 55. Typical filter values for
all eight channels of a single AD9279 are 100 Ω for RA, 500 Ω
for RFILT, and 2.0 nF for CFILT; these values implement a 100 kHz,
single-pole LPF.
The rail-to-rail output and the high output current drive of
the ADA4896-2/ADA4897-1/ADA4897-2 make them suitable
candidates for the I-to-V converter, current summer, and ADC
driver.
The gain of the I-to-V converter can be increased by increasing
the filter resistor, RFILT. To keep the corner frequency unchanged,
decrease the filter capacitor, CFILT, by the same factor. The factor
limiting the magnitude of the gain is the output swing and drive
capability of the op amp selected for the I-to-V converter, in this
example, the ADA4896-2/ADA4897-1/ADA4897-2. Because
any amplifier has limited drive capability, a finite number of
channels can be summed.
Figure 55 shows an interconnection block diagram of all
eight channels of the AD9279. Two stages of the ADA4896-2
amplifiers are used. The first stage performs an I-to-V conver-
sion and filters the high frequency content that results from
the demodulation process. The second stage of the ADA4896-2
amplifiers is used to sum the output currents of multiple AD9279
devices, to provide gain, and to drive the AD7982 device, an
18-bit SAR ADC.
Rev.B | Page 23 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
Paralleling different values and sizes of capacitors helps to ensure
that the power supply pins are provided with a low ac impedance
across a wide band of frequencies. This is important for minimiz-
ing the coupling of noise into the amplifier—especially when the
amplifier PSRR begins to roll off—because the bypass capacitors
can help lessen the degradation in PSRR performance.
PALOST5CONꢀIDERATIONꢀ5
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
Ground Plane
It is important to avoid ground in the areas under and around the
input and output of the ADA4896-2/ADA4897-1/ADA4897-2.
Stray capacitance created between the ground plane and the
input and output pads of a device is detrimental to high speed
amplifier performance. Stray capacitance at the inverting input,
along with the amplifier input capacitance, lowers the phase
margin and can cause instability. Stray capacitance at the output
creates a pole in the feedback loop, which can reduce phase margin
and can cause the circuit to become unstable.
The smallest value capacitor should be placed on the same side
of the board as the amplifier and as close as possible to the amp-
lifier power supply pins. The ground end of the capacitor should
be connected directly to the ground plane.
It is recommended that a 0.1 μF ceramic capacitor with a 0508
case size be used. The 0508 case size offers low series inductance
and excellent high frequency performance. A 10 μF electrolytic
capacitor should be placed in parallel with the 0.1 μF capacitor.
Depending on the circuit parameters, some enhancement to
performance can be realized by adding additional capacitors.
Each circuit is different and should be analyzed individually for
optimal performance.
Power Supply Bypassing
Power supply bypassing is a critical aspect in the performance
of the ADA4896-2/ADA4897-1/ADA4897-2. A parallel connec-
tion of capacitors from each power supply pin to ground works
best. Smaller value capacitor electrolytics offer better high
frequency response, whereas larger value capacitor electrolytics
offer better low frequency performance.
Rev.B | Page 24 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
EXPOSED
PAD
1.70
1.60
1.50
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
Rev.B | Page 25 of 28
ADA4896-2/ADA4897-1/ADA4897-2
Data Sheet
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 58. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 59. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev.B | Page 26 of 28
Data Sheet
ADA4896-2/ADA4897-1/ADA4897-2
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 60. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING5GSIDE5
Uackage5
Option5
Ordering5
Quantity5Branding5
Model1
Temperature5Range5
Uackage5Description5
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
Evaluation Board for the 8-Lead LFCSP
Evaluation Board for the 8-Lead MSOP
8-Lead SOIC_N
ADA4896-2ARMZ
ADA4896-2ARMZ-R7
ADA4896-2ARMZ-RL
ADA4896-2ACPZ-R2
ADA4896-2ACPZ-R7
ADA4896-2ACPZ-RL
ADA4896-2ACP-EBZ
ADA4896-2ARM-EBZ
ADA4897-1ARZ
ADA4897-1ARZ-R7
ADA4897-1ARZ-RL
ADA4897-1ARJZ-R2
ADA4897-1ARJZ-R7
ADA4897-1ARJZ-RL
ADA4897-1AR-EBZ
ADA4897-1ARJ-EBZ
ADA4897-2ARMZ
ADA4897-2ARMZ-R7
ADA4897-2ARMZ-RL
ADA4897-2ARM-EBZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
RM-8
RM-8
RM-8
CP-8-11
CP-8-11
CP-8-11
50
H2P
H2P
H2P
H2P
H2P
H2P
1,000
3,000
250
1,500
5,000
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
98
8-Lead SOIC_N
8-Lead SOIC_N
6-Lead SOT-23
6-Lead SOT-23
1,000
2,500
250
3,000
10,000
H2K
H2K
H2K
6-Lead SOT-23
Evaluation Board for the 8-Lead SOIC_N
Evaluation Board for the 6-Lead SOT-23
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
RM-10
RM-10
RM-10
50
1,000
3,000
H2N
H2N
H2N
Evaluation Board for the 10-Lead MSOP
1 Z = RoHS Compliant Part.
Rev.B | Page 27 of 28
ADA4896-2/ADA4897-1/ADA4897-2
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09447-0-4/12(B)
Rev. B | Page 28 of 28
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