AD8001AR-REEL7 [ADI]
800 MHz, 50 mW Current Feedback Amplifier; 800兆赫， 50毫瓦电流反馈放大器
| 型号： | AD8001AR-REEL7 |
| 厂家： | 
ADI |
| 描述： | 800 MHz, 50 mW Current Feedback Amplifier |
| 文件： | 总16页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
800 MHz, 50 mW
a
Current Feedback Amplifier
AD8001
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Excellent Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness 0.1 dB to 100 MHz
0.01% Differential Gain Error
0.025؇ Differential Phase Error
Low Power
5.5 mA Max Power Supply Current (55 mW)
High Speed and Fast Settling
880 MHz, –3 dB Bandwidth (G = +1)
440 MHz, –3 dB Bandwidth (G = +2)
1200 V/s Slew Rate
8-Lead DIP (N-8, Q-8)
and SOIC (SO-8)
5-Lead
SOT-23-5
AD8001
NC
–IN
+IN
V–
8
7
6
5
NC
V+
1
2
3
4
+V
5
V
1
2
3
S
OUT
–V
S
OUT
NC
4
–IN
+IN
AD8001
10 ns Settling Time to 0.1%
Low Distortion
–65 dBc THD, fC = 5 MHz
33 dBm 3rd Order Intercept, F1 = 10 MHz
–66 dB SFDR, f = 5 MHz
High Output Drive
NC = NO CONNECT
transimpedance linearization circuitry. This allows it to drive
video loads with excellent differential gain and phase perfor-
mance on only 50 mW of power. The AD8001 is a current
feedback amplifier and features gain flatness of 0.1 dB to 100 MHz
while offering differential gain and phase error of 0.01% and
0.025°. This makes the AD8001 ideal for professional video
electronics such as cameras and video switchers. Additionally,
the AD8001’s low distortion and fast settling make it ideal for
buffer high-speed A-to-D converters.
70 mA Output Current
Drives Up to Four Back-Terminated Loads (75 ⍀ Each)
While Maintaining Good Differential Gain/Phase
Performance (0.05%/0.25؇)
APPLICATIONS
A-to-D Driver
The AD8001 offers low power of 5.5 mA max (VS = ±5 V) and
can run on a single +12 V power supply, while being capable of
delivering over 70 mA of load current. These features make this
amplifier ideal for portable and battery-powered applications
where size and power are critical.
Video Line Driver
Professional Cameras
Video Switchers
Special Effects
RF Receivers
The outstanding bandwidth of 800 MHz along with 1200 V/µs
of slew rate make the AD8001 useful in many general purpose
high-speed applications where dual power supplies of up to ±6 V
and single supplies from 6 V to 12 V are needed. The AD8001 is
available in the industrial temperature range of –40°C to +85°C.
PRODUCT DESCRIPTION
The AD8001 is a low power, high-speed amplifier designed
to operate on ±5 V supplies. The AD8001 features unique
9
V
= ؎5V
S
R
= 820⍀
6
3
FB
G = +2
= 100⍀
R
L
0
V
R
= ؎5V
S
–3
–6
= 1k⍀
FB
–9
–12
10M
100M
FREQUENCY – Hz
1G
Figure 2. Transient Response of AD8001; 2 V Step, G = +2
Figure 1. Frequency Response of AD8001
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ T = + 25؇C, V = ؎5 V, R = 100
⍀
, unless otherwise noted)
AD8001–SPECIFICATIONS
A
S
L
Model
AD8001A
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, N Package
G = +2, < 0.1 dB Peaking, RF = 750 Ω
G = +1, < 1 dB Peaking, RF = 1 kΩ
G = +2, < 0.1 dB Peaking, RF = 681 Ω
G = +1, < 0.1 dB Peaking, RF = 845 Ω
G = +2, < 0.1 dB Peaking, RF = 768 Ω
G = +1, < 0.1 dB Peaking, RF = 1 kΩ
350
650
350
575
300
575
440
880
440
715
380
795
MHz
MHz
MHz
MHz
MHz
MHz
R Package
RT Package
Bandwidth for 0.1 dB Flatness
N Package
G = +2, RF = 750 Ω
G = +2, RF = 681 Ω
G = +2, RF = 768 Ω
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step, RF = 649 Ω
85
110
125
145
1000
1200
10
MHz
MHz
MHz
V/µs
V/µs
ns
R Package
100
120
800
960
RT Package
Slew Rate
Settling Time to 0.1%
Rise and Fall Time
1.4
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p
G = +2, RL = 100 Ω
f = 10 kHz
f = 10 kHz, +In
–In
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
f = 10 MHz
–65
dBc
Input Voltage Noise
Input Current Noise
2.0
2.0
18
0.01
0.025
33
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
dBm
Differential Gain Error
Differential Phase Error
Third Order Intercept
1 dB Gain Compression
SFDR
0.025
0.04
f = 10 MHz
f = 5 MHz
14
–66
dBm
dB
DC PERFORMANCE
Input Offset Voltage
2.0
2.0
10
5.5
9.0
mV
mV
TMIN–TMAX
Offset Drift
–Input Bias Current
µV/°C
±µA
±µA
±µA
±µA
kΩ
5.0
25
35
6.0
10
TMIN–TMAX
TMIN–TMAX
+Input Bias Current
3.0
Open Loop Transresistance
V
O = ±2.5 V
250
175
900
TMIN–TMAX
kΩ
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
10
50
1.5
3.2
MΩ
Ω
pF
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
±V
VCM = ±2.5 V
50
54
dB
–Input Current
+Input Current
VCM = ±2.5 V, TMIN–TMAX
VCM = ±2.5 V, TMIN–TMAX
0.3
0.2
1.0
0.7
µA/V
µA/V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
RL = 150 Ω
2.7
50
85
3.1
70
110
±V
mA
mA
R
L = 37.5 Ω
Short Circuit Current
POWER SUPPLY
Operating Range
±3.0
±6.0
V
Quiescent Current
Power Supply Rejection Ratio
TMIN–TMAX
5.0
75
56
0.5
0.1
5.5
mA
dB
dB
µA/V
+VS = +4 V to +6 V, –VS = –5 V
–VS = – 4 V to –6 V, +VS = +5 V
TMIN–TMAX
60
50
–Input Current
+Input Current
2.5
0.5
TMIN–TMAX
µA/V
Specifications subject to change without notice.
–2–
REV. C
AD8001
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
The maximum power that can be safely dissipated by the
AD8001 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-
perature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W
SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
While the AD8001 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
2.0
T
= +150؇C
J
8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead Cerdip Package: θJA = 110°C/W
8-LEAD
PLASTIC DIP PACKAGE
1.5
8-LEAD
SOIC PACKAGE
5-Lead SOT-23-5 Package: θJA = 260°C/W
1.0
0.5
0
5-LEAD
SOT-23-5 PACKAGE
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Brand
Code
Model
AD8001AN
AD8001AQ
AD8001AR
AD8001AR-REEL
AD8001AR-REEL7
AD8001ART-REEL
AD8001ART-REEL7
AD8001ACHIPS
5962-9459301MPA1
AD8001R-EB+22
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Lead Plastic DIP
8-Lead Cerdip
8-Lead SOIC
13" Tape and REEL
7" Tape and REEL
13" Tape and REEL
7" Tape and REEL
Die Form
N-8
Q-8
SO-8
SO-8
SO-8
RT-5
RT-5
HEA
HEA
8-Lead Cerdip
SOIC Evaluation Board, G = +2
Q-8
NOTES
1Standard Military Drawing Device.
2Refer to Evaluation Board section.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8001 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD8001
806⍀
0.001F
+V
S
V
TO
OUT
0.1F
TEKTRONIX
CSA 404 COMM.
SIGNAL
806⍀
50⍀
ANALYZER
AD8001
0.1F
R
= 100⍀
V
L
IN
HP8133A
PULSE
GENERATOR
0.001F
T
/T = 50ps
F
R
–V
S
400mV
5ns
Figure 7. 2 V Step Response, G = +2
Figure 4. Test Circuit , Gain = +2
909⍀
0.001F
+V
S
V
TO
OUT
0.1F
TEKTRONIX
CSA 404 COMM.
SIGNAL
ANALYZER
AD8001
0.1F
R
= 100⍀
V
L
IN
LeCROY 9210
PULSE
GENERATOR
50⍀
0.001F
T
/T = 350ps
F
R
–V
S
Figure 5. 1 V Step Response, G = +2
Figure 8. Test Circuit, Gain = +1
0.5V
5ns
Figure 6. 2 V Step Response, G = +1
Figure 9. 100 mV Step Response, G = +1
–4–
REV. C
AD8001
1000
800
600
400
200
0
9
6
V
R
= ؎5V
S
V
R
= ؎5V
= 100⍀
S
= 820⍀
FB
L
G = +2
G = +2
= 100⍀
3
R
L
N
0
PACKAGE
V
R
= ؎5V
= 1k⍀
S
–3
–6
FB
R
PACKAGE
–9
–12
10M
500
600
700
800
900
1000
100M
1G
FREQUENCY – Hz
VALUE OF FEEDBACK RESISTOR (R ) – ⍀
F
Figure 10. Frequency Response, G = +2
Figure 13. –3 dB Bandwidth vs. RF
–50
–60
0.1
0
R
649⍀
=
F
؎5V SUPPLIES
R
= 698⍀
F
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
V
= 2V p-p
OUT
R
= 100⍀
L
R
= 750⍀
F
G = +2
–70
G = +2
R
= 100⍀
L
2ND HARMONIC
V
= 50mV
IN
–80
3RD HARMONIC
–90
–100
10k
100k
1M
FREQUENCY – Hz
10M
100M
1M
10M
FREQUENCY – Hz
100M
Figure 11. 0.1 dB Flatness, R Package (for N Package Add
50 Ω to RF)
Figure 14. Distortion vs. Frequency, RL = 100 Ω
0.08
–50
G = +2
0.06
؎5V SUPPLIES
R
= 806⍀
V
= 2V p-p
F
OUT
2 BACK TERMINATED
–60
–70
R
= 1k⍀
L
0.04
0.02
0.00
LOADS (75⍀)
G = +2
2ND HARMONIC
1 BACK TERMINATED
LOAD (150⍀)
–80
0.02
0.01
1 AND 2 BACK TERMINATED
LOADS (150⍀ AND 75⍀)
–90
3RD HARMONIC
0.00
–100
–110
–0.01
–0.02
0
100
10k
100k
1M
FREQUENCY – Hz
10M
100M
IRE
Figure 15. Differential Gain and Differential Phase
Figure 12. Distortion vs. Frequency, RL = 1 kΩ
REV. C
–5–
AD8001
5
1000
900
800
700
600
500
0
N PACKAGE
R PACKAGE
–5
–10
–15
–20
–25
–30
–35
V
= –26dBm
IN
R
= 909⍀
F
V
= 50mV
IN
R
= 100⍀
L
G = +1
1100
100M
900
1G
3G
700
800
1000
600
FREQUENCY – Hz
VALUE OF FEEDBACK RESISTOR (R ) – ⍀
F
Figure 16. Frequency Response, G = +1
Figure 19. –3 dB Bandwidth vs. RF, G = +1
+1
–40
–50
–60
–70
–80
–90
–100
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
R
= 649⍀
F
R
= 100⍀
L
G = +1
= 2V p-p
V
R
= 953⍀
OUT
F
2ND HARMONIC
G = +1
R
= 100⍀
L
V
= 50mV
IN
3RD HARMONIC
2M
10M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 17. Flatness, R Package, G = +1 (for N Package Add
100 Ω to RF)
Figure 20. Distortion vs. Frequency, RL = 100 Ω
3
0
–40
G = +1
–50
–60
R
= 1k⍀
= 2V p-p
L
–3
–6
V
OUT
–9
–70
2ND HARMONIC
–12
–80
–15
–18
3RD HARMONIC
–90
R
= 100⍀
L
–21
–24
–27
G = +1
–100
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
1M
10M
FREQUENCY – Hz
100M
Figure 18. Distortion vs. Frequency, RL = 1 kΩ
Figure 21. Large Signal Frequency Response, G = +1
–6–
REV. C
AD8001
45
40
35
30
25
20
15
10
5
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
DEVICE #1
G = +100
G = +10
R
= 1000⍀
F
DEVICE #2
DEVICE #3
R
= 470⍀
F
0
–5
–10
–15
–20
–25
R
= 100⍀
L
1M
10M
100M
1G
–60
–40
–20
0
20
40
60
80
100
FREQUENCY – Hz
JUNCTION TEMPERATURE – ؇C
Figure 22. Frequency Response, G = +10, G = +100
Figure 25. Input Offset vs. Temperature
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
3.35
3.25
3.15
3.05
2.95
2.85
2.75
2.65
2.55
+V
OUT
R
V
= 150⍀
= ؎5V
L
S
| –V
|
OUT
V
= ؎5V
S
+V
OUT
R
= 50⍀
= ؎5V
L
S
V
| –V
|
OUT
–60 –40 –20
0
20
40
60
80
100 120 140
–60
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 26. Supply Current vs. Temperature
Figure 23. Output Swing vs. Temperature
5
4
3
125
120
115
110
105
100
95
SOURCE I
SC
–IN
2
| SINK I
|
1
0
SC
–1
+IN
–2
–3
–4
90
85
–60
–40
–20
0
20
40
60
80
100
–60 –40 –20
0
20
40
60
80
100 120 140
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 27. Short Circuit Current vs. Temperature
Figure 24. Input Bias Current vs. Temperature
REV. C
–7–
AD8001
6
1k
100
10
5
4
3
2
1
0
V
R
= ؎5V
= 150⍀
= ؎2.5V
S
L
V
OUT
1
–T
Z
G = +2
0.1
0.01
+T
Z
R
= 909⍀
F
–60 –40 –20
0
20
40
60
80
100 120 140
10M
100M
10k
1M
100k
JUNCTION TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 28. Transresistance vs. Temperature
Figure 31. Output Resistance vs. Frequency
100
100
1
R
= 576⍀
F
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
INVERTING CURRENT V = ؎5V
S
R
= 649⍀
F
G = –1
R
= 750⍀
F
R
= 100⍀
L
10
10
V
= 50mV
IN
NONINVERTING CURRENT V = ؎5V
S
VOLTAGE NOISE V = ؎5V
S
1
100k
1
10
1M
10M
100M
1G
100
1k
10k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 29. Noise vs. Frequency
Figure 32. –3 dB Bandwidth vs. Frequency, G = –1
–48
–49
–50
–51
–52
–53
–54
–55
–56
–52.5
–55.0
–PSRR
–CMRR
–57.5
–60.0
–62.5
–65.0
–67.5
–70.0
–72.5
–75.0
–77.5
3V SPAN
+CMRR
CURVES ARE FOR WORST
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
2.5V SPAN
+PSRR
0
–60 –40 –20
0
20
40
60
80
100 120 140
–60
–40
–20
20
40
60
80
100
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 30. CMRR vs. Temperature
Figure 33. PSRR vs. Temperature
–8–
REV. C
AD8001
30
20
–10
–20
CURVES ARE FOR WORST
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
910⍀
150⍀
+PSRR
910⍀
150⍀
V
IN
10
51⍀
V
OUT
0
62⍀
–10
–20
–30
–40
–50
–60
–30
–40
–50
–PSRR
–PSRR
+PSRR
R
= 909⍀
F
G = +2
1M
10M
100M
1G
300k
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
Figure 34. CMRR vs. Frequency
Figure 37. PSRR vs. Frequency
1
0
R
= 549⍀
F
–1
–2
–3
–4
–5
–6
–7
–8
–9
R
= 649⍀
F
G = –2
R
= 100⍀
L
V
= 50mV
R = 750⍀
F
IN
rms
1M
10M
100M
1G
FREQUENCY – Hz
Figure 38. 2 V Step Response, G = –1
Figure 35. –3 dB Bandwidth vs. Frequency, G = –2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3 WAFER LOTS
COUNT = 895
MEAN = 1.37
STD DEV = 1.13
MIN = –2.45
MAX = +4.69
CUMULATIVE
FREQ DIST
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT OFFSET VOLTAGE – mV
Figure 39. Input Offset Voltage Distribution
Figure 36. 100 mV Step Response, G = –1
REV. C
–9–
AD8001
THEORY OF OPERATION
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
A very simple analysis can put the operation of the AD8001, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8001’s open-loop behavior is ex-
pressed as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop
transimpedance behaves just as the open-loop voltage gain of a
voltage feedback amplifier, that is, it has a large dc value and
decreases at roughly 6 dB/octave in frequency.
1M
100k
10k
1k
Since the RIN is proportional to 1/gM, the equivalent voltage
gain is just TZ × gM, where the gM in question is the trans-
conductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 40, basic
analysis yields the following result.
100
VO
VIN
TZ (S)
TZ (S) + G × RIN + R1
= G ×
10
100k
1M
10M
100M
1G
FREQUENCY – Hz
R1
R2
G = 1 +
RIN = 1/gM ≈ 50 Ω
Figure 41. Transimpedance vs. Frequency
Recognizing that G × RIN << R1 for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G). This simple analysis in conjunction with Figure 41
can, in fact, predict the behavior of the AD8001 over a wide
range of conditions.
0.1
0
R
649⍀
=
F
R
= 698⍀
F
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
R1
G = +2
R
= 750⍀
F
R2
R
IN
V
OUT
V
IN
1M
10M
FREQUENCY – Hz
100M
Figure 40.
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice
parasitic capacitance at Pin 2 will also add phase in the feedback
loop, so picking an optimum value for RF can be difficult. Fig-
ure 42 illustrates this problem. Here the fine scale (0.1 dB/div)
flatness is plotted vs feedback resistance. These plots were taken
using an evaluation card which is available to customers so that
these results may readily be duplicated (see Evaluation Board
section).
Figure 42. 0.1 dB Flatness vs. Frequency
Choice of Feedback and Gain Resistors
Because of the above-mentioned relationship between the band-
width and feedback resistor, the fine scale gain flatness will, to
some extent, vary with feedback resistance. It, therefore, is
recommended that once optimum resistor values have been
determined, 1% tolerance values should be used if it is desired
to maintain flatness over a wide range of production lots. In
addition, resistors of different construction have different associ-
ated parasitic capacitance and inductance. Surface mount resis-
tors were used for the bulk of the characterization for this data
sheet. It is not recommended that leaded components be used
with the AD8001.
–10–
REV. C
AD8001
Printed Circuit Board Layout Considerations
Driving Capacitive Loads
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than
5 mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.
The AD8001 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 44. The accompanying graph
shows the optimum value for RSERIES vs. capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of RSERIES and CL.
909⍀
Power Supply Bypassing
R
SERIES
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈4.7 Ω for
optimum results.
I
N
R
L
C
L
500⍀
Figure 44. Driving Capacitive Loads
40
G = +1
DC Errors and Noise
30
20
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa-
tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 43) they are
input offset (VIO) which appears at the output multiplied by the
noise gain of the circuit (1 + RF/RI), noninverting input current
(IBN × RN) also multiplied by the noise gain, and the inverting
input current, which when divided between RF and RI and sub-
sequently multiplied by the noise gain always appears at the
output as IBN × RF. The input voltage noise of the AD8001 is a
low 2 nV/√Hz. At low gains though the inverting input current
noise times RF is the dominant noise source. Careful layout and
device matching contribute to better offset and drift specifica-
tions for the AD8001 compared to many other current feedback
amplifiers. The typical performance curves in conjunction with
the equations below can be used to predict the performance of
the AD8001 in any application.
10
0
5
10
15
20
25
0
C
– pF
L
Figure 45. Recommended RSERIES vs. Capacitive Load
RF
RI
RF
RI
VOUT = VIO × 1 +
± IBN × RN × 1 +
± IBI × RF
R
F
I
BI
R
I
V
OUT
I
BN
R
N
Figure 43. Output Offset Voltage
REV. C
–11–
AD8001
Communications
Operation as a Video Line Driver
Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamen-
tals and do not lend themselves to filtering. Theory predicts that
the third order harmonic distortion components increase in
power at three times the rate of the fundamental tones. The
specification of third order intercept as the virtual point where
fundamental and harmonic power are equal is one standard
measure of distortion performance. Op amps used in closed-
loop applications do not always obey this simple theory. At a
gain of two, the AD8001 has performance summarized in Fig-
ure 46. Here the worst third order products are plotted vs. input
power. The third order intercept of the AD8001 is +33 dBm at
10 MHz.
The AD8001 has been designed to offer outstanding perfor-
mance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.025°) meet
the most exacting HDTV demands for driving one video load.
The AD8001 also drives up to two back terminated loads as
shown in Figure 47, with equally impressive performance (0.01%,
0.07°). Another important consideration is isolation between
loads in a multiple load application. The AD8001 has more
than 40 dB of isolation at 5 MHz when driving two 75 Ω back
terminated loads.
75⍀
CABLE
909⍀
909⍀
75⍀
V
#1
OUT
75⍀
+V
0.001F
S
+
0.1F
75⍀
CABLE
–45
75⍀
75⍀
CABLE
G = +2
V
#2
AD8001
OUT
F
= 10MHz
–50
–55
–60
–65
–70
–75
–80
1
2
75⍀
V
0.1F
IN
F
= 12MHz
75⍀
2F – F
2
1
0.001F
–V
S
2F – F
1
2
Figure 47. Video Line Driver
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
INPUT POWER – dBm
Figure 46. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
–12–
REV. C
AD8001
Driving A-to-D Converters
to both ADCs as shown in Figure 48 reduces the number of
external components required to create a complete data
acquisition system. The 20 Ω resistors in series with ADC in-
puts are used to help the AD8001s drive the 10 pF ADC input
capacitance. The AD8001 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.
The AD8001 is well suited for driving high speed analog-to-
digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below the AD8001 is shown
driving the inputs of the AD9058, which are configured for 0 V
to +2 V ranges. Bipolar input signals are buffered, amplified
(–2×), and offset (by +1.0 V) into the proper input range of the
ADC. Using the AD9058’s internal +2 V reference connected
1k⍀
ENCODE
74ACT04
10pF
50⍀
10
36
ENCODE A
ENCODE B
8
649⍀
–V
5, 9, 22,
REF A
REF B
+5V
+V
S
38
24, 37, 41
–V
0.1F
ANALOG
IN A
؎0.5V
324⍀
AD9058
RZ1
(J-LEAD)
20⍀
6
18
17
16
15
14
13
12
11
A
AD8001
IN A
D
(LSB)
0A
1.3k⍀
2
3
–2V
+V
+V
+V
8
INT
AD707
20k⍀
0.1F
0.1F
REF A
REF B
43
20k⍀
649⍀
D
(MSB)
(LSB)
7A
1.3k⍀
324⍀
RZ2
28
29
30
31
32
33
34
35
D
0B
ANALOG
IN B
؎0.5V
20⍀
40
1
8
A
AD8001
IN B
COMP
0.1F
D
(MSB)
7B
7, 20,
CLOCK
–V
–5V
1N4001
S
26, 39
RZ1, RZ2 = 2,000⍀ SIP (8-PKG)
0.1F
4,19, 21 25, 27, 42
Figure 48. AD8001 Driving a Dual A-to-D Converter
REV. C
–13–
AD8001
Layout Considerations
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
The specified high speed performance of the AD8001 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component selec-
tion are mandatory.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Chip capacitors should be used for supply bypassing (see Figure
49). One end should be connected to the ground plane and the
other within 1/8-inch of each power pin. An additional large
R
F
R
F
+V
+V
S
S
+V
S
R
C1
0.1F
C3
10F
R
G
G
IN
R
R
O
O
OUT
OUT
R
T
IN
C2
0.1F
C4
10F
R
S
R
T
–V
–V
S
S
–V
S
Inverting Configuration
Supply Bypassing
Noninverting Configuration
Figure 49. Inverting and Noninverting Configurations for Evaluation Boards
Table I. Recommended Component Values
AD8001AN (DIP)
Gain
AD8001AR (SOIC)
Gain
AD8001ART (SOT-23-5)
Gain
Component
–1
+1
+2
+10
+100
–1
+1
+2
+10
+100
–1
+1
+2
+10
+100
RF (Ω)
RG (Ω)
RO (Nominal) (Ω) 49.9
RS (Ω)
RT (Nominal) (Ω) 54.9
Small Signal
BW (MHz)
0.1 dB Flatness
(MHz)
649
649
1050
750
750
49.9
470
51
49.9
1000
10
49.9
604
604
49.9
0
54.9
370
953
681
681
49.9
470
51
49.9
1000
10
49.9
845 1000 768
845 768
49.9 49.9 49.9
0
54.9 49.9 49.9
240 795 380
470
51
49.9
1000
10
49.9
49.9
49.9
0
49.9
880
49.9
460
49.9
260
49.9
20
49.9
710
49.9
440
49.9
260
49.9
20
49.9
260
49.9
20
340
105
70
105
130
100
120
110 300 145
–14–
REV. C
AD8001
Evaluation Board
ordering information, please refer to the Ordering Guide. The
layout of the evaluation board can be used as shown or serve as
a guide for a board layout.
An evaluation board for the AD8001 is available that has been
carefully laid-out and tested to demonstrate that the specified
high speed performance of the device can be realized. For
Figure 52. Evaluation Board Layout
(Component Side)
Figure 50. Evaluation Board
Silkscreen (Top)
Figure 51. Evaluation Board Layout
(Solder Side)
REV. C
–15–
AD8001
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead Cerdip
(Q-8)
0.430 (10.92)
0.348 (8.84)
0.005 (0.13) 0.055 (1.4)
MIN
MAX
8
5
8
5
0.280 (7.11)
0.240 (6.10)
0.310 (7.87)
0.220 (5.59)
1
4
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.100 (2.54) BSC
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.210
(5.33)
MAX
0.195 (4.95)
0.060 (1.52)
0.015 (0.38)
0.115 (2.93)
0.200.(5.08)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.150
(3.81)
MIN
0.200 (5.08)
0.015 (0.381)
0.008 (0.204)
0.125 (3.18)
0.022 (0.558) 0.070 (1.77) SEATING
0.015 (0.38)
0.008 (0.20)
PLANE
0.014 (0.356) 0.045 (1.15)
SEATING
PLANE
15°
0°
0.023 (0.58) 0.070 (1.78)
0.014 (0.36) 0.030 (0.76)
8-Lead Plastic SOIC
(SO-8)
5-Lead Plastic Surface Mount (SOT-23)
(RT-5)
0.1181 (3.00)
0.1102 (2.80)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
5
1
4
3
0.1574 (4.00)
0.1497 (3.80)
0.1181 (3.00)
0.1024 (2.60)
0.0669 (1.70)
0.0590 (1.50)
2
PIN 1
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0374 (0.95) BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0748 (1.90)
BSC
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0079 (0.20)
0.0031 (0.08)
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0512 (1.30)
0.0354 (0.90)
0.0571 (1.45)
0.0374 (0.95)
0.0098 (0.25)
0.0075 (0.19)
10؇
0؇
SEATING
PLANE
0.0197 (0.50)
0.0138 (0.35)
0.0059 (0.15)
0.0019 (0.05)
0.0217 (0.55)
0.0138 (0.35)
–16–
REV. C
相关型号：
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