AD8002AN [ADI]
Dual 600 MHz, 50 mW Current Feedback Amplifier; 双600兆赫， 50毫瓦电流反馈放大器
| 型号： | AD8002AN |
| 厂家： | 
ADI |
| 描述： | Dual 600 MHz, 50 mW Current Feedback Amplifier |
| 文件： | 总18页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 600 MHz, 50 mW
a
Current Feedback Amplifier
AD8002
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Excellent Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness 0.1 dB to 60 MHz
0.01% Differential Gain Error
8-Lead Plastic DIP, SOIC and SOIC
0.02؇ Differential Phase Error
Low Power
OUT1
–IN1
+IN1
V–
V+
1
2
3
4
8
7
6
5
5.5 mA/Amp Max Power Supply Current (55 mW)
High Speed and Fast Settling
600 MHz, –3 dB Bandwidth (G = +1)
500 MHz, –3 dB Bandwidth (G = +2)
1200 V/s Slew Rate
OUT2
–IN2
+IN2
AD8002
16 ns Settling Time to 0.1%
Low Distortion
–65 dBc THD, fC = 5 MHz
33 dBm 3rd Order Intercept, F1 = 10 MHz
–66 dB SFDR, f = 5 MHz
–60 dB Crosstalk, f = 5 MHz
The outstanding bandwidth of 600 MHz along with 1200 V/µs
of slew rate make the AD8002 useful in many general purpose
high speed applications where dual power supplies of up to ±6 V
and single supplies from 6 V to 12 V are needed. The AD8002 is
available in the industrial temperature range of –40°C to +85°C.
High Output Drive
Over 70 mA Output Current
1
Drives Up to Eight Back-Terminated 75 ⍀ Loads
(Four Loads/Side) While Maintaining Good
Differential Gain/Phase Performance (0.01%/0.17؇)
Available in 8-Lead Plastic DIP, SOIC and SOIC Packages
0
SIDE 1
G = +2
–1
–2
–3
–4
–5
–6
–7
–8
–9
SIDE 2
SIDE 1
R
= 100⍀
L
V
= 50mV
IN
APPLICATIONS
A-to-D Driver
0.1
0
Video Line Driver
Differential Line Driver
Professional Cameras
Video Switchers
Special Effects
–0.1
–0.2
–0.3
–0.4
–0.5
SIDE 2
RF Receivers
1M
10M
100M
1G
PRODUCT DESCRIPTION
FREQUENCY – Hz
The AD8002 is a dual, low power, high speed amplifier de-
signed to operate on ±5 V supplies. The AD8002 features
unique transimpedance linearization circuitry. This allows it to
drive video loads with excellent differential gain and phase per-
formance on only 50 mW of power per amplifier. The AD8002
is a current feedback amplifier and features gain flatness of 0.1 dB
to 60 MHz while offering differential gain and phase error of
0.01% and 0.02°. This makes the AD8002 ideal for professional
video electronics such as cameras and video switchers. Addition-
ally, the AD8002’s low distortion and fast settling make it ideal
for buffer high speed A-to-D converters.
Figure 1. Frequency Response and Flatness, G = +2
The AD8002 offers low power of 5.5 mA/amplifier max (VS =
±5 V) and can run on a single +12 V power supply, while ca-
pable of delivering over 70 mA of load current. It is offered in
an 8-lead plastic DIP, SOIC and µSOIC package. These features
make this amplifier ideal for portable and battery powered appli-
cations where size and power is critical.
Figure 2. 1 V Step Response, G = +1
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
1
(@ T = + 25؇C, V = ؎5 V, R = 100
⍀
, RC = 75
⍀
, unless otherwise noted)
AD8002–SPECIFICATIONS
A
S
L
Model
AD8002A
Typ
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, N Package
G = +2, RF = 750 Ω
G = +1, RF = 1.21 kΩ
G = +2, RF = 681 Ω
G = +1, RF = 953 Ω
G = +2, RF = 681 Ω
G = +1, RF = 1 kΩ
500
600
500
600
500
600
MHz
MHz
MHz
MHz
MHz
MHz
R Package
RM Package
Bandwidth for 0.1 dB Flatness
N Package
G = +2, RF = 750 Ω
G = +2, RF = 681 Ω
G = +2, RF = 681 Ω
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
60
90
60
700
1200
16
MHz
MHz
MHz
V/µs
V/µs
ns
R Package
RM Package
Slew Rate
Settling Time to 0.1%
Rise & Fall Time
G = +2, VO = 2 V Step, RF = 750 Ω
2.4
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p
G = +2, RL = 100 Ω
f = 5 MHz, G = +2
f = 10 kHz, RC = 0 Ω
f = 10 kHz, +In
–65
dBc
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
–60
2.0
2.0
18
0.01
0.02
33
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
dBm
–In
Differential Gain Error
Differential Phase Error
Third Order Intercept
1 dB Gain Compression
SFDR
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
f = 10 MHz
f = 10 MHz
f = 5 MHz
14
–66
dBm
dB
DC PERFORMANCE
Input Offset Voltage
2.0
2.0
10
6
9
mV
mV
TMIN–TMAX
Offset Drift
–Input Bias Current
µV/°C
±µA
±µA
±µA
±µA
kΩ
5.0
25
35
6.0
10
TMIN–TMAX
+Input Bias Current
3.0
TMIN–TMAX
VO = ±2.5 V
TMIN–TMAX
Open Loop Transresistance
250
175
900
kΩ
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
10
50
1.5
3.2
MΩ
Ω
pF
±V
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
VCM = ±2.5 V
49
54
dB
–Input Current
+Input Current
V
CM = ±2.5 V, TMIN–TMAX
0.3
0.2
1.0
0.9
µA/V
µA/V
VCM = ±2.5 V, TMIN–TMAX
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current2
RL = 150 Ω
2.7
85
3.1
70
110
±V
mA
mA
Short Circuit Current2
POWER SUPPLY
Operating Range
Quiescent Current/Both Amplifiers
Power Supply Rejection Ratio
±3.0
±6.0
11.5
V
mA
dB
TMIN–TMAX
+VS = +4 V to +6 V, –VS = –5 V
–VS = – 4 V to –6 V, +VS = +5 V
10.0
75
56
60
49
dB
–Input Current
+Input Current
T
MIN–TMAX
0.5
0.1
2.5
0.5
µA/V
µA/V
TMIN–TMAX
NOTES
1RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, RC is not required.
2Output current is limited by the maximum power dissipation in the package. See the power derating curves.
Specifications subject to change without notice.
–2–
REV. C
AD8002
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
The maximum power that can be safely dissipated by the
AD8002 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-
perature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W
µSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R, RM . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
While the AD8002 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
2.0
8-LEAD PLASTIC-DIP PACKAGE
8-LEAD SOIC PACKAGE
8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
1.5
8-Lead µSOIC Package: θJA = 200°C/W
T
= +150؇C
J
1.0
8-LEAD SOIC
PACKAGE
0.5
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Brand Code
AD8002AN
AD8002AR
AD8002AR-REEL
AD8002AR-REEL7
AD8002ARM
AD8002ARM-REEL
AD8002ARM-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead PDIP
8-Lead SOIC
8-Lead SOIC 13" REEL
8-Lead SOIC 7" REEL
8-Lead µSOIC
8-Lead µSOIC 13" REEL
8-Lead µSOIC 7" REEL
N-8
Standard
Standard
Standard
Standard
HFA
HFA
HFA
SO-8
SO-8
SO-8
RM-8
RM-8
RM-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD8002
750⍀
953⍀
10F
10F
+5V
+5V
0.1F
0.1F
750⍀
AD8002
AD8002
75⍀
50⍀
75⍀
50⍀
0.1F
0.1F
R = 100⍀
L
V
R
= 100⍀
V
IN
L
IN
PULSE
GENERATOR
PULSE
GENERATOR
10F
10F
T
/T = 250ps
F
T
/T = 250ps
F
R
R
–5V
–5V
Figure 7. Test Circuit, Gain = +2
Figure 4. Test Circuit , Gain = +1
Figure 5. 100 mV Step Response, G = +1
Figure 8. 100 mV Step Response, G = +2
Figure 9. 1 V Step Response, G = +2
Figure 6. 1 V Step Response, G = +1
–4–
REV. C
AD8002
1
–20
–30
V
R
= –4dBV
= 100⍀
IN
0
SIDE 1
L
OUTPUT SIDE 1
G = +2
V
= ؎5.0V
S
R
= 100⍀
–1
–2
–3
–4
–5
–6
–7
–8
–9
–40
–50
SIDE 2
SIDE 1
L
G = +2
= 750⍀
V
= 50mV
IN
R
F
0.1
0
–60
–70
–80
OUTPUT SIDE 2
–0.1
–0.2
–0.3
–0.4
–0.5
75⍀
50⍀
50⍀
SIDE 2
–90
–100
–110
–120
R
681⍀
F
681⍀
1M
10M
100M
1G
100k
1M
10M
FREQUENCY – Hz
100M
FREQUENCY – Hz
Figure 10. Frequency Response and Flatness, G = +2
Figure 13. Crosstalk (Output-to-Output) vs. Frequency
–50
G = +2
R
= 100⍀
L
–60
–70
2ND HARMONIC
–80
3RD HARMONIC
–90
–100
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
NOTES: SIDE 1: V = 0V; 8mV/div RTO
IN
SIDE 2: 1V STEP RTO; 400mV/div
Figure 11. Distortion vs. Frequency, G = +2, RL = 100 Ω
Figure 14. Pulse Crosstalk, Worst Case, 1 V Step
0.02
–60
2 BACK TERMINATED
G = +2
LOADS (75⍀)
0.01
R
= 1k⍀
L
V
= 2V p-p
–70
–80
OUT
0.00
–0.01
–0.02
1 BACK TERMINATED
LOAD (150⍀)
G = +2
= 750⍀
NTSC
2ND HARMONIC
R
F
2 BACK TERMINATED
–90
LOADS (75⍀)
3RD HARMONIC
0.08
0.06
–100
–110
–120
1 BACK TERMINATED
0.04
0.02
0.00
LOAD (150⍀)
10k
100k
1M
FREQUENCY – Hz
10M
100M
1
2
3
4
5
6
7
8
9
10
11
IRE
Figure 12. Distortion vs. Frequency, G = +2, RL = 1 kΩ
Figure 15. Differential Gain and Differential Phase
(per Amplifier)
REV. C
–5–
AD8002
+6
+3
0
0
–3
+2
+1
0
V
= 50mV
IN
G = +1
R
R
SIDE 1
SIDE 2
= 953⍀
= 100⍀
F
L
–6
–3
–6
–9
–1
–2
–3
–4
–5
–6
–12
–15
–18
–21
–24
–27
–9
75⍀
50⍀
G = +2
–12
–15
50⍀
R
= 681⍀
F
V
= ؎5V
S
R
= 100⍀
L
953⍀
–18
–21
1M
10M
FREQUENCY – Hz
100M
500M
1M
10M
100M
FREQUENCY – Hz
1G
Figure 16. Frequency Response, G = +1
Figure 19. Large Signal Frequency Response, G = +2
+9
–40
R
= 100⍀
L
+6
+3
G = +1
G = +1
= 1.21k⍀
R
= 100⍀
L
–50
–60
R
F
V
= 2V p-p
OUT
0
–3
–6
–70
75⍀
50⍀
50⍀
2ND HARMONIC
–9
–80
–12
–15
–18
–27
3RD HARMONIC
1.21k⍀
–90
–100
1M
10M
100M
500M
10k
100k
1M
FREQUENCY – Hz
10M
100M
FREQUENCY – Hz
Figure 20. Large Signal Frequency Response, G = +1
Figure 17. Distortion vs. Frequency, G = +1, RL = 100 Ω
+45
+40
–40
G = +1
V
= ؎5V
S
R
= 1k⍀
L
–50
–60
R
= 100⍀
L
+35
+30
G = +100
R
= 1000⍀
F
+25
+20
–70
2ND HARMONIC
3RD HARMONIC
G = +10
R = 499⍀
F
–80
+15
+10
+5
0
–90
–100
–110
–5
10k
100k
1M
10M
100M
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
Figure 18. Distortion vs. Frequency, G = +1, RL = 1 kΩ
Figure 21. Frequency Response, G = +10, G = +100
–6–
REV. C
AD8002
Figure 22. Short-Term Settling Time
Figure 25. Long-Term Settling Time
4
3
3.4
DEVICE #1
3.3
3.2
3.1
R
= 150⍀
L
V
= ؎5V
S
2
1
+V
OUT
|–V
|
3.0
2.9
2.8
OUT
DEVICE #2
DEVICE #3
0
R
= 50⍀
L
–1
V
= ؎5V
S
2.7
2.6
2.5
+V
OUT
–2
–3
|–V
5
|
OUT
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
25
45
65
85
105
125
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 26. Input Offset Voltage vs. Temperature
Figure 23. Output Swing vs. Temperature
11.5
11.0
10.5
5
4
–IN
3
2
1
V
= ؎5V
S
10.0
9.5
0
–1
+IN
–2
9.0
–3
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 24. Input Bias Current vs. Temperature
Figure 27. Total Supply Current vs. Temperature
REV. C
–7–
AD8002
120
100
R
= 50⍀
bT
115
110
R
R
V
= 750⍀
= 75⍀
= ؎5.0V
F
C
S
10
1
105
100
95
POWER = 0dBm
(223.6mVrms)
G = +2
|SINK I
|
SC
SOURCE I
SC
R
= 0⍀
bT
90
0.1
0.01
85
80
75
70
–55
10k
100k
1M
10M
100M
1G
–35
–15
5
25
45
65
85
105
125
FREQUENCY – Hz
JUNCTION TEMPERATURE – ؇C
Figure 31. Output Resistance vs. Frequency
Figure 28. Short Circuit Current vs. Temperature
1
100
100
–3dB BANDWIDTH
0.1dB FLATNESS
SIDE 1
0
SIDE 2
+0.2
+0.1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
INVERTING CURRENT V = ؎5V
S
SIDE 1
–0.1
–0.2
–0.3
10
10
V
V
= ؎5V
= 50mV
S
IN
SIDE 2
NONINVERTING CURRENT V = ؎5V
G = –1
S
R
R
= 100⍀
= 549⍀
L
F
VOLTAGE NOISE V = ؎5V
S
1
100k
1
1M
10M
100M
1G
100
1k
10k
10
FREQUENCY – Hz
FREQUENCY – Hz
Figure 32. –3 dB Bandwidth vs. Frequency, G = –1
Figure 29. Noise vs. Frequency
–50.0
–48
–49
–50
–52.5
–PSRR
–55.0
–57.5
–CMRR
+CMRR
2V SPAN
–60.0
–51
–52
CURVES ARE FOR WORST
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
–62.5
–65.0
–53
–54
–55
–67.5
–70.0
–72.5
–75.0
+PSRR
–56
–55
–55
–35
–15
5
25
45
65
85
105
125
–35
–15
5
25
45
65
85
105
125
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 33. PSRR vs. Temperature
Figure 30. CMRR vs. Temperature
–8–
REV. C
AD8002
0
–10
–20
–30
–40
–50
0
V
= 200mV
V
IN
IN
G = +2
604⍀
–10
604⍀
154Ω
50⍀
–20
–30
–40
–50
–60
57.6⍀
154⍀
0.1F
–PSRR
–5V
+PSRR
–60
–70
–80
–90
SIDE 1
V
= ؎5.0V
= 100⍀
= 200mV
S
R
V
L
SIDE 2
IN
30k 100k
1M
10M
FREQUENCY – Hz
100M
500M
1M
10M
100M
1G
FREQUENCY – Hz
Figure 37. PSRR vs. Frequency
Figure 34. CMRR vs. Frequency
Figure 38. 2 V Step Response, G = –2
Figure 35. 2 V Step Response, G = –1
549⍀
576⍀
274⍀
576⍀
50⍀
50⍀
61.9⍀
50⍀
54.9⍀
50⍀
Figure 39. 100 mV Step Response, G = –2
Figure 36. 100 mV Step Response, G = –1
REV. C
–9–
AD8002
THEORY OF OPERATION
Printed Circuit Board Layout Considerations
A very simple analysis can put the operation of the AD8002, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8002’s open-loop behavior is ex-
pressed as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop
transimpedance behaves just as the open-loop voltage gain of a
voltage feedback amplifier, that is, it has a large dc value and
decreases at roughly 6 dB/octave in frequency.
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than 5
mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.
Since the RIN is proportional to 1/gM, the equivalent voltage
gain is just TZ × gM, where the gM in question is the trans-
conductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 40, basic
analysis yields the following result.
Power Supply Bypassing
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈4.7 Ω for
optimum results.
VO
VIN
TZ (S)
TZ (S) + G × RIN + R1
= G ×
R1
R2
G = 1 +
RIN = 1/gM ≈ 50 Ω
R1
R2
DC Errors and Noise
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa-
tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 41) they are
input offset (VIO) which appears at the output multiplied by the
noise gain of the circuit (1 + RF/RI), noninverting input current
(IBN × RN) also multiplied by the noise gain, and the inverting
input current, which when divided between RF and RI and sub-
sequently multiplied by the noise gain always appears at the
output as IBN × RF. The input voltage noise of the AD8002 is a
low 2 nV/√Hz. At low gains though the inverting input current
noise times RF is the dominant noise source. Careful layout and
device matching contribute to better offset and drift specifica-
tions for the AD8002 compared to many other current feedback
amplifiers. The typical performance curves in conjunction with
the equations below can be used to predict the performance of
the AD8002 in any application.
R
IN
V
OUT
V
IN
Figure 40.
Recognizing that G × RIN << R1 for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G).
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice
parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop, so picking an optimum value for RF
can be difficult.
RF
RI
RF
RI
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
VOUT = VIO × 1 +
± IBN × RN × 1 +
± IBI × RF
R
F
Choice of Feedback and Gain Resistors
The fine scale gain flatness will, to some extent, vary with feed-
back resistance. It, therefore, is recommended that once opti-
mum resistor values have been determined, 1% tolerance values
should be used if it is desired to maintain flatness over a wide
range of production lots. In addition, resistors of different con-
struction have different associated parasitic capacitance and
inductance. Surface mount resistors were used for the bulk of
the characterization for this data sheet. It is not recommended
that leaded components be used with the AD8002.
I
BI
R
I
V
OUT
I
BN
R
N
Figure 41. Output Offset Voltage
–10–
REV. C
AD8002
–45
–50
–55
–60
–65
–70
–75
–80
Driving Capacitive Loads
The AD8002 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 42. The accompanying graph
G = +2
F
= 10MHz
1
2
F
= 12MHz
2F – F
2
1
909⍀
2F – F
1
2
R
SERIES
I
N
R
L
C
L
500⍀
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
Figure 42. Driving Capacitive Loads
INPUT POWER – dBm
Figure 44. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
shows the optimum value for RSERIES vs. capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of RSERIES and CL.
Operation as a Video Line Driver
The AD8002 has been designed to offer outstanding perfor-
mance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.02°) meet the
most exacting HDTV demands for driving one video load with
each amplifier. The AD8002 also drives four back terminated
loads (two each), as shown in Figure 45, with equally impressive
performance (0.01%, 0.07°). Another important consideration
is isolation between loads in a multiple load application. The
AD8002 has more than 40 dB of isolation at 5 MHz when driv-
ing two 75 Ω back terminated loads.
40
30
20
75⍀
CABLE
750⍀
750⍀
75⍀
V
#1
OUT
10
0
75⍀
+V
4.7F
+
S
0.1F
0
5
10
15
20
25
75⍀
CABLE
C
– pF
L
75⍀
1/2
AD8002
V
#2
OUT
Figure 43. Recommended RSERIES vs. Capacitive Load
75⍀
0.1F
4.7F
Communications
75⍀
CABLE
Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamen-
tals and do not lend themselves to filtering. Theory predicts that
the third order harmonic distortion components increase in
power at three times the rate of the fundamental tones. The
specification of third order intercept as the virtual point where
fundamental and harmonic power are equal is one standard
measure of distortion performance. Op amps used in closed-
loop applications do not always obey this simple theory. At a
gain of two, the AD8002 has performance summarized in Fig-
ure 44. Here the worst third order products are plotted vs. input
power. The third order intercept of the AD8002 is +33 dBm at
10 MHz.
V
IN
–V
S
75⍀
75⍀
CABLE
75⍀
75⍀
1/2
AD8002
V
#3
OUT
75⍀
75⍀
750⍀
75⍀
CABLE
750⍀
V
#4
OUT
Figure 45. Video Line Driver
REV. C
–11–
AD8002
Driving A-to-D Converters
ADC. Using the AD9058’s internal +2 V reference connected
to both ADCs as shown in Figure 46 reduces the number of
external components required to create a complete data
acquisition system. The 20 Ω resistors in series with ADC in-
puts are used to help the AD8002s drive the 10 pF ADC input
capacitance. The AD8002 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.
The AD8002 is well suited for driving high speed analog-to-
digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below the AD8002 is shown
driving the inputs of the AD9058 which are configured for 0 V
to +2 V ranges. Bipolar input signals are buffered, amplified
(–2×), and offset (by +1.0 V) into the proper input range of the
1k⍀
74ACT04
ENCODE
10pF
50⍀
10
36
ENCODE A
ENCODE B
8
–V
549⍀
5, 9, 22,
REF A
REF B
+5V
+V
S
38
24, 37, 41
–V
0.1F
ANALOG
IN A
؎0.5V
274⍀
RZ1
20⍀
1/2
AD8002
6
A
18
17
16
15
14
13
12
11
IN A
D
(LSB)
0A
50⍀
1.1k⍀
2
3
–2V
+V
+V
+V
8
INT
AD707
20k⍀
0.1F
0.1F
REF A
REF B
43
20k⍀
549⍀
D
(MSB)
(LSB)
7A
1.1k⍀
RZ2
AD9058
28
29
30
31
32
33
34
35
(J-LEAD)
D
0B
ANALOG
IN B
؎0.5V
274⍀
40
1
20⍀
1/2
AD8002
8
A
IN B
50⍀
COMP
0.1F
D
(MSB)
7B
7, 20,
CLOCK
–V
–5V
1N4001
S
26, 39
RZ1, RZ2 = 2,000⍀ SIP (8-PKG)
0.1F
4,19, 21 25, 27, 42
Figure 46. AD8002 Driving a Dual A-to-D Converter
–12–
REV. C
AD8002
Single-Ended to Differential Driver Using an AD8002
The two halves of an AD8002 can be configured to create a
single-ended to differential high speed driver with a –3 dB band-
width in excess of 200 MHz as shown in Figure 47. Although
the individual op amps are each current feedback, the overall
architecture yields a circuit with attributes normally associated
with voltage feedback amplifiers, while offering the speed advan-
tages inherent in current feedback amplifiers. In addition, the
gain of the circuit can be changed by varying a single resistor,
RF, which is often not possible in a dual op amp differential
driver.
With a feedback resistor RF, an input resistor RG, and grounding
of the +input of Op Amp #2, a feedback amplifier is formed.
This configuration is just like a voltage feedback amplifier in an
inverting configuration if only Output #2 is considered. The
addition of Output #1 makes the amplifier differential output.
The differential gain of this circuit is:
RF
RG
RA
RB
G =
× 1 +
The RF/RG term is the gain of the overall op amp configuration
and is the same as for an inverting op amp except for the polar-
ity. If Output #1 is used as the output reference, then the gain is
positive. The 1+RA/RB term is the noise gain of each individual
op amp in its noninverting configuration.
C
0.5–1.5pF
C
R
511⍀
F
R
G
511⍀
OP AMP #1
50⍀
V
IN
The resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either RF or RG will change the gain as in an inverting op amp
circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
CMR.
1/2
AD8002
OUTPUT #1
R
A
511⍀
R
511⍀
R
511⍀
B
B
R
511⍀
A
Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. The circuit described requires
about 0.9 pF of capacitance in shunt across RF in order to opti-
mize peaking and realize a –3 dB bandwidth of more than
200 MHz.
50⍀
1/2
AD8002
OUTPUT #2
OP AMP #2
Figure 47. Differential Line Driver
The current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of more
than 3 V p-p into a 20 Ω load for each output at 20 MHz. On
the other hand, the voltage feedback nature provides symmetri-
cal high impedance inputs and allows the use of reactive compo-
nents in the feedback network.
The peaking exhibited by the circuit is very sensitive to the value
of this capacitor. Parasitics in the board layout on the order of
tenths of picofarads will influence the frequency response and
the value required for the feedback capacitor, so a good layout is
essential.
The shunt capacitor type selection is also critical. A good micro-
wave type chip capacitor with high Q was found to yield best
performance. The part selected for this circuit was a muRata
Erie part no. MA280R9B.
The circuit consists of the two op amps each configured as a
unity gain follower by the 511 Ω RA feedback resistors between
each op amp’s output and inverting input. The output of each
op amp has a 511 Ω RB resistor to the inverting input of the
other op amp. Thus, each output drives the other op amp
through a unity gain inverter configuration. By connecting the
two amplifiers as cross-coupled inverters, their outputs are freed
to be equal and opposite, assuring zero-output common-mode
voltage.
The distortion was measured at 20 MHz with a 3 V p-p input
and a 100 Ω load on each output. For Output #1 the distortion
is –37 dBc and –41 dBc for the second and third harmonics
respectively. For Output #2 the second harmonic is –35 dBc
and the third harmonic is –43 dBc.
With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the
negative input to the other op amp drives its output to go
slightly lower and thus preserves the symmetry of the comple-
mentary outputs which reduces the common-mode signal. The
common-mode output signal was measured to be –50 dB at
1 MHz.
+6
C
= 0.9pF
C
+4
+2
0
–2
–4
–6
Looking at this configuration overall, there are two high imped-
ance inputs (the + inputs of each op amp), two low impedance
outputs and high open loop gain. If we consider the two nonin-
verting inputs and just the output of Op Amp #2, the structure
looks like a voltage feedback op amp having two symmetrical,
high impedance inputs and one output. The +input to Op Amp
#2 is the noninverting input (it has the same polarity as Output
#2) and the +input to Amplifier #1 is the inverting input (oppo-
site polarity of Output #2).
OUT+
–8
–10
–12
–14
OUT–
1M
10M
100M
1G
FREQUENCY – Hz
Figure 48. Differential Driver Frequency Response
REV. C
–13–
AD8002
Layout Considerations
R
F
The specified high speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component selec-
tion are mandatory.
+V
S
R
G
IN
R
BT
OUT
R
T
R
S
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
–V
S
Inverting Configuration
Chip capacitors should be used for supply bypassing (see Figure
49). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
+V
–V
S
C1
0.1F
C3
10F
C2
0.1F
C4
10F
S
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Supply Bypassing
R
F
+V
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
S
R
G
R
BT
OUT
*R
C
IN
R
T
–V
S
*SEE TABLE I
Noninverting Configuration
Figure 49. Inverting and Noninverting Configurations
Table I. Recommended Component Values
AD8002AN (DIP)
Gain
AD8002AR (SOIC)
Gain
Component
–10
–2
–1
+1
1210 750
750
+2
+10
+100 –10
–2
–1
+1
+2
+10
+100
RF (Ω)
RG (Ω)
499
49.9 274
549
576
576
499
54.9 10
1000 499
499
549
549
953
–
681
681
499
54.9 10
1000
–
49.9 249
RBT (Nominal) (Ω)
RC (Ω)*
RS(Ω)
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
75 75 75 75
0
0
0
0
49.9 49.9 49.9
61.9 54.9 49.9 49.9 49.9 49.9
49.9 49.9 49.9
RT (Nominal) (Ω)
–
–
61.9 54.9 49.9 49.9 49.9 49.9
Small Signal BW (MHz) 270
380
80
410
130
600
35
500
60
170
24
17
3
250
50
410
100
410
100
600
35
500
90
170
24
17
3
0.1 dB Flatness (MHz)
45
AD8002ARM (SOIC)
Gain
Component
–10
–2
–1
+1
1000 681
681
+2
+10
+100
RF (Ω)
RG (Ω)
499
49.9 249
499
590
590
499
54.9 10
1000
–
RBT (Nominal) (Ω)
RC (Ω)*
RS(Ω)
49.9 49.9 49.9 49.9 49.9 49.9 49.9
75 75
0
0
49.9 49.9 49.9
61.9 49.9 49.9 49.9 49.9 49.9
RT (Nominal) (Ω)
–
Small Signal BW (MHz) 270
0.1 dB Flatness (MHz) 60
400
100
410
100
600
35
450
70
170
35
19
3
*RC is recommended to reduce peaking and minimizes input reflections at frequencies above 300 MHz. However, R C is not required.
–14–
REV. C
AD8002
Figure 50. Board Layout (Silkscreen)
REV. C
–15–
AD8002
Figure 51. Board Layout (Component Layer)
–16–
REV. C
AD8002
Figure 52. Board Layout (Solder Side) (Looking Through the Board)
REV. C
–17–
AD8002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
5
4
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
PLANE
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
8-Lead SOIC (RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33؇
27؇
0.018 (0.46)
0.008 (0.20)
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
–18–
REV. C
相关型号：
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