AD8004ANZ [ADI]
Quad 3000 V/mu s, 35 mW Current Feedback Amplifier; 四核3000 V /亩？ S， 35毫瓦电流反馈放大器
| 型号： | AD8004ANZ |
| 厂家： | 
ADI |
| 描述： | Quad 3000 V/mu s, 35 mW Current Feedback Amplifier |
| 文件： | 总17页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 3000 V/ꢀs, 35 mW
Current Feedback Amplifier
a
AD8004
FEATURES
CONNECTION DIAGRAM
High Speed
250 MHz –3 dB Bandwidth (G = +1)
3000 V/ꢀs Slew Rate
PDIP (N), CERDIP (Q), and
SOIC (R) Packages
21 ns Settling Time to 0.1%
1.8 ns Rise Time for 2 V Step
Low Power
3.5 mA/Amp Power Supply Current (35 mW/Amp)
Single Supply Operation
Fully Specified for +5 V Supply
Good Video Specifications (RL = 150 ꢁ, G = +2)
Gain Flatness 0.1 dB to 30 MHz
0.04% Differential Gain Error
0.10ꢂ Differential Phase Error
Low Distortion
OUTPUT
–IN
1
2
3
4
5
6
7
14
13
12
OUTPUT
–IN
1
4
+IN
+IN
AD8004
TOP VIEW)
+V
11 –V
S
S
(
+IN
+IN
–IN
10
9
–IN
2
3
OUTPUT
OUTPUT
8
30 MHz while offering differential gain and phase error of
0.04% and 0.10∞. This makes the AD8004 suitable for video
electronics such as cameras and video switchers.
–78 dBc THD at 5 MHz
–61 dBc THD at 20 MHz
High Output Current of 50 mA
Available in a 14-Lead PDIP, SOIC, and CERDIP
The AD8004 offers low power of 3.5 mA/amplifier and can run
on a single +4 V to +12 V power supply, while being capable of
delivering up to 50 mA of load current. All this is offered in a
small 14-lead DIP or 14-lead SOIC package. These features
make this amplifier ideal for portable and battery powered appli-
cations where size and power are critical.
APPLICATIONS
Image Scanners
Active Filters
Video Switchers
Special Effects
The outstanding bandwidth of 250 MHz along with 3000 V/ms
of slew rate make the AD8004 useful in many general-purpose,
high speed applications where dual power supplies of up to ±6 V
and single supplies from 4 V to 12 V are needed. The AD8004
is available in the industrial temperature range of –40∞C to +85∞C
in the N and R packages, and in the military temperature range
of –55∞C to +125∞C in the Q package.
GENERAL DESCRIPTION
The AD8004 is a quad, low power, high speed amplifier designed
to operate on single or dual supplies. It utilizes a current feed-
back architecture and features high slew rate of 3000 V/ms
making the AD8004 ideal for handling large amplitude pulses.
Additionally, the AD8004 provides gain flatness of 0.1 dB to
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
1
0
G = +2
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
= 50mV rms
= 100ꢁ
= 1.10kꢁ
80 IRE
IN
R
R
R
V
= 150ꢁ
= ꢃ5V
= 1.21kꢁ
L
L
S
ꢃ5V
S
F
+5V
S
R
R PACKAGE
F
0.1
0
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.1
–0.2
–0.3
–0.4
–0.5
ꢃ5V
S
+5V
S
80 IRE
R
V
= 150ꢁ
= ꢃ5V
= 1.21kꢁ
L
S
R
F
–0.04
100
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
1
10
40
500
FREQUENCY – MHz
Figure 2. Differential Gain/Differential Phase
Figure 1. Frequency Response and Flatness, G = +2
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD8004*
Last content update 08/18/2013 01:36 am
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DOCUMENTATION
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
AN-356: User's Guide to Applying and Measuring Operational
Amplifier Specifications
MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
Telephone our Customer Interaction Centers toll free:
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00800-266-822-82
4006-100-006
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A Stress-Free Method for Choosing High-Speed Op Amps
UG-111: Universal Evaluation Board for Quad, High Speed Op Amps
Offered in 14-Lead SOIC Packages
India:
Russia:
ADI Warns Against Misuse of COTS Integrated Circuits
Current Feedback Amplifiers Part 1: Ask The Applications Engineer-22
Current Feedback Amplifiers Part 2: Ask The Applications Engineer-23
Two-Stage Current-Feedback Amplifier
Quality and Reliability
Lead(Pb)-Free Data
Space Qualified Parts List
SAMPLE & BUY
AD8004
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
View Price & Packaging
Request Evaluation Board
Analog Filter Wizard 2.0
Request Samples Check Inventory & Purchase
AD8004A SPICE Macro-Model
Find Local Distributors
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for documentation and
purchasing
Symbols and Footprints
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
(@ T = +25ꢀC, V = ꢁ5 V, R = 100 ꢂ, unless otherwise noted.)
AD8004–SPECIFICATIONS
A
S
L
AD8004A
AD8004S
Parameter
Conditions
Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth, N Package
G = +2, RF = 698 Ω
G = +1, RF = 806 Ω
G = +2
G = +2, VO = 4 V Step
G = –2, VO = 4 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
185
250
30
3000
2000
21
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
30
3000
2000
21
Settling Time to 0.1%
Rise and Fall Time (10% to 90%)
1.8
1.8
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Crosstalk, R Package, Worst Case
Crosstalk, N Package, Worst Case
Input Voltage Noise
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = +2, RL = 1 kΩ
f = 5 MHz, G = +2, RL = 1 kΩ
f = 10 kHz
–78
–69
–64
1.5
38
38
0.04
0.10
0.01
0.04
–78
dBc
dB
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
%
1.5
38
38
0.04
0.10
0.01
0.04
Input Current Noise
f = 10 kHz, +In
–In
Differential Gain Error
Differential Phase Error
Differential Gain Error
Differential Phase Error
NTSC, G = +2, RL = 150 Ω, RF = 1.21 kΩ
NTSC, G = +2, RL = 150 Ω, RF = 1.21 kΩ
NTSC, G = +2, RL = 1 kΩ, RF = 1.21 kΩ
NTSC, G = +2, RL = 1 kΩ, RF = 1.21 kΩ
Degree
DC PERFORMANCE
Input Offset Voltage
1.0 3.5
1.0 3.5
mV
T
MIN to TMAX
1.5
15
35
5
1.5
15
35
6
mV
µV/°C
90 µA
Offset Drift
–Input Bias Current
90
TMIN to TMAX
110
110
120
120 µA
110 µA
130 µA
kΩ
+Input Bias Current
40
40
TMIN to TMAX
VO = 2.5 V
TMIN to TMAX
Open-Loop Transresistance
170 290
220
170 290
220
kΩ
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
2
2
MΩ
50
1.5
3.2
50
1.5
3.2
Ω
Input Capacitance
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
–Input Current
+Input Current
VCM
VCM
VCM
=
=
=
2.5 V
2.5 V, TMIN to TMAX
2.5 V, TMIN to TMAX
52
58
1
12
52
58
1
12
dB
µA/V
µA/V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
RL = 150 Ω
3.9
50
100 180
3.9
50
100 180
V
mA
mA
Short Circuit Current
POWER SUPPLY
Operating Range
Total Quiescent Current
2.0
14
16
6.0
17
20
2.0
14
16
6.0
17
23
V
mA
mA
dB
µA/V
µA/V
TMIN to TMAX
Power Supply Rejection Ratio
–Input Current
+Input Current
∆VS = 2 V
56
62
0.5
4
56
62
0.5
4
TMIN to TMAX
TMIN to TMAX
Specifications subject to change without notice.
–2–
REV. C
AD8004
SPECIFICATIONS (@ TA = +25ꢀC, VS = +5 V, RL = 100 ꢂ, unless otherwise noted.)
AD8004A
AD8004S
Typ
Parameter
Conditions
Min
Typ
Max Min
Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth, N Package
G = +2, RF = 698 Ω
G = +1, RF = 806 Ω
G = +2
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
150
200
30
1100
24
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Rise and Fall Time (10%
to 90%)
30
1100
24
G = +2, VO = 2 V Step
2.3
2.3
ns
NOISE/HARMONIC
PERFORMANCE
Total Harmonic Distortion
Crosstalk, R Package,
Worst Case
Crosstalk, N Package,
Worst Case
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = +2, RL = 1 kΩ
–65
–69
–65
dBc
dB
f = 5 MHz, G = +2, RL = 1 kΩ
f = 10 kHz
f = 10 kHz, +In
–64
1.5
38
dB
Input Voltage Noise
Input Current Noise
1.5
38
38
0.06
0.25
0.01
0.08
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
%
–In
38
Differential Gain Error
Differential Phase Error
Differential Gain Error
Differential Phase Error
NTSC, G = +2, RL = 150 Ω, RF = 1.21 kΩ
NTSC, G = +2, RL = 150 Ω, RF = 1.21 kΩ
NTSC, G = +2, RL = 1 kΩ, RF = 1.21 kΩ
NTSC, G = +2, RL = 1 kΩ, RF = 1.21 kΩ
0.06
0.25
0.01
0.08
Degree
DC PERFORMANCE
Input Offset Voltage
1.0
1
2.5
3
1.0
1
2.5
4
mV
mV
TMIN to TMAX
Offset Drift
–Input Bias Current
15
20
15
20
µV/°C
80 µA
80
TMIN to TMAX
MIN to TMAX
VO = +1.5 V to +3.5 V
TMIN to TMAX
100
100
115
140
110 µA
100 µA
125 µA
kΩ
+Input Bias Current
35
35
T
Open Loop Transresistance
140
230
170
230
170
kΩ
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
2
50
1.5
2
50
1.5
MΩ
Ω
Input Capacitance
Input Common-Mode
Voltage Range
pF
3.2
3.2
V
Common-Mode Rejection Ratio
Offset Voltage
–Input Current
VCM = +1 V to +3 V
VCM = +1 V to +3 V, TMIN to TMAX
VCM = +1 V to +3 V, TMIN to TMAX
52
57
2
15
52
57
2
15
dB
µA/V
µA/V
+Input Current
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
RL = 150 Ω
0.9 to 4.1
50
95
0.9 to 4.1
50
95
V
mA
mA
Short Circuit Current
POWER SUPPLY
Operating Range
Total Quiescent Current
0, +4
56
+12 0, +4
14
+12
14
17.5 mA
V
mA
13
14.5
62
1
13
14.5
62
1
T
MIN to TMAX
∆VS = +1 V, VCM = +2.5 V
MIN to TMAX
TMIN to TMAX
15.5
Power Supply Rejection Ratio
–Input Current
+Input Current
56
dB
µA/V
µA/V
T
6
6
Specifications subject to change without notice.
REV. C
–3–
AD8004
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . Note 2
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (N, Q, R) . . . . –65°C to +125°C
Operating Temperature Range
The maximum power that can be safely dissipated by the
AD8004 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsu-
lated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Exceeding this limit
temporarily may cause a shift in parametric performance due to
a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
S Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
While the AD8004 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power ratings.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
14-Lead PDIP Package: θJA = 90°C/W, θJC = 30°C/W
14-Lead SOIC Package: θJA = 140°C/W, θJC = 30°C/W
14-Lead CERDIP Package: θJA = 110°C/W, θJC = 30°C/W
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8004AN
AD8004AR-14
–40°C to +85°C 14-Lead PDIP
–40°C to +85°C 14-Lead SOIC
N-14
R-14
AD8004AR-14-REEL –40°C to +85°C 13" Tape and Reel R-14
AD8004AR-14-REEL7 –40°C to +85°C 7" Tape and Reel
R-14
AD8004SQ
–55°C to +125°C 14-Lead CERDIP
Q-14
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8004 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SCOPE
INPUT
SCOPE
INPUT
249ꢂ
604ꢂ
50ꢂ
499ꢂ
50ꢂ
604ꢂ
V
IN
50ꢂ
50ꢂ
61.9ꢂ
V
IN
+V
–V
+V
–V
S
S
50ꢂ
0.1ꢃF
0.1ꢃF
0.1ꢃF
0.1ꢃF
10ꢃF
10ꢃF
10ꢃF
10ꢃF
S
S
Figure 4. Test Circuit; Gain = –2
Figure 3. Test Circuit; Gain = –2
–4–
REV. C
Typical Performance Characteristics–AD8004
TPC 1.* 100 mV Step Response; G = +2, VS = 2.5 V or 5 V
TPC 4.* 100 mV Step Response; G = –2, VS = 2.5 V or 5 V
TPC 2.* Step Response; G = +2, VS = 5 V
TPC 5.* Step Response; G = –2, VS = 5 V
2
1
1
G = +1,
= 698ꢂ
G = –1
R
F
0
V
= ꢁ5V
= 499ꢂ
= 50mV rms
= 100ꢂ
–1
–2
–3
–4
–5
–6
S
0
R
V
G = –2
F
R
= 100ꢂ
= 50mV (G = +1, +2)
= 5mV (G = +10)
L
–1
–2
IN
V
V
IN
IN
R
L
N PACKAGE
G = +2,
G = –10
R
= 604ꢂ
–3
–4
–5
–6
–7
–8
F
G = +10,
= 499ꢂ
R
–7
–8
–9
F
1
10
40
100
500
1
10
40
100
500
FREQUENCY – MHz
FREQUENCY – MHz
TPC 3. Frequency Response; G = +1, +2, +10; VS = 5 V
TPC 6. Frequency Response; G = –1, –2, –10
*VS
=
2.5 V operation is identical to VS = +5 V single-supply operation.
REV. C
–5–
AD8004
9
3
0
1V rms
6
3
–3
1V rms
0
–6
–9
–3
–6
–9
–12
–12
–15
–18
G = +2
G = +2
V
= ꢁ5V
V
= +5V
–15
–18
–21
S
S
–21
–24
R
= 604ꢂ
R
= 604ꢂ
F
F
–27
1
10
40
100
500
1
10
40
100
500
FREQUENCY – MHz
FREQUENCY – MHz
TPC 10. Large Signal Frequency Response; VS = +5.0 V,
TPC 7. Large Signal Frequency Response; VS = 5.0 V,
G = +2, RF = 604 Ω
G = +2, RF = 604 Ω
–40
–40
3RD
= 150ꢂ
G = +2
O
R
G = +2
O
L
V
= 2V p-p
2ND
= 150ꢂ
V
= 2V p-p
–50
–60
–70
–50
–60
R
= 698ꢂ
R
F
L
3RD
= 150ꢂ
R
= 698ꢂ
F
R
L
3RD
L
2ND
= 150ꢂ
R
= 1kꢂ
R
L
–70
–80
–90
–80
2ND
= 1kꢂ
R
2ND
L
R
= 1kꢂ
–90
L
3RD
= 1kꢂ
R
L
–100
–100
1
10
20
1
10
20
FREQUENCY – MHz
FREQUENCY – MHz
TPC 11. Distortion vs. Frequency; VS = +5 V
TPC 8. Distortion vs. Frequency; VS = 5 V
–10
1
ꢁ5V
604ꢂ
154ꢂ
S
–15
–20
604ꢂ
154ꢂ
0
50ꢂ
V
IN
G = +2
V
OUT
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
R
R
= 50mV rms
= 100ꢂ
= 1.10kꢂ
IN
L
57.6ꢂ
+5V
ꢁ5V
–25
–30
S
S
F
+5V
S
R PACKAGE
0.1
0
–35
–40
–0.1
–0.2
–0.3
–0.4
–0.5
+5V
ꢁ5V
S
S
–45
+5V
S
–50
–55
–60
ꢁ5V
S
1
10
40
100
500
0.03
0.1
1
10
100
500
FREQUENCY – MHz
FREQUENCY – MHz
TPC 12. CMRR vs. Frequency; VS = 5 V or +5 V,
IN = 200 mV rms, Other Sides Are Equal, RTO
TPC 9. Frequency Response and Flatness, G = +2
V
–6–
REV. C
AD8004
100
10
1
1000
500
0
–10
–20
–30
–40
–50
–60
–70
–80
G = +2
ꢁ5V OR ꢁ2.5V
S
S
R
= 1kꢂ
F
100mV rms ON TOP
OF dc BIAS
300
200
+PSRR
–PSRR
100
70
+ OR – INPUT
CURRENT NOISE
50
40
30
20
VOLTAGE NOISE
10
1M
10
100
1k
10k
100k
10k
100k
1M
10M
100M
500M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 13. Noise vs. Frequency, VS = +5 V or 5 VS
TPC 16. PSRR vs. Frequency
–20
–30
G = +2
= 1.10kꢂ
R
100
F
ꢁ5V
S
–40
R
= 50ꢂ
V
= 200mV rms
BT
IN
G = +2
= 698ꢂ
POWER = 0dBm
ꢁ5V OR +5V
S
INPUT TO SIDE 1
= 1kꢂ
R PACKAGE
S
OUTPUT =
SIDE 2
–50
R
R
F
L1
10
1
–60
OUTPUT =
SIDE 4
(224mV rms)
R
= 0
–70
BT
+5V
S
–80
OUTPUT =
SIDE 3
–90
0.1
ꢁ5V
S
–100
–110
–120
0.01
0.03
0.03
0.1
1
100
500
0.1
1
10
100
500
10
FREQUENCY – MHz
FREQUENCY – MHz
TPC 14. Output Impedance vs. Frequency
TPC 17. Crosstalk (Output to Output) vs. Frequency
110
60
50
40
30
20
10
0
0
100
GAIN
GAIN
90
80
70
60
50
40
30
20
10
0
90
–50
–100
–150
–200
PHASE
PHASE
–180
V
V
= –40dBm
= ꢁ5V
–240
–360
IN
S
–10
0.03
0.1
1
10
100
500
100k
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – MHz
TPC 15. Open-Loop Voltage Gain and Phase
TPC 18. Open-Loop Transimpedance Gain
REV. C
–7–
AD8004
9
8
G = +2
= 1.21kꢂ
R
ꢁ5V
F
S
7
6
5
4
3
2
+5V
S
1
0
10
100
1000
10000
LOAD RESISTANCE – ꢂ
TPC 22. Output Voltage Swing vs. Load
TPC 19. Short-Term Settling Time
10
9
G = +2
F
R
= 1.21kꢂ
8
f = 100kHz
R
= 1kꢂ
L
7
6
5
4
R
= 100ꢂ
L
3
2
1
0
3
4
5
6
7
8
9
10
11
12
TOTAL SUPPLY VOLTAGE – V
TPC 23. Output Swing vs. Supply
TPC 20. Long-Term Settling Time
0.03
0.02
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
80 IRE
R
= 1kꢂ
L
S
F
V
= ꢁ5V
= 1.21kꢂ
0.01
R
80 IRE
0.00
R
V
= 150ꢂ
= ꢁ5V
L
–0.01
S
R
= 1.21kꢂ
F
–0.02
–0.03
–0.04
1ST
2ND
3
RD
4
TH
5TH
6TH
7TH
8TH
9TH 10TH 11TH
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8
TH
9TH 10TH 11TH
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
80 IRE
R
= 150ꢂ
= ꢁ5V
L
80 IRE
V
R
= 1kꢂ
S
L
V
= ꢁ5V
R
= 1.21kꢂ
S
F
R
= 1.21kꢂ
F
–0.04
–0.04
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH 10TH 11TH
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
9TH 10TH 11TH
TPC 21. Differential Gain/Differential Phase
TPC 24. Differential Gain/Phase, RL = 1 kΩ
–8–
REV. C
AD8004
THEORY OF OPERATION
The more exact relationships that take into account open-loop
gain errors are:
The AD8004 is a member of a new family of high speed current-
feedback (CF) amplifiers offering new levels of bandwidth,
distortion, and signal-swing capability vs. power. Its wide dynamic
range capabilities are due to both a complementary high speed
bipolar process and a new design architecture. The AD8004 is
basically a two stage (Figure 30) rather than the conventional
one stage design. Both stages feature the current-on-demand
property associated with current feedback amplifiers. This
gives an unprecedented ratio of quiescent current to dynamic
performance. The important properties of slew rate and full
power bandwidth benefit from this performance. In addition
the second gain stage buffers the effects of load impedance,
significantly reducing distortion.
G
1− G
AO(s) TO(s)
AV
=
RF
for inverting (G is negative)
1+
+
G
AV =
RF
G
for noninverting (G is positive)
1+
+
AO(s) TO(s)
In these equations the open-loop voltage gain (AO(s)) is common
to both voltage and current-feedback amplifiers and is the ratio
of output voltage to differential input voltage. The open-loop
transimpedance gain (TO(s)) is the ratio of output voltage to
inverting input current and is applicable to current-feedback
amplifiers. The open-loop voltage gain and open-loop transim-
pedance gain (TO(s)) of the AD8004 are plotted vs. frequency
in TPCs 15 and 18. These plots and the basic relationships can
be used to predict the first order performance of the AD8004 over
frequency. At low closed-loop gains the term (RF/TO(s)) dominates
the frequency response characteristics. This gives the result that
bandwidth is constant with gain, a familiar property of current
feedback amplifiers.
A full discussion of this new amplifier architecture is available on
the data sheet for the AD8011. This discussion only covers the
basic principles of operation.
DC AND AC CHARACTERISTICS
As with traditional op amp circuits the dc closed-loop gain is
defined as:
RF
RN
AV = G = 1+
noninverting operation
inverting operation
An RF of 1 k⍀ has been chosen as the nominal value to give
optimum frequency response with acceptable peaking at gains of
+2/–1. As can be seen from the above relationships, at higher
closed-loop gains reducing RF has the effect of increasing closed-
loop bandwidth. Table I gives optimum values for RF and RG
for a variety of gains.
RF
RN
AV = G = −
A1
IPN
IQ1
C
D
IPP
A2
C
1
P
Q3
C 2
P
ICQ + IO
V
Q1
Q2
V
V
N
P
O
´
Z
I
A3
V
O
R
C
L
L
Z2
R
F
IE
R
G
Q4
IQ1
A2
C
C
1
P
IPN
INP
A1
AD8004
D
Figure 5. Simplified Block Diagram
REV. C
–9–
AD8004
DRIVING CAPACITIVE LOADS
region of the summing junction will cause some bandwidth
extension and/or increased peaking. In noninverting gains, the
effect of extra capacitance on summing junctions is far more
pronounced than with inverting gains. Figure 9 shows an example
of this. Note that only 1 pF of added junction capacitance causes
about a 70% bandwidth extension and additional peaking on a
gain = +2. For an inverting gain = –2, 5 pF of additional summing
junction capacitance caused a small 10% bandwidth extension.
The AD8004 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 6. The accompanying graph shows
the optimum value for RSERIES vs. capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off of
RSERIES and CL.
Extra output capacitive loading also causes bandwidth exten-
sions and peaking. The effect is more pronounced with less
resistive loading from the next stage. Figure 10 shows the effect
of direct output capacitive loads for gains of +2 and –2. For both
gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading).
For each of the four traces in Figure 10 the resistive loads were
100 ⍀. Figure 11 also shows capacitive loading effects with a
lighter output resistive load. Note that even though bandwidth
is extended 2¥, the flatness dramatically suffers.
1k⍀
R
SERIES
1k⍀
AD8004
R
1k⍀
L
C
L
Figure 6. Driving Capacitive Load
2
40
30
20
10
R
= 698⍀
F
1
0
G = +1
G = +2
R
= 1.1k⍀
F
R
= 909⍀
F
–1
–2
–3
–4
–5
–6
–7
–8
1
0
R
= 604⍀
F
–1
–2
–3
–4
–5
V
V
R
= 50mV rms
= ؎5V
IN
R
= 1.10k⍀
F
S
= 100⍀
R PACKAGE
L
R
= 845⍀
F
100
1
10
FREQUENCY – MHz
40
500
0
5
10
15
20
25
C
L
– pF
Figure 8. RFEEDBACK vs. Frequency Response, G = +1/+2
Figure 7. Recommended RSERIES vs. Capacitive Load for
£ 30 ns Settling to 0.1%
2
OPTIMIZING FLATNESS
G = +2
G = –2
C
= 1pF
C
J
0
The fine scale gain flatness and –3 dB bandwidth is affected by
RFEEDBACK selection as is normal of current feedback amplifiers.
With the exception of gain = +1, the AD8004 can be adjusted
for either maximal flatness with modest closed-loop bandwidth
or for mildly peaked-up frequency response with much more
bandwidth. Figure 8 shows the effect of three evenly spaced RF
changes upon gain = +1 and gain = +2. Table I shows the
recommended component values for achieving maximally flat
frequency response as well as a faster slightly peaked-up fre-
quency response.
= 0
2
0
–2
J
–4
–6
–2
V
R
= 50mV rms
IN
–4
= 100⍀
–8
L
؎5V
C
= 5.1pF
S
J
–6
–10
–12
–14
–8
C
= 0
J
–10
–12
–14
Printed circuit board parasitics and device lead frame parasitics
also control fine scale gain flatness. The AD8004R package,
because of its small lead frame, offers superior parasitics relative
to the N package. In the printed circuit board environment,
parasitics such as extra capacitance caused by two parallel and
vertical flat conductors on opposite PC board sides in the
1
10
40
100
500
FREQUENCY – MHz
Figure 9. Frequency Response vs. Added Summing
Junction Capacitance
REV. C
–10–
AD8004
2
0
through R2. This current flows toward the summing junction
and requires that the output be 2 V higher than the summing
junction or at 3.6 V.
G = +2, R = 1.10kꢂ
F
C
= 10pF
L
2
0
–2
–4
–6
–8
–10
–12
C
= 0
L
G = –2, R = 698ꢂ
F
When the input is at 1 V, there is 1.2 mA flowing into the sum-
ming junction through R3 and 1.2 mA flowing out through R1.
These currents balance and leave no current to flow through
R2. Thus the output is at the same potential as the inverting
input or 1.6 V.
–2
C
= 10pF
L
–4
V
= 50mV
IN
–6
ꢁ5V
S
R
= 100ꢂ
L
C
= 0
The input of the AD876 has a series MOSFET switch that turns
on and off at the sampling rate. This MOSFET is connected to
a hold capacitor internal to the device. The on impedance of the
MOSFET is about 50 Ω, while the hold capacitor is about 5 pF.
L
–8
–14
–10
–12
–14
In a worst case condition, the input voltage to the AD876 will
change by a full-scale value (2 V) in one sampling cycle. When
the input MOSFET turns on, the output of the op amp will be
connected to the charged hold capacitor through the series
resistance of the MOSFET. Without any other series resistance,
the instantaneous current that flows would be 40 mA. This
would cause settling problems for the op amp.
1
10
40
100
500
FREQUENCY – MHz
Figure 10. Frequency Response vs. Capacitive Loading,
RL = 100 Ω Output
2
C
= 10pF
L
0
–2
The series 100 Ω resistor limits the current that flows instanta-
neously after the MOSFET turns on to about 13 mA. This
resistor cannot be made too large or the high frequency perfor-
mance will be affected.
G = +2
= 1kꢂ
R
L
ꢁ5V
S
–4
V
= 50mV rms
IN
C
= 0
R
= 1.2kꢂ
L
F
–6
The sampling MOSFET of the AD876 is closed for only half of
each cycle or for 25 ns. Approximately seven time constants are
required for settling to 10 bits. The series 100 Ω resistor along
with the 50 Ω on resistance and the hold capacitor, create a
750 ps time constant. These values leave a comfortable margin
for settling. Obtaining the same results with the op amp A/D
combination as compared to driving with a signal generator
indicates that the op amp is settling fast enough.
–8
–10
–12
–14
1
10
40
100
500
FREQUENCY – MHz
Overall the AD8004 provides adequate buffering for the AD876
A/D converter without introducing distortion greater than that
of the A/D converter by itself.
Figure 11. Flatness with 10 pF Capacitive Load
DRIVING A SINGLE-SUPPLY A/D CONVERTER
New CMOS A/D converters are placing greater demands on the
amplifiers that drive them. Higher resolutions, faster conversion
rates, and input switching irregularities require superior settling
characteristics. In addition, these devices run off a single +5 V
supply and consume little power, so good single-supply operation
with low power consumption is very important. The AD8004 is
well positioned for driving this new class of A/D converters.
+5V
R3
R2
1kꢂ
1.65kꢂ
0.1ꢃF
10ꢃF
3.6V
0.1ꢃF
+3.6V
REFT
R1
499kꢂ
V
IN
1V
0V
100ꢂ
1/4
AD8004
50ꢂ
Figure 12 shows a circuit that uses an AD8004 to drive an
AD876, a single supply, 10-bit, 20 MSPS A/D converter that
requires only 140 mW. Using the AD8004 for level shifting and
driving, the A/D exhibits no degradation in performance com-
pared to when it is driven from a signal generator.
AD876
3.6V
1.6V
REFB
+1.6V
0.1ꢃF
1.6V
Figure 12. AD8004 Driving the AD876
The analog input of the AD876 spans 2 V centered at about
2.6 V. The resistor network and bias voltages provide the level
shifting and gain required to convert the 0 V to 1 V input signal
to a 3.6 V to 1.6 V range that the AD876 wants to see.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8004 requires
careful attention to board layout and component selection.
Table I shows the recommended component values for the
AD8004 and Figures 14–16 show the layout for the AD8004
evaluation boards (14-lead DIP and SOIC). Proper RF design
techniques and low parasitic component selection are mandatory.
Biasing the noninverting input of the AD8004 at 1.6 V dc forces
the inverting input to be at 1.6 V dc for linear operation of the
amplifier. When the input is at 0 V, there is 3.2 mA flowing out
of the summing junction via R1 (1.6 V/499 Ω). R3 has a current
of 1.2 mA flowing into the summing junction (3.6 V – 1.6 V)/
1.65 kΩ. The difference of these two currents (2 mA) must flow
REV. C
–11–
AD8004
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
R
R
R
, 50ꢂ
F
G
BT
V
V
OUT
IN
R
T
1/4
+V
S
C1
C3
Chip capacitors should be used for supply bypassing (see
Figure 13). One end should be connected to the ground plane and
the other within 1/8" of each power pin. An additional (4.7 µF to
10 µF) tantalum electrolytic capacitor should be connected in
parallel.
0.1ꢃF
10ꢃF
C4
10ꢃF
C2
0.1ꢃF
–V
S
INVERTING CONFIGURATION
R
F
R
R
BT
, 50ꢂ
G
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on the plot of Figure 10.
V
OUT
1/4
V
+V
IN
S
C1
C3
R
T
0.1ꢃF
10ꢃF
C2
0.1ꢃF
C4
10ꢃF
–V
S
Stripline design techniques should be used for long signal traces
(greater than about 1"). These should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
NONINVERTING CONFIGURATION
Figure 13. Inverting and Noninverting Configurations
Table I. Recommended Component Values1 and Typical Bandwidths
Alternate
–2
Alternate
–1
Alternate
+1
Alternate
+2
Gain
–10
–2
–1
+1
+2
+10
AD8004 (DIP)
PACKAGE TYPE
RF (Ω)
RG (Ω)
RT2 (Ω)
499
49.9
None
698
348
57.6
499
249
61.9
649
649
53.6
499
499
54.9
1.21 k
50
806
50
1.10 k
1.10 k
50
698
698
50
499
54.9
50
Small Signal BW
@
5 VS (MHz)
155
125
180
135
190
150
250
115
185
135
Peaking @ 5 VS
0.1 dB Flatness
< 0.3 dB
None
0.3 dB
None
0.3 dB
1.3 dB
1.7 dB
< 0.14 dB
0.4 dB
< 0.3 dB
@
5 VS (MHz)
25
30
35
95
Small Signal BW
@ +5 VS (MHz)
135
105
155
120
160
130
200
150
120
AD8004 (SOIC)
PACKAGE TYPE
RF (Ω)
RG (Ω)
RT2 (Ω)
499
49.9
None
698
348
57.6
499
249
61.9
750
750
53.6
499
499
54.9
1.10 k
50
698
50
1.10 k
1.10 k
50
604
604
50
499
54.9
50
Small Signal BW
@
5 VS (MHz)
155
130
190
125
195
150
225
110
175
135
Peaking @ 5 VS
0.1 dB Flatness
< 0.7 dB
< 0.1 dB
0.5 dB
None
0.4 dB
1.3 dB
1.8 dB
< 0.1 dB
0.5 dB
< 0.2 dB
@
5 VS (MHz)
35
25
30
95
Small Signal BW
@ +5 VS (MHz)
135
115
175
110
165
130
195
155
120
NOTES
1Resistor values listed are standard 1% tolerance.
2RT chosen for 50 Ω characteristic input impedance.
–12–
REV. C
AD8004
Figure 14. Evaluation Board Silkscreen (Top)
REV. C
–13–
AD8004
Figure 15 Evaluation Board Layout (Top Side)
Figure 16. Evaluation Board Layout (Bottom Side, Looking Through the Board)
–14–
REV. C
AD8004
OUTLINE DIMENSIONS
14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
14-Lead Standard Small Outline Package [SOIC]
(R-14)
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.685 (17.40)
0.665 (16.89)
0.645 (16.38)
8.75 (0.3445)
8.55 (0.3366)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
14
1
8
7
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
0.100 (2.54)
BSC
1.75 (0.0689)
1.35 (0.0531)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
ꢄ 45ꢀ
0.25 (0.0098)
0.10 (0.0039)
0.015 (0.38)
MIN
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
8ꢀ
0ꢀ
0.180 (4.57)
MAX
0.51 (0.0201)
0.33 (0.0130)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.19 (0.0075)
COPLANARITY
0.10
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-012AB
0.022 (0.56) 0.060 (1.52)
0.018 (0.46) 0.050 (1.27)
0.014 (0.36) 0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
0.098 (2.49) MAX
0.005 (0.13) MIN
14
8
0.310 (7.87)
PIN 1
0.220 (5.59)
1
7
0.320 (8.13)
0.290 (7.37)
0.100 (2.54) BSC
0.785 (19.94) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
15
0
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
–15–
AD8004
Revision History
Location
Page
3/03—Data Sheet changed from REV. B to REV. C.
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added CERDIP (Q) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Added text to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edited MAXIMUM POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edited Y axis of TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edited OPTIMIZING FLATNESS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REV. C
–16–
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