AD8007AKS-RL7 [ADI]
IC OP-AMP, 4000 uV OFFSET-MAX, PDSO5, SC-70, 5 PIN, Operational Amplifier;
| 型号： | AD8007AKS-RL7 |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 4000 uV OFFSET-MAX, PDSO5, SC-70, 5 PIN, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总21页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion,
High Speed Amplifiers
AD8007/AD8008
FEATURES
CONNECTION DIAGRAMS
Extremely low distortion
Second harmonic
AD8007
1
2
3
4
8
7
6
5
NC
–IN
+IN
(Top View)
NC
+V
S
−88 dBc @ 5 MHz
V
−83 dBc @ 20 MHz (AD8007)
−77 dBc @ 20 MHz (AD8008)
Third harmonic
OUT
–V
S
NC
−101 dBc @ 5 MHz
NC = NO CONNECT
−92 dBc @ 20 MHz (AD8007)
−98 dBc @ 20 MHz (AD8008)
High speed
650 MHz, −3 dB bandwidth (G = +1)
1000 V/μs slew rate
Figure 1. 8-Lead SOIC (R)
AD8007
V
5
+V
S
OUT
1
2
3
(Top View)
–V
S
Low noise
4
+IN
–IN
2.7 nV/√Hz input voltage noise
22.5 pA/√Hz input inverting current noise
Low power: 9 mA/amplifier typical supply current
Wide supply voltage range: 5 V to 12 V
0.5 mV typical input offset voltage
Small packaging: 8-lead SOIC, 8-lead MSOP, and 5-lead SC70
Figure 2. 5-Lead SC70 (KS)
AD8008
(Top View)
V
1
2
3
4
8
7
6
5
+V
V
OUT1
–IN1
S
OUT2
–IN2
+IN2
+IN1
APPLICATIONS
–V
S
Instrumentation
IF and baseband amplifiers
Filters
Figure 3. 8-Lead SOIC (R) and 8-Lead MSOP (RM)
A/D drivers
DAC buffers
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both an
8-lead SOIC and an 8-lead MSOP. These amplifiers are rated to
work over the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
The AD8007 (single) and AD8008 (dual) are high performance
current feedback amplifiers with ultralow distortion and noise.
Unlike other high performance amplifiers, the low price and
low quiescent current allow these amplifiers to be used in a
wide range of applications. Analog Devices, Inc., proprietary
second-generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low power
consumption.
–30
G = +2
R
= 150Ω
= ±5V
= 2V p-p
L
S
–40
–50
V
V
OUT
–60
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/√Hz
voltage noise, −83 dB SFDR at 20 MHz (AD8007), and −77 dBc
SFDR at 20 MHz (AD8008).
–70
SECOND
–80
–90
With the wide supply voltage range (5 V to 12 V) and wide
bandwidth, the AD8007/AD8008 are designed to work in a
variety of applications. The AD8007/AD8008 amplifiers have
a low power supply current of 9 mA/amplifier.
THIRD
–100
–110
1
10
FREQUENCY (MHz)
100
Figure 4. AD8007 Second and Third Harmonic Distortion vs. Frequency
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD8007_8008*
Last content update 08/18/2013 06:08 pm
PARAMETRIC SELECTION TABLES
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
Analog Filter Wizard 2.0
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
AD8007/AD8008 SPICE Macro-Model
DOCUMENTATION
DESIGN COLLABORATION COMMUNITY
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
Collaborate Online with the ADI support team and other designers
about select ADI products.
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MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
A Stress-Free Method for Choosing High-Speed Op Amps
Current Feedback Amplifiers Part 1: Ask The Applications Engineer-22
Current Feedback Amplifiers Part 2: Ask The Applications Engineer-23
Two-Stage Current-Feedback Amplifier
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
FOR THE AD8007
AN-358: Noise and Operational Amplifier Circuits
Telephone our Customer Interaction Centers toll free:
AN-356: User's Guide to Applying and Measuring Operational
Americas:
Europe:
China:
1-800-262-5643
00800-266-822-82
4006-100-006
Amplifier Specifications
AN-257: Careful Design Tames High Speed Op Amps
AN-253: Find Op Amp Noise with Spreadsheet
India:
Russia:
1800-419-0108
8-800-555-45-90
UG-112: Universal Evaluation Board for Single, High Speed Op Amps
Offered in SC-70 Packages
Quality and Reliability
Lead(Pb)-Free Data
UG-101: Evaluation Board User Guide
FOR THE AD8008
UG-129: Evaluation Board User Guide
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
SAMPLE & BUY
AD8007
AD8008
View Price & Packaging
Request Evaluation Board
Request Samples Check Inventory & Purchase
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the AD8007
Find Local Distributors
View the Evaluation Boards and Kits page for the AD8008
Symbols and Footprints for the AD8007
Symbols and Footprints for the AD8008
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD8007/AD8008
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 15
Using the AD8007/AD8008...................................................... 15
Layout Considerations............................................................... 16
Layout And Grounding Considerations...................................... 17
Grounding................................................................................... 17
Input Capacitance ...................................................................... 17
Output Capacitance ................................................................... 17
Input-to-Output Coupling........................................................ 17
External Components and Stability......................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
VS = 5 V....................................................................................... 3
VS = 5 V.......................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ......................................................... 6
Output Short Circuit ........................................................................ 6
ESD Caution.................................................................................. 6
REVISION HISTORY
11/09—Rev. D to Rev. E
9/02—Rev. A to Rev. B
Change to Output Capacitance Section....................................... 17
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
Updated Outline Dimensions....................................................... 19
8/02—Rev. 0 to Rev. A
Added AD8008 ..................................................................Universal
Added SOIC-8 (RN) and MSOP-8 (RM) ......................................1
Changes to Features ..........................................................................1
Changes to General Description ....................................................1
Changes to Specifications ................................................................2
Edits to Maximum Power Dissipation Section .............................4
New Figure 2 .....................................................................................4
Changes to Ordering Guide ............................................................5
New TPCs 19 to 24 and TPCs 27, 29, 30, and 35..........................9
Changes to Evaluation Board Section ......................................... 16
MSOP-8 (RM) Added ................................................................... 19
6/03—Rev. C to Rev. D
Change to Layout Considerations Section.................................. 15
Deleted Figure 7.............................................................................. 16
Deleted Evaluation Board Section................................................ 16
Updated Outline Dimensions....................................................... 16
10/02—Rev. B to Rev. C
Connection Diagrams Captions Updated .................................... 1
Ordering Guide Updated ................................................................ 5
Figure 5 Edited ............................................................................... 14
Updated Outline Dimensions....................................................... 19
Rev. E | Page 2 of 20
AD8007/AD8008
SPECIFICATIONS
VS = 5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 1.
AD8007/AD8008
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 2 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V input step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V step
540
250
180
200
50
650
500
230
235
90
30
1000
18
MHz
MHz
MHz
MHz
MHz
ns
V/μs
ns
ns
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
900
G = +2, VO = 2 V step
G = +2, VO = 2 V step
35
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ, VO = 2 V p-p
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
−Input, f = 100 kHz
+Input, f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−88
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dB
−83/−77
−101
−92/−98
−77
43.0/42.5
42.5
−68
2.7
22.5
2
Third Harmonic
IMD
Third-Order Intercept
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
nV/√Hz
pA/√Hz
pA/√Hz
%
Differential Gain Error
Differential Phase Error
0.015
0.010
Degree
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
0.5
3
4
0.4
16
9
1.5
0.8
4
mV
μV/°C
μA
+Input
−Input
+Input
−Input
VO = 2.5 V, RL = 1 kΩ
RL = 150 Ω
8
6
μA
Input Bias Current Drift
Transimpedance
nA/°C
nA/°C
MΩ
1.0
0.4
MΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short-Circuit Current, Source
Short-Circuit Current, Sink
Capacitive Load Drive
+Input
+Input
4
1
MΩ
pF
V
−3.9 to +3.9
59
VCM = 2.5 V
56
dB
VCC − VOH, VOL − VEE, RL = 1 kΩ
1.1
130
90
8
1.2
V
mA
mA
pF
30% overshoot
Rev. E | Page 3 of 20
AD8007/AD8008
AD8007/AD8008
Typ
Parameter
Conditions
Min
Max Unit
12
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
5
V
9
10.2 mA
59
59
64
65
dB
dB
−PSRR
VS = 5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 2.
AD8007/AD8008
Unit
Parameter
Conditions
Min Typ
Max
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 1 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V input step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V step
520 580
350 490
190 260
270 320
MHz
MHz
MHz
MHz
MHz
ns
V/μs
ns
ns
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
72
120
30
665 740
G = +2, VO = 2 V step
G = +2, VO = 2 V step
18
35
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 1 V p-p
−96/−95
−83/−80
−100
−85/−88
−89/−87
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Third-Order Intercept
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
Output-to-output, f = 5 MHz, G = +2
f = 100 kHz
−Input, f = 100 kHz
+Input, f = 100 kHz
43.0
42.5/41.5
−68
2.7
22.5
2
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
0.5
3
4
0.7
15
8
1.3
0.6
4
mV
μV/°C
μA
+Input
−Input
+Input
−Input
VO = 1.5 V to 3.5 V, RL = 1 kΩ
RL = 150 Ω
8
6
μA
Input Bias Current Drift
Transimpedance
nA/°C
nA/°C
MΩ
0.5
0.4
MΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
+Input
+Input
4
1
MΩ
pF
V
1.1 to 3.9
56
VCM = 1.75 V to 3.25 V
54
dB
Rev. E | Page 4 of 20
AD8007/AD8008
AD8007/AD8008
Unit
Parameter
Conditions
Min Typ
Max
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short-Circuit Current, Source
Short-Circuit Current, Sink
Capacitive Load Drive
POWER SUPPLY
VCC − VOH, VOL − VEE, RL = 1 kΩ
1.05
70
50
8
1.15
V
mA
mA
pF
30% overshoot
Operating Range
5
12
9
V
mA
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
8.1
59
59
62
63
dB
dB
−PSRR
Rev. E | Page 5 of 20
AD8007/AD8008
ABSOLUTE MAXIMUM RATINGS
Table 3.
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, then the total drive power is
Parameter
Rating
VS × IOUT
.
Supply Voltage
12.6 V
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply
Power Dissipation
See Figure 5
VS
Common-Mode Input Voltage
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
2
1.0 V
V
4
⎛
⎜
⎞
⎟
S
See Figure 5
−65°C to +125°C
−40°C to +85°C
300°C
⎝
⎠
PD =(VS × IS ) +
RL
In single-supply operation, with RL referenced to VS, worst case is
VOUT = VS/2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes
reduces the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps, see the
Layout Considerations section.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8 (125°C/W),
MSOP-8 (150°C/W), and SC70-5 (210°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
2.0
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8007/AD8008.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
1.5
MSOP-8
SOIC-8
1.0
SC70-5
0.5
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
0
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
TJ = TA + (PD × θJA)
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL ) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
RL
VS VOUT
PD = (VS × IS ) +
×
−
2
RL
Rev. E | Page 6 of 20
AD8007/AD8008
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
3
2
6.4
6.3
G = +2
G = +1
1
0
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
G = +2
–1
–2
–3
–4
–5
–6
–7
V
= +5V
S
V
= ±5V
S
G = +10
G = –1
5.4
1
10
100
1000
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Gains
Figure 9. 0.1 dB Gain Flatness; VS = +5, VS = 5 V
3
9
8
G = +1
2
G = +2
1
7
6
R
= 1kΩ, V = ±5V
S
L
R
= 1kΩ, V = +5V
S
L
0
–1
–2
–3
–4
–5
–6
–7
5
R
V
= 150kΩ,
= +5V
L
S
R
= 150kΩ, V = ±5V
S
L
4
3
R
= 150kΩ, V = ±5V
S
L
2
R
= 150kΩ, V = 5V
R
= 1kΩ, V = ±5V
L
S
1
L
S
0
–1
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for VS and RL
Figure 10. Small Signal Frequency Response for VS and RL
3
2
9
8
G = +2
G = +1
R
= R = 324Ω
G
F
R
= 1kΩ
L
1
0
7
R
= 200Ω
S
R = R = 249Ω
F G
6
5
4
–1
–2
–3
–4
–5
–6
R
= 301Ω
S
R
= R = 499Ω
F
G
3
R
= 249Ω
S
2
1
R
= R = 649Ω
F
G
0
–7
–1
10
100
FREQUENCY (MHz)
1000
10
100
1000
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various RS Values
Figure 11. Small Signal Frequency Response for Various Feedback Resistors,
RF = RG
Rev. E | Page 7 of 20
AD8007/AD8008
10M
1M
10
90
G = +2
9
20pF
20pF AND
10Ω SNUB
30
0
20pF AND
20Ω SNUB
TRANSIMPEDANCE
8
7
6
5
100k
10k
1k
–30
PHASE
–90
–150
–180
499Ω
4
0pF
499Ω
R
3
SNUB
–210
100
200Ω
2
C
LOAD
–270
–330
49.9Ω
10
1
1
0
1M
1
10
100
1000
10k
100k
10M
100M
1G 2G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 12. Small Signal Frequency Response for
Capacitive Load and Snub Resistor
Figure 15. Transimpedance and Phase vs. Frequency
3
9
8
V
V
= +5V, +85°C
S
S
G = +1
G = +2
2
1
= ±5V, +85°C
7
6
V
= +5V, +85°C
S
0
V
= ±5V, +85°C
S
–1
5
V
= +5V, –40°C
S
V
= +5V, –40°C
S
–2
4
V
= ±5V, –40°C
S
–3
–4
–5
3
V
= ±5V, –40°C
S
2
1
–6
–7
0
–1
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 13. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = 5 V
Figure 16. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = 5 V
3
9
V
= 2V p-p
G = +2
OUT
2
1
8
7
6
5
4
G = +2
G = +1
0
–1
–2
–3
–4
–5
–6
–7
G = +10
G = –1
R
= 150Ω, V = ±5V, V = 2V p-p
S O
L
3
2
R
= 1kΩ, V = ±5V, V = 2V p-p
S O
L
R
= 150Ω, V = +5V, V = 1V p-p
S O
L
1
R
= 1kΩ,V = +5V, V = 1V p-p
L
S
O
0
–1
1
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Large Signal Frequency Response for Various Gains
Figure 17. Large Signal Frequency Response for VS and RL
Rev. E | Page 8 of 20
AD8007/AD8008
–40
–50
–60
–70
–80
–90
–100
–40
–50
G = +2
G = +1
V
V
= 5V
= 1V p-p
S
V
V
= 5V
= 1V p-p
S
HD2, R = 150Ω
L
O
O
HD3, R = 150Ω
L
HD2, R = 1kΩ
–60
L
HD2, R = 1kΩ
L
–70
–80
HD2, R = 150Ω
L
HD3, R = 1kΩ
L
–90
HD3, R = 150Ω
L
–100
–110
HD3, R = 1kΩ
L
–110
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 21. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
Figure 18. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
–40
–40
G = +2
G = +1
V
V
= ±5V
= 2V p-p
S
V
V
= ±5V
= 2V p-p
S
–50
–60
–50
–60
O
O
HD2, R = 1kΩ
L
HD2, R = 150Ω
–70
L
–70
HD2, R = 150Ω
L
–80
HD2, R = 1kΩ
–80
L
HD3, R = 150Ω
L
–90
HD3, R = 150Ω
–90
L
HD3, R = 1kΩ
–100
L
–100
HD3, R = 1kΩ
L
–110
–110
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 22. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
Figure 19. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
–30
–30
G = +2
V
V
R
= ±5V
= 2V p-p
= 150Ω
S
V
= ±5V
S
O
–40
–50
–40
–50
–60
–70
R
= 150Ω
L
L
HD3, V = 4V p-p
O
HD2, G = +10
HD2, V = 4V p-p
O
–60
–70
–80
HD3, G = +10
HD2, V = 2V p-p
O
–80
HD3, G = +1
HD2, G = +1
–90
–100
–110
–90
–100
–110
HD3, V = 2V p-p
O
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 20. AD8007 Second and Third Harmonic Distortion vs. Frequency and Gain
Figure 23. AD8007 Second and Third Harmonic Distortion vs. Frequency and VO
Rev. E | Page 9 of 20
AD8007/AD8008
VS = 5 V, RS = 200 Ω, RF = 499 Ω, RL = 150 Ω, @ 25°C, unless otherwise noted.
–40
–40
–50
G = 1
G = 2
V
V
= 5V
= 1V p-p
V
V
= 5V
= 1V p-p
S
S
–50
–60
O
O
–60
–70
HD2, R = 150Ω
HD2, R = 150Ω
L
L
–70
HD2, R = 1kΩ
HD2, R = 1kΩ
L
L
–80
–80
–90
–90
HD3, R = 1kΩ
HD3, R = 1kΩ
L
L
–100
–110
–100
–110
HD3, R = 150Ω
HD3, R = 150Ω
L
L
1
1
10
100
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
Figure 24. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
–40
–40
G = 2
G = 1
V
V
= ±5V
= 2V p-p
S
V
V
S
= 5V
= 1V p-p
–50
–60
–50
–60
O
O
HD2, R = 1kΩ
L
–70
–70
HD2, R = 150Ω
HD2, R = 150Ω
L
L
–80
–80
HD2, R = 1kΩ
L
–90
–90
HD3, R = 1kΩ
L
–100
–110
–100
–110
HD3, R = 1kΩ
HD3, R = 150Ω
L
L
HD3, R = 150Ω
L
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 28. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
Figure 25. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
–30
–30
G = 2
V
V
R
= ±5V
= 2V p-p
= 150Ω
S
R
V
= 150Ω
= ±5V
L
O
–40
–50
–40
–50
–60
–70
–80
–90
–100
S
L
HD2, G = 10
–60
HD2, V = 4V p-p
O
–70
HD2, V = 2V p-p
O
–80
HD2, G = 1
–90
HD3, V = 4V p-p
O
–100
–110
HD3, G = 10
HD3, V = 2V p-p
O
HD3, G = 1
–110
1
1
10
100
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 26. AD8008 Second and Third Harmonic Distortion vs. Frequency and Gain
Figure 29. AD8008 Second and Third Harmonic Distortion vs. Frequency and VO
Rev. E | Page 10 of 20
AD8007/AD8008
–60
–65
–70
–75
–80
G = +2
G = +2
HD3, R = 1kΩ
HD3, R = 1kΩ
L
V
F
= 5V
= 20MHz
L
V
F
= ±5V
= 20MHz
S
S
O
O
–65
–70
–75
HD2, R = 1kΩ
HD2, R = 150Ω
L
L
–85
–90
HD3, R = 150Ω
L
HD2, R = 1kΩ
L
HD3, R = 150Ω
–80
–85
–90
L
–95
–100
–105
–110
HD2, R = 150Ω
L
1.0
1.5
2.0
2.5
1
2
3
4
5
6
V
(V p-p)
V
(V p-p)
OUT
OUT
Figure 30. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
Figure 33. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
44
44
G = +2
G = +2
V
V
R
= ±5V
= 2V p-p
= 1kΩ
V
V
R
= ±5V
= 2V p-p
= 1kΩ
S
S
43
42
41
40
39
43
42
O
O
L
L
41
40
39
38
38
37
37
36
35
36
35
5
10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (MHz)
5
10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (MHz)
Figure 31. AD8007 Third-Order Intercept vs. Frequency
Figure 34. AD8008 Third-Order Intercept vs. Frequency
–65
–70
–75
–80
–85
–90
–65
–70
G = +2
HD2, R = 1kΩ
L
V
F
= 5V
= 20MHz
S
HD2, R = 150Ω
O
L
HD2, R = 150Ω
L
–75
HD2, R = 1kΩ
L
–80
–85
HD3, R = 150Ω
L
HD3, R = 1kΩ
L
–90
HD3, R = 150Ω
L
–95
HD3, R = 1kΩ
L
–100
–105
G = +2
V
= 5V
S
F
= 20MHz
O
–110
1.0
1.5
2.0
2.5
1
2
3
4
5
6
V
(V p-p)
OUT
V
(V p-p)
OUT
Figure 32. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
Figure 35. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
Rev. E | Page 11 of 20
AD8007/AD8008
VS = 5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
100
1000
100
10
INVERTING CURRENT NOISE 22.5pA/ Hz
10
2.7nV/ Hz
NONINVERTING CURRENT NOISE 2.0pA/ Hz
100 1k 10k 100k
FREQUENCY (Hz)
1
1
10
100
1k
10k
100k
1M
1G
1G
10
1M
10M
FREQUENCY (Hz)
Figure 36. Input Voltage Noise vs. Frequency
Figure 39. Input Current Noise vs. Frequency
–20
–30
–40
–50
–60
–70
–80
–90
–100
1k
G = +2
R = 150Ω
G = +2
V
V
= ±5V
= 1V p-p
S
100
10
M
SIDE B DRIVEN
1
SIDE A DRIVEN
0.1
0.01
100k
1M
10M
100M
100k
10M
100M
1G
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Output Impedance vs. Frequency
Figure 40. AD8008 Crosstalk vs. Frequency (Output to Output)
0
–10
–20
–30
–40
–50
–60
–70
20
10
V
= ±5V, +5V
S
0
–10
–20
–30
+PSRR
–40
–50
–60
–70
–80
–PSRR
100k
1M
10M
100M
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. CMRR vs. Frequency
Figure 41. PSRR vs. Frequency
Rev. E | Page 12 of 20
AD8007/AD8008
G = +2
R
R
= 150Ω, V = +5V AND ±5V
S
G = +1
L
R
= 150Ω, V = +5V AND ±5V
S
L
= 150Ω, V = +5V AND ±5V
R = 1kΩ, V = +5V AND ±5V
L S
L
S
50mV/DIV
50mV/DIV
20
0
10
20
30
TIME (ns)
40
50
30
TIME (ns)
40
50
0
10
Figure 45. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = 5 V
Figure 42. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = 5 V
G = –1
G = +1
R
= 150Ω
L
INPUT
R
= 1kΩ
L
OUTPUT
1V/DIV
10
1V/DIV
0
20
30
40
50
0
10
20
TIME (ns)
30
40
50
TIME (ns)
Figure 46. Large Signal Transient Response, G = −1, RL = 150 Ω
Figure 43. Large Signal Transient Response for RL = 150 Ω, RL = 1 kΩ
G = +2
G = +2
C
= 0pF
C
C
C
= 0pF
L
LOAD
LOAD
LOAD
C
= 20pF
L
C
= 20pF
= 10pF
= 20pF
L
R
= 10Ω
SNUB
499Ω
499Ω
200Ω
RSNUB
CLOAD
–
+
49.9Ω
50mV/DIV
10
1V/DIV
10
0
20
30
TIME (ns)
40
50
0
20
30
40
50
TIME (ns)
Figure 44. Large Signal Transient Response for
CLOAD = 0 pF, CLOAD = 10 pF, and CLOAD = 20 pF
Figure 47. Small Signal Transient Response, Effect of Series Snub Resistor
when Driving Capacitive Load
Rev. E | Page 13 of 20
AD8007/AD8008
4
3
G = +2
G = +10
V
V
= ±5V
+V
S
S
= ±0.75V
IN
R
= 1kΩ
L
2
R
= 150Ω
1
L
0
–1
–2
OUTPUT (2V/DIV)
INPUT (1V/DIV)
–V
S
–3
–4
0
100
200
TIME (ns)
300
400
500
0
200
400
600
800
1000
Figure 48. Output Overdrive Recovery, RL = 1 kΩ, 150 Ω, VIN
=
2.5 V
R
(Ω)
L
Figure 50. VOUT Swing vs. RL, VS = 5 V, G = +10, VIN
= 0.75 V
0.5
G = +2
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
18ns
0
5
10
15
20
25
30
35
40
45
TIME (ns)
Figure 49. 0.1% Settling Time, 2 V Step
Rev. E | Page 14 of 20
AD8007/AD8008
THEORY OF OPERATION
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 51. It
closely resembles a classic current feedback amplifier comprised
of a complementary emitter-follower input stage, a pair of signal
mirrors, and a diamond output stage. However, in the case of
the AD8007/AD8008, several modifications were made to improve
the distortion performance over that of a classic current feedback
topology.
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically separate
(and possibly distant) grounds can lead to degraded even-order
harmonic performance. This situation is shown in Figure 52 using
the AD8007 as an example; however, it is not recommended. For a
sinusoidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
+V
S
M1
R
F
–
I
499Ω
3
I
–
1
GND 1
C 1
Q5
J
10µF
0.1µF
+V
+V
S
Q1
IN–
Q3
+
D1
D2
S
R
499Ω
I
G
HIGH-Z
DO
IN+
I
DI
OUT
R
200Ω
S
OUT
AD8007
Q2
Q4
–V
S
IN
C 2
Q6
J
–V
S
I
–
2
10µF
0.1µF
–
I
4
+
M2
–V
S
GND 2
R
F
Figure 52. High Frequency Capacitors Returned to Physically Separate
Grounds (Not Recommended)
R
G
The decoupling scheme shown in Figure 53 is recommended.
In Figure 53, the two high frequency decoupling capacitors are
first tied together at a common node and are then returned to
the ground plane through a single connection. By first adding
the two currents flowing through each high frequency decoupling
capacitor, this ensures that the current returned into the ground
plane is only at the fundamental frequency.
Figure 51. Simplified Schematic of AD8007
The signal mirrors were replaced with low distortion, high
precision mirrors. In Figure 51, they are shown as M1 and M2.
Their primary function from a distortion standpoint is to reduce
the effect of highly nonlinear distortion caused by capacitances,
CJ1 and CJ2. These capacitors represent the collector-to-base
capacitances of the output devices of the mirrors.
R
F
499Ω
A voltage imbalance arises across the output stage, as measured
from the high impedance node, high-Z, to the output node, OUT.
This imbalance is a result of delivering high output currents and
is the primary cause of output distortion. Circuitry is included
to sense this output voltage imbalance and generate a compensating
current, IDO. When injected into the circuit, IDO reduces the
distortion that could be generated at the output stage. Similarly, the
nonlinear voltage imbalance across the input stage (measured from
the noninverting to the inverting input) is sensed, and a current,
IDI, is injected to compensate for input-generated distortion.
10µF
+
+V
S
R
499Ω
G
0.1µF
R
S
OUT
AD8007
200Ω
IN
0.1µF
–V
S
10µF
+
The design and layout are strictly top-to-bottom symmetric to
minimize the presence of even-order harmonics.
Figure 53. High Frequency Capacitors Returned to Ground at a Single Point
(Recommended)
Rev. E | Page 15 of 20
AD8007/AD8008
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 53, the user can connect one of the
high frequency decoupling capacitors directly across the supplies
and connect the other high frequency decoupling capacitor to
ground (see Figure 54).
LAYOUT CONSIDERATIONS
The standard noninverting configuration with recommended
power supply bypassing is shown in Figure 54. The 0.1 μF high
frequency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +VS pin to the −VS pin.
Connect C1 from the +VS pin to signal ground.
R
F
499Ω
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads works against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical.
10µF
+
+V
S
C1
0.1µF
R
499Ω
G
R
S
OUT
AD8007
C2
200Ω
IN
0.1µF
–V
S
10µF
+
Figure 54. High Frequency Capacitors Connected Across the Supplies
(Recommended)
Rev. E | Page 16 of 20
AD8007/AD8008
LAYOUT AND GROUNDING CONSIDERATIONS
GROUNDING
EXTERNAL COMPONENTS AND STABILITY
The AD8007/AD8008 are current feedback amplifiers and, to a
first order, the feedback resistor determines the bandwidth and
stability. The gain, load impedance, supply voltage, and input
impedances also have an effect.
A ground plane layer is important in densely packed printed
circuit boards (PCB) to minimize parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high frequency impedance of
the path. High speed currents in an inductive ground return
create unwanted voltage noise. Broad ground plane areas reduce
parasitic inductance.
Figure 11 shows the effect of changing RF on the bandwidth and
peaking for a gain of 2. Increasing RF reduces peaking but also
reduces bandwidth. Figure 6 shows that for a given RF increasing
the gain also reduces peaking and bandwidth. Table 4 shows the
recommended RF and RG values that optimize bandwidth with
minimal peaking.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifier, which
causes peaking of the frequency response or even oscillations if
severe enough. Place the external passive components that are
connected to the input pins as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a distance of at least 0.05 mm from the input pins on
all layers of the board.
Table 4. Recommended Component Values
Gain
RF (Ω)
RG (Ω)
RS (Ω)
200
200
200
200
−1
499
499
+1
499
Not applicable
+2
+5
+10
499
499
499
499
124
54.9
200
The load resistor also affects bandwidth, as shown in Figure 7 and
Figure 10. A comparison between Figure 7 and Figure 10 also
demonstrates the effect of gain and supply voltage.
OUTPUT CAPACITANCE
When driving loads with a capacitive component, stability
improves by using a series snub resistor, RSNUB, at the output.
The frequency and pulse responses for various capacitive
loads are illustrated in Figure 12 and Figure 47, respectively.
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. The following two methods
minimize its effect:
•
Put a small value resistor in series with the output to isolate
the load capacitance from the output stage of the amplifier
(see Figure 12).
Increase the phase margin by increasing the gain of the
amplifier or by increasing the value of the feedback resistor.
For noninverting configurations, a resistor in series with the
input, RS, is needed to optimize stability for a gain of 1, as
illustrated in Figure 8. For larger noninverting gains, the effect
of a series resistor is reduced.
•
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling, the input and output signal
traces should not be parallel. When they are not parallel, they
help reduce unwanted positive feedback.
Rev. E | Page 17 of 20
AD8007/AD8008
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. E | Page 18 of 20
AD8007/AD8008
2.20
2.00
1.80
2.40
2.10
1.80
5
1
4
3
1.35
1.25
1.15
2
0.65 BSC
1.10
1.00
0.90
0.70
0.40
0.10
0.80
0.46
0.36
0.26
0.22
0.08
SEATING
PLANE
0.10 MAX
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 57. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
5-Lead SC70
5-Lead SC70
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Package Outline
Branding
HTA
HTC
HTC
HTC
AD8007AKS-R2
AD8007AKSZ-R21
AD8007AKSZ-REEL1
AD8007AKSZ-REEL71
AD8007AR
AD8007AR-REEL
AD8007AR-REEL7
AD8007ARZ1
AD8007ARZ-REEL1
AD8007ARZ-REEL71
AD8008AR
AD8008AR-REEL7
AD8008AR-REEL
AD8008ARZ1
AD8008ARZ-REEL71
AD8008ARZ-REEL1
AD8008ARM
AD8008ARM-REEL
AD8008ARM-REEL7
AD8008ARMZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
KS-5
KS-5
KS-5
KS-5
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
H2B
H2B
H2B
H2B#
H2B#
H2B#
AD8008ARMZ-REEL1
AD8008ARMZ-REEL71
1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
Rev. E | Page 19 of 20
AD8007/AD8008
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02866-0-11/09(E)
Rev. E | Page 20 of 20
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