AD8017 [ADI]
Dual High Output Current, High Speed Amplifier; 双路高输出电流，高速放大器
| 型号： | AD8017 |
| 厂家： | 
ADI |
| 描述： | Dual High Output Current, High Speed Amplifier |
| 文件： | 总16页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual High Output Current,
High Speed Amplifier
a
AD8017
PIN CONFIGURATION
FEATURES
8-Lead Thermal Coastline SOIC (SO-8)
High Output Drive Capability
20 V p-p Differential Output Voltage, RL = 50 ⍀
10 V p-p Single-Ended Output Voltage While
Delivering 200 mA to a 25 ⍀ Load
Low Power Operation
AD8017
1
2
3
4
8
7
6
5
+V
OUT1
–IN1
+IN1
S
OUT2
–IN2
+IN2
–
+
–
+
+5 V to +12 V Voltage Supply @ 7 mA/Amplifier
Low Distortion
–V
S
–78 dBc @ 500 kHz SFDR, RL = 100 ⍀, VO = 2 V p-p
–58 dBc Highest Harmonic @ 1 MHz, IO = 270 mA
(RL = 10 ⍀)
High Speed
160 MHz, –3 dB Bandwidth (G = +2)
1600 V/s Slew Rate
12
10
8
V
S
= ؎6V
APPLICATIONS
xDSL PCI Cards
Consumer DSL Modems
Line Driver
6
Video Distribution
4
V
= ؎2.5V
S
2
PRODUCT DESCRIPTION
The AD8017 is a low cost, dual high speed amplifier capable of
driving low distortion signals to within 1.0 V of the supply rail.
It is intended for use in single supply xDSL systems where low
distortion and low cost are essential. The amplifiers will be able
to drive a minimum of 200 mA of output current per amplifier.
The AD8017 will deliver –78 dBc of SFDR at 500 kHz, required
for many xDSL applications.
0
10
100
1000
1
LOAD RESISTANCE – ⍀
Figure 1. Output Swing vs. Load Resistance
The AD8017 drive capability comes in a very compact form.
Utilizing ADI’s proprietary Thermal Coastline SOIC package,
the AD8017’s total (static and dynamic) power on +12 V sup-
plies is easily dissipated without external heatsink, other than to
place the AD8017 on a 4-layer PCB.
Fabricated in ADI’s high speed XFCB process, the high band-
width and fast slew rate of the AD8017 keep distortion to a
minimum, while dissipating a minimum amount of power. The
quiescent current of the AD8017 is 7 mA/amplifier.
The AD8017 will operate over the commercial temperature
range –40°C to +85°C.
Low distortion, high output voltage drive, and high output
current drive make the AD8017 ideal for use in low cost Cus-
tomer Premise End (CPE) equipment for ADSL, SDSL, VDSL
and proprietary xDSL systems.
+V
S
+
R1
+
R
OR
135⍀
= 100⍀
LINE
POWER
IN dB
L
V
V
V
OUT
IN
REF
R2
–
N :N
S
P
–
TRANSFORMER
–V
S
Figure 2. Differential Drive Circuit for xDSL Applications
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ +25؇C, V = ؎6 V, R = 100 ⍀, R = R = 619 ⍀, unless otherwise noted)
AD8017–SPECIFICATIONS
S
L
F
G
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
0.1 dB Bandwidth
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time
G = +2, VOUT < 0.4 V p-p
100
160
70
105
1600
2.6
35
MHz
MHz
MHz
V/µs
ns
VOUT < 0.4 V p-p
VOUT = 4 V p-p
Noninverting, VOUT = 2 V p-p, G = +2
Noninverting, VOUT = 2 V p-p
0.1%, VOUT = 4 V Step
ns
Overload Recovery
VIN = 5 V p-p
74
ns
NOISE/HARMONIC PERFORMANCE
Distortion
VOUT = 2 V p-p
2nd Harmonic
500 kHz, RL = 100 Ω/25 Ω
1 MHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
1 MHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
26 kHz to 1.1 MHz
–78/–71
–76/–69
–105/–91
–81/–72
40/35
–76/–66
–66
dBc
dBc
dBc
dBc
dBm
dBc
dBc
3rd Harmonic
IP3
IMD
MTPR
Input Noise Voltage
Input Noise Current
f = 10 kHz
1.9
23
21
–66
nV/√Hz
pA√Hz
pA√Hz
dB
f = 10 kHz (+ Inputs)
f = 10 kHz (– Inputs)
f = 5 MHz, G = +2
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.8
3.0
4.0
mV
mV
kΩ
TMIN–TMAX
Open Loop Transimpedance
VOUT = 2 V p-p
185
143
700
TMIN–TMAX
kΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
+Input
+Input
50
2.4
16
kΩ
pF
µA
µA
µA
µA
dB
V
Input Bias Current (+)
45
67
25
32
TMIN–TMAX
Input Bias Current (–)
1.0
T
MIN–TMAX
CMRR
Input CM Voltage Range
VCM 2.5 V
=
59
63
5.1
OUTPUT CHARACTERISTICS
Output Resistance
0.2
5.0
270
Ω
Output Voltage Swing
RL = 25 Ω
4.6
200
V
Output Current1
Highest Harmonic < –58 dBc,
f = 1 MHz, RL = 10 Ω
mA
TMIN–TMAX, Highest Harmonic < –52 dBc 100
mA
mA
Short-Circuit Current
1500
7.0
POWER SUPPLY
Supply Current/Amp
7.7
7.8
6.0
mA
mA
V
dB
°C
TMIN–TMAX
Dual Supply
Operating Range
Power Supply Rejection Ratio
Operating Temperature Range
2.2
58
–40
61
+85
NOTES
1Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( RL = 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
–2–
REV. A
AD8017
(@ +25؇C, V = ؎2.5 V, R = 100 ⍀, R = R = 619 ⍀, unless otherwise noted)
SPECIFICATIONS
S
L
F
G
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
0.1 dB Bandwidth
Large Signal Bandwidth
Slew Rate
Rise and Fall Time
Settling Time
G = +2, VOUT < 0.4 V p-p
VOUT < 0.4 V p-p
75
120
40
100
800
2.0
35
MHz
MHz
MHz
V/µs
ns
V
OUT = 4 V p-p
Noninverting, VOUT = 2 V p-p, G = +2
Noninverting, VOUT = 2 V p-p
0.1%, VOUT = 2 V Step
ns
Overload Recovery
VIN = 2.5 V p-p
74
ns
NOISE/HARMONIC PERFORMANCE
Distortion
V
OUT = 2 V p-p
2nd Harmonic
500 kHz, RL = 100 Ω/25 Ω
1 MHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
1 MHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
26 kHz to 1.1 MHz
–75/–68
–73/–66
–91/–88
–79/–74
40/36
–78/–64
–66
dBc
dBc
dBc
dBc
dBm
dBc
dBc
3rd Harmonic
IP3
IMD
MTPR
Input Noise Voltage
Input Noise Current
f = 10 kHz
1.8
23
21
–66
nV/√Hz
pA√Hz
pA√Hz
dB
f = 10 kHz (+ Inputs)
f = 10 kHz (– Inputs)
f = 5 MHz, G = +2
Crosstalk
DC PERFORMANCE
Input Offset Voltage
0.8
2.0
2.6
mV
mV
kΩ
T
MIN–TMAX
Open Loop Transimpedance
VOUT = 2 V p-p
TMIN–TMAX
40
45
166
kΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
+Input
+Input
50
2.4
16
kΩ
pF
µA
µA
µA
µA
dB
V
Input Bias Current (+)
40
62
25
32
TMIN–TMAX
TMIN–TMAX
Input Bias Current (–)
2
CMRR
Input CM Voltage Range
VCM
=
1.0 ( 1.0)
57
60
1.6
OUTPUT CHARACTERISTICS
Output Resistance
0.2
1.65
120
Ω
Output Voltage Swing
RL = 25 Ω
1.55
100
V
Output Current1
Highest Harmonic < –55 dBc,
f = 1 MHz, RL = 10 Ω
mA
TMIN–TMAX Highest Harmonic < 50 dBc 60
mA
mA
Short-Circuit Current
1300
6.2
POWER SUPPLY
Supply Current/Amp
7
7.3
6.0
mA
mA
V
TMIN–TMAX
Dual Supply
Operating Range
2.2
Power Supply Rejection Ratio
Operating Temperature Range
59
–40
62
dB
°C
+85
NOTES
1Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( RL = 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
REV. A
–3–
AD8017
ABSOLUTE MAXIMUM RATINGS1
The output stage of the AD8017 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8017 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V
Internal Power Dissipation2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
2.5 V
Output Short Circuit Duration
2.0
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
1.5
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device on a two-layer board with 2500 mm2 of 2 oz. copper at
+25°C 8-lead SOIC package: θJA = 95.0°C/W.
T
= +150؇C
J
1.0
T
= +125؇C
J
0.5
0
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8017
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately +150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of +175°C for an extended period can result in
device failure.
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE – ؇C
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature for AD8017
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8017AR
AD8017AR-REEL
AD8017AR-REEL7 –40°C to +85°C
AD8017AR-EVAL
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
SO-8
SO-8
SO-8
Tape and Reel 13"
Tape and Reel 7"
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8017 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
Typical Performance Characteristics–AD8017
619⍀
619⍀
619⍀
619⍀
V
V
V
IN
OUT
OUT
R
R
54.4⍀
L
L
V
IN
+V
+V
S
S
49.9⍀
+
+
0.1F
0.1F
10F
0.1F
0.1F
10F
+
+
10F
10F
–V
–V
S
S
Figure 4. Test Circuit: Gain = +2
Figure 7. Test Circuit: Gain = –1
OUTPUT = 100mV
OUTPUT = 100mV
INPUT = 100mV
INPUT = 50mV
200ns/DIV
200ns/DIV
Figure 8. 100 mV Step Response; G = –1, VS = 2.5 V or
6 V, RL = 100 Ω
Figure 5. 100 mV Step Response; G = +2, VS = 2.5 V or
6 V, RL = 100 Ω
OUTPUT = 4V
OUTPUT = 4V
INPUT = 2V
INPUT = 4V
200ns/DIV
200ns/DIV
Figure 9. 4 V Step Response; G = –1, VS = 6 V,
RL = 100 Ω
Figure 6. 4 V Step Response; G = +2, VS = 6 V,
RL = 100 Ω
REV. A
–5–
AD8017
0
0
V
= 2V p-p
V
= 2V p-p
OUT
G = +2
OUT
G = +2
–20
–40
–20
–40
–60
–80
–60
2ND
2ND
–80
3RD
3RD
–100
–100
–120
–120
1
10
FREQUENCY – MHz
100
0.1
0.1
1
10
FREQUENCY – MHz
100
Figure 10. Distortion vs. Frequency; VS = 6 V, RL = 100 Ω
Figure 13. Distortion vs. Frequency; VS = 2.5 V, RL = 100 Ω
0
0
V
= 2V p-p
V
= 2V p-p
OUT
G = +2
OUT
G = +2
–10
–20
–30
–20
–40
–60
–40
–50
2ND
2ND
–60
–70
3RD
3RD
–80
–80
–90
–100
0.1
1
10
FREQUENCY – MHz
100
0.1
1
10
FREQUENCY – MHz
100
Figure 11. Distortion vs. Frequency; VS = 6 V, RL = 25 Ω
Figure 14. Distortion vs. Frequency; VS = 2.5 V, RL = 25 Ω
–20
–20
V
R
= ؎2.5V
= 25⍀
S
L
V
R
= ؎6V
= 25⍀
S
V
R
= ؎6V
= 10⍀
S
–30
–40
–30
–40
–50
L
L
V
S
= ؎2.5V
= 5⍀
V
R
= ؎2.5V
= 10⍀
S
R
L
L
V
R
= ؎6V
= 5⍀
S
L
–50
–60
–70
–60
–70
0
100
200
300
400
500
0
100
200
300
400
600
OUTPUT CURRENT – mA
OUTPUT CURRENT – mA
Figure 12. Distortion vs. Output Current; VS = 6 V,
f = 1 MHz, G = +2
Figure 15. Distortion vs. Output Current; VS = 2.5 V,
f = 1 MHz, G = +2
–6–
REV. A
AD8017
–20
–40
0
–20
–40
–60
–80
–60
2ND
–80
2ND
3RD
–100
–120
–140
–100
3RD
–120
–140
0
10
100
1000
0
10
100
1000
LOAD RESISTANCE – ⍀
LOAD RESISTANCE – ⍀
Figure 16. Distortion vs. RL, VS = 6 V, G = +2, VOUT = 2 V p-p,
f = 1 MHz
Figure 19. Distortion vs. RL, VS = 2.5 V, G = +2,
VOUT = 2 V p-p, f = 1 MHz
0
0
V
= ؎6V
V
= ؎2.5V
S
S
f = 1MHz
G = +2
f = 1MHz
G = +2
–10
–10
–20
–30
–40
–50
–20
–30
–40
–50
–60
R
= 25⍀
R
= 25⍀
L
L
–60
–70
–80
R
= 100⍀
L
–70
–80
R
= 100⍀
L
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
Figure 17. Distortion vs. Output Voltage, VS = 6 V, G = +2,
f = 1 MHz
Figure 20. Distortion vs. Output Voltage, VS = 2.5 V,
G = +2, f = 1 MHz
0
0
V
= ؎6V
S
V
= ؎2.5V
S
f = 10MHz
G = +2
–10
–10
–20
–30
–40
–50
–60
–70
–80
f = 10MHz
G = +2
–20
–30
–40
R
= 25⍀
L
R
= 25⍀
L
–50
–60
–70
R
= 100⍀
L
R
= 100⍀
L
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
OUTPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
Figure 18. Distortion vs. Output Voltage, VS = 6 V, G = +2,
f = 10 MHz
Figure 21. Distortion vs. Output Voltage, VS = 2.5 V,
G = +2, f = 10 MHz
REV. A
–7–
AD8017
2
1
3
R
= 100⍀
L
R
= 100⍀
L
0
GAIN = +2
0
–1
–2
–3
–4
–5
–6
GAIN = +10
GAIN = +2
GAIN = +5
GAIN = +10
–3
GAIN = +5
–6
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 25. Frequency Response; VS = 2.5 V
Figure 22. Frequency Response; VS = 6 V
0.3
0.3
G = +2
R
= 100⍀
L
0.2
0.1
G = +2
0.2
0.1
R
= 100⍀
L
0.0
0.0
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
1
10
100
1000
0.1
1
10
100
1000
0.1
FREQUENCY – MHz
FREQUENCY – MHz
Figure 26. Gain Flatness; VS = 2.5 V
Figure 23. Gain Flatness; VS = 6 V
3
0
0
–3
V
= 1V
RMS
OUT
V
= 2V p-p
OUT
–3
–6
–6
–9
–9
–12
–15
–18
–21
–12
–15
–18
–21
–24
–27
–30
G = +2
= 100⍀
R
–24
–27
–30
–33
L
G = +2
= 100⍀
R
L
0.1
1
10
FREQUENCY – MHz
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
Figure 27. Output Voltage vs. Frequency; VS = 2.5 V
Figure 24. Output Voltage vs. Frequency; VS = 6 V
–8–
REV. A
AD8017
120
100
+20
0
80
60
40
20
0
–20
–40
–60
–80
0
2
4
6
8
0
50
100
150
SERIES RESISTANCE – ⍀
FREQUENCY – kHz
Figure 31. RS and CL vs. 30% Overshoot
Figure 28. Multitone Power Ratio: VS = 6 V, 13 dBm
Output Power into 25 Ω
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–PSRR
+PSRR
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 32. PSRR vs. Frequency; VS = 6 V or VS = 2.5 V
Figure 29. CMRR vs. Frequency; VS = 6 V or VS = 2.5 V
180
120
60
1000
100
10
12
10
8
0.4
0.3
PHASE
6
0.2
0.1
0
TRANSIMPEDANCE
iN
eN
4
2
1
0
1000
0
100
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
FREQUENCY – MHz
FREQUENCY – kHz
Figure 33. Open-Loop Transimpedance and Phase vs.
Frequency
Figure 30. Noise vs. Frequency
REV. A
–9–
AD8017
6
5
G = +2
V
= 2V
- 100⍀
= ؎6V
OUT
STEP
V
4
OUT
R
L
S
V
3
+2mV
(+0.1%)
2
1
0
0
V
IN
–1
–2
–2mV
(+0.1%)
–10
10
30
50
70
90
110
130
150
2
1
0
V
IN
0
10 20 30 40 50 60 70 80 90
TIME – ns
–3
–3
–3
–4
–5
–6
Figure 34. Settling Time; VS = 6.0 V
V
OUT
–20
–30
–40
–50
V
= 2V p-p
OUT
G = +2
= 100⍀
–10
10
30
50
70
TIME – ns
90
110
130
150
R
L
Figure 37. Overload Recovery; VS = 6 V, G = +2,
RL = 100 Ω, VIN = 5 V p-p, T = 1 µs
–60
–70
–80
–90
–100
0.1
1
10
100
1000
FREQUENCY – MHz
Figure 35. Output Crosstalk vs. Frequency
1000000
100
10
1
Z
IN
100000
10000
1000
Z
OUT
0.1
1000
0.1
1
10
100
FREQUENCY – MHz
Figure 36. Input and Output Impedance vs. Frequency
–10–
REV. A
AD8017
THEORY OF OPERATION
Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8017 will provide excellent results for low power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying RG) will be much lower compared to a
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes less than half the quiescent power (vs. 12 V
supply) with little degradation in its ac and dc performance
characteristics. See specification pages for comparisons.
The AD8017 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing,
under heavy current loads. Its wide dynamic performance (in-
cluding noise) is the result of both a new complementary high
speed bipolar process and a new and unique architectural
design. The AD8017 basically uses a two gain stage complemen-
tary design approach versus the traditional “single stage”
complementary mirror structure sometimes referred to as the
Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascode design much like the AD9617.
This design allows for the standing or quiescent current to add
to the high signal or slew current-induced stages. In the time
domain, the large signal output rise/fall time and slew rate is
typically controlled by the small signal BW of the amplifier and
the input signal step amplitude respectively, not the dc quies-
cent current of the gain stages (with the exception of input level
shift diodes Q1/Q2). Using two stages as opposed to one, also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus providing lower signal distortion and the
ability to drive heavier external loads. In addition, the second
gain stage also isolates (divides down) A3’s input reflected load
drive and the nonlinearities created resulting in relatively lower
distortion and higher open-loop gain. See Figure 38.
DC GAIN CHARACTER
Gain stages A1/A1 and A2/A2 combined provide negative
feedforward transresistance gain. See Figure 38. Stage A3 is a
unity gain buffer which provides external load isolation to A2.
Each stage uses a symmetrical complementary design. (A3 is
also complementary, though not explicitly shown). This is done
to reduce both second order signal distortion and overall quies-
cent power as discussed above. In the quasi dc-to-low frequency
region, the closed loop gain relationship can be approximated as:
G = 1+RF/RG for Noninverting Operation
G = –RF/RG for Inverting Operation
These basic relationships above are common to all traditional
operational amplifiers.
C
D
A1
Z1 = R1 || C1
Z1
IPN
IQ1
IPP
–V
I
–A2
C 1
P
Q3
C 2
P
ICQ + IO
IR + IFC
Q1
V
V
N
P
V
9
O
Z1
+
–
–A3
V
O
R
C
L
L
Z2
R
Q2
F
IE
R
N
Q4
IR – IFC
ICQ – IO
Z1
IQ1
–A2
–V
I
INP
C 1
P
IPN
AD8017
A1
C
D
Figure 38. Simplified Block Diagram
REV. A
–11–
AD8017
APPLICATIONS
Single +12 V Supply ADSL Remote Terminal (RT) Transmitter
For consumer use, it is desirable to create an ADSL modem
that can be a plug-in accessory for a PC. In such an application,
the circuit should dissipate a minimum of power, yet still meet
the ADSL specification.
Output Power Characteristics as Applied to ADSL Signals
The AD8017 was designed to provide both relatively high cur-
rent and voltage output capability. Figures 17 and 20 quantify
the ac load current versus distortion of the device at loads of
100 Ω and 25 Ω at 1 MHz. Using approximately –50 dBc as the
worst case distortion limit, the AD8017 exhibits acceptable
linearity to within approximately 1.4 V of either supply rail (12 V
or 6 V) while simultaneously providing 200 mA of load cur-
rent. These levels are achieved at only 7 mA of quiescent cur-
rent for each amplifier.
The circuit in Figure 39 shows a single +12 V supply circuit
that uses the AD8017 as a remote terminal transmitter. This
supply voltage is readily available on the PCI connector of PCs.
The circuit configures each half of the AD8017 as an inverter
with a gain of about six. Both of the amplifier circuits are ac
coupled at both the inputs and the outputs. This makes the dc
levels of the circuit independent of the other dc levels of the
signal chain.
ADSL applications require signal line powers of 13 dBm that
can randomly peak to an instantaneous power (or V × I product)
of 28.5 dBm. This equates to peak-to-rms voltage ratio of 5.3-
to-1. Using a 1:2 transformer in the ADSL circuit illustrated
below and 100 Ω as the line resistance, a peak voltage of 4.2 V
at a peak current of 168 mA will be required from the line driver
output (see Table I). See detailed application below. A higher
turns ratio transformer can be used to reduce the primary out-
put voltage swing of the amplifier (for devices that do not have
the voltage swing, but do have the current drive capability).
However, this requires more than an equivalent increase in
current due to the added I × R losses from the transformer for
the same receiver power. Generally this will result in added
distortion. Table I below shows the ADSL ac current and volt-
ages required for both a 1:1 and 1:2 transformer turns ratio.
The inputs will generally be driven by the output of an active
filter, which has a low output impedance. Thus there will be a
minimum of loading of the source caused by the 169 Ω input
impedance in the pass band. The output will require a 1:2 step-
up transformer to drive a 100 Ω line. The reflected impedance
back to the primary will be 25 Ω. With 25 Ω of series termina-
tion added (12.5 Ω in each output), the effective load that the
differential amplifier outputs will drive is 50 Ω.
The input and output ac coupling provides two high pass cir-
cuits. The inputs are formed by the 0.1 µF capacitor and the
169 Ω resistor, which provides a break frequency of about
9.4 kHz. The two 1 µF capacitors in the output along with the
50 Ω effective load provides a 6.4 kHz break frequency in the
output side. Both of these circuits want to reject the Plain Old
Telephone System (POTS) band (dc to 4 kHz) while passing
the ADSL upstream band, which starts at about 20 kHz.
+12V
0.1F
0.1F
10F
169⍀
1k⍀
The positive inputs must be biased at mid supply, which is
nominally +6 V. This will maintain the maximum dynamic
range of the output in each direction, regardless of the tolerance
of the supply. The inverting configuration was chosen as this
requires a steady dc current from this supply, as opposed to the
signal-dependent current that would be required in a noninvert-
ing configuration. Several options were studied for creating this
supply.
2
8
1F
1:2
12.5⍀
1
4.7V
3
50⍀
EFFECTIVE
LOAD
1k⍀
V
V
OUT
AD8017
100⍀
IN
0.1F
1k⍀
5
6
7
4.7V
12.5⍀
1F
4
169⍀
A voltage regulator could be used, but there are several disad-
vantages. The first is that this will not track the middle of the
supplies as it will always have an output that is a fixed voltage
from ground. This also requires an additional active component
that will impact the cost of the total solution.
1k⍀
0.1F
Figure 39. Single +12 V Supply ADSL Remote Terminal
Transmitter
A two-resistor divider could also be used. There is a tradeoff
required here in the selection of the value of the resistors. As the
resistors become smaller, the amount of power that they will
dissipate will increase. For two 1 kΩ resistors, the power dissi-
pation in this circuit would be 72 mW. Thus, in order to keep
this power to a minimum, it is desirable to make the resistors as
large as possible.
Table I. DSL Drive Amplifier Requirements for Various Combinations of Line Power, Line Impedance and Turn Ratios
Line
Power
Insertion Line
Loss Load
Turns Crest
Ratio Factor Impedance R1 = R2 Voltage
Reflected
Per Amp
Peak Per Amplifier Peak Current
Voltage Output
Output
13 dBm 1 dB
13 dBm 1 dB
100 Ω 1:1
100 Ω 1:2
5.3
5.3
100 Ω
25 Ω
50 Ω
12.5 Ω
1.585 V rms
0.792 V rms
8.4 V peak
4.2 V peak
84 mA
168 mA
–12–
REV. A
AD8017
VCC
The practical maximum value that these resistors can have is
determined by the offset voltage that is created by the input bias
current that flows through them. The maximum input bias
current into the + inputs is 45 µA. This will create an offset
voltage of 45 mV per 1 kΩ of bias resistor. Fortunately, the ac
coupling of the stages provides only unity gain for this dc offset
voltage, which is another advantage of this configuration. Any
dc offset in the output will limit the amount of dynamic signal
swing that will be available between the rails.
A1
V
V
O1
R
L
A1
O2
The circuit shown uses two 4.7 V Zener diodes that provide a
voltage drop which serves to limit the power dissipation in the
bias circuit. This allows the use of smaller value resistors in the
bias circuit. Thus, for this circuit the current will be (12 V –
(2 × 4.7 V))/2 kΩ = 1.3 mA. Thus, this circuit will dissipate
only 15.6 mW, yet only induce a maximum of 40 mV of offset
at the output. This circuit will also track the midpoint of the
supplies over their specified tolerance range.
VEE
Figure 40. Differential Driver Simplified Circuit Schematic
It is important to consider the total power dissipation of the
AD8017 in order to properly size the heatsinking area for your
application. The dc power dissipation for VIN = 0 is simply,
IQ. (VCC + VEE), or 2 × IQ × VS. For the AD8017, this number is
0.17 W. In this purely differential circuit we can use symmetry
to simplify the computation for a dc input signal,
The distortion of the circuit was measured with a 50 Ω load.
The frequency used was 500 kHz, which is beyond the maxi-
mum required for the upstream signal. For ADSL over POTS, a
maximum frequency of 135 kHz is required. For ADSL over
ISDN, the maximum frequency is 276 kHz. The amplitude was
20 V p-p (10 V p-p for each amplifier), which is the maximum
crest signal that will be required. The second harmonic was
better than –80 dBc, while the third harmonic was –64 dBc.
This represents a worst case of the absolute maximum signal
that will be required for only a very small statistical basis and at
a frequency that is higher than the maximum required. For a
statistical majority of the time, the signal will be at a lower am-
plitude and frequency, where the distortion performance will be
better.
VO
RL
PD = 2× IQ ×VS +4× VS –VO
×
(
)
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current commutates during sourcing or
sinking current into the load. For a sine wave source, integra-
tion over a half cycle yields:
2
4VOVS VO
π RL
P = 2× I ×V +2×
−
D
Q
S
(Refer to Figure 41)
R
L
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by > 15%. For
example:
When the circuit was run while providing the upstream drive
signal in an ADSL system, the supply current to the part was
measured at 25 mA. Thus, the total power to the drive circuit
was 300 mW. This power winds up in three places: the drive
amplifier, down the line and in the termination and interface
circuitry.
P
V
OUT = 16 dBm = 40 mW
OUT @ 50 Ω = 1.41 V rms or VO = 1.0 V
at each amplifier output, which yields a PD of 0.436 W. By
actual measurement, PD for a DMT signal of 16 dBm requires
0.38 W of power to be dissipated by the AD8017.
The ADSL specification calls for 13 dBm or 20 mW into the
line. The line termination will consume an equal amount of
power, as it is the same resistance value. About a 1 dB loss can
be expected in the losses in the interface circuitry, which trans-
lates into about 10 mW of power. Thus, the total power dissi-
pated in the AD8017 when used as a driver in this application is
about 250 mW.
REV. A
–13–
AD8017
area of copper foil without affecting the ac performance of the
part. On the surface side of the board, the copper area that
connects to Pins 4 and 8 should be enlarged and spread out to
the maximum extent possible. As a practical matter, there will
be diminishing returns from adding copper more than a few
centimeters from the pins.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
When the power supplies are run on the board on internal
power planes, then these should also be made as large as practi-
cal, and multiple vias (~0.012 in. or 0.3 mm) should be pro-
vided from the component layer near the power supply pins of
the AD8017 to the inner layers. These vias should not have any
of the traditional “thermal relief” spokes to the planes, because
the function of these is to impede heat flow for ease of soldering.
This is counter to the effect desired for heatsinking.
0
0
1
2
3
4
5
6
OUTPUT VOLTAGE (V ) – V
O
PK
On the side of the board opposite the component, additional
heatsinking can be provided by adding copper area near the vias
to further lower the thermal resistance. Additional vias can be
provided throughout to better conduct heat from the inner
layers to the outer layers.
Figure 41. Power Dissipation (PD) vs. Output Voltage (VO),
RL = 50 Ω
Thermal Considerations
The AD8017 in a “Thermal Coastline” SO-8 package relies on
the device pins to assist in removing heat from the die at a faster
rate than that of conventional packages. The effect is to provide
a lower θJC for the device. To make the most effective use of
this, special details should be worked into the copper traces of
the printed circuit board.
The remainder of the device pins are active signal pins and must
be treated a bit more carefully. Pins 2 and 6 are the summing
junctions of the op amps and will be the most adversely affected by
stray capacitance. For this reason, the copper area of these pins
should be minimized. In addition, the copper nearby on the
component layer should be kept more than 3 mm–5 mm away
from these pins, where possible. The inner and opposite side
circuit layers directly below the summing junctions should also
be void of copper.
There will be a tradeoff, however, between designing a board
that will maximally remove heat, and one that will provide the
desired ac performance. This is the result of the additional para-
sitic capacitance on some of the pins that would be caused by
the addition of extra heatsinking copper traces.
The positive inputs and outputs can withstand somewhat more
capacitance than the summing junctions without adversely af-
fecting ac performance. However, these pins should be treated
carefully, and the amount of heatsinking and excess capacitance
should be analyzed and adjusted depending on the application.
If maximum ac performance is desired and the power dissipa-
tion is not extreme, then the copper area connected to these
pins should be minimized. If the ac performance is not very
critical and maximum power must be dissipated, then the cop-
per area connected to these pins can be increased. As in many
other areas of analog design, the designer must use some judg-
ment based on the consideration of the above, in order to pro-
duce a satisfactory design.
The first technique for maximum heatsinking is to use a heavy
layer of copper. 2 oz. copper will provide better heatsinking than
1 oz. copper. Additional internal circuit layers can also be used
to more effectively remove heat, and to provide better power
and ground distribution.
There are no “ground” pins per se on the AD8017 (when run
on a dual supply), but the power supplies (Pins 4 and 8) are at
ac ground. Thus, these pins can be safely tied to a maximum
–14–
REV. A
AD8017
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8017 requires
careful attention to board layout and component selection.
Table II shows recommended component values for the AD8017
and Figures 42–44 show recommended layouts for the 8-lead
SOIC package for a positive gain. Proper RF design techniques
and low parasitic component selections are mandatory.
Table II. Typical Bandwidth vs. Gain Setting Resistors
(VS = 6 V, RL = 100 ⍀)
Small Signal
–3 dB BW (MHz)
Gain
RF (⍀)
RG (⍀) RT (⍀)
–1
619
619
619
619
619
54.5
49.9
49.9
49.9
110
320
160
40
Figure 43. Universal SOIC Noninverter Top
+1
+2
+10
619
68.8
RT chosen for 50 Ω characteristic input impedance.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ures 4 and 7). One end should be connected to the ground
plane and the other within 1/8 in. of each power pin. An addi-
tional (4.7 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gain.
Figure 44. Universal SOIC Noninverter Bottom
Figure 42. Universal SOIC Noninverter Top Silkscreen
REV. A
–15–
AD8017
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–16–
REV. A
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