AD8021ARMZ-REEL [ADI]
Low Noise, High Speed Amplifier for 16-Bit Systems; 低噪声，高速放大器，用于16位系统
| 型号： | AD8021ARMZ-REEL |
| 厂家： | 
ADI |
| 描述： | Low Noise, High Speed Amplifier for 16-Bit Systems |
| 文件： | 总28页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, High Speed Amplifier
for 16-Bit Systems
AD8021
CONNECTION DIAGRAM
FEATURES
Low noise
AD8021
LOGIC
REFERENCE
1
2
3
4
8
7
6
5
DISABLE
2.1 nV/√Hz input voltage noise
2.1 pA/√Hz input current noise
Custom compensation
Constant bandwidth from G = −1 to G = −10
High speed
+V
S
–IN
V
+IN
OUT
–V
S
C
COMP
200 MHz (G = −1)
Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8)
190 MHz (G = −10)
Low power
34 mW or 6.7 mA typical for 5 V supply
Output disable feature, 1.3 mA
Low distortion
−93 dBc second harmonic, fC = 1 MHz
−108 dBc third harmonic, fC = 1 MHz
DC precision
1 mV maximum input offset voltage
0.5 μV/°C input offset voltage drift
Wide supply range, 5 V to 24 V
Low price
The AD8021 allows the user to choose the gain bandwidth
product that best suits the application. With a single capacitor,
the user can compensate the AD8021 for the desired gain with
little trade-off in bandwidth. The AD8021 is a well-behaved
amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
overload recovery of ±0 ns.
The AD8021 is stable over temperature with low input offset
voltage drift and input bias current drift, 0.± μV/°C and 10 nA/°C,
respectively. The AD8021 is also capable of driving a 7± Ω line
with ±3 V video signals.
Small packaging
Available in SOIC-8 and MSOP-8
The AD8021 is both technically superior and priced considerably
less than comparable amps drawing much higher quiescent
current. The AD8021 is a high speed, general-purpose amplifier,
ideal for a wide variety of gain configurations and can be used
throughout a signal processing chain and in control loops. The
AD8021 is available in both standard 8-lead SOIC and MSOP
packages in the industrial temperature range of −40°C to +8±°C.
APPLICATIONS
ADC preamps and drivers
Instrumentation preamps
Active filters
Portable instrumentation
Line receivers
Precision instruments
Ultrasound signal processing
High gain circuits
24
V
= 50mV p-p
OUT
21
18
15
12
9
G = –10, R = 1kΩ, R = 100Ω,
F
G
R
= 100Ω, C = 0pF
C
IN
GENERAL DESCRIPTION
G = –5, R = 1kΩ, R = 200Ω,
The AD8021 is an exceptionally high performance, high speed
voltage feedback amplifier that can be used in 16-bit resolution
systems. It is designed to have both low voltage and low current
noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating
at the lowest quiescent supply current (7 mA @ ±± V) among
today’s high speed, low noise op amps. The AD8021 operates
over a wide range of supply voltages from ±2.2± V to ±12 V, as
well as from single ± V supplies, making it ideal for high speed,
low power instruments. An output disable pin allows further
reduction of the quiescent supply current to 1.3 mA.
F
G
R
= 66.5Ω, C = 1.5pF
C
IN
6
G = –2, R = 499Ω, R = 249Ω,
F
G
R
= 63.4Ω, C = 4pF
C
3
IN
0
G = –1, R = 499Ω, R = 499Ω,
F
G
R
= 56.2Ω, C = 7pF
–3
–6
IN
C
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 2. Small Signal Frequency Response
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8021
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications..................................................................................... 19
Using the Disable Feature.......................................................... 20
Theory of Operation ...................................................................... 21
PCB Layout Considerations...................................................... 21
Driving 16-Bit ADCs ................................................................. 22
Differential Driver...................................................................... 22
Using the AD8021 in Active Filters ......................................... 23
Driving Capacitive Loads.......................................................... 23
Outline Dimensions....................................................................... 2±
Ordering Guide .......................................................................... 2±
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits................................................................................. 17
REVISION HISTORY
5/06—Rev. E to Rev. F
7/03—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 3.......................................................................... 7
Changes to Figure 60...................................................................... 19
Changes to Table 9.......................................................................... 23
Deleted All References to Evaluation Board...................Universal
Replaced Figure 2 ..............................................................................±
Updated Outline Dimensions....................................................... 20
2/03—Rev. A to Rev. B
Edits to Evaluation Board Applications....................................... 20
Edits to Figure 17 ........................................................................... 20
3/05—Rev. D to Rev. E
Updated Format..................................................................Universal
Change to Figure 19 ....................................................................... 11
Change to Figure 2± ....................................................................... 12
Change to Table 7 and Table 8 ...................................................... 22
Change to Driving 16-Bit ADCs Section .................................... 22
6/02—Rev. 0 to Rev. A
Edits to Specifications.......................................................................2
10/03—Rev. C to Rev. D
Updated Format..................................................................Universal
Rev. F | Page 2 of 28
AD8021
SPECIFICATIONS
VS = ±± V, @ TA = 2±°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 1.
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V step, RL = 500 Ω
2.5 V input step, G = +2
355
160
150
110
95
120
250
380
490
205
185
150
120
150
300
420
23
MHz
MHz
MHz
MHz
V/μs
V/μs
V/μs
V/μs
ns
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
50
ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
−93
−108
dBc
dBc
f = 5 MHz
HD2
HD3
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
−70
−80
2.1
2.1
0.03
0.04
dBc
dBc
nV/√Hz
pA/√Hz
%
2.6
Degrees
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
0.4
0.5
7.5
10
0.1
86
1.0
mV
μV/°C
μA
nA/°C
μA
dB
TMIN to TMAX
+Input or −input
10.5
0.5
82
INPUT CHARACTERISTICS
Input Resistance
10
1
MΩ
pF
V
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
−4.1 to +4.6
−98
VCM = 4 V
−86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
−3.5 to +3.2 −3.8 to +3.4
V
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot
60
75
15/120
mA
mA
pF
VO = 50 mV p-p/1 V p-p
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
f = 10 MHz
VO = 0 V to 2 V, 50% logic to 50% output
VO = 0 V to 2 V, 50% logic to 50% output
−40
45
50
1.75/1.90
70
2
dB
ns
ns
V
μA
μA
V
DISABLE − VLOGIC REFERENCE
LOGIC REFERENCE = 0.4 V
DISABLE = 4.0 V
Rev. F | Page 3 of 28
AD8021
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
30
33
Max
Unit
μA
μA
Disabled Leakage Current
LOGIC REFERENCE = 0.4 V
DISABLE = 0.4 V
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
7.0
1.3
−95
−95
12.0
7.7
1.6
V
Output enabled
Output disabled
VCC = 4 V to 6 V, VEE = −5 V
VCC = 5 V, VEE = −6 V to −4 V
mA
mA
dB
dB
+Power Supply Rejection Ratio
−Power Supply Rejection Ratio
−86
−86
VS = ±12 V, @ TA = 2±°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 2.
AD8021AR/AD8021ARM
Typ
Parameter
Conditions
Min
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V step, RL = 500 Ω
6 V input step, G = +2
520
175
170
125
105
140
265
400
560
220
200
165
130
170
340
460
21
MHz
MHz
MHz
MHz
V/μs
V/μs
V/μs
V/μs
ns
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
90
ns
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
−95
−116
dBc
dBc
f = 5 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
−71
−83
2.1
2.1
0.03
0.04
dBc
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
2.6
Degrees
0.4
0.2
8
10
0.1
88
1.0
mV
μV/°C
μA
nA/°C
μA
dB
TMIN to TMAX
+Input or −input
11.3
0.5
84
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
1
MΩ
pF
V
−11.1 to +11.6
−96
VCM = 10 V
−86
dB
Rev. F | Page 4 of 28
AD8021
AD8021AR/AD8021ARM
Typ
Parameter
Conditions
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
−10.2 to +9.8 −10.6 to +10.2
V
70
115
15/120
mA
mA
pF
VO = 50 mV p-p/1 V p-p
f = 10 MHz
VO = 0 V to 2 V, 50% logic to 50% output
VO = 0 V to 2 V, 50% logic to 50% output
−40
45
50
1.80/1.95
dB
ns
ns
V
V
DISABLE − VLOGIC REFERENCE
LOGIC REFERENCE = 0.4 V
DISABLE = 4.0 V
70
2
μA
μA
μA
μA
Disabled Leakage Current
LOGIC REFERENCE = 0.4 V
DISABLE = 0.4 V
30
33
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
7.8
1.7
−96
−100
12.0
8.6
2.0
V
Output enabled
Output disabled
VCC = 11 V to 13 V, VEE = −12 V
VCC = 12 V, VEE = −13 V to −11 V
mA
mA
dB
dB
+Power Supply Rejection Ratio
−Power Supply Rejection Ratio
−86
−86
VS = ± V, @ TA = 2±°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 3.
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
VO = 1 V step, RL = 500 Ω
0 V to 2.5 V input step, G = +2
270
155
135
95
305
190
165
130
110
140
280
390
28
MHz
MHz
MHz
MHz
V/μs
V/μs
V/μs
V/μs
ns
Slew Rate, 1 V Step
80
110
210
290
Settling Time to 0.01%
Overload Recovery (50%)
40
ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
−84
−91
dBc
dBc
f = 5 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
−68
−81
2.1
dBc
dBc
nV/√Hz
pA/√Hz
Input Voltage Noise
Input Current Noise
2.6
2.1
Rev. F | Page 5 of 28
AD8021
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max
Unit
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
0.4
0.8
7.5
10
0.1
76
1.0
mV
μV/°C
μA
nA/°C
μA
dB
TMIN to TMAX
+Input or −input
10.3
0.5
72
INPUT CHARACTERISTICS
Input Resistance
10
1
0.9 to 4.6
−98
MΩ
pF
V
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot
DISABLE CHARACTERISTICS
Off Isolation
1.5 V to 3.5 V
−84
dB
1.25 to 3.38 1.10 to 3.60
V
30
50
10/120
mA
mA
pF
VO = 50 mV p-p/1 V p-p
f = 10 MHz
VO = 0 V to 1 V, 50% logic to 50% output
VO = 0 V to 1 V, 50% logic to 50% output
−40
45
50
1.55/1.70
dB
ns
ns
V
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
V
DISABLE − VLOGIC REFERENCE
LOGIC REFERENCE = 0.4 V
DISABLE = 4.0 V
70
2
μA
μA
μA
μA
Disabled Leakage Current
LOGIC REFERENCE = 0.4 V
DISABLE = 0.4 V
30
33
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
6.7
1.2
−82
−84
12.0
7.5
1.5
V
Output enabled
Output disabled
VCC = 4.5 V to 5.5 V, VEE = 0 V
VCC = 5 V, VEE = −0.5 V to +0.5 V
mA
mA
dB
dB
+Power Supply Rejection Ratio
−Power Supply Rejection Ratio
−74
−76
Rev. F | Page 6 of 28
AD8021
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
MAXIMUM POWER DISSIPATION
Rating
The maximum power that can be safely dissipated by the
AD8021 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 1±0°C. Temporarily
exceeding this limit can cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 17±°C for an extended
period can result in device failure.
Supply Voltage
Power Dissipation
26.4 V
Observed power
derating curves
VS 1 V
0.8 V
10 mA
Observed power
derating curves
−65°C to +125°C
−40°C to +85°C
300°C
Input Voltage (Common Mode)
Differential Input Voltage1
Differential Input Current
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
While the AD8021 is internally short-circuit protected, this can
not be sufficient to guarantee that the maximum junction tem-
perature (1±0°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum
power derating curves.
1 The AD8021 inputs are protected by diodes. Current-limiting resistors are
not used to preserve the low noise. If a differential input exceeds 0.8 V, the
input current should be limited to 10 mA.
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
0.01
–55 –45 –35 –25 –15 –5
5 15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature1
1 Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead
MSOP: θJA = 145°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 28
AD8021
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8021
LOGIC
REFERENCE
1
2
3
4
8
7
6
5
DISABLE
+V
S
–IN
V
+IN
OUT
–V
S
C
COMP
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
LOGIC REFERENCE
−IN
+IN
−VS
CCOMP
VOUT
+VS
Reference for Pin 81 Voltage Level. Connect to logic low supply.
Inverting Input.
Noninverting Input.
Negative Supply Voltage.
Compensation Capacitor. Tie to −VS. (See the Applications section for value.)
Output.
Positive Supply Voltage.
Disable, Active Low.
DISABLE
1 When Pin 8 (
) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of
DISABLE
Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to
+VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.
Rev. F | Page 8 of 28
AD8021
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 2±°C, VS = ±± V, RL = 1 kΩ, G = +2, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 976 Ω, RD = ±3.6 Ω, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
frequency = 1 MHz, unless otherwise noted.
24
21
18
15
12
9
9
G = +2
V
= ±2.5V
S
G = +10, R = 1kΩ, R = 110Ω, C = 0pF
F
G
C
8
V
= ±5V
S
7
G = +5, R = 1kΩ, R = 249Ω, C = 2pF
F
G
C
6
5
4
G = +2, R = R = 499Ω, C = 7pF
F
G
C
V
= ±12V
S
6
3
3
2
G = +1, R = 75Ω, C = 10pF
F
C
V
= ±2.5V
100M
S
0
1
–3
–6
0
–1
1M
10M
1G
0.1M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Small Signal Frequency Response vs. Frequency and Gain,
VOUT = 50 mV p-p, Noninverting (See Figure 48)
Figure 8. Small Signal Frequency Response vs. Frequency and Supply,
OUT = 50 mV p-p, Noninverting (See Figure 48)
V
3
2
24
21
G = –1
V
= ±2.5V
S
V
= ±5V
S
G = –10, R = 1kΩ, R = 100Ω,
F
G
1
18
15
12
9
R
= 100Ω, C = 0pF
C
IN
0
G = –5, R = 1kΩ, R = 200Ω,
F
G
–1
–2
–3
–4
–5
–6
–7
V
= ±12V
S
R
= 66.5Ω, C = 1.5pF
C
IN
6
G = –2, R = 499Ω, R = 249Ω,
F
G
3
R
= 63.4Ω, C = 4pF
C
IN
0
G = –1, R = 499Ω, R = 499Ω,
F
G
V
= ±2.5V
S
–3
–6
R
= 56.2Ω, C = 7pF
IN
C
1M
10M
100M
1G
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 6. Small Signal Frequency Response vs. Frequency and
Gain, VOUT = 50 mV p-p Inverting (See Figure 48)
Figure 9. Small Signal Frequency Response vs. Frequency and Supply,
VOUT = 50 mV p-p, Inverting (See Figure 50)
9
9
G = +2
C
= 5pF
G = +2
C
8
8
7
7
V
= 0.1V AND 50mV p-p
OUT
C
= 7pF
C
6
5
6
5
C
= 9pF
C
4
4
V
= 4V p-p
OUT
3
3
2
2
V
= 1V p-p
OUT
1
1
C
= 7pF
C
0
0
C
= 9pF
C
–1
–1
1M
10M
100M
1G
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 7. Small Signal Frequency Response vs. Frequency and
Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48)
Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting
(See Figure 48)
Rev. F | Page 9 of 28
AD8021
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
G = +2
= R
R
= 1kΩ
G = +2
F
R
F
G
R
= 499Ω
F
R
= 250Ω
F
R
= 150Ω
F
R
= 1kΩ
L
R
= 100Ω
L
R
= 75Ω
F
R
= 1kΩ AND C = 2.2pF
F
F
0.1M
1M
10M
100M
1G
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 11. Large Signal Frequency Response vs. Frequency and
Load, Noninverting (See Figure 49)
Figure 14. Small Signal Frequency Response vs. Frequency and RF,
Noninverting, VOUT = 50 mV p-p (See Figure 48)
9
15
+85°C
G = +2
G = +2
12
8
7
6
5
4
3
2
1
0
+25°C
9
6
3
–40°C
V
=
OUT
50mV p-p
R
= 49.9Ω
S
+85°C
0
–3
V
=
OUT
2V p-p
R
= 100Ω
–6
S
+25°C
–9
R
= 249Ω
S
–12
–15
–40°C
–1
1M
10M
100M
1G
0.1M
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 12. Frequency Response vs. Frequency, Temperature, and
VOUT, Noninverting (See Figure 48)
Figure 15. Small Signal Frequency Response vs. Frequency and RS,
Noninverting, VOUT = 50 mV p-p (See Figure 48)
18
100
50pF
G = +2
15
12
9
90
80
70
60
50
40
30
20
10
0
30pF
20pF
10pF
180
135
90
6
3
0pF
0
45
–3
–6
–9
–12
0
–45
–90
–135
100M
10M
FREQUENCY (Hz)
1M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 13. Small Signal Frequency Response vs.
Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p
(See Figure 49 and Figure 71)
Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 Ω,
RF = 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50)
Rev. F | Page 10 of 28
AD8021
6.4
6.2
6.0
5.8
5.6
5.4
–20
–30
G = +2
V
= ±2.5V
S
–40
f1
f2
–50
P
Δf = 0.2MHz
OUT
–60
976Ω
–70
V
= ±5V
53.6Ω
50Ω
S
V
= ±12V
S
–80
–90
–100
–110
–120
1M
10M
FREQUENCY (Hz)
100M
9.5
9.7
10.0
FREQUENCY (MHz)
10.3
10.5
Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p,
RL = 150 Ω, Noninverting (See Figure 49)
Figure 20. Intermodulation Distortion vs. Frequency
50
45
40
35
30
25
20
–20
–30
–40
–50
–60
SECOND
V
= ±5V
S
–70
R
= 100Ω
L
–80
R
= 1kΩ
L
V
= ±2.5V
S
–90
–100
–110
–120
–130
THIRD
0
5
10
FREQUENCY (MHz)
15
20
0.1M
1M
FREQUENCY (Hz)
10M
20M
Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL
Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage
–30
–40
–50
–60
–50
–60
–70
SECOND
–70
–80
THIRD
= ±2.5V
–80
–90
R
= 100Ω
SECOND
L
V
S
THIRD
–90
SECOND
SECOND
–100
–110
–120
–130
–100
–110
–120
V
= ±5V
S
R
= 1kΩ
L
V
= ±12V
S
SECOND
THIRD
THIRD
100k
1M
FREQUENCY (Hz)
10M
20M
1
2
3
V
4
5
6
(V p-p)
OUT
Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS
Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL
Rev. F | Page 11 of 28
AD8021
–50
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
–3.1
–3.2
–3.3
–3.4
–3.5
–3.6
–3.7
–3.8
–60
SECOND
POSITIVE OUTPUT
–70
fC = 5MHz
–80
THIRD
SECOND
–90
fC = 1MHz
–100
–110
–120
NEGATIVE OUTPUT
1600
THIRD
2
0
400
800
LOAD (
1200
2000
1
3
V
4
5
6
(V p-p)
Ω)
OUT
Figure 23. Second and Third Harmonic Distortion vs. VOUT and
Fundamental Frequency (fC), G = +2
Figure 26. DC Output Voltages vs. Load (See Figure 48)
–40
120
100
80
–50
V
= ±12V
= ±5.0V
fC = 5MHz
S
–60
–70
SECOND
V
S
THIRD
60
40
20
0
–80
V
= ±2.5V
S
SECOND
fC = 1MHz
–90
THIRD
2
–100
–110
1
3
V
4
5
6
–50
–30
–10
10
30
50
70
90
110
(V p-p)
OUT
TEMPERATURE (°C)
Figure 24. Second and Third Harmonic Distortion vs. VOUT and
Fundamental Frequency (fC), G = +10
Figure 27. Short-Circuit Current to Ground vs. Temperature
–70
50
G = 2
40
fC = 1MHz
R
= 1kΩ
L
R
= 1kΩ, 150Ω
R
= R
L
F
G
–80
–90
30
20
10
G = +2
SECOND
THIRD
600
–100
–110
–120
–10
–20
–30
–40
–50
0
200
400
800
1000
0
40
80
120
TIME (ns)
160
200
FEEDBACK RESISTANCE (Ω)
Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF)
Figure 28. Small Signal Transient Response vs.
RL, VO = 50 mV p-p, Noninverting (See Figure 49)
Rev. F | Page 12 of 28
AD8021
V
G = 2
= 4V p-p
O
V
G = 2
= 2V p-p
O
2.0
1.0
2.0
1.0
R
= 1kΩ
L
R
= 150Ω
V
= ±2.5V
L
S
–1.0
–2.0
–1.0
–2.0
V
= ±5V
S
120
TIME (ns)
160
200
0
40
80
120
160
200
0
40
80
TIME (ns)
Figure 32. Large Signal Transient Response vs. VS (See Figure 48)
Figure 29. Large Signal Transient Response vs. RL, Noninverting
(See Figure 49)
5
V
= ±3V
IN
G = +2
V
= 4V p-p
O
G = –1
4
3
2
1
V
= 1V/DIV
= 2V/DIV
V
, R = 1kΩ
IN
OUT
L
V
OUT
V
IN
R
= 150Ω
L
–1
–2
–3
–4
–5
V
OUT
V
IN
100
0
200
300
400
500
0
50
100
150
200
250
TIME (ns)
TIME (ns)
Figure 33. Overdrive Recovery vs. RL (See Figure 49)
Figure 30. Large Signal Transient Response, Inverting (See Figure 50)
C
= 50pF
V = 4V p-p
O
G = 2
L
G = 2
2.0
1.0
C
= 10pF, 0pF
L
+0.01%
–0.01%
25ns
–1.0
–2.0
VERT = 0.2mV/DIV
HOR = 5ns/DIV
0
40
80
120
160
200
TIME (ns)
Figure 34. 0.01% Settling Time, 2 V Step
Figure 31. Large Signal Transient Response vs. CL (See Figure 48)
Rev. F | Page 13 of 28
AD8021
100
100
80
60
40
PULSE WIDTH = 120ns
PULSE WIDTH = 300µs
20
0
10
–20
–40
–60
–80
–100
5V
0V
t1
1
10
0
4
8
12
16
20
24
28
32
100
1k
10k
100k
1M
10M
TIME (µs)
FREQUENCY (Hz)
Figure 35. Long-Term Settling, 0 V to 5 V, VS = 12 V, G = +13
Figure 38. Input Current Noise vs. Frequency
50
0.48
0.44
0.40
0.36
0.32
0.28
0.24
G = +1
40
30
20
10
–10
–20
–30
–40
–50
–50
–25
0
25
50
75
100
0
40
80
120
TIME (ns)
160
200
TEMPERATURE (°C)
Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1
(See Figure 48)
Figure 39. VOS vs. Temperature
100
8.4
8.0
7.6
7.2
6.8
6.4
6.0
10
2.1nV/√Hz
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 37. Input Voltage Noise vs. Frequency
Figure 40. Input Bias Current vs. Temperature
Rev. F | Page 14 of 28
AD8021
0
–10
–20
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
–90
–100
–90
–110
–120
–100
10k
100k
1M
10M
100M
0.1M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. CMRR vs. Frequency (See Figure 51)
Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54)
300
100
30
300k
100k
30k
10k
3k
10
3
1
1k
0.3
0.1
0.03
0.01
0.003
300
100
30
10
3
10k
10k
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. Output Impedance vs. Frequency, Chip Enabled
(See Figure 52)
Figure 45. Output Impedance vs. Frequency, Chip Disabled
(See Figure 55)
0
DISABLE
4V
2V
–10
–PSRR
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
OUTPUT
V
= ±2.5V
+PSRR
= ±12V
S
2V
1V
V
S
tEN = 45ns
tDIS = 50ns
V
= ±5V
S
0
100
200
300
TIME (ns)
400
500
10k
100k
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53)
Figure 46. PSRR vs. Frequency and Supply Voltage
(See Figure 56 and Figure 57)
Rev. F | Page 15 of 28
AD8021
8.5
8.0
7.5
7.0
6.5
6.0
5.5
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 47. Quiescent Supply Current vs. Temperature
Rev. F | Page 16 of 28
AD8021
TEST CIRCUITS
+V
C
S
AD8021
+V
S
50Ω CABLE
HP8753D
R
S
50Ω CABLE
R
NETWORK
ANALYZER
O
50Ω
5
R
C
100Ω
IN
5
50Ω
R
D
49.9Ω
C
C
–V
S
R
C
7pF
F
R
G
–V
S
R
499Ω
G
R
F
F
499Ω
Figure 48. Noninverting Gain
Figure 52. Output Impedance, Chip Enabled
FET
PROBE
AD8021
+V
+V
S
S
50Ω CABLE
49.9Ω
R
S
50Ω
1
49.9Ω
976Ω
1.0V
5
LOGIC REF
DISABLE
C
L
R
IN
49.9Ω
8
53.6Ω
R
5
L
C
C
C
C
4V
49.9Ω
–V
S
7pF
R
–V
S
F
R
G
499Ω
499Ω
C
F
Figure 49. Noninverting Gain and FET Probe
Figure 53. Enable/Disable
+V
S
HP8753D
50Ω CABLE
R
NETWORK
ANALYZER
O
49.9Ω
5
R
D
50Ω
50Ω
C
50Ω CABLE
–V
C
S
50Ω CABLE
+V
S
R
50Ω
R
F
G
R
IN
49.9Ω
49.9Ω
49.9Ω
AD8021
FET
PROBE
1
8
LOGIC REF
DISABLE
Figure 50. Inverting Gain
1kΩ
5
C
7pF
C
–V
HP8753D
S
NETWORK
ANALYZER
499Ω
499Ω
Figure 54. Input-to-Output Isolation, Chip Disabled
50Ω
50Ω
AD8021
49.9Ω
+V
S
AD8021
1
HP8753D
499Ω
+V
NETWORK
ANALYZER
S
8
499Ω
5
C
C
100Ω
50Ω
5
7pF
–V
S
C
C
7pF
499Ω
499Ω
55.6Ω
–V
S
Figure 55. Output Impedance, Chip Disabled
Figure 51. CMRR
Rev. F | Page 17 of 28
AD8021
BIAS
BNC
BIAS
BNC
HP8753D
NETWORK
ANALYZER
HP8753D
NETWORK
ANALYZER
50Ω
50Ω
ꢀ
50Ω
+V
50Ω
–V
S
S
50Ω CABLE
50Ω CABLE
+V
S
49.9Ω, 5W
976Ω
+V
S
249Ω
5
976Ω
53.6Ω
249Ω
5
53.6Ω
C
7pF
C
–V
S
C
7pF
C
49.9Ω
5W
–V
S
499Ω
499Ω
499Ω
499Ω
Figure 56. Positive PSRR
Figure 57. Negative PSRR
Rev. F | Page 18 of 28
AD8021
APPLICATIONS
degraded to about 20 MHz and the phase margin increases to
90° (Arrow B). However, by reducing CC to 0 pF, the bandwidth
and phase margin return to about 200 MHz and 60° (Arrow C),
respectively. In addition, the slew rate is dramatically increased,
as it roughly varies with the inverse of CC.
The typical voltage feedback op amp is frequency stabilized
with a fixed internal capacitor, CINTERNAL, using dominant pole
compensation. To a first-order approximation, voltage feedback
op amps have a fixed gain bandwidth product. For example, if
its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain
of G = +10, its bandwidth is only about 20 MHz. The AD8021 is
a voltage feedback op amp with a minimal CINTERNAL of about
1.± pF. By adding an external compensation capacitor, CC, the
user can circumvent the fixed gain bandwidth limitation of
other voltage feedback op amps.
10
9
8
7
6
Unlike the typical op amp with fixed compensation, the
AD8021 allows the user to:
5
4
3
•
Maximize the amplifier bandwidth for closed-loop gains
between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.
2
1
0
•
•
Optimize the trade-off between bandwidth and phase
margin for a particular application.
1
2
3
4
5
6
7
8
9
10
11
NOISE GAIN (V/V)
Figure 59. Suggested Compensation Capacitance vs. Gain for
Maintaining 1 dB Peaking
Match bandwidth in gain blocks with different noise gains,
such as when designing differential amplifiers (as shown in
Figure 6±).
Table 6 and Figure ±9 provide recommended values of com-
pensation capacitance at various gains and the corresponding
slew rate, bandwidth, and noise. Note that the value of the
compensation capacitor depends on the circuit noise gain, not
the voltage gain. As shown in Figure 60, the noise gain, GN, of
an op amp gain block is equal to its noninverting voltage gain,
regardless of whether it is actually used for inverting or nonin-
verting gain. Thus,
110
100
180
135
90
45
0
90
86
80
(A)
(C)
(B)
C
= 0pF
C
70
60
50
40
30
20
10
0
C
= 10pF
C
Noninverting GN = RF/RG + 1
Inverting GN = RF/RG + 1
(C)
R
R
F
G
249Ω
1kΩ
R
S
3
(B)
+
–
1
2
3
(A)
6
–
+
–10
1k
AD8021
10k
100k
1M
10M
100M
1G
10G
6
5
FREQUENCY (Hz)
AD8021
2
R
1kΩ
F
–V
S
Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response
5
G = –4
–V
S
G
= +5
C
N
COMP
Figure ±8 is the AD8021 gain and phase plot that has been
simplified for instructional purposes. Arrow A in Figure ±8
shows a bandwidth of about 200 MHz and a phase margin at
about 60° when the desired closed-loop gain is G = +1 and
the value chosen for the external compensation capacitor is
CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at
10 pF, then (as expected for a typical op amp) the bandwidth is
R
G
249Ω
G = G = +5
N
C
COMP
NONINVERTING
INVERTING
Figure 60. The Noise Gain of Both is 5
Rev. F | Page 19 of 28
AD8021
CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49).
Table 6. Recommended Component Values
Noise Gain
−3 dB
Output Noise
Output Noise
(Noninverting
Gain)
SS BW (AD8021 Only)
(AD8021 with Resistors)
(nV/√Hz)
RS (Ω) RF (Ω) RG (Ω) CCOMP (pF)
Slew Rate (V/μs)
(MHz)
490
205
185
150
42
(nV/√Hz)
2.1
4.3
10.7
21.2
1
2
5
10
20
100
75
75
NA
10
7
120
150
300
420
200
34
2.8
8.2
15.5
27.9
52.7
264.1
49.9
49.9
49.9
49.9
49.9
499
1 k
1 k
1 k
1 k
499
249
110
52.3
10
2
0
0
0
42.2
6
211.1
With the AD8021, a variety of trade-offs can be made to fine-
tune its dynamic performance. Sometimes more bandwidth
or slew rate is needed at a particular gain. Reducing the
compensation capacitance, as illustrated in Figure 7, increases
the bandwidth and peaking due to a decrease in phase margin.
On the other hand, if more stability is needed, increasing the
compensation capacitor decreases the bandwidth while
increasing the phase margin.
Additionally, any resistance in series with the source creates a
pole with the input capacitance (as well as dampen high
frequency resonance due to package and board inductance
and capacitance), the effect of which is shown in Figure 1±.
It must also be noted that increasing resistor values increases
the overall noise of the amplifier and that reducing the feedback
resistor value increases the load on the output stage, thus
increasing distortion (see Figure 22).
As with all high speed amplifiers, parasitic capacitance and
inductance around the amplifier can affect its dynamic
USING THE DISABLE FEATURE
DISABLE
) is higher than Pin 1 (LOGIC
response. Often, the input capacitance (due to the op amp itself,
as well as the PC board) has a significant effect. The feedback
resistance, together with the input capacitance, can contribute
to a loss of phase margin, thereby affecting the high frequency
response, as shown in Figure 14. A capacitor (CF) in parallel
with the feedback resistor can compensate for this phase loss.
When Pin 8 (
REFERENCE) by approximately 2 V or more, the part is
enabled. When Pin 8 is brought down to within about 1.± V
of Pin 1, the part is disabled. See Table 1 for exact disable and
enable voltage levels. If the disable feature is not used, Pin 8 can
be tied to VS or a logic high source, and Pin 1 can be tied to
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part is in an enabled state.
Rev. F | Page 20 of 28
AD8021
THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog
Devices proprietary High Voltage eXtra-Fast Complementary
Bipolar (XFCB) process, which enables the construction of PNP
and NPN transistors with similar fTs in the 3 GHz region. The
transistors are dielectrically isolated from the substrate (and
each other), eliminating the parasitic and latch-up problems
caused by junction isolation. It also reduces nonlinear capaci-
tance (a source of distortion) and allows a higher transistor, fT,
for a given quiescent current. The supply current is trimmed,
which results in less part-to-part variation of bandwidth, slew
rate, distortion, and settling time.
PCB LAYOUT CONSIDERATIONS
As with all high speed op amps, achieving optimum performance
from the AD8021 requires careful attention to PC board layout.
Particular care must be exercised to minimize lead lengths
between the ground leads of the bypass capacitors and between
the compensation capacitor and the negative supply. Otherwise,
lead inductance can influence the frequency response and even
cause high frequency oscillations. Use of a multilayer printed
circuit board, with an internal ground plane, reduces ground
noise and enables a compact component arrangement.
Due to the relatively high impedance of Pin ± and low values of
the compensation capacitor, a guard ring is recommended. The
guard ring is simply a PC trace that encircles Pin ± and is
connected to the output, Pin 6, which is at the same potential as
Pin ±. This serves two functions. It shields Pin ± from any local
circuit noise generated by surrounding circuitry. It also
minimizes stray capacitance, which would tend to otherwise
reduce the bandwidth. An example of a guard ring layout is
shown in Figure 62.
As shown in Figure 61, the AD8021 input stage consists of an
NPN differential pair in which each transistor operates at a
0.8 mA collector current. This allows the input devices a high
transconductance; thus, the AD8021 has a low input noise of
2.1 nV/√Hz @ ±0 kHz. The input stage drives a folded cascode
that consists of a pair of PNP transistors. The folded cascode
and current mirror provide a differential-to-single-ended
conversion of signal current. This current then drives the high
impedance node (Pin ±), where the CC external capacitor is
connected. The output stage preserves this high impedance with
a current gain of ±000, so that the AD8021 can maintain a high
open-loop gain even when driving heavy loads.
Also shown in Figure 62, the compensation capacitor is located
immediately adjacent to the edge of the AD8021 package, spanning
Pin 4 and Pin ±. This capacitor must be a high quality surface-
mount COG or NPO ceramic. The use of leaded capacitors is
not recommended. The high frequency bypass capacitor(s)
should be located immediately adjacent to the supplies,
Pin 4 and Pin 7.
Two internal diode clamps across the inputs (Pin 2 and Pin 3)
protect the input transistors from large voltages that could
otherwise cause emitter-base breakdown, which would result in
degradation of offset voltage and input bias current.
To achieve the shortest possible lead length at the inverting
input, the feedback resistor RF is located beneath the board and
spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of Resistor RG should be situated as close
as possible to the return node of the negative supply bypass
capacitor connected to Pin 4.
+V
S
OUTPUT
+IN
–IN
(TOP VIEW)
BYPASS
CAPACITOR
LOGIC REFERENCE
1
2
3
4
8
7
6
5
DISABLE
C
1.5pF
INTERNAL
+V
–IN
+IN
S
–V
S
V
OUT
GROUND
PLANE
C
COMP
C
C
–V
S
C
COMP
Figure 61. Simplified Schematic
METAL
BYPASS
CAPACITOR
COMPENSATION
CAPACITOR
GROUND
PLANE
Figure 62. Recommended Location of
Critical Components and Guard Ring
Rev. F | Page 21 of 28
AD8021
Table 8. Summary of ADC Driver Performance
(fC = 100 kHz, VOUT = 20 V p-p)
DRIVING 16-BIT ADCs
Low noise and adjustable compensation make the AD8021
especially suitable as a buffer/driver for high resolution ADCs.
Parameter
Measurement
Unit
dBc
dBc
dBc
dBc
Second Harmonic Distortion
−92.6
As seen in Figure 19, the harmonic distortion is better than 90 dBc
at frequencies between 100 kHz and 1 MHz. This is an
Third Harmonic Distortion
THD
SFDR
−86.4
−84.4
+5.4
advantage for complex waveforms that contain high frequency
information, because the phase and gain integrity of the sampled
waveform can be preserved throughout the conversion process.
The increase in loop gain results in improved output regulation
and lower noise when the converter input changes state during
a sample. This advantage is particularly apparent when using
16-bit high resolution ADCs with high sampling rates.
DIFFERENTIAL DRIVER
The AD8021 is uniquely suited as a low noise differential driver
for many ADCs, balanced lines, and other applications requiring
differential drive. If pairs of internally compensated op amps are
configured as inverter and follower, the noise gain of the inverter
is higher than that of the follower section, resulting in an
imbalance in the frequency response (see Figure 66).
Figure 63 shows a typical ADC driver configuration. The
AD8021 is in an inverting gain of −7.±, fC is 6± kHz, and its
output voltage is 10 V p-p. The results are listed in Table 7.
A better solution takes advantage of the external compensation
feature of the AD8021. By reducing the CCOMP value of the
inverter, its bandwidth can be increased to match that of the
follower, avoiding compromises in gain bandwidth and phase
delay. The inverting and noninverting bandwidths can be
closely matched using the compensation feature, thus
minimizing distortion.
+12V
+5V
3
+
6
IN
HI
590Ω
AD8021
–
5
2
C
C
10pF
AD7665
570kSPS
R
200Ω
R
1.5kΩ
G
F
–12V
Figure 6± illustrates an inverter-follower driver circuit operating
at a gain of 2, using individually compensated AD8021s. The
values of feedback and load resistors were selected to provide a
total load of less than 1 kΩ, and the equivalent resistances seen
at each op amp’s inputs were matched to minimize offset voltage
and drift. Figure 67 is a plot of the resulting ac responses of
driver halves.
50Ω
IN
HI
56pF
Figure 63. Inverting ADC Driver, Gain = −7.5, fC = 65 kHz
Table 7. Summary of ADC Driver Performance (fC = 65 kHz,
OUT = 10 V p-p)
V
Parameter
Measurement
−101.3
−109.5
−100.0
+100.3
Unit
dBc
dBc
dBc
dBc
249Ω
G = +2
3
+
V
IN
49.9Ω
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
6
AD8021
–
5
2
–V
S
7pF
499Ω
499Ω
V
OUT1
Figure 64 shows another ADC driver connection. The circuit
was tested with a noninverting gain of 10.1 and an output
voltage of approximately 20 V p-p for optimum resolution and
noise performance. No filtering was used. An FFT was
performed using Analog Devices evaluation software for the
AD766± 16-bit converter. The results are listed in Table 8.
1kΩ
232Ω
G = –2
3
2
+
6
V
AD8021
–
OUT2
5
1kΩ
–V
S
5pF
332Ω
664Ω
+12V
+5V
Figure 65. Differential Amplifier
50Ω
3
+
50Ω
6
IN
HI
AD8021
50Ω
5
F
2
–
C
C
AD7665
570kSPS
R
750Ω
–12V
ADC
R
G
82.5Ω
OPTIONAL C
F
IN
LO
Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
Rev. F | Page 22 of 28
AD8021
12
9
C1
+V
S
AD8021
R1
R2
C2
3
2
V
IN
6
6
5
V
OUT
3
0
G = –2
G = +2
C
C
–V
S
–3
–6
–9
–12
–15
–18
R
F
R
G
Figure 68. Schematic of a Second-Order, Low-Pass Active Filter
Table 9. Typical Component Values for Second-Order, Low-
Pass Active Filter of Figure 68
Gain R1
(Ω)
R2
(Ω)
RF
(Ω)
RG
(Ω)
C1
(nF)
C2
(nF)
CC
(pF)
100k
1M
10M
FREQUENCY (Hz)
100M
1G
2
5
71.5
44.2
215
365
499
365
499
90.9
10
10
10
10
7
2
Figure 66. AC Response of Two Identically Compensated High Speed Op
Amps Configured for a Gain of +2 and a Gain of −2
12
9
50
40
30
6
3
G = ±2
20
G = 5
0
–3
10
0
G = 2
–6
–10
–20
–30
–40
–50
–9
–12
–15
–18
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps
(Figure 66) Configured for a Gain of +2 and a Gain of −2,
(Note the Close Gain Match)
Figure 69. Frequency Response of the Filter Circuit of Figure 68
for Two Different Gains
DRIVING CAPACITIVE LOADS
USING THE AD8021 IN ACTIVE FILTERS
When the AD8021 drives a capacitive load, the high frequency
response can show excessive peaking before it rolls off. Two
techniques can be used to improve stability at high frequency
and reduce peaking. The first technique is to increase the
compensation capacitor, CC, which reduces the peaking while
maintaining gain flatness at low frequencies. The second
technique is to add a resistor, RSNUB, in series between the output
pin of the AD8021 and the capacitive load, CL. Figure 70 shows
the response of the AD8021 when both CC and RSNUB are used to
reduce peaking. For a given CL, Figure 71 can be used to
determine the value of RSNUB that maintains 2 dB of peaking in
the frequency response. Note, however, that using RSNUB attenuates
the low frequency output by a factor of RLOAD/(RSNUB + RLOAD).
The low noise and high gain bandwidth of the AD8021 make it
an excellent choice in active filter circuits. Most active filter
literature provides resistor and capacitor values for various
filters but neglects the effect of the op amp’s finite bandwidth on
filter performance; ideal filter response with infinite loop gain is
implied. Unfortunately, real filters do not behave in this manner.
Instead, they exhibit finite limits of attenuation, depending on
the gain bandwidth of the active device. Good low-pass filter
performance requires an op amp with high gain bandwidth for
attenuation at high frequencies, and low noise and high dc gain
for low frequency, pass-band performance.
Figure 68 shows the schematic of a 2-pole, low-pass active filter
and lists typical component values for filters having a Bessel-
type response with a gain of 2 and a gain of ±. Figure 69 is a
network analyzer plot of this filter’s performance.
Rev. F | Page 23 of 28
AD8021
18
20
18
16
14
12
10
8
FET
PROBE
+V
S
16
C
R
= 7pF;
= 0
C
R
SNUB
5
6
Ω
49.9
Ω
SNUB
14
49.9
Ω
R
L
33pF
C
R
= 8pF;
C
1kΩ
12
10
–V
= 0
Ω
S
SNUB
C
C
499Ω
499
Ω
8
6
4
2
0
6
4
C
R
= 8pF;
C
2
= 17.4Ω
SNUB
0
0.1
1.0
10
FREQUENCY (MHz)
100
1000
0
5
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD (pF)
Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF
Figure 71. Relationship of RSNUB vs. CL for 2 dB Peaking at a Gain of +2
Rev. F | Page 24 of 28
AD8021
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 72. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 73. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8021AR
Temperature Range
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
Package Option
Branding
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
AD8021AR-REEL
AD8021AR-REEL7
AD8021ARZ1
AD8021ARZ-REEL1
AD8021ARZ-REEL71
AD8021ARM
AD8021ARM-REEL
AD8021ARM-REEL7
AD8021ARMZ1
AD8021ARMZ-REEL1
AD8021ARMZ-REEL71
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
HNA
HNA
HNA
HNA#
HNA#
HNA#
1Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. F | Page 25 of 28
AD8021
NOTES
Rev. F | Page 26 of 28
AD8021
NOTES
Rev. F | Page 27 of 28
AD8021
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01888-0-5/06(F)
Rev. F | Page 28 of 28
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