AD8030ARJ-R2 [ADI]
Low Power, High Speed Rail-to-Rail Input/Output Amplifier; 低功耗，高速轨到轨输入/输出放大器
| 型号： | AD8030ARJ-R2 |
| 厂家： | 
ADI |
| 描述： | Low Power, High Speed Rail-to-Rail Input/Output Amplifier |
| 文件： | 总20页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, High Speed
Rail-to-Rail Input/Output Amplifier
AD8029/AD8030/AD8040
CONNECTION DIAGRAMS
FEATURES
Low power
1.3 mA supply current/amplifier
High speed
125 MHz, –3 dB bandwidth (G = +1)
60 V/µs slew rate
NC
–IN
+IN
1
2
3
4
8
7
6
5
DISABLE
V
1
2
3
6
5
4
+V
S
OUT
+V
V
S
OUT
–V
S
DISABLE
–IN
+
–
–V
S
NC
+IN
NC = NO CONNECT
80 ns settling time to 0.1%
Rail-to-rail input and output
No phase reversal, inputs 200 mV beyond rails
Wide supply range: 2.7 V to 12 V
Offset voltage: 6 mV max
Low input bias current
+0.7 µA to –1.5 µA
Small packaging
SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14
Figure 1. SOIC-8 (R)
Figure 2. SC70-6 (KS)
V
1
1
14
V
OUT
4
OUT
–IN 1
2
13 –IN 4
12 +IN 4
+IN 1
3
4
5
6
7
+V
S
11
V
1
1
8
7
6
5
–V
+V
+V
OUT
S
S
+IN 2
–IN 2
10
–IN 1
+IN 1
2
3
4
+IN 3
2
OUT
9
8
–IN 3
–IN 2
+IN 2
APPLICATIONS
Battery-powered instrumentation
Filters
–V
S
V
2
V
3
OUT
OUT
Figure 3. SOIC-8(R) and
SOT23-8 (RJ)
Figure 4. SOIC-14 (R) and
TSSOP-14 (RU)
A-to-D drivers
Buffering
GENERAL DESCRIPTION
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output high speed amplifiers with a
quiescent current of only 1.3 mA per amplifier. Despite their
low power consumption, the amplifiers provide excellent
performance with 125 MHz small signal bandwidth and
60 V/µs slew rate. ADI’s proprietary XFCB process enables high
speed and high performance on low power.
powered systems with large bandwidth requirements to high
speed systems where component density requires lower power
dissipation.
The AD8029/AD8030 are the only low power, rail-to-rail input
and output high speed amplifiers available in SOT23 and SC70
micro packages. The amplifiers are rated over the extended
industrial temperature range, –40°C to +125°C.
This family of amplifiers exhibits true single-supply operation
with rail-to-rail input and output performance for supply
voltages ranging from 2.7 V to 12 V. The input voltage range
extends 200 mV beyond each rail without phase reversal. The
dynamic range of the output extends to within 40 mV of each
rail.
5.0
INPUT
4.5
OUTPUT
4.0
3.5
3.0
2.5
2.0
1.5
The AD8029/AD8030/AD8040 provide excellent signal quality
with minimal power dissipation. At G = +1, SFDR is –72 dBc at
1 MHz and settling time to 0.1% is only 80 ns. Low distortion
and fast settling performance make these amplifiers suitable
drivers for single-supply A/D converters.
1.0
G = +1
V
R
= +5V
0.5
0
S
The versatility of the AD8029/AD8030/AD8040 allows the user
to operate the amplifiers on a wide range of supplies while
consuming less than 6.5 mW of power. These features extend
the operation time in applications ranging from battery-
= 1kΩ TIED TO MIDSUPPLY
1µs/DIV
L
TIME (µs)
03679-A-010
Figure 5. Rail-to-Rail Response
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8029/AD8030/AD8040
TABLE OF CONTENTS
Specifications..................................................................................... 3
Specifications with ±± V Supply................................................. 3
Specifications with +± V Supply................................................. 4
Specifications with +3 V Supply................................................. ±
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 1±
Input Stage................................................................................... 1±
Output Stage................................................................................ 1±
Applications..................................................................................... 16
Wideband Operation ................................................................. 16
Output Loading sensitivity........................................................ 16
Disable Pin .................................................................................. 17
Circuit Considerations .............................................................. 18
Design Tools and Technical Support....................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide............................................................................... 20
ESD Caution................................................................................ 20
REVISION HISTORY
Revision A
11/03—Data Sheet Changed from Rev. 0 to Rev. A
Change
Page
Added AD8040 part .......................................................Universal
Change to Figure ± ....................................................................... 1
Changes to Specifications............................................................ 3
Changes to Figures 10–12............................................................ 7
Change to Figure 14 ..................................................................... 8
Changes to Figures 20 and 21 ..................................................... 9
Inserted new Figure 36............................................................... 11
Change to Figure 40 ................................................................... 12
Inserted new Figure 41............................................................... 12
Added Output Loading Sensitivity section............................. 16
Changes to Table ±...................................................................... 17
Changes to Power Supply Bypassing section .......................... 18
Changes to Ordering Guide ...................................................... 20
Rev. A | Page 2 of 20
AD8029/AD8030/AD8040
SPECIFICATIONS
SPECIFICATIONS WITH 5 V SUPPLY
Table 1. VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted. All specifications are per amplifier.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.1 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.1 V p-p
G = +1, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
80
14
125
19
6
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
62
63
80
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
fC = 1 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
f = 100 kHz
–74
–56
16.5
1.1
dBc
dBc
nV/√
pA/√
dB
Input Voltage Noise
Input Current Noise
Hz
Hz
f = 100 kHz
Crosstalk (AD8030/AD8040)
DC PERFORMANCE
f = 5 MHz, VIN = 2 V p-p
–79
Input Offset Voltage
PNP Active, VCM = 0 V
NPN Active, VCM = 4.5 V
TMIN to TMAX
1.6
2
5
6
mV
mV
Input Offset Voltage Drift
Input Bias Current1
30
0.7
1
µV/°C
µA
NPN Active, VCM = 4.5 V
TMIN to TMAX
1.3
µA
PNP Active, VCM = 0 V
TMIN to TMAX
–1.7
2
–2.8
0.9
µA
µA
Input Offset Current
Open-Loop Gain
0.1
74
µA
Vo = 4.0 V
65
80
dB
INPUT CHARACTERISTICS
Input Resistance
6
MΩ
pF
V
Input Capacitance
2
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
–5.2 to +5.2
90
VCM = –4.5 V to +3 V, RL = 10 kΩ
dB
DISABLE
PIN (AD8029)
DISABLE
–VS + 0.8
–6.5
V
Low Voltage
Low Current
High Voltage
High Current
DISABLE
µA
V
DISABLE
DISABLE
–VS + 1.2
0.2
µA
ns
Turn-Off Time
DISABLE
150
50% of
VIN = –1 V, G = –1
DISABLE
to <10% of Final VO,
Turn-On Time
85
ns
50% of
VIN = –1 V, G = –1
to <10% of Final VO,
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
VIN = +6 V to –6 V, G = –1
RL = 1 kΩ
55/45
ns
V
Output Voltage Swing
–VS + 0.22
–VS + 0.05
+VS – 0.22
+VS – 0.05
RL = 10 kΩ
V
Short-Circuit Current
Off Isolation (AD8029)
Capacitive Load Drive
POWER SUPPLY
Sinking and Sourcing
170/160
–55
mA
dB
pF
DISABLE
= Low
VIN = 0.1 V p-p, f = 1 MHz,
30% Overshoot
20
Operating Range
2.7
73
12
V
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1.4
150
80
1.5
200
mA
µA
dB
DISABLE
Vs 1 V
= Low
1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.
Rev. A | Page 3 of 20
AD8029/AD8030/AD8040
SPECIFICATIONS WITH +5 V SUPPLY
Table 2. VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.1 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.1 V p-p
G = +1, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
80
13
120
18
6
55
60
82
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
fC = 1 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
f = 100 kHz
–73
–55
16.5
1.1
dBc
dBc
nV/√
pA/√
dB
Input Voltage Noise
Input Current Noise
Hz
Hz
f = 100 kHz
Crosstalk (AD8030/AD8040)
DC PERFORMANCE
f = 5 MHz, VIN = 2 V p-p
-79
Input Offset Voltage
PNP Active, VCM = 2.5 V
NPN Active, VCM = 4.5 V
TMIN to TMAX
NPN Active, VCM = 4.5 V
TMIN to TMAX
1.4
1.8
25
0.8
1
5
6
mV
mV
µV/°C
µA
Input Offset Voltage Drift
Input Bias Current1
1.2
µA
PNP Active, VCM = 2.5 V
TMIN to TMAX
–1.8
2
0.1
74
–2.8
0.9
µA
µA
µA
dB
Input Offset Current
Open-Loop Gain
Vo = 1 V to 4 V
65
80
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
6
2
MΩ
pF
V
–0.2 to +5.2
90
VCM = 0.25 V to 2 V, RL = 10 kΩ
dB
DISABLE
PIN (AD8029)
DISABLE
–VS + 0.8
–6.5
V
Low Voltage
Low Current
High Voltage
High Current
DISABLE
µA
V
DISABLE
DISABLE
–VS + 1.2
0.2
µA
ns
Turn-Off Time
DISABLE
155
50% of
VIN = –1 V, G = –1
DISABLE
to <10% of Final VO,
Turn-On Time
90
ns
50% of
VIN = –1 V, G = –1
to <10% of Final VO,
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
VIN = –1 V to +6 V, G = –1
RL = 1 kΩ
RL = 10 kΩ
45/50
ns
V
V
Output Voltage Swing
–VS + 0.17
–VS + 0.04
+VS – 0.17
+VS – 0.04
Short-Circuit Current
Off Isolation (AD8029)
Capacitive Load Drive
POWER SUPPLY
Sinking and Sourcing
Vin = 0.1 V p-p, f = 1 MHz,
30% Overshoot
95/60
–55
15
mA
dB
pF
DISABLE
= Low
Operating Range
2.7
73
12
1.5
200
V
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1.3
140
80
mA
µA
dB
DISABLE
VS 1 V
= Low
1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.
Rev. A | Page 4 of 20
AD8029/AD8030/AD8040
SPECIFICATIONS WITH +3 V SUPPLY
Table 3. VS = +3 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.1 V p-p
G = +1, VO = 2 V p-p
G = +2, VO = 0.1 V p-p
G = +1, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step
80
13
112
18
6
55
57
110
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
fC = 1 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
f = 100 kHz
–72
–60
16.5
1.1
dBc
dBc
nV/√
pA/√
dB
Input Voltage Noise
Input Current Noise
Hz
Hz
f = 100 kHz
Crosstalk (AD8030/AD8040)
DC PERFORMANCE
f = 5 MHz, VIN = 2 V p-p
-80
Input Offset Voltage
PNP Active, VCM = 1.5 V
NPN Active, VCM = 2.5 V
TMIN to TMAX
NPN Active, VCM = 2.5 V
TMIN to TMAX
1.1
1.6
24
0.7
1
–1.5
1.6
0.1
73
5
6
mV
mV
µV/°C
µA
µA
µA
µA
µA
dB
Input Offset Voltage Drift
Input Bias Current1
1.2
Input Bias Current1
PNP Active, VCM = 1.5 V
TMIN to TMAX
–2.5
0.9
Input Offset Current
Open-Loop Gain
Vo = 0.5 V to 2.5 V
64
78
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
6
2
MΩ
pF
V
–0.2 to +3.2
88
VCM = 0.25 V to 1.25 V, RL = 10 kΩ
dB
DISABLE
PIN (AD8029)
DISABLE
–VS + 0.8
–6.5
V
Low Voltage
Low Current
High Voltage
High Current
DISABLE
µA
V
DISABLE
DISABLE
–VS + 1.2
0.2
µA
ns
Turn-Off Time
DISABLE
165
50% of
VIN = –1 V, G = –1
DISABLE
to <10% of Final VO,
Turn-On Time
95
ns
50% of
VIN = –1 V, G = –1
to <10% of Final VO,
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
VIN = –1 V to +4 V, G = –1
RL = 1 kΩ
RL = 10 kΩ
75/100
ns
V
V
Output Voltage Swing
–VS + 0.09
–VS + 0.04
+VS – 0.09
+VS – 0.04
Short-Circuit Current
Off Isolation (AD8029)
Capacitive Load Drive
POWER SUPPLY
Sinking and Sourcing
VIN = 0.1 V p-p, f = 1 MHz,
30% Overshoot
80/40
–55
10
mA
dB
pF
DISABLE
= Low
Operating Range
2.7
70
12
1.4
200
V
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1.3
145
76
mA
µA
dB
DISABLE
VS 1 V
= Low
1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin.
Rev. A | Page 5 of 20
AD8029/AD8030/AD8040
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8029/AD8030/AD8040 Stress Ratings
PD = Quiescent Power + (Total Drive Power – Load Power)
Parameter
Rating
Supply Voltage
Power Dissipation
12.6 V
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
See Figure 6
VS 0.5 V
1.8 V
–65°C to +125°C
–40°C to +125°C
300°C
PD
=
(
VS × IS
)
+
×
–
2
RL
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, then the total drive power is
VS × IOUT
.
If the rms signal levels are indeterminate, consider the worst
Junction Temperature
150°C
case, when VOUT = VS/4 for RL to midsupply:
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
(
VS/4
RL
)
PD
=
(
VS × IS +
)
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps, as discussed in
the PCB Layout section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8029/AD8030/
AD8040 package is limited by the associated rise in junction
temperature (TJ) on the die. The plastic encapsulating the die
locally reaches the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8029/AD8030/AD8040. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in silicon devices, potentially causing failure.
Figure 6 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
2.5
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die. The
junction temperature can be calculated as
2.0
SOIC-14
1.5
TSSOP-14
TJ = TA + (PD × θJA)
SOIC-8
1.0
SOT-23-8
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
SC70-6
0.5
0
–40–30–20–10
0
10 20 30 40 50 60 70 80 90 100 110120
AMBIENT TEMPERATURE (°C)
Figure 6. Maximum Power Dissipation
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8029/AD8030/AD8040 could cause catastrophic
failure.
Rev. A | Page 6 of 20
AD8029/AD8030/AD8040
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: VS = 5 V (TA = 25°C, RL = 1 kΩ tied to midsupply, unless otherwise noted.)
1
0
0.2
R
= 1kΩ
F
DASHED LINES: V
SOLID LINES: V
= 2V p-p
OUT
G = –1
= 0.1V p-p
R
= R = 1kΩ
0.1
OUT
F
G
–1
–2
0
G = +10
–3
R
= 9kΩ, R = 1kΩ
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
F
G
–4
G = +1
–5
G = +1
G = +2
= R = 1kΩ
–6
R
= 0Ω
R
F
F
G
–7
–8
G = +2
–9
–10
–11
–12
–13
–14
V
= 0.1V p-p
O
0.1
1
10
100
1000
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
03679-0-004
03679-A-011
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. 0.1 dB Flatness Frequency Response
1
1
0
G = +1
= 0.1V p-p
+3V
G = +2
V
O
V
= 0.1V p-p
O
0
–1
–2
–3
–4
–5
–6
–7
–8
R
= 1kΩ
F
±5V
–1
–2
–3
–4
–5
–6
–7
–8
±5V
+5V
+5V
+3V
1
10
100
1000
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
03679-0-005
03679-A-012
Figure 8. Small Signal Frequency Response for Various Supplies
Figure 11. Small Signal Frequency Response for Various Supplies
1
1
G = +1
G = +2
V = 2V p-p
O
R
= 1kΩ
F
V
= 2V p-p
O
0
–1
–2
–3
–4
–5
–6
–7
–8
0
–1
–2
–3
–4
–5
–6
–7
–8
±5V
V
= ±5
S
+3V
V
= +5
S
V
= +3
S
+5V
1
10
FREQUENCY (MHz)
100
1
10
100
FREQUENCY (MHz)
03679-0-006
03679-A-013
Figure 9. Large Signal Frequency Response for Various Supplies
Figure 12. Large Signal Frequency Response for Various Supplies
Rev. A | Page 7 of 20
AD8029/AD8030/AD8040
6
2
1
G = +1
5
G = +1
V = 0.1V p-p
O
V
= V – 0.2V
S+
ICM
V
= 0.1V p-p
O
20pF
10pF
4
3
V
= 0V
ICM
0
2
–1
–2
–3
–4
–5
–6
–7
–8
5pF
1
V
= V + 0.2V
S–
ICM
0
–1
–2
–3
–4
–5
–6
–7
–8
0pF
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
03679-0-010
03679-0-013
Figure 13. Small Signal Frequency Response for Various CLOAD
Figure 16. Small Signal Frequency Response for Various
Input Common-Mode Voltages
1
2
G = +2
G = +1
= 0.1V p-p
+125°C
+85°C
+25°C
R
= 1kΩ
F
V
0
–1
–2
–3
–4
–5
–6
–7
–8
O
1
0
–40°C
–1
–2
–3
–4
–5
–6
2V p-p
1V p-p
0.1V p-p
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
03679-A-014
03679-0-014
Figure 14. Frequency Response for Various Output Amplitudes
Figure 17. Small Signal Frequency Response vs. Temperature
80
225
180
135
90
1
G = +1
V
= 2V p-p
70
60
50
40
30
20
10
0
O
0
–1
–2
–3
–4
–5
–6
–7
–8
+125°C
+25°C
+85°C
–40°C
45
–10
–20
0
1G
10
100
1k
10k
100k
1M
10M
100M
1
10
FREQUENCY (MHz)
100
FREQUENCY (Hz)
03679-0-054
03679-0-015
Figure 15. Open-Loop Gain and Phase vs. Frequency
Figure 18. Large Signal Frequency Response vs. Temperature
Rev. A | Page 8 of 20
AD8029/AD8030/AD8040
–40
–50
–35
–45
–55
–65
–75
–85
–95
–105
G = +1
= 2V p-p
SECOND HARMONIC: SOLID LINE
G = +1
= 2V p-p
V
V
OUT
OUT
R
= 1kΩ
L
THIRD HARMONIC: DASHED LINE
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–60
–70
R
= 1kΩ
L
V
= +3V
S
–80
–90
V
= +5V
R
= 5kΩ
S
L
V
= ±5V
S
–100
–110
R
= 2kΩ
L
0.01
0.1
FREQUENCY (MHz)
1
10
0.01
0.1
FREQUENCY (MHz)
1
10
03679-0-016
03679-0-075
Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage
Figure 22. Harmonic Distortion vs. Frequency and Load
–40
–40
G = +2
FREQ = 1MHz
G = +1
= 2V p-p
FREQ = 1MHz
V
OUT
R
= 1kΩ
–45
–50
–55
–60
–65
–70
–75
–80
F
–50
–60
V
= +5V
V = +10V
S
S
V
= +3V
V = +5V
S
S
V
= +3V
S
–70
–80
–90
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–100
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT AMPLITUDE (V p-p)
03679-A-015
INPUT COMMON-MODE VOLTAGE (V)
03679-0-020
Figure 23. Harmonic Distortion vs. Input Common Mode Voltage
Figure 20. Harmonic Distortion vs. Output Amplitude
1000
100
10
1
–30
–40
V
V
R
R
= +5V
S
= 2.0V p-p
OUT
= 1kΩ
= 1kΩ
L
F
–50
G = +2
G = –1
100
10
1
–60
–70
VOLTAGE NOISE
CURRENT NOISE
–80
–90
G = +1
–100
–110
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
0.1
10M
10
100
1k
10k
100k
1M
0.01
0.1
FREQUENCY (MHz)
1
10
FREQUENCY (Hz)
03679-0-069
03679-A-016
Figure 24. Voltage and Current Noise vs. Frequency
Figure 21. Harmonic Distortion vs. Frequency and Gain
Rev. A | Page 9 of 20
AD8029/AD8030/AD8040
100
100
75
G = +1
= ±2.5V
G = +1
C
C
= 20pF
= 10pF
L
L
V
V
= ±2.5V
S
S
75
50
C
= 5pF
L
50
25
25
0
0
–25
–50
–75
–100
–25
–50
–75
–100
25mV/DIV
20ns/DIV
25mV/DIV
20ns/DIV
TIME (ns)
03679-0-025
TIME (ns)
03679-0-022
Figure 28. Small Signal Transient Response with Capacitive Load
Figure 25. Small Signal Transient Response
5.0
2.5
2.0
G = +1
= ±2.5V
INPUT
4V p-p
2V p-p
4.5
V
S
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
OUTPUT
G = +1
= +5V
V
0.5
0
S
R
= 1kΩ TIED TO MIDSUPPLY
1µs/DIV
L
0.5V/DIV
25ns/DIV
TIME (Seconds)
03679-0-059
TIME (ns)
Figure 29. Rail-to-Rail Response, G = +1
Figure 26. Large Signal Transient Response
4
3
4
3
G = +1
INPUT
G = –1 (R = 1kΩ)
INPUT
F
R
V
= 1kΩ
= ±2.5V
L
R
V
= 1kΩ
L
S
S
= ±2.5V
2
2
OUTPUT
OUTPUT
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
–4
1V/DIV
200ns/DIV
1V/DIV
200ns/DIV
TIME (ns)
03679-0-027
03679-0-024
TIME (ns)
Figure 30. Input Overdrive Recovery
Figure 27. Output Overdrive Recovery
Rev. A | Page 10 of 20
AD8029/AD8030/AD8040
V
(250mV/DIV)
G = +2
= ±2.5V
IN
G = +2
V
S
V
(500mV/DIV)
OUT
+1V
+0.1%
–0.1%
+0.1%
–0.1%
V
– 2V (0.1%/DIV)
IN
OUT
V
– 2V (0.1%/DIV)
IN
OUT
V
(500mV/DIV)
OUT
–1V
500ns/DIV
20ns/DIV
03679-0-062
03679-0-063
Figure 31. Long-Term Settling Time
Figure 34.0.1% Short-Term Settling Time
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
–40
–50
–60
–70
–80
–90
+PSRR
–PSRR
–100
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
03679-0-078
03679-0-033
Figure 32. Common-Mode Rejection Ratio vs. Frequency
Figure 35. PSRR vs. Frequency
–20
–30
–40
G = +1
= 1kΩ
V
IN
DRIVE AMP
R
L
50Ω
DISABLE = LOW
= 0.1V p-p
–30
–40
–50
–60
–70
–80
1kΩ
V
–50
IN
–60
LISTEN AMP
V
OUT
–70
1kΩ
–80
V
OUT
CROSSTALK = 20log
(
)
AD8030
(AMP 2 DRIVE
AMP 1 LISTEN)
V
IN
–90
–100
–110
–120
–130
AD8040
(AMP 4 DRIVE
AMP 1 LISTEN)
0.1
1
10
100
1000
0.01
0.1
1.0
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
03679-0-055
Figure 36. AD8030/AD8040 Crosstalk vs. Frequency
Figure 33. AD8029 Off-Isolation vs. Frequency
Rev. A | Page 11 of 20
AD8029/AD8030/AD8040
2.5
2.0
4
3
R
= 1kΩ TO
L
MIDSUPPLY
G = +1
V
= +5V
V
= +3V
V = +10V
S
S
S
V
= +3V
V
= +5V
V = +10V
S
1.5
1.0
S
S
2
1
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–1
–2
–3
–4
–1
0
1
2
3
4
5
6
7
8
9
10 11
–1
0
1
2
3
4
5
6
7
8
9
10 11
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
03679-0-074
03679-A-017
Figure 37. Input Bias Current vs. Input Common-Mode Voltage
Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage
–1.0
1.0
0.8
0.6
0.4
0.2
0
4
3
2
–1.2
–1.4
–1.6
–1.8
–2.0
NPN ACTIVE
V
= ±5V
S
1
0
V
= ±5
V
= +5
V = +3
S
S
S
V
= +5V
S
–1
–2
–3
–4
V
= +3V
S
PNP ACTIVE
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
03679-0-073
Figure 38. Input Bias Current vs. Temperature
Figure 41. Input Offset Voltage vs. Temperature
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
120
COUNT = 1088
MEAN = 0.44mV
STDEV = 1.05mV
100
80
60
40
20
0
V
= +5V
S
V
= ±5V
S
V
= +3V
S
–40
–20
0
20
40
60
80
100
120
–5
–4
–3
–2
–1
0
1
2
3
4
5
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)
03679-0-067
03679-0-064
Figure 39 Quiescent Supply Current vs. Temperature
Figure 42. Input Offset Voltage Distribution
Rev. A | Page 12 of 20
AD8029/AD8030/AD8040
1M
100k
10k
1k
1000
100
10
G = +1
DISABLE = LOW
100
10
1
1
100k
0.1
1k
10k
100k
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
03679-0-060
03679-0-061
Figure 45. Output Impedance vs. Frequency, Enabled
Figure 43. AD8029 Output Impedance vs. Frequency, Disabled
2.0
1.5
0.5
LOAD RESISTANCE TIED
TO MIDSUPPLY
V
=
±2.5V
S
0.4
0.3
0.2
1.0
V
– V
S
OL
OH
0.5
0.1
0
R
= 10kΩ
L
0
V
= +3V
V
= +5V
V = ±5V
S
S
S
R
= 1kΩ
L
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
V
– V
S
–2.5 –2.0 –1.5 –1.0 –0.5 –0
0.5
1.0
1.5
2.0
2.5
100
1000
10000
OUTPUT VOLTAGE (V)
LOAD RESISTANCE (Ω)
03679-0-072
03679-0-041
Figure 46. Input Error Voltage vs. Output Voltage
Figure 44. Output Saturation Voltage vs. Load Resistance
170
150
130
110
90
V
= ±5V
S
V
V
= +5V
= +3V
S
S
70
50
R
= 1kΩ TIED TO MIDSUPPLY
L
SOLID LINE: V – VOH
S+
DASHED LINE: VOL – V
S–
30
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
03679-0-066
Figure 42. Output Saturation Voltage vs. Temperature
Rev. A | Page 13 of 20
AD8029/AD8030/AD8040
1.5
1
0
DISABLE (–0.5V TO –2V)
V
= +3V, +5V, +10V
S
1.0
0.5
–1
–2
–3
–4
–5
–6
–7
R
R
R
= 100Ω
= 1kΩ
L
L
L
OUTPUT DISABLED
0
= 10kΩ
–0.5
–1.0
–1.5
V
= ±2.5V
S
G = –1 (R = 1kΩ)
F
0
50
100
150
200
250
300
350
0
0.8
1
1.2
2
3
TIME (ns)
DISABLE PIN VOLTAGE (V)
03679-A-020
03679-A-022
DISABLE
Figure 47. AD8029
Turn-Off Timing
DISABLE
DISABLE
Pin Voltage
Figure 49. AD8029
Pin Current vs.
1.5
1.0
DISABLE (–2V TO –0.5V)
OUTPUT ENABLED
0.5
0
R
= 100Ω
= 1kΩ
= 10kΩ
L
L
L
–0.5
–1.0
–1.5
R
R
V
= ±2.5V
S
G = –1 (R = 1kΩ)
F
0
50
100
150
200
250
300
350
TIME (ns)
03679-A-021
DISABLE
Figure 48. AD8029
Turn-On Timing
Rev. A | Page 14 of 20
AD8029/AD8030/AD8040
THEORY OF OPERATION
+V
S
R
TH
I
TAIL
SPD
+V –1.2V
S
DISABLE
Q
9
OUTPUT
BUFFER
R
R
R
R
1
2
3 4
I
TO DISABLE
CIRCUITRY
TH
–V
S
Q
10
AD8029 ONLY
IN–
M
TOP
Q
1
C
MT
Q
2
Q
Q
6
5
V
OUT
C
MB
Q
Q
Q
3
7
8
IN+
Q
4
M
BOT
R
R
R
R
Q
5
6
7 8
11
OUT
IN
COM
–V
S
03679-0-051
Figure 50. Simplified Schematic
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output amplifiers fabricated using Analog
Devices’ XFCB process. The XFCB process enables the AD8029/
AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a
120 MHz bandwidth and a 60 V/µs slew rate. A simplified sche-
matic of the AD8029/AD8030/AD8040 is shown in Figure 50.
OUTPUT STAGE
The currents derived from the PNP and NPN input differential
pairs are injected into the current mirrors MBOT and MTOP, thus
establishing a common-mode signal voltage at the input of the
output buffer.
The output buffer performs three functions:
INPUT STAGE
1. It buffers and applies the desired signal voltage to the
output devices, Q10 and Q11.
For input common-mode voltages less than a set threshold
(1.2 V below VCC), the resistor degenerated PNP differential pair
(comprising Q1 toQ4) carries the entire ITAIL current, allowing
the input voltage to go 200 mV below –VS. Conversely, input
common-mode voltages exceeding the same threshold cause
ITAIL to be routed away from the PNP differential pair and into
the NPN differential pair through transistor Q9. Under this
condition, the input common-mode voltage is allowed to rise
200 mV above +VS while still maintaining linear amplifier
behavior. The transition between these two modes of operation
leads to a sudden, temporary shift in input stage transconduc-
tance, gm, and dc parameters (such as the input offset voltage
VOS), which in turn adversely affect the distortion performance.
The SPD block shortens the duration of this transition, thus
improving the distortion performance. As shown in Figure 50,
the input differential pair is protected by a pair of two series
diodes, connected in anti-parallel, which clamp the differential
input voltage to approximately 1.5 V.
2. It senses the common-mode current level in the output
devices.
3. It regulates the output common-mode current by
establishing a common-mode feedback loop.
The output devices Q10 and Q11 work in a common-emitter
configuration, and are Miller-compensated by internal
capacitors, CMT and CMB
.
The output voltage compliance is set by the output devices’
collector resistance RC (about 25 Ω), and by the required load
current IL. For instance, a light equivalent load (5 kΩ) allows the
output voltage to swing to within 40 mV of either rail, while
heavier loads cause this figure to deteriorate as RC × IL.
Rev. A | Page 15 of 20
AD8029/AD8030/AD8040
APPLICATIONS
WIDEBAND OPERATION
R
F
For example, if using the values shown in Table 5 for a gain of 2,
with resistor values of 2.5 kΩ, the effective load at the output is
1.67 kΩ. For inverting configurations, only the feedback resistor
RF is in parallel with the output load. If the load is greater than
that specified in the data sheet, the amplifier can introduce
nonlinearities in its open-loop response, which increases
distortion. Figure 53 and Figure 54 illustrate effective output
loading and distortion performance. Increasing the resistance of
the feedback network can reduce the current consumption, but
has other implications.
C2
10µF
+V
S
C1
0.1µF
R
G
–
V
AD8029
OUT
R1
V
+
IN
DISABLE
C4
0.1µF
C3
R1 = R ||R
10µF
F
G
–40
V
V
= 5V
S
= 2.0V p-p
OUT
–V
03679-0-052
S
–50
–60
SECOND HARMONIC – SOLID LINES
THIRD HARMONIC – DOTTED LINES
Figure 51. Wideband Non-inverting Gain Configuration
R
F
–70
R
= 1kΩ
L
C2
10µF
+V
S
–80
–90
C1
0.1µF
R
= 5kΩ
L
–100
–110
–120
R
G
R
= 2.5kΩ
V
L
–
IN
V
AD8029
OUT
+
DISABLE
R1 = R ||R
C4
0.1µF
F
G
0.01
0.1
1.0
10
FREQUENCY (MHz)
R1
C3
10µF
Figure 53. Gain of 1 Distortion
–40
–50
V
V
= 5V
–V
03679-0-053
S
S
= 2.0V p-p
OUT
SECOND HARMONIC – SOLID LINES
THIRD HARMONIC – DOTTED LINES
Figure 52. Wideband Inverting Gain Configuration
–60
R
= R = 1kΩ
F
L
OUTPUT LOADING SENSITIVITY
–70
To achieve maximum performance and low power dissipation,
the designer needs to consider the loading at the output of
AD8029/AD8030/AD8040. Table 5 shows the effects of output
loading and performance.
–80
R
= R = 5kΩ
L
F
–90
–100
–110
–120
R
= R = 2.5kΩ
F
L
When operating at unity gain, the effective load at the amplifier
output is the resistance (RL) being driven by the amplifier. For
gains other than 1, in noninverting configurations, the feedback
network represents an additional current load at the amplifier
output. The feedback network (RF + RG) is in parallel with RL,
which lowers the effective resistance at the output of the
amplifier. The lower effective resistance causes the amplifier to
supply more current at the output. Lower values of feedback
resistance increase the current draw, thus increasing the
amplifier’s power dissipation.
0.01
0.1
1.0
10
FREQUENCY (MHz)
Figure 54. Gain of 2 Distortion
Rev. A | Page 16 of 20
AD8029/AD8030/AD8040
Table 5. Effect of Load on Performance
Noninverting
Gain
RF
(kΩ)
RG
(kΩ)
RLOAD
(kΩ)
–3 dB SS BW
(MHz)
Peaking
(dB)
HD2 at 1 MHz,
2 V p-p (dB)
HD3 at 1 MHz,
2 V p-p (dB)
Output Noise
(nV/√Hz)
1
1
1
2
2
2
–1
–1
–1
0
0
0
1
2.5
5
1
2.5
5
N/A
N/A
N/A
1
2.5
5
1
2.5
5
1
2
5
1
2.5
5
1
2.5
5
120
130
139
36
44.5
43
40
40
34
0.02
0.6
1
0
0.2
2
0.01
0.05
1
–80
–84
–87.5
–72
–79
–84
–68
–74
–78
–72
–83
–92.5
–60
–72.5
–86
–57
–68
–80
16.5
16.5
16.5
33.5
34.4
36
33.6
34
36
The feedback resistance (RF || RG) combines with the input
capacitance to form a pole in the amplifier’s loop response. This
can cause peaking and ringing in the amplifier’s response if the
RC time constant is too low. Figure 55 illustrates this effect.
Peaking can be reduced by adding a small capacitor (1 pF–4 pF)
across the feedback resistor. The best way to find the optimal
value of capacitor is to empirically try it in your circuit. Another
factor of higher resistance values is the impact it has on noise
performance. Higher resistor values generate more noise. Each
application is unique and therefore a balance must be reached
between distortion, peaking, and noise performance. Table 5
outlines the trade-offs that different loads have on distortion,
peaking, and noise performance. In gains of 1, 2, and 10,
equivalent loads of 1 kΩ, 2 kΩ, and 5 kΩ are shown.
DISABLE PIN
The AD8029 disable pin allows the amplifier to be shut down
for power conservation or multiplexing applications. When in
the disable mode, the amplifier draws only 150 µA of quiescent
current. The disable pin control voltage is referenced to the
negative supply. The amplifier enters power-down mode any
time the disable pin is tied to the most negative supply or within
0.8 V of the negative supply. If left open, the amplifier will
operate normally. For switching levels, refer to Table 6.
Table 6. Disable Pin Control Voltage
Supply Voltage
Disable Pin
Voltage
+3 V
+5 V
±5 V
Low
(Disabled)
High
(Enabled)
0 V to <0.8 V
1.2 V to 3 V
0 V to <0.8 V
1.2 V to 5 V
–5 V to <–4 .2 V
–3.8 V to +5 V
With increasing load resistance, the distortion and –3 dB
bandwidth improve, while the noise and peaking degrade
slightly.
2
V
V
= 5V
S
R
= R = 5kΩ
F
L
= 0.1V p-p
OUT
R
= 1kΩ
1
0
L
R
= 2.5kΩ
L
–1
–2
–3
–4
–5
–6
–7
–8
R
= R = 2.5kΩ
L
F
R
= 5kΩ
L
R
= R = 1kΩ
L
F
G = +1
G = +2
1
10
100
1000
FREQUENCY (MHz)
Figure 55. Frequency Response for Various Feedback/Load Resistances
Rev. A | Page 17 of 20
AD8029/AD8030/AD8040
CIRCUIT CONSIDERATIONS
PCB Layout
Power Supply Bypassing
High speed op amps require careful attention to PCB layout to
achieve optimum performance. Particular care must be
exercised to minimize lead lengths of the bypass capacitors.
Excess lead inductance can influence the frequency response
and even cause high frequency oscillations. Using a multilayer
board with an internal ground plane can help reduce ground
noise and enable a more compact layout.
Power supply pins are actually inputs to the op amp. Care must
be taken to provide the op amp with a clean, low noise dc
voltage source.
Power supply bypassing is employed to provide a low imped-
ance path to ground for noise and undesired signals at all
frequencies. This cannot be achieved with a single capacitor
type; but with a variety of capacitors in parallel the bandwidth
of power supply bypassing can be greatly extended. The bypass
capacitors have two functions:
To achieve the shortest possible trace length at the inverting
input, the feedback resistor, RF, should be located the shortest
distance from the output pin to the input pin. The return node
of the resistor RG should be situated as close as possible to the
return node of the negative supply bypass capacitor.
1. Provide a low impedance path for noise and undesired
signals from the supply pins to ground.
2. Provide local stored charge for fast switching conditions
and minimize the voltage drop at the supply pins during
transients. This is typically achieved with large electrolytic
capacitors.
On multilayer boards, all layers beneath the op amp should be
cleared of metal to avoid creating parasitic capacitive elements.
This is especially true at the summing junction, i.e., the inver-
ting input, –IN. Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.
Good quality ceramic chip capacitors should be used and
always kept as close as possible to the amplifier package. A
parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic
covers a wide range of rejection for unwanted noise. The 10 µF
capacitor is less critical for high frequency bypassing and, in
most cases, one per supply line is sufficient. The values of
capacitors are circuit-dependant and should be determined by
the system’s requirements.
Grounding
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and thus the high frequency impedance of
the path. Fast current changes in an inductive ground return
will create unwanted noise and ringing.
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to the design process by providing
technical support and online design tools. ADI offers technical
support via free evaluation boards, sample ICs, Spice models,
interactive evaluation tools, application notes, phone and email
support—all available at www.analog.com.
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
from ground, the load should be placed at the same physical
location as the bypass capacitor ground. For large values of
capacitors, which are intended to be effective at lower
frequencies, the current return path length is less critical.
Rev. A | Page 18 of 20
AD8029/AD8030/AD8040
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8.75 (0.3445)
8.55 (0.3366)
8
1
5
4
14
1
8
7
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0689)
1.35 (0.0531)
× 45°
ꢁ
ꢀ
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0039)
0.25 (0.0098)
8°
ꢀ
0.10 (0.0040)
0.51 (0.0201)
0.31 (0.0122)
ꢀ
0°
SEATING
PLANE
8°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8)
Dimensions shown in millimeters and (inches)
Figure 59. 14-Lead Standard Small Outline Package [SOIC] (R-14)
Dimensions shown in millimeters and (inches)
2.00 BSC
5.10
5.00
4.90
6
5
2
4
3
2.10 BSC
1.25 BSC
14
8
7
1
4.50
4.40
4.30
PIN 1
1.30 BSC
6.40
BSC
0.65 BSC
1.00
0.90
0.70
1
1.10 MAX
PIN 1
0.22
0.08
0.65
BSC
1.05
1.00
0.80
0.46
0.36
0.26
8°
4°
0°
0.30
0.15
0.20
0.09
1.20
MAX
0.10 MAX
SEATING
PLANE
0.75
0.60
0.45
8°
0°
0.15
0.05
0.10 COPLANARITY
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-203AB
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6)
Dimensions shown in millimeters
Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
PIN 1
2.80 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 58. 8-Lead Small Outline Transistor Package [SOT23] (RJ-8)
Dimensions shown in millimeters
Rev. A | Page 19 of 20
AD8029/AD8030/AD8040
ORDERING GUIDE
Model
Minimum Ordering Quantity
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
6-Lead SC70
6-Lead SC70
6-Lead SC70
8-Lead SOIC
8-Lead SOIC
Package Option
R-8
R-8
R-8
KS-6
KS-6
KS-6
R-8
R-8
R-8
RJ-8
RJ-8
RJ-8
R-14
R-14
R-14
Branding
AD8029AR
1
AD8029AR-REEL
AD8029AR-REEL7
AD8029AKS-R2
AD8029AKS-REEL
AD8029AKS-REEL7
AD8030AR
2,500
1,000
250
10,000
3,000
1
H6B
H6B
H6B
AD8030AR-REEL
AD8030AR-REEL7
AD8030ARJ-R2
AD8030ARJ-REEL
AD8030ARJ-REEL7
AD8040AR
2,500
1,000
250
10,000
3,000
1
8-Lead SOIC
8-Lead SOT23-8
8-Lead SOT23-8
8-Lead SOT23-8
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
H7B
H7B
H7B
AD8040AR-REEL
AD8040AR-REEL7
AD8040ARU
2500
1000
1
RU-14
RU-14
RU-14
AD8040ARU-REEL
AD8040ARU-REEL7
2500
1000
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03679–0–11/03(A)
Rev. A | Page 20 of 20
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