AD8042ACHIPS [ADI]
Dual 160 MHz Rail-to-Rail Amplifier; 双160 MHz轨到轨放大器
| 型号： | AD8042ACHIPS |
| 厂家： | 
ADI |
| 描述： | Dual 160 MHz Rail-to-Rail Amplifier |
| 文件： | 总15页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 160 MHz
a
Rail-to-Rail Amplifier
AD8042
CONNECTION DIAGRAM
8-Lead Plastic DIP and SOIC
FEATURES
Single AD8041 and Quad AD8044 also Available
Fully Specified at +3 V, +5 V, and ؎5 V Supplies
Output Swings to Within 30 mV of Either Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 0.5 V Beyond Supplies
Low Power of 5.2 mA per Amplifier
High Speed and Fast Settling on +5 V:
160 MHz –3 dB Bandwidth (G = +1)
200 V/s Slew Rate
+V
1
2
3
4
8
7
6
5
OUT1
–IN1
+IN1
S
OUT2
–IN2
+IN2
–V
S
AD8042
39 ns Settling Time to 0.1%
Good Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness of 0.1 dB to 14 MHz
0.02% Differential Gain Error
0.04؇ Differential Phase Error
Low Distortion
The output voltage swing extends to within 30 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 14 MHz while offering differ-
ential gain and phase error of 0.04% and 0.06° on a single +5 V
supply. This makes the AD8042 useful for professional video
electronics such as cameras, video switchers or any high speed
portable equipment. The AD8042’s low distortion and fast
settling make it ideal for buffering single supply, high speed
A-to-D converters.
–64 dBc Worst Harmonic @ 10 MHz
Drives 50 mA 0.5 V from Supply Rails
APPLICATIONS
Video Switchers
Distribution Amplifiers
A/D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)
The AD8042 offers low power supply current of 12 mA max
and can run on a single +3.3 V power supply. These features are
ideally suited for portable and battery powered applications
where size and power are critical.
The wide bandwidth of 160 MHz along with 200 V/µs of slew
rate on a single +5 V supply make the AD8042 useful in many
general purpose, high speed applications where single supplies
from +3.3 V to +12 V and dual power supplies of up to ±6 V
are needed. The AD8042 is available in 8-lead plastic DIP and
SOIC.
PRODUCT DESCRIPTION
The AD8042 is a low power voltage feedback, high speed am-
plifier designed to operate on +3 V, +5 V or ±5 V supplies. It
has true single supply capability with an input voltage range
extending 200 mV below the negative rail and within 1 V of the
positive rail.
15
VS = +5V
12
G = +1
C
L = 5pF
G = 1
9
6
RL = 2k⍀ TO 2.5V
R
= 2k⍀ TO +2.5V
L
5V
3
0
2.5V
0V
–3
–6
–9
–12
–15
1V
1s
1
10
100
500
Figure 1. Output Swing: Gain = –1, VS = +5 V
FREQUENCY – MHz
Figure 2. Frequency Response
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD8042–SPECIFICATIONS(@ TA = +25؇C, VS = +5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted)
AD8042A
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
G = +1
125
130
160
14
200
30
MHz
MHz
V/µs
MHz
ns
G = +2, RL = 150 Ω. RF = 200 Ω
G = –1, VO = 2 V Step
VO = 2 V p-p
G = –1, VO = 2 V Step
26
Settling Time to 0.1%
39
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 75 Ω to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 75 Ω to 2.5 V
f = 5 MHz, RL = 150 Ω to 2.5 V
–73
15
dB
nV/√Hz
fA/√Hz
%
700
0.04
0.04
0.06
0.24
–63
0.06
0.12
%
Differential Phase Error (NTSC, 100 IRE)
Worst Case Crosstalk
Degrees
Degrees
dB
DC PERFORMANCE
Input Offset Voltage
3
9
12
mV
mV
µV/°C
µA
µA
µA
T
MIN–TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.5
TMIN–TMAX
Input Offset Current
Open-Loop Gain
0.2
100
90
RL = 1 kΩ
TMIN –TMAX
90
68
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
300
1.5
–0.2 to 4
74
kΩ
pF
V
VCM = 0 V to 3.5 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
RL = 10 kΩ to 2.5 V
RL = 1 kΩ to 2.5 V
RL = 50 Ω to 2.5 V
0.03 to 4.97
0.05 to 4.95
0.36 to 4.45
50
90
100
20
V
V
V
mA
mA
mA
pF
0.10 to 4.9
0.4 to 4.4
TMIN to TMAX, VOUT = 0.5 V to 4.5 V
Short Circuit Current
Sourcing
Sinking
G = +1
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
3
12
6
V
mA
dB
5.2
80
VS– = 0 V to –1 V, or VS+ = +5 V to +6 V
72
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
–40
+85
°C
–2–
REV. A
AD8042
(@ T = +25؇C, V = +3 V, R = 2 k⍀ to 1.5 V, unless otherwise noted)
SPECIFICATIONS
A
S
L
AD8042A
Typ
Parameter
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
G = +1
120
120
140
11
170
25
MHz
MHz
V/µs
MHz
ns
G = +2, RL = 150 Ω, RF = 200 Ω
G = –1, VO = 2 V Step
VO = 2 V p-p
G = –1, VO = 1 V Step
30
Settling Time to 0.1%
45
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
fC = 5 MHz, VO = 2 V p-p, G = –1, RL = 100 Ω
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V
RL = 75 Ω to 1.5 V, Input VCM = 1 V
G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V
RL = 75 Ω to 1.5 V, Input VCM = 1 V
f = 5 MHz, RL = 1 kΩ to 1.5 V
–56
16
dB
nV/√Hz
fA/√Hz
%
500
0.10
0.10
0.12
0.27
–68
%
Differential Phase Error (NTSC, 100 IRE)
Worst Case Crosstalk
Degrees
Degrees
dB
DC PERFORMANCE
Input Offset Voltage
3
9
12
mV
mV
µV/°C
µA
µA
µA
T
MIN –TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.6
TMIN –TMAX
Input Offset Current
Open-Loop Gain
0.2
100
90
RL = 1 kΩ
TMIN –TMAX
90
66
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
300
1.5
–0.2 to 2
kΩ
pF
V
VCM = 0 V to 1.5 V
74
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
RL = 10 kΩ to 1.5 V
RL = 1 kΩ to 1.5 V
RL = 50 Ω to 1.5 V
0.03 to 2.97
0.05 to 2.95
0.25 to 2.65
50
50
70
17
V
V
V
mA
mA
mA
pF
0.1 to 2.9
0.3 to 2.6
T
MIN to TMAX, VOUT = 0.5 V to 2.5 V
Short Circuit Current
Sourcing
Sinking
G = +1
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
3
12
6
V
mA
dB
5.0
80
VS– = 0 V to –1 V, or VS+ = +3 V to +4 V
68
0
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
+70
°C
REV. A
–3–
AD8042–SPECIFICATIONS (@ TA = +25؇C, VS = ؎5 V, RL = 2 k⍀ to 0 V, unless otherwise noted)
AD8042A
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
G = +1
125
145
170
18
225
35
MHz
MHz
V/µs
MHz
ns
G = +2, RL = 150 Ω, RF = 200 Ω
G = –1, VO = 2 V Step
VO = 2 V p-p
G = –1, VO = 2 V Step
22
Settling Time to 0.1%
32
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC, 100 IRE)
fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
G = +2, RL = 75 Ω
G = +2, RL = 150 Ω
G = +2, RL = 75 Ω
–78
15
dB
nV/√Hz
fA/√Hz
%
700
0.02
0.02
0.04
0.12
–63
0.05
0.10
%
Differential Phase Error (NTSC, 100 IRE)
Worst Case Crosstalk
Degrees
Degrees
dB
f = 5 MHz, RL = 150 Ω
DC PERFORMANCE
Input Offset Voltage
3
9.8
14
mV
mV
µV/°C
µA
µA
µA
T
MIN –TMAX
Offset Drift
Input Bias Current
12
1.2
3.2
4.8
0.6
TMIN –TMAX
Input Offset Current
Open-Loop Gain
0.2
94
86
RL = 1 kΩ
TMIN –TMAX
90
66
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
300
1.5
–5.2 to 4
74
kΩ
pF
V
VCM = –5 V to 3.5 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
RL = 10 kΩ
RL = 1 kΩ
RL = 50 Ω
–4.97 to +4.97
–4.9 to +4.9
–4.2 to +3.5
50
100
100
25
V
V
V
mA
mA
mA
pF
–4.8 to +4.8
–4 to +3.2
TMIN to TMAX, VOUT = –4.5 V to 4.5 V
Short Circuit Current
Sourcing
Sinking
G = +1
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current (Per Amplifier)
Power Supply Rejection Ratio
6
80
7
mA
dB
VS– = –5 V to –6 V, or VS+ = +5 V to +6 V
68
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
–40
+85
°C
–4–
REV. A
AD8042
ABSOLUTE MAXIMUM RATINGS1
While the AD8042 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.3 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . ±VS ± 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V
Output Short Circuit Duration
2.0
8-LEAD PLASTIC-DIP PACKAGE
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
T
= +150؇C
J
1.5
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for the device in free air:
1.0
0.5
0
8-LEAD SOIC PACKAGE
8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
MAXIMUM POWER DISSIPATION
AMBIENT TEMPERATURE – ؇C
The maximum power that can be safely dissipated by the
AD8042 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic encap-
sulated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Exceeding this limit tem-
porarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Supply
Voltages
Temperature
Range
Package
Description
Package
Option
Model
AD8042AN
AD8042AN
AD8042AR
AD8042AR
AD8042AR-REEL
AD8042AR-REEL7
AD8042ACHIPS
+5 V, ±5 V
+3 V
+5 V, ±5 V
+3 V
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead Plastic SOIC
8-Lead Plastic SOIC
13" Tape and REEL
7" Tape and REEL
Die
N-8
N-8
SO-8
SO-8
SO-8
SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8042 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
AD8042–Typical Performance Characteristics
100
100
95
V
= +5V
S
90
80
T = +25؇C
140 PARTS, SIDE A & B
MEAN = –1.52mV
STD DEVIATION = 1.15
SAMPLE SIZE = 280
(140 AD8042S)
70
60
90
85
80
75
70
50
40
30
20
10
0
V
= +5V
S
T = +25؇C
–6 –5 –4 –3 –2 –1
V
0
1
2
3
4
5
6
0
250
500
750
1000 1250
1500 1750
2000
– mV
LOAD RESISTANCE – ⍀
OS
Figure 7. Open-Loop Gain vs. RL to +2.5 V
Figure 4. Typical Distribution of VOS
100
30
25
20
V
= +5V
S
98
MEAN = –12.6V/؇C
STD DEV = 2.02V/؇C
SAMPLE SIZE = 60
V
= +5V
S
R
= 1k⍀
L
96
94
15
10
5
92
90
88
86
0
–18 –16 –14 –12 –10
–8
–6
–4
–2
0
–40
–20
0
20
40
60
80
V
DRIFT – V/؇C
OS
TEMPERATURE – ؇C
Figure 8. Open-Loop Gain vs. Temperature
Figure 5. VOS Drift Over –40°C to +85°C
0
100
V
= +5V
S
V
V
= +5V
S
R
= 500⍀ TO 2.5V
= 50⍀ TO 2.5V
–0.2
L
= 0V
CM
90
80
–0.4
–0.6
R
–0.8
–1
L
70
60
50
40
–1.2
–1.4
–1.6
–1.8
–2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
OUTPUT VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 9. Open-Loop Gain vs. Output Voltage
Figure 6. IB vs. Temperature
–6–
REV. A
AD8042
0.04
0.03
NTSC Subcarrier (3.579 MHz)
V
= +5V
S
G = +2
= 150⍀ TO 2.5V
R
300
100
30
10
3
L
0.02
0.01
0.00
V
= ؎5V
S
G = +2
R
= 150⍀
L
–0.01
0.05
V
= +5V
S
0.04
0.03
0.02
0.01
G = +2
= 150⍀ TO 2.5V
R
L
V
= ؎5V
S
G = +2
1
R
= 150⍀
L
0
–0.01
1k
10k
100k
10
100
1M
10M 100M
1G
20
0
10
30
40
50
60
70
80
90 100
FREQUENCY – Hz
MODULATING RAMP LEVEL – IRE
Figure 13. Differential Gain and Phase Errors
Figure 10. Input Voltage Noise vs. Frequency
–30
0.6
V
= +5V
S
0.5
0.4
0.3
0.2
0.1
V
= +3V, A = –1,
V
= 100⍀ TO 1.5V
S
–40
–50
–60
G = +2
R
R
R
= 200⍀
= 150⍀ TO 2.5V
L
F
L
V
= +5V, A = +2,
V
= 100⍀ TO 2.5V
S
R
L
V
= +5V, A = +1,
V
= 100⍀ TO 2.5V
S
R
L
–70
–80
–90
0
14MHz
–0.1
V
= +5V, A = +2,
S
V
R
= 1k⍀ TO 2.5V
L
–0.2
–0.3
–0.4
V
= +5V, A = +1,
V
= 1k⍀ TO 2.5V
S
R
L
–100
1
2
3
4
5
6
7 8 9 10
1
10
FREQUENCY – MHz
100
500
FUNDAMENTAL FREQUENCY – MHz
Figure 14. 0.1 dB Gain Flatness
Figure 11. Total Harmonic Distortion
120
100
80
–30
–40
V
= +5V
S
G = +2
R
R
= 200⍀
= 150⍀ TO 2.5V
F
10MHz
5MHz
L
–50
GAIN
60
45
–60
40
0
20
–70
–45
–90
–135
–180
0
–80
PHASE
–20
1MHz
–90
–40
–60
–80
V
= +5V, G = +2,
S
–100
–110
R
= 1k⍀ TO 2.5V
L
–225
–270
100
0.0
0.5 1.0
1.5
2.0
2.5 3.0
3.5 4.0
4.5 5.0
0.01
0.1
1
10
500
FREQUENCY – MHz
OUTPUT VOLTAGE – V p-p
Figure 12. Worst Harmonic vs. Output Voltage
Figure 15. Open-Loop Gain and Phase
vs. Frequency
REV. A
–7–
AD8042–Typical Performance Characteristics
10
60
G = –1
V
= +3V, 0.1%
V
= +5V
S
S
8
6
4
2
0
55
50
45
40
35
30
R
C
= 2k⍀ TO MIDPOINT
G = +1
C
R
L
L
= 5pF
= 2k⍀ TO 2.5V
= 5pF
L
L
T = +85؇C
T = +25؇C
V
= +3V, 1%
S
T = –40؇C
V
= +5V, 0.1%
S
–2
–4
V
= ؎5V, 0.1%
S
–6
–8
V
V
= +5V, 1%
S
25
20
= ؎5V, 1%
S
–10
1
10
FREQUENCY – MHz
100
500
0.5
1
1.5
2
BIPOLAR INPUT STEP – V
Figure 16. Closed-Loop Frequency Response
vs. Temperature
Figure 19. Settling Time
12
V
= +3V
S
G = +1
10
8
V
= +5V
0
s
R
& C TO 1.5V
L
C
= 5pF
L
TEST CIRCUIT:
L
L
1.02k⍀
R
= 2k⍀
–10
1.02k⍀
V
= +5V
& C TO 2.5V
L
S
OUT
R
IN
CM
L
–20
–30
6
V
= ؎5V
1.02k⍀
S
1.02k⍀
4
–40
–50
–60
2
0
–2
–4
–70
–80
–6
–8
–90
10k
1M
10M
100M
500M
100k
1
10
FREQUENCY – MHz
100
500
FREQUENCY – Hz
Figure 17. Closed-Loop Frequency Response vs. Supply
Figure 20. CMRR vs. Frequency
0.80
0.70
0.60
0.50
0.40
0.30
0.20
V
= +5V
S
100
+5V – V (+125؇C)
OH
R
= 50⍀
BT
+5V – V (+25؇C)
OH
V
= +5V
S
10
1
G = +1
+5V – V (–55؇C)
OH
R
= 0
BT
R
BT
V
OUT
0.1
+V (+125؇C)
OL
+V (+25؇C)
OL
0.10
0
0.01
+V (–55؇C)
OL
100
0.01
0.1
1
10
500
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – MHz
LOAD CURRENT – mA
Figure 18. Output Resistance vs. Frequency
Figure 21. Output Saturation Voltage vs. Load Current
REV. A
–8–
AD8042
12
11.5
11
50
40
30
20
10
0
V
V
= ؎5V
S
V
V
= +5V
S
= 100mV STEP
OUT
G = +2
= +5V
= +3V
S
10.5
10
V
S
9.5
9
G = +3
8.5
8
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0
20
40
60
80 100 120
140 160 180 200
TEMPERATURE – ؇C
LOAD CAPACITANCE – pF
Figure 25. % Overshoot vs. Load Capacitance
Figure 22. Supply Current vs. Temperature
6
V
= +5V
S
V
= +5V
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
5
4
R
R
= 2k⍀
F
L
= 2k⍀ TO +2.5V
3
G = +2
2
1
–PSRR
0
G = +2
= 200⍀
R
+PSRR
F
–1
–2
–3
–4
G = +10
G = +5
10k
1M
10M
100M
500M
100k
1
10
FREQUENCY – MHz
100
500
FREQUENCY – Hz
Figure 23. PSRR vs. Frequency
Figure 26. Frequency Response vs. Closed-Loop Gain
10
9
–10
V
V
= +5V
S
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
= 0.6V p-p
IN
V
R
= ؎5V
= 2k⍀
S
G = +2
R
8
L
= 1k⍀
F
G = –1
7
V
V
1
2
OUT
, R = 1k⍀ TO +2.5V
L
OUT
6
V
V
1
OUT
5
, R = 150⍀ TO +2.5V
L
2
OUT
4
3
V
V
2
1
OUT
, R = 150⍀ TO +2.5V
L
OUT
2
1
0
V
V
2
1
OUT
, R = 1k⍀ TO +2.5V
L
OUT
100.0
1.0
10.0
0.1
0.1
1
10
100 200
FREQUENCY – MHz
FREQUENCY – MHz
Figure 24. Output Voltage Swing vs. Frequency
Figure 27. Crosstalk (Output-to-Output) vs. Frequency
REV. A
–9–
AD8042–Typical Performance Characteristics
5V
A
= +1
4.770V
V
V
= +5V
S
+2.6V
V
V
= +5V
G = –1
= 150⍀ TO +2.5V
S
R
= 100mV p-p
= 1k⍀ TO 2.5V
= 5pF
4V
3V
2V
1V
0V
L
IN
R
C
L
L
+2.5V
+2.4V
0.160V
25mV
10ns
200
s
0.5V
Figure 28a. Output Swing with Load Reference to Supply
Midpoint
Figure 30. 100 mV Pulse Response, VS = +5 V
5V
G = –1
R
= 2k⍀ TO +1.5V
V = +5V
S
L
4V
3V
2V
1V
0V
4.59V
G = –1
3V
1.5V
0V
R = 150⍀ TO GND
L
0.035V
0.5V
0.5V
1s
200s
Figure 28b. Output Swing with Load Reference to Negative
Supply
Figure 31. Rail-to-Rail Output Swing, VS = +3 V
4.5V
A
= +2
V
= 100mV p-p
= 1k⍀ TO 1.5V
= +3V
V
IN
+1.6V
V
= +5V
S
R
L
C
R
= 5pF
L
V
S
= 1k⍀ TO +2.5V
L
3.5V
2.5V
C
= 5pF
L
V
= 1V p-p
IN
A
= +1V
V
+1.5V
+1.4V
1.5V
25mV
10ns
0.5V
10ns
0.5V
Figure 29. One Volt Pulse Response, VS = +5 V
Figure 32. 100 mV Pulse Response, VS = +3 V
–10–
REV. A
AD8042
Overdrive Recovery
This circuit topology allows the AD8042 to drive 40 mA of
output current with the outputs within 0.5 V of the supply rails.
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 33, the AD8042 recovers
within 30 ns from negative overdrive and within 25 ns from
positive overdrive.
On the input side, the device can handle voltages from 0.2 V
below the negative rail to within 1.2 V of the positive rail. Ex-
ceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
DRIVING CAPACITIVE LOADS
The capacitive load drive of the AD8042 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for vary-
ing voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less over-
shoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.
+5V
+2.5V
V
V
= +5V
S
0V
= +5V p-p
IN
G = +2
= 1k⍀ TO +2.5V
R
L
50ns
1V
1000
V
= +5V
Figure 33. Overdrive Recovery
S
200mV STEP WITH 30% OVERSHOOT
Circuit Description
The AD8042 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar fTs in the 2 GHz–4 GHz region. The process is dielectri-
cally isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construc-
tion of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –77 dB
@ 1 MHz into 100 Ω with VOUT = 2 V p-p (Gain = +2) on a
single 5 volt supply is achieved.
R = 5⍀
S
R
S
C
L
R
= 0
S
100
R
= 20⍀
S
10
1
2
3
4
5
CLOSED-LOOP GAIN – V/V
Figure 35. Capacitive Load Drive vs. Closed-Loop Gain
Single Supply Composite Video Line Driver
The two op amps of an AD8042 can be configured as a single
supply dual line driver for composite video. The wide signal
swing of the AD8042 enables this function to be performed
without using any type of clamping or dc restore circuit which
can cause signal distortion.
V
CC
I1
I10
I2
I 3
I9
Q50
Q39
Q25
Q51
R26
Q4
R39
Q5
Q36
I5
Figure 36 shows a schematic for a circuit that is driven by a
single composite video source that is ac coupled, level shifted
and applied to both + inputs of the two amplifiers. Each op amp
provides a separate 75 Ω composite video output. To obtain
single supply operation, ac coupling is used throughout. The
large capacitor values are required to ensure that there is mini-
mal tilting of the video signals due to their low frequency
(30 Hz) signal content. The circuit shown was measured to have
a differential gain of 0.06% and a differential phase of 0.06°.
Q23
V
Q40
EE
R15 R2
Q22
R27
R23
Q21
V
EE
C3
C9
Q31
Q7
Q17
V
P
Q13
V
IN
OUT
Q27
V
N
IN
SIN
SIP
Q2
Q11
R3
Q8
I8
Q3
Q24
I7
Q47
V
CC
C7
R5
R21
V
EE
The input is terminated in 75 Ω and ac coupled via CIN to a
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding of
the nature of composite video signals and the video performance
of the AD8042.
Figure 34. AD8042 Simplified Schematic
The AD8042’s rail-to-rail output range is provided by a
complementary common-emitter output stage. High output
drive capability is provided by injecting all output stage
predriver currents directly into the bases of the output devices
Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and
I5, along with a common-mode feedback loop (not shown).
REV. A
–11–
AD8042
+5V
8
To test this, the differential gain and differential phase were
measured for the AD8042 while the supplies were varied. As the
lower supply is raised to approach the video signal, the first
effect to be observed is that the sync tips become compressed
before the differential gain and differential phase are adversely
affected. Thus, there must be adequate swing in the negative
direction to pass the sync tips without compression.
4.99k⍀
10F
10F
0.1µF
1000F
75⍀
COAX
4.99k⍀
3
1
V
COMPOSITE
VIDEO
IN
2
OUT
R
T
75⍀
R
R
L
F
75⍀
1k⍀
0.1F
75⍀
R
G
10k⍀
1k⍀
As the upper supply is lowered to approach the video, the differ-
ential gain and differential phase were not significantly adversely
affected until the difference between the peak video output and
the supply reached 0.6 V. Thus, the highest video level should
be kept at least 0.6 V below the positive supply rail.
220F
5
6
1000F
0.1F
7
V
OUT
R
T
75⍀
R
L
4
75⍀
Taking the above into account, it was found that the optimal
point to bias the noninverting input is at 2.2 V dc. Operating at
this point, the worst case differential gain is measured at 0.06%
and the worst case differential phase is 0.06°.
R
R
G
F
1k⍀
1k⍀
220F
The ac coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower fre-
quency band edge of 30 Hz. The resistances at the various ac
coupling points—especially at the output—are quite small. In
order to minimize phase shifts and baseline tilt, the large value
capacitors are required. For video system performance that is
not to be of the highest quality, the value of these capacitors can
be reduced by a factor of up to five with only a slightly observ-
able change in the picture quality.
Figure 36. Single Supply Composite Video Line Driver
Using AD8042
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-to-
peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required will approach twice the peak-to-peak
value. The two bounding cases are for a duty cycle that is mostly
low, but occasionally goes high at a fraction of a percent duty
cycle and vice versa.
Single-Ended-to-Differential Driver
Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame,
but has a white (full intensity), minimum width spike at least
once per frame.
Using a cross-coupled single-ended-to-differential converter, the
AD8042 makes a good general purpose differential line driver.
This can be used for applications such as driving category 5
twisted pair wire which is becoming common for data communi-
cations in buildings. Figure 37 shows a configuration for a cir-
cuit that performs this function that can be used for video
transmission over a differential pair or various data communica-
tion purposes.
The other extreme is for a video signal that is full white every-
where. The blanking intervals and sync tips of such a signal will
have negative going excursions in compliance with composite
video specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at its highest level
(white) for only about 75% of the time.
10F
0.1F
As a result of the duty cycle variations between the two extremes
presented above, a 1 V p-p composite video signal that is multi-
plied by a gain of two requires about 3.2 V p-p of dynamic volt-
age swing at the output for an op amp to pass a composite video
signal of arbitrary duty cycle without distortion.
R
IN
R
F
1k⍀
1k⍀
3
2
8
V
IN
60.4⍀
1
AMP1
49.9⍀
R
A
1k⍀
50m
Some circuits use a sync tip clamp along with ac coupling to
hold the sync tips at a relatively constant level in order to lower
the amount of dynamic signal swing required. However, these
circuits can have artifacts like sync tip compression unless they
are driven by sources with very low output impedance.
R
R
1k⍀
B
B
V
121⍀
OUT
AD8042
1k⍀
R
A
1k⍀
6
5
60.4⍀
10F
7
AMP2
4
The AD8042 not only has ample signal swing capability to
handle the dynamic range required without using a sync tip
clamp, but also has good video specifications like differential
gain and differential phase when buffering these signals in an
ac-coupled configuration.
100⍀
0.1F
–5V
Figure 37. Single-Ended-to-Differential Twisted Pair Line
Driver
–12–
REV. A
AD8042
+5V
Each of the AD8042’s op amps is configured as a unity gain
follower by the feedback resistors (RA). Each op amp output
also drives the other as a unity gain inverter via the two RBs,
creating a totally symmetrical circuit.
+5V
0.1F
1k⍀
0.1F
1k⍀
3
2
8
V
If the + input to Amp 2 is grounded and a small positive signal
is applied to the + input of Amp 1, the output of Amp 1 will be
driven to saturation in the positive direction and the input of
Amp 2 driven to saturation in the negative direction. This is
similar to the way a conventional op amp behaves without any
feedback.
IN
1
+5V
+5V
0.1F
+5V
0.1F
0.1F
1k⍀
1k⍀
26
AV
15
AV
28
DV
1k⍀
1k⍀
AD8042
DD
DD
DD
14
13
+5V
OTR
BIT1
V
V
A
B
IN
6
5
If a resistor (RF) is connected from the output of Amp 2 to the
+ input of Amp 1, negative feedback is provided which closes
the loop. An input resistor (RI) will make the circuit look like a
conventional inverting op amp configuration with differential
outputs.
7
12
2.49k⍀
IN
BIT2
BIT3
11
10
4
2.49k⍀
0.1F
CAPT
CAPB
BIT4
9
0.1F
BIT5
BIT6
AD9220
10/16
8
7
0.1F
18
17
22
BIT7
The gain of this circuit from input to either output will be ±RF/
RI. Or the single-ended-to-differential gain will be 2 × RF/RI.
This gives the circuit the advantage of being able to adjust its
gain by changing a single resistor.
0.1F
6
5
4
V
REF
BIT8
BIT9
SENSE
BIT10
BIT11
CML
3
2
0.1F
1
BIT12
CLOCK
CLK
The cable has a characteristic impedance of about 120 Ω. Each
driver output is back terminated with a pair of 60.4 Ω resistors
to make the source look like 120 Ω. The receive end is termi-
nated with 121 Ω, and the signal is measured differentially with
a pair of scope probes. One channel on the oscilloscope is in-
verted and then the signals are added.
DV
AV
AV
REFCOM
19
SS
SS SS
25
27
16
Figure 39. AD8042 Differential Driver for the AD9220
12-Bit, 10 MSPS A/D Converter
The circuit was tested with a 1 MHz input signal and clocked at
10 MHz. An FFT response of the digital output is shown in
Figure 40.
The scope photo in Figure 38 shows a 10 MHz, 2 V p-p input
signal driving the circuit with 50 m of category 5 twisted pair
wire.
Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
This biases each output at 2.5 V. VIN is ac coupled such that VIN
going positive makes VINA go positive and VINB go in the nega-
tive direction. The opposite happens for a negative going VIN.
50ns
200mV
1V
100
90
V
IN
1
V
OUT
10
0%
3
7
2
8
6
4
200mV
5
9
Figure 38. Differential Driver Frequency Response
Single Supply Differential A/D Driver
The single-ended-to-differential converter circuit is also useful
as a differential driver for video speed, single-ended, differential
input A/D converters. Figure 39 is a schematic that shows such
a circuit differentially driving an AD9220, a 12-bit, 10 MSPS
A/D converter.
HARMONICS (dBc)
FUND FRQ 1000977
SMPL FRQ 10000000
THD –82.00
2nd –88.34 6th –99.47
3rd –86.74 7th –91.16
4th –99.26 8th –97.25
5th –90.67 9th –91.61
SNR
71.13
SINAD 70.79
SFDR –86.74
Figure 40. FFT of AD9220 Output When Driven by AD8042
REV. A
–13–
AD8042
HDSL Line Driver
Layout Considerations
HDSL or high-bit-rate digital subscriber line is becoming popu-
lar as a means to provide data communication at DS1 rates
(1.544 MBPS) over moderate distances via conventional tele-
phone twisted pair wires. In these systems, the transceiver at the
customer’s end is sometimes powered via the twisted pair from a
power source at the central office. It is sometimes required to
raise the dc voltage of the power source to compensate for IR
drops in long lines or lines with narrow gauge wires.
The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
Because of this, it is highly desirable to keep the power con-
sumption of the customer’s transceiver as low as possible. One
means to realize significant power savings is to run the trans-
ceiver from a ±5 V supply instead of the more conventional
±12 V.
Chip capacitors should be used for the supply bypassing.
One end should be connected to the ground plane and the
other within 1/8 inch of each power pin. An additional large
(0.47 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large signal changes at the output.
The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 41
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in-
verting input will significantly affect high speed performance.
2k⍀
2k⍀
3k⍀
ATT
2718AF
93DJ39
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
6
5
7
V
232⍀
OUT
V
IN
1/2
AD8042
1
4
3k⍀
10
5
2
3
1
1/2
2
9
7
6
0.001F
AD8042
912⍀
0.0027F
34⍀
2k⍀
2k⍀
2
3
249⍀
1
V
2k⍀
REC
1/4
AD8044
2k⍀
2k⍀
0.001F
Figure 41. HDSL Line Driver
–14–
REV. A
AD8042
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8
5
0.25
(6.35)
0.31
(7.87)
PIN 1
1
4
0.30 (7.62)
REF
0.39 (9.91) MAX
0.035±0.01
(0.89±0.25)
0.165±0.01
(4.19±0.25)
0.011±0.003
(0.28±0.08)
0.18±0.03
(4.57±0.76)
0.125
(3.18)
MIN
15°
0°
0.018±0.003
(0.46±0.08) (2.54)
0.10
0.033
(0.84)
NOM
SEATING
PLANE
BSC
8-Lead Plastic SOIC
(SO-8)
8
1
5
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
4
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
REV. A
–15–
相关型号：
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