AD8045ACPZ-R2 [ADI]
3 nV/Hz Ultralow Distortion, High Speed Op Amp; 3内华达州/ Hz的超低失真，高速运算放大器
| 型号： | AD8045ACPZ-R2 |
| 厂家： | 
ADI |
| 描述： | 3 nV/Hz Ultralow Distortion, High Speed Op Amp |
| 文件： | 总24页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 nV/√Hz Ultralow Distortion,
High Speed Op Amp
AD8045
FEATURES
Ultralow distortion
SFDR
−101 dBc @ 5 MHz
APPLICATIONS
Instrumentation
IF and baseband amplifiers
Active filters
−90 dBc @ 20 MHz
ADC drivers
−63 dBc @ 70 MHz
DAC buffers
Third-order intercept
43 dBm @ 10 MHz
CONNECTION DIAGRAMS
Low noise
3 nV/√Hz
3 pA/√Hz
High speed
1
2
3
4
8
7
6
5
NC
FEEDBACK
–IN
+V
S
OUTPUT
NC
+IN
–V
S
1 GHz, −3 dB bandwidth (G = +1)
1350 V/µs slew rate
7.5 ns settling time to 0.1%
Standard and low distortion pinout
Supply current: 15 mA
Offset voltage: 1.0 mV max
Wide supply voltage range: 3.3 V to 12 V
Figure 1. 8-Lead AD8045 LFCSP (CP-8)
1
2
3
4
8
7
6
5
FEEDBACK
NC
–IN
+IN
+V
S
OUTPUT
NC
–V
S
Figure 2. 8-Lead AD8045 SOIC/EP (RD-8)
GENERAL DESCRIPTION
The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP
and the standard 8-lead SOIC. Both packages feature an
exposed paddle that provides a low thermal resistance path to
the PCB. This enables more efficient heat transfer, and increases
reliability. The AD8045 works over the extended industrial
temperature range (−40°C to +125°C).
The AD8045 is a unity gain stable voltage feedback amplifier
with ultralow distortion, low noise, and high slew rate. With a
spurious-free dynamic range of −90 dBc @ 20 MHz, the
AD8045 is an ideal solution in a variety of applications,
including ultrasound, ATE, active filters, and ADC drivers.
ADI’s proprietary next generation XFCB process and innovative
architecture enables such high performance amplifiers.
–20
G = +1
V
V
R
= ±5V
S
–30
–40
= 2V p-p
The AD8045 features a low distortion pinout for the LFCSP,
which improves second harmonic distortion and simplifies the
layout of the circuit board.
OUT
= 1kΩ
= 100Ω
L
S
R
–50
–60
The AD8045 has 1 GHz bandwidth, 1350 V/µs slew rate, and
settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V
to 12 V) and low offset voltage (200 µV), the AD8045 is an ideal
candidate for systems that require high dynamic range, preci-
sion, and high speed.
–70
–80
HD3 LFCSP
–90
HD2 LFCSP
–100
–110
–120
0.1
1
10
FREQUENCY (MHz)
100
Figure 3. Harmonic Distortion vs. Frequency for Various Packages
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8045
TABLE OF CONTENTS
Specifications with 5 V Supply ..................................................... 3
Applications..................................................................................... 19
Low Distortion Pinout............................................................... 19
High Speed ADC Driver ........................................................... 19
90 MHz Active Low-Pass Filter (LPF)..................................... 20
Printed Circuit Board Layout ....................................................... 22
Signal Routing............................................................................. 22
Power Supply Bypassing............................................................ 22
Grounding................................................................................... 22
Exposed Paddle........................................................................... 23
Driving Capacitive Loads.......................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Specifications with +5 V Supply ..................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Configurations................................................................... 16
Wideband Operation ................................................................. 16
Theory of Operation ...................................................................... 17
Frequency Response................................................................... 17
DC Errors .................................................................................... 17
Output Noise............................................................................... 18
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Features......................................................................... 1
Changes to Specifications............................................................... 4
Changes to Figure 58.....................................................................15
Changes to Figure 63.....................................................................17
Changes to Frequency Response Section ...................................17
Changes to Figure 64.....................................................................17
Changes to DC Errors Section.....................................................17
Changes to Figure 65.....................................................................17
Changes to Figure 66.....................................................................18
Changes to Output Noise Section ...............................................18
Changes to Ordering Guide .........................................................24
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8045
SPECIFICATIONS WITH 5 V SUPPLY
TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. Exposed paddle must be floating or connected to −VS.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VOUT = 0.2 V p-p
G = +1, VOUT = 2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +2, VOUT = 2 V p-p, RL = 150 Ω
G = +1, VOUT = 4 V step
G = +2, VOUT = 2 V step
1000
350
400
55
1350
7.5
MHz
300
320
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
1000
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
fC = 5 MHz, VOUT = 2 V p-p
LFCSP
SOIC
−102/−101
−106/−101
dBc
dBc
fC = 20 MHz, VOUT = 2 V p-p
LFCSP
SOIC
−98/−90
−97/−90
dBc
dBc
fC = 70 MHz, VOUT = 2 V p-p
LFCSP
SOIC
f = 100 kHz
f = 100 kHz
−71/−71
−60/−71
3
3
0.01
dBc
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
0.01
Degrees
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
0.2
8
2
8
0.2
64
1.0
6.3
1.3
mV
µV/°C
µA
nA/°C
µA
dB
See Figure 54
VOUT = −3 V to +3 V
62
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Common-mode/differential
Common-mode
3.6/1.0
1.3
3.8
MΩ
pF
V
VCM = 1 V
−83
−91
dB
VIN = 3 V, G = +2
RL = 1 kΩ
RL = 100 Ω
8
ns
V
V
mA
mA
pF
−3.8 to +3.8
−3.4 to +3.5
−3.9 to +3.9
−3.6 to +3.6
70
90/170
18
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Sinking/sourcing
30% overshoot, G = +2
Operating Range
1.65
5
6
V
Quiescent Current
Positive Power Supply Rejection
Negative Power Supply Rejection
16
−68
−73
19
mA
dB
dB
+VS = +5 V to +6 V, −VS = −5 V
+VS = +5 V, −VS = −5 V to −6 V
−61
−66
Rev. A | Page 3 of 24
AD8045
SPECIFICATIONS WITH +5 V SUPPLY
TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VOUT = 0.2 V p-p
G = +1, VOUT = 2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +2, VOUT = 2 V p-p, RL = 150 Ω
G = +1, VOUT = 2 V step
G = +2, VOUT = 2 V step
900
200
395
60
1060
10
MHz
MHz
MHz
MHz
V/µs
ns
160
320
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
480
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
fC = 5 MHz, VOUT = 2 V p-p
LFCSP
SOIC
−89/−83
−92/−83
dBc
dBc
fC = 20 MHz, VOUT = 2 V p-p
LFCSP
SOIC
−81/−70
−83/−70
dBc
dBc
fC = 70 MHz, VOUT = 2 V p-p
LFCSP
SOIC
f = 100 kHz
f = 100 kHz
−57/−46
−57/−46
3
3
0.01
dBc
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
0.01
Degrees
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
0.5
7
2
7
0.2
63
1.4
6.6
1.3
mV
µV/°C
µA
nA/°C
µA
dB
See Figure 54
VOUT = 2 V to 3 V
61
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Common-mode/differential
Common-mode
3/0.9
1.3
1.2 to 3.8
−94
MΩ
pF
V
VCM = 2 V to 3 V
−78
dB
VIN = −0.5 V to +3 V, G = +2
RL = 1 kΩ
RL = 100 Ω
10
ns
V
V
mA
mA
pF
2.2 to 3.7
2.5 to 3.5
1.1 to 4.0
1.2 to 3.8
55
70/140
15
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Sinking/sourcing
30% overshoot, G = +2
Operating Range
Quiescent Current
Positive Power Supply Rejection
Negative Power Supply Rejection
3.3
5
15
−67
−73
12
18
V
mA
dB
dB
+VS = +5 V to +6 V, −VS = 0 V
+VS = +5 V, −VS = 0 V to −1 V
−65
−70
Rev. A | Page 4 of 24
AD8045
ABSOLUTE MAXIMUM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the qui-
escent power dissipation and the power dissipated in the die
due to the AD8045 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 4
−VS − 0.7 V to +VS + 0.7 V
±VS
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature
Operating Temperature Range
PD = Quiescent Power + (Total Drive Power – Load Power)
−VS
−65°C to +125°C
−40°C to +125°C
300°C
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
PD =
(
VS × IS
)
+
×
–
2
RL
Lead Temperature Range
(Soldering 10 sec)
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
VS /4
RL
)
PD =
(
VS ×IS +
)
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
THERMAL RESISTANCE
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θJA.
θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
80
93
θJC
30
35
Unit
°C/W
°C/W
SOIC
LFCSP
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
Maximum Power Dissipation
4.0
3.5
3.0
2.5
2.0
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the AD8045. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in
silicon devices, potentially causing degradation or loss of
functionality.
1.5
SOIC
1.0
LFCSP
0.5
0.0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
Rev. A | Page 5 of 24
AD8045
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD8045
NC
8
7
6
5
1
2
3
4
FEEDBACK
–IN
8
7
6
5
1
2
3
4
+V
NC
+V
S
S
BOTTOM
VIEW
(Not to Scale)
OUTPUT
NC
FEEDBACK
–IN
OUTPUT
+IN
BOTTOM VIEW
(Not to Scale)
NC
–V
S
–V
+IN
S
NC = NO CONNECT
NC = NO CONNECT
Figure 5. SOIC Pin Configuration
Figure 6 . 8-Lead LFCSP Pin Configuration
Note: The exposed paddle must be connected to −VS or it must be electrically isolated (floating).
Table 5. 8-Lead SOIC Pin Function Descriptions
Table 6. 8-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
Feedback Pin
Inverting Input
Noninverting Input
Negative Supply
NC
Output
Positive Supply
NC
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
9
FEEDBACK
−IN
+IN
−VS
NC
OUTPUT
+VS
NC
1
2
3
4
5
6
7
8
9
NC
FEEDBACK
−IN
+IN
−VS
NC
OUTPUT
+VS
No Connect
Feedback Pin
Inverting Input
Noninverting Input
Negative Supply
No Connect
Output
Positive Supply
Must Be Connected to −VS or
Electrically Isolated
Exposed Paddle
Must Be Connected to −VS or
Electrically Isolated
Exposed Paddle
Rev. A | Page 6 of 24
AD8045
TYPICAL PERFORMANCE CHARACTERISTICS
1
12
11
10
9
V
R
= ±5V
= 1kΩ
G = +2
= ±5V
S
V
L
S
18pF
10pF
0
–1
–2
–3
–4
–5
–6
–7
R
R
= 1kΩ
= 499Ω
L
F
G = +2
G = –1
8
7
G = +10
6
5
5pF
4
0pF
3
2
1
0
10
1
10
100
1000
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Small Signal Frequency Response for Various Capacitive Loads
4
4
G = +1
G = +1
= ±5V
R
= 1kΩ
L
V
= ±5V
V
S
3
2
3
2
S
R = 1kΩ
R
= 100Ω
L
S
R
= 500Ω
L
1
1
0
0
R
= 100Ω
L
–1
–2
–3
–4
–5
–6
–1
–2
–3
–4
–5
–6
–40°C
+125°C
+25°C
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 8. Small Signal Frequency Response for Various Loads
Figure 11. Small Signal Frequency Response for Various Temperatures
5
6.3
G = +2
G = +1
V
R
R
= ±5V
= 499Ω
= 150Ω
R
R
= 1kΩ
= 100Ω
S
L
S
4
3
F
L
V
= ±2.5V
6.2
6.1
6.0
5.9
5.8
5.7
S
2
V
= ±5V
S
V
= 2V p-p
OUT
1
0
V
= 200mV p-p
OUT
–1
–2
–3
–4
–5
10
100
FREQUENCY (MHz)
1000
1
10
FREQUENCY (MHz)
100
Figure 9. Small Signal Frequency Response for Various Supplies
Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages
Rev. A | Page 7 of 24
AD8045
2
1
70
60
50
40
30
20
10
0
0
G = +1
V
R
= ±5V
= 1kΩ
S
R
= 1kΩ
L
L
–45
R
= 100Ω
S
0
V
= 2V p-p
OUT
–1
–2
–3
–4
–5
–6
–7
–8
–9
–90
V
= ±5V
S
–135
–180
–225
–270
–315
–360
V
= ±2.5V
S
–10
10
–10
0.01
100
FREQUENCY (MHz)
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 13. Large Signal Frequency Response for Various Supplies
Figure 16. Open-Loop Gain and Phase vs. Frequency
–20
–30
2
G = +1
G = +1
V
S
= ±5V
V
V
= ±5V
1
0
S
S
R
= 100Ω
= 2V p-p
= 2V p-p
OUT
V
R
R
= 1kΩ
= 100Ω
OUT
L
S
–40
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
R
= 1kΩ
–50
L
–60
–70
R
= 100Ω
L
–80
HD3 SOIC AND LFCSP
–90
HD2 LFCSP
HD2 SOIC
–100
–110
–120
0.1
1
10
FREQUENCY (MHz)
100
10
100
FREQUENCY (MHz)
1000
Figure 17. Harmonic Distortion vs. Frequency for Various Packages
Figure 14. Large Signal Frequency Response for Various Loads
2
–30
G = +1
G = +2
V
V
= ±5V
S
1
0
–40
–50
= 4V p-p
OUT
HD2 SOIC
R
= 1kΩ
L
HD2 LFCSP
–1
–2
–60
G = +10
–70
G = –1
HD3 LFCSP AND SOIC
–3
–4
–5
–6
–7
–8
–80
–90
–100
–110
–120
V
R
R
V
= ±5V
= 499Ω
= 1kΩ
S
F
L
= 2V p-p
OUT
1
10
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Large Signal Frequency Response for Various Gains
Figure 18. Harmonic Distortion vs. Frequency for Various Packages
Rev. A | Page 8 of 24
AD8045
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–30
–40
G = +2
G = +1
V
V
= ±5V
V
V
= ±5V
S
S
= 2V p-p
= 2V p-p
OUT
OUT
R
R
= 150Ω
= 499Ω
R
R
= 100Ω
= 100Ω
L
F
L
S
–50
–60
HD2 SOIC
–70
HD2 SOIC
–80
HD2 LFCSP
–90
HD2 LFCSP
–100
HD3 SOIC AND LFCSP
100
HD3 SOIC AND LFCSP
100
–110
0.1
1
10
FREQUENCY (MHz)
0.1
1
10
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency for Various Packages
Figure 22. Harmonic Distortion vs. Frequency for Various Packages
–40
–20
G = +10
G = –1
V
V
= ±5V
S
V
V
= ±5V
S
–30
–40
= 2V p-p
= 2V p-p
OUT
–50
–60
OUT
R
= 1kΩ
L
R
= 1kΩ
HD2 SOIC
L
SOIC AND LFCSP
–50
HD2 LFCSP
–70
–60
–70
–80
–80
HD2
–90
–90
HD3 SOIC AND LFCSP
HD3
–100
–100
–110
–110
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
100
FREQUENCY (MHz)
Figure 23. Harmonic Distortion vs. Frequency for Various Packages
Figure 20. Harmonic Distortion vs. Frequency for Various Packages
–30
–50
G = –1
G = +1
V
R
V
= ±5V
= 150Ω
S
V
= ±5V
= 1kΩ
= 100Ω
S
–40
–50
L
R
R
–60
–70
L
S
= 2V p-p
OUT
f = 10MHz
HD2 LFCSP
HD3 SOIC AND LFCSP
–60
–80
HD2 SOIC
–70
–90
–80
–100
–110
–120
–90
HD2 SOIC
–100
HD2 LFCSP
HD3 SOIC AND LFCSP
100
–110
0.1
1
10
FREQUENCY (MHz)
0
1
2
3
4
5
6
7
8
OUTPUT AMPLITUDE (V p-p)
Figure 21. Harmonic Distortion vs. Frequency for Various Packages
Figure 24. Harmonic Distortion vs. Output Voltage for Various Packages
Rev. A | Page 9 of 24
AD8045
–40
–30
–40
–50
–60
–70
–80
–90
–100
G = +1
G = +1
V
= ±5V
V
V
= ±2.5
S
S
R
R
= 150Ω
= 100Ω
= 2V p-p
–50
–60
L
OUT
R
R
= 1kΩ
= 100Ω
S
L
S
f = 10MHz
HD2 LFCSP
–70
HD2 SOIC
HD3 SOIC AND LFCSP
–80
–90
HD2 LFCSP
HD2 SOIC
–100
–110
HD3 SOIC AND LFCSP
0
1
2
3
4
5
6
7
8
1
10
FREQUENCY (MHz)
100
OUTPUT AMPLITUDE (V p-p)
Figure 25. Harmonic Distortion vs. Output Voltage for Various Packages
Figure 28. Harmonic Distortion vs. Frequency for Various Packages
–20
–40
G = –1
G = +1
V
R
= ±5V
= 1kΩ
V
V
R
= ±2.5V
S
S
–30
–40
–50
–60
–70
–80
–90
–100
–50
–60
= 2V p-p
L
OUT
f = 10MHz
SOIC AND LFCSP
= 100Ω
= 100Ω
L
S
R
–70
–80
HD3 SOIC AND LFCSP
HD2
–90
HD3
–100
–110
–120
HD2 LFCSP
HD2 SOIC
1
10
100
0
1
2
3
4
5
6
7
8
FREQUENCY (MHz)
OUTPUT VOLTAGE (V p-p)
Figure 29. Harmonic Distortion vs. Frequency for Various Packages
Figure 26. Harmonic Distortion vs. Output Voltage
–20
–40
–50
G = –1
G = –1
V
V
= ±2.5V
S
V
= ±5V
S
–30
–40
–50
–60
–70
–80
–90
–100
= 2V p-p
OUT
R
= 150Ω
L
R
= 1kΩ
L
f = 10MHz
SOIC AND LFCSP
–60
–70
HD2 SOIC
HD2 LFCSP
–80
HD3
–90
HD3 SOIC AND LFCSP
–100
–110
–120
HD2
0.1
1
10
FREQUENCY (MHz)
100
0
1
2
3
4
5
6
7
8
OUTPUT VOLTAGE (V p-p)
Figure 30. Harmonic Distortion vs. Frequency for Various Packages
Figure 27. Harmonic Distortion vs. Output Voltage
Rev. A | Page 10 of 24
AD8045
–40
–50
0.15
0.10
0.05
0
R
R
= 100Ω
= 150Ω
G = +1
= +5V
S
L
V
S
G = +1
= ±2.5
R
R
= 1kΩ
= 100Ω
L
S
V
S
OR V = ±5V
f = 10MHz
S
–60
HD3 SOIC AND LFCSP
–70
–80
–0.05
–0.10
–0.15
–90
HD2 SOIC
–100
HD2 LFCSP
–110
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
OUTPUT VOLTAGE (V p-p)
TIME (ns)
Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages
Figure 34. Small Signal Transient Response for Various Supplies and Loads
–40
0.15
R
C
R
= 1kΩ
= 10pF
L
L
G = +1
V
= +5V
S
= 30Ω
–50
–60
SNUB
= ±5V
R
R
= 150Ω
= 100Ω
L
0.10
0.05
0
V
S
S
G = +1
f = 10MHz
–70
HD3 SOIC AND LFCSP
–80
–0.05
–0.10
–0.15
R
30Ω
SNUB
–90
C
R
L
1kΩ
L
–100
10pF
HD2 SOIC
HD2 LFCSP
–110
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
0
5
10
15
20
25
OUTPUT VOLTAGE (V p-p)
TIME (ns)
Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages
Figure 35. Small Signal Transient Response for Various Supplies and Loads
1600
0.15
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
V
= ±2.5V
G = +2
R
V
= 1kΩ
= ±5V
S
L
S
1400
1200
1000
800
600
400
200
0
R
= 1kΩ
C
0.10
0.05
0
OR R = 150kΩ
C
–0.05
–0.10
–0.15
0
1
2
3
4
5
0
5
10
15
20
25
OUTPUT VOLTAGE STEP (V)
TIME (ns)
Figure 33. Slew Rate vs. Output Voltage
Figure 36. Small Signal Transient Response for Various Loads
Rev. A | Page 11 of 24
AD8045
0.20
0.15
0.10
0.05
0
3
2
V
R
= ±5V
= 1kΩ
S
18pF
0pF
L
G = +2
1
0
–1
–2
–3
–4
–0.05
–0.10
0pF
10pF
18pF
G = +2
–0.15
–0.20
V
= ±5V
S
R
= 1kΩ
L
0
5
10
15
20
25
0
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 37. Small Signal Transient Response with Capacitive Load
Figure 40. Large Signal Transient Response with Capacitive Load
3
3
V
= ±5V
S
R
= 100Ω
S
G = +2
2
1
2
1
LOAD = 1kΩ OR 150Ω
0
0
–1
–2
–3
–1
–2
G = –1
V
= ±5V
S
R
= 1kΩ
L
–3
0
5
10
15
20
25
0
5
10
15
20
25
TIME (ns)
TIME (ns)
Figure 38. Large Signal Transient Response for Various Loads
Figure 41. Large Signal Transient Response, Inverting
3
6
5
R
R
= 1kΩ
G = +1
V = ±5V
S
f = 5MHz
INPUT
L
= 100Ω
S
G = +1
V
= ±5V
2
1
4
S
3
OUTPUT
2
V
= ±2.5V
1
S
0
0
–1
–2
–3
–4
–5
–6
–1
–2
–3
0
5
10
15
20
25
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
TIME (ns)
Figure 39. Large Signal Transient Response for Various Supplies
Figure 42. Input Overdrive Recovery
Rev. A | Page 12 of 24
AD8045
6
5
0
–10
–20
–30
–40
–50
–60
–70
–80
G = +2
= ±5V
f = 5MHz
V
= ±5V
S
2 × INPUT
V
S
4
3
2
OUTPUT
1
–PSR
0
+PSR
–1
–2
–3
–4
–5
–6
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 43. Output Overdrive Recovery
Figure 46. Power Supply Rejection vs. Frequency
100
10
1
–30
V
R
= ±5V
= 499Ω
S
F
–40
–50
–60
–70
–80
–90
10
100
1k
10k
100k
1M
10M
100M
1G
0.1
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 44. Voltage Noise vs. Frequency
Figure 47. Common-Mode Rejection vs. Frequency
100k
10k
1000
100
10
100
V
= ±5V
S
G = +1
10
1
100
1
10
100
1000
1k
10k
100k
1M
10M
100M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 48. Input Impedance vs. Frequency
Figure 45. Current Noise vs. Frequency
Rev. A | Page 13 of 24
AD8045
1000
V
= ±5V
S
G = +1
= ±5V
N = 450
X = 50µV
σ = 180µV
100
80
60
40
20
0
V
S
100
10
1
0.1
0.01
–900
–600
–300
0
300
600
900
1
10
100
1000
V
(µV)
OFFSET
FREQUENCY (MHz)
Figure 49. Output Impedance vs. Frequency
Figure 52. VOS Distribution for VS = 5 V
50
48
46
44
42
40
38
36
34
32
30
V
= +5V
S
G = +10
N = 450
X = 540µV
σ = 195µV
V
R
= ±5V
= 1kΩ
S
L
80
60
40
20
0
–300
0
300
600
900
1200
1500
5
10
20
30
40
V
(µV)
OFFSET
FREQUENCY (MHz)
Figure 50. Third-Order Intercept vs. Frequency
Figure 53. VOS Distribution for VS = +5 V
500
300
0
0.25
0.20
0.15
0.10
0.05
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
–0.20
GAIN
G = +2
= ±5V
V
S
100
V
= +5V
S
–100
–300
–500
–700
–900
–1100
V
= ±5V
S
PHASE
–40 –25 –10
5
20
35
50
65
80
95 110 125
1
10
TEMPERATURE (°C)
NUMBER OF 150Ω LOADS
Figure 54. Offset Voltage vs. Temperature for Various Supplies
Figure 51. Differential Gain and Phase vs. Number of 150 Ω Loads
Rev. A | Page 14 of 24
AD8045
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
1.5
1.0
+V – V
S
OUT
I
–, V = ±5V
S
B
0.5
I
+, V = ±5V
S
V
= ±5V
V = +5V
S
B
S
0
I
–, V = 5V
S
B
–0.5
–1.0
–1.5
I
+, V = 5V
S
B
–V – V
S
OUT
–40 –25 –10
5
20
35
50
65
80
95 110 125
0.1
1
LOAD (kΩ)
10
TEMPERATURE (°C)
Figure 55. Input Bias Current vs. Temperature for Various Supplies
Figure 58. Output Saturation Voltage vs. Load for Various Supplies
1.20
4
3
2
1
0
R
= 1kΩ
L
V
= ±5V
S
1.15
1.10
1.05
1.00
0.95
0.90
–V + V
S
OUT
R
= 1kΩ
L
V
= 5V
–1
–2
–3
–4
S
+V – V
S
OUT
–V + V
OUT
+V – V
S
S
OUT
R
= 150Ω
L
125
–40 –25 –10
5
20
35
50
65
80
95 110
–4
–3
–2
–1
0
1
2
3
4
TEMPERATURE (°C)
V
(V)
OUT
Figure 56. Output Saturation Voltage vs. Temperature for Various Supplies
Figure 59. Input Offset Voltage vs. Output Voltage for Various Loads
17.0
0.30
G = +2
V
V
R
R
= ±5V
S
= 2V p-p
OUT
0.20
0.10
0
= 150Ω
= 499Ω
L
F
16.5
V
= ±5V
S
16.0
15.5
15.0
14.5
V
= 5V
S
–0.10
–0.20
–0.30
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
TIME (ns)
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 60. Short Term 0.1% Settling Time
Figure 57. Supply Current vs. Temperature for Various Supplies
Rev. A | Page 15 of 24
AD8045
CIRCUIT CONFIGURATIONS
WIDEBAND OPERATION
R
F
Figure 61 and Figure 62 show the recommended circuit
configurations for noninverting and inverting amplifiers. In
unity gain (G = +1) applications, RS helps to reduce high
frequency peaking. It is not needed for any other configurations.
For more information on layout, see the Printed Circuit Board
Layout section.
10µF
+V
S
+
0.1µF
R
G
V
IN
R
SNUB
V
AD8045
OUT
0.1µF
The resistor at the output of the amplifier, labeled RSNUB, is used
only when driving large capacitive loads. Using RSNUB improves
stability and minimizes ringing at the output. For more infor-
mation, see the Driving Capacitive Loads section.
R = R ||R
G
F
10µF
+
–V
S
R
F
Figure 62. Inverting Configuration
10µF
+V
S
+
0.1µF
R
G
R
SNUB
V
AD8045
OUT
R
S
V
IN
0.1µF
10µF
+
–V
S
Figure 61. Noninverting Configuration
Rev. A | Page 16 of 24
AD8045
THEORY OF OPERATION
R
The AD8045 is a high speed voltage feedback amplifier fabri-
cated on ADI’s second generation eXtra Fast Complementary
Bipolar (XFCB) process. An H-bridge input stage is used to
attain a 1400 V/µs slew rate and low distortion in addition to a
low 3 nV/√Hz input voltage noise. Supply current and offset
voltage are laser trimmed for optimum performance.
S
+V
–
OUT
V
IN
R
F
R
G
FREQUENCY RESPONSE
The AD8045’s open-loop response over frequency can be
approximated by the integrator response shown in Figure 63.
Figure 64. Noninverting Configuration
DC ERRORS
V
V
OUT
Figure 65 shows the dc error contributions. The total output
error voltage is
IN
R +R
RG
R +R
G
F
RG
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
G
F
VOUT(ERROR)=−I R
+I R +V
B−
F
OS
B+
S
⎝
⎠
⎝
⎠
V
OS
R
S
I
+
–
B
+V
–
OUT
fCROSSOVER
fCROSSOVER = 400MHz
V
/V
=
OUT IN
f
I
B
0
1
10
100
FREQUENCY (MHz)
1000
R
F
Figure 63. Open-Loop Response
R
G
The closed-loop transfer function for the noninverting configu-
ration is shown in Figure 64 and is written as
Figure 65. Amplifier DC Errors
The voltage error due to IB+ and IB− is minimized if RS = RF||RG.
To include the effects of common-mode and power supply
rejection, model VOS as
2 π× fCROSSOVER ×(RG + RF )
RF + RG s +2 π× fCROSSOVER ×RG
VOUT
VIN
=
(
)
where:
s is (2 πj)f.
CROSSOVER is the frequency where the amplifier’s open-loop gain
∆VS ∆VCM
PSR CMR
VOS =VOS
+
+
nom
where:
f
equals 1 (0 dB).
Vos is the offset voltage at nominal conditions.
nom
DC gain is therefore
ΔVS is the change in the power supply voltage from nominal
conditions.
VOUT
VIN
(
RG + RF
RG
)
=
PSR is the power supply rejection.
Closed-loop −3 dB bandwidth equals
CMR is the common-mode rejection.
VOUT
VIN
RG
RG + RF
)
= fCROSSOVER
×
ΔVCM is the change in common-mode voltage from nominal
conditions.
(
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (RF + RG)/RG. This simple
model can be used to predict the −3 dB bandwidth for noise
gains above +2. The actual bandwidth of circuits with noise
gains at or below +2 is higher due to the influence of other
poles present in the real op amp.
Rev. A | Page 17 of 24
AD8045
OUTPUT NOISE
Ven ,
, and
are due to the amplifier. V , VR , and
IN−
RF
G
IN+
Figure 66 shows the contributors to the noise at the output of a
noninverting configuration.
VR are due to the feedback network resistors. RG and RF, and
S
source resistor, RS. Total output voltage noise, VOUT _ EN , is the
V
V
RS
EN
R
rms sum of all the contributions.
S
I
+
–
EN
+V
–
OUT
V
=
OUT _ EN
I
EN
2
2
2
2
2
(
G
×Ven
)
+
(
IN + × R ×G
)
+
(
IN −× R ||R ×G
)
+ 4kTR + 4kTR G + 4kTR G
( ) ( )
n n
G S
f
n
n
F
n
S
G
V
RF
R
where:
Gn is the noise gain
F
R
G
R
+ R
⎛
⎜
⎞
F
G
.
⎟
⎠
V
RG
R
G
⎝
Figure 66. Amplifier DC Errors
Ven is the op amp input voltage noise.
IN is the op amp input current noise.
Table 7 lists the expected output voltage noise spectral density
for several gain configurations.
Table 7. Noise and Bandwidth for Various Gains
Output
Noise
(nV/√Hz)
−3 dB
Gain
+1
+2
+5
+10
−1
RF
RG
RS
100
0
0
0
Bandwidth1
0
−
1 GHz
3.3
7.4
16.4
31
499
499
499
499
499
124
56
400 MHz
90 MHz
40 MHz
300 MHz
499
N/A
7.4
1 RL = 1 kΩ.
Rev. A | Page 18 of 24
AD8045
APPLICATIONS
LOW DISTORTION PINOUT
This dc-coupled differential driver is best suited for 5 V
operation in which optimum distortion performance is required
and the input signal is ground referenced.
The AD8045 LFCSP package features Analog Devices new low
distortion pinout. The new pinout provides two advantages
over the traditional pinout. First, improved second harmonic
distortion performance, which is accomplished by the physical
separation of the noninverting input pin and the negative power
supply pin. Second, the simplification of the layout due to the
dedicated feedback pin and easy routing of the gain set resistor
back to the inverting input pin. This allows a compact layout,
which helps to minimize parasitics and increase stability.
511Ω
V
– V
IN
CML
AD8045
511Ω
33Ω
V
INA
511Ω
511Ω
511Ω
511Ω
V
IN
20pF
AD9244
V
+ V
IN
CML
The traditional SOIC pinout has been slightly modified as well
to incorporate a dedicated feedback pin. Pin 1, previously a no
connect pin on the amplifier, is now a dedicated feedback pin. The
new pinout reduces parasitics and simplifies the board layout.
AD8045
33Ω
V
INB
511Ω
511Ω
2.5kΩ
0.1µF
Existing applications that use the traditional SOIC pinout can
take full advantage of the outstanding performance offered by
the AD8045. An electrical insulator may be required if the SOIC
rests on the ground plane or other metal trace. This is covered
in more detail in the Exposed Paddle section of this data sheet.
In existing designs, which have Pin 1 tied to ground or to
another potential, simply lift Pin 1 of the AD8045 or remove the
potential on the Pin 1 solder pad. The designer does not need to
use the dedicated feedback pin to provide feedback for the
AD8045. The output pin of the AD8045 can still be used to pro-
vide feedback to the inverting input of the AD8045.
100Ω
1µF
CML
0.1µF
OP27
Figure 67. High Speed ADC Driver
The outputs of the AD8045s are centered about the AD9244’s
common-mode range of 2.5 V. The common-mode reference
voltage from the AD9244 is buffered and filtered via the OP27
and fed to the noninverting resistor network used in the level
shifting circuit.
HIGH SPEED ADC DRIVER
The spurious-free dynamic range (SFDR) performance is
shown in Figure 68. Figure 69 shows a 50 MHz single-tone FFT
performance.
When used as an ADC driver, the AD8045 offers results compa-
rable to transformers in distortion performance. Many ADC
applications require that the analog input signal be dc-coupled
and operate over a wide frequency range. Under these require-
ments, operational amplifiers are very effective interfaces to
ADCs. An op amp interface provides the ability to amplify and
level shift the input signal to be compatible with the input range
of the ADC. Unlike transformers, operational amplifiers can be
operated over a wide frequency range down to and including dc.
120
100
AD8045
80
60
40
20
0
Figure 67 shows the AD8045 as a dc-coupled differential driver
for the AD9244, a 14-bit 65 MSPS ADC. The two amplifiers are
configured in noninverting and inverting modes. Both amplifi-
ers are set with a noise gain of +2 to provide better bandwidth
matching. The inverting amplifier is set for a gain of –1, while
the noninverting is set for a gain of +2. The noninverting input
is divided by 2 in order to normalize its output and make it
equal to the inverting output.
1
10
100
INPUT FREQUENCY (MHz)
Figure 68. SFDR vs. Frequency
Rev. A | Page 19 of 24
AD8045
0
A
= –1dBFS
Setting the resistors and capacitors equal to each other greatly
simplifies the design equations for the Sallen-Key filter. The
corner frequency, or −3 dB frequency, can be described by the
equation
IN
SNR = 69.9dBc
SFDR = 65.3dBc
–20
–40
1
fc =
–60
2πRC
The quality factor, or Q, is shown in the equation
–80
1
Q =
–100
3 − K
–120
0
The gain, or K, of the circuits are
5
10
15
20
25
30
FREQUENCY (MHz)
R3
R4
R8
R7
Figure 69. Single-Tone FFT, FIN = 50 MHz, Sample Rate = 65 MSPS
Shown in the First Nyquist Zone
First Stage K =
+1, Second Stage K =
+1
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response. Due to the low
capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical.A few picofarads can detune
the filters corner frequency, fc. The capacitor values shown in
Figure 73 actually incorporate some stray PCB capacitance.
90 MHZ ACTIVE LOW-PASS FILTER (LPF)
Active filters are used in many applications such as antialiasing
filters and high frequency communication IF strips.
With a 400 MHz gain bandwidth product and high slew rate,
the AD8045 is an ideal candidate for active filters. Figure 70
shows the frequency response of the 90 MHz LPF. In addition to
the bandwidth requirements, the slew rate must be capable of
supporting the full power bandwidth of the filter. In this case, a
90 MHz bandwidth with a 2 V p-p output swing requires at least
1200 V/µs. This performance is achievable only at 90 MHz
because of the AD8045’s wide bandwidth and high slew rate.
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors and silver mica, are good choices for filter
elements.
20
10
The circuit shown in Figure 73 is a 90 MHz, 4-pole, Sallen-Key,
LPF. The filter comprises two identical cascaded Sallen-Key LPF
sections, each with a fixed gain of G = +2. The net gain of the
filter is equal to G = +4 or 12 dB. The actual gain shown in
Figure 70 is only 6 dB. This is due to the output voltage being
divided in half by the series matching termination resistor, RT,
and the load resistor.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 70. 90 MHz Low-Pass Filter Response
Rev. A | Page 20 of 24
AD8045
1
1
CH1 50.0mV
M4.00ns
A CH1
0.00V
CH1 500mV
M4.00ns
A CH1
0.00V
Figure 71. Small Signal Transient Response of 90 MHz LPF
Figure 72. Large Signal Transient Response of 90 MHz LPF
C1
7.1pF
10µF
0.1µF
C3
7.1pF
+5V
U1
10µF
+5V
U1
R1
249Ω
R2
249Ω
0.1µF
R6
249Ω
INPUT
R
49.9Ω
T
R
T
C2
7.1pF
10µF
R5
249Ω
49.9Ω
OUTPUT
C4
7.1pF
10µF
R9
24.9Ω
0.1µF
0.1µF
C5
5pF
–5V
–5V
R4
R3
499Ω
499Ω
R7
499Ω
R8
499Ω
Figure 73. 4-Pole, 90 MHz, Sallen-Key Low-Pass Filter
Rev. A | Page 21 of 24
AD8045
PRINTED CIRCUIT BOARD LAYOUT
Laying out the printed circuit board (PCB) is usually the last
step in the design process and often proves to be one of the
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Since the AD8045 can operate into
the RF frequency spectrum, high frequency board layout con-
siderations must be taken into account. The PCB layout, signal
routing, power supply bypassing, and grounding all must be
addressed to ensure optimal performance.
requirements. Additional smaller value capacitors help to
provide a low impedance path for unwanted noise out to higher
frequencies but are not always necessary.
Placement of the capacitor returns (grounds), where the capaci-
tors enter into the ground plane, is also important. Returning
the capacitors grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
SIGNAL ROUTING
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. It is brought to the designer’s
attention here as another option to improve performance.
The AD8045 LFCSP features the new low distortion pinout with
a dedicated feedback pin and allows a compact layout. The
dedicated feedback pin reduces the distance from the output to
the inverting input, which greatly simplifies the routing of the
feedback network.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduce the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distor-
tion due to high frequency compression at the output. The use
of vias should be minimized in the direct path to the amplifier
power supply pins since vias can introduce parasitic inductance,
which can lead to instability. When required, use multiple large
diameter vias because this lowers the equivalent parasitic
inductance.
When laying out the AD8045 as a unity gain amplifier, it is rec-
ommended that a short, but wide, trace between the dedicated
feedback pin and the inverting input to the amplifier be used to
minimize stray parasitic inductance.
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which
degrades phase margin. Signals that are susceptible to noise
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Ground and power planes should not be used under
any of the pins of the AD8045. The mounting pads and the
ground or power planes can form a parasitic capacitance at the
amplifiers input. Stray capacitance on the inverting input and
the feedback resistor form a pole, which degrades the phase
margin, leading to instability. Excessive stray capacitance on the
output also forms a pole, which degrades phase margin.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8045 power supply pins
need to be properly bypassed.
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps to ensure that the power supply
pins “see” a low ac impedance across a wide band of frequencies.
This is important for minimizing the coupling of noise into the
amplifier. Starting directly at the power supply pins, the smallest
value and sized component should be placed on the same side
of the board as the amplifier, and as close as possible to the
amplifier, and connected to the ground plane. This process
should be repeated for the next larger value capacitor. It is
recommended for the AD8045 that a 0.1 µF ceramic 0508 case
be used. The 0508 offers low series inductance and excellent
high frequency performance. The 0.1 µF case provides low
impedance at high frequencies. A 10 µF electrolytic capacitor
should be placed in parallel with the 0.1 µF. The 10 µf capacitor
provides low ac impedance at low frequencies. Smaller values
of electrolytic capacitors may be used depending on the circuit
Rev. A | Page 22 of 24
AD8045
EXPOSED PADDLE
The AD8045 features an exposed paddle, which lowers the
thermal resistance by 25% compared to a standard SOIC plastic
package. The exposed paddle of the AD8045 is internally con-
nected to the negative power supply pin. Therefore, when laying
out the board, the exposed paddle must either be connected to
the negative power supply or left floating (electrically isolated).
Soldering the exposed paddle to the negative power supply metal
ensures maximum thermal transfer. Figure 74 and Figure 75 show
the proper layout for connecting the SOIC and LFCSP exposed
paddle to the negative supply.
THERMAL CONDUCTIVE INSULATOR
Figure 76. SOIC with Thermal Conductive Pad Material
The thermal pad provides high thermal conductivity but
isolates the exposed paddle from ground or other potential. It is
recommended, when possible, to solder the paddle to the nega-
tive power supply plane or trace for maximum thermal transfer.
Note that soldering the paddle to ground shorts the negative
power supply to ground and can cause irreparable damage to
the AD8045.
DRIVING CAPACITIVE LOADS
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest. The difficulty arises
because the load capacitance, CL, forms a pole with the output
resistance, RO, of the amplifier. The pole can be described by the
equation
Figure 74. SOIC Exposed Paddle Layout
The use of thermal vias or “heat pipes” can also be incorporated
into the design of the mounting pad for the exposed paddle.
These additional vias help to lower the overall theta junction to
ambient (θJA). Using a heavier weight copper on the surface to
which the amplifier’s exposed paddle is soldered can greatly
reduce the overall thermal resistance “seen” by the AD8045.
1
fP
=
2πROCL
If this pole occurs too close to the unity gain crossover point,
the phase margin degrades. This is due to the additional phase
loss associated with the pole.
The AD8045 output can drive 18 pF of load capacitance directly,
in a gain of +2 with 30% overshoot, as shown in Figure 37.
Larger capacitance values can be driven but must use a snub-
bing resistor (RSNUB) at the output of the amplifier, as shown in
Figure 75. LFCSP Exposed Paddle Layout
For existing designs that want to incorporate the AD8045,
electrically isolating the exposed paddle is another option. If the
exposed paddle is electrically isolated, the thermal dissipation is
primarily through the leads, and the thermal resistance of the
package now approaches 125°C/W, the standard SOIC θJA.
However, a thermally conductive and electrically isolated pad
material may be used. A thermally conductive spacer, such as
the Bergquist Company’s Sil-Pad, is an excellent solution to this
problem. Figure 76 shows a typical implementation using
thermal pad material.
Figure 61 and Figure 62. Adding a small series resistor, RSNUB
creates a zero that cancels the pole introduced by the load
capacitance. Typical values for RSNUB can range from 25 Ω to
,
50 Ω. The value is typically arrived at empirically and based on
the circuit requirements.
Rev. A | Page 23 of 24
AD8045
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
BOTTOM VIEW
(PINS UP)
2.29 (0.092)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
2.29 (0.092)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
1.27 (0.05)
BSC
0.50 (0.020)
0.25 (0.010)
× 45°
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
1.27 (0.050)
0.40 (0.016)
0.51 (0.020)
0.31 (0.012)
0.25 (0.0098)
0.17 (0.0068)
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 77. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP], Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches)
0.50
0.40
0.30
1
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
0.45
PIN 1
INDICATOR
1.90
1.75
1.60
2.75
BSC SQ
TOP
VIEW
1.50
REF
EXPOSED
PAD
0.50
BSC
(BOTTOM VIEW)
4
5
0.25
MIN
1.60
1.45
1.30
0.80 MAX
0.65TYP
0.90
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 78. 8-Lead Lead Frame Chip Scale Package [LFCSP], 3 mm × 3 mm Body (CP-8-2)—Dimensions shown in millimeters
ORDERING GUIDE
Minimum
Ordering Quantity
Package
Option
Model
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
Branding
AD8045ARD
1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
AD8045ARD-REEL
AD8045ARD-REEL7
AD8045ARDZ1
AD8045ARDZ-REEL1
AD8045ARDZ-REEL71
AD8045ACP-R2
AD8045ACP-REEL
AD8045ACP-REEL7
AD8045ACPZ-R21
AD8045ACPZ-REEL1
AD8045ACPZ-REEL71
2,500
1,000
1
2,500
1,000
250
5,000
1,500
250
5,000
1,500
H8B
H8B
H8B
H8B
H8B
H8B
8-Lead LFCSP
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04814–0–9/04(A)
Rev. A | Page 24 of 24
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