AD8052ARZ [ADI]
Low Cost, High Speed, Rail-to-Rail Amplifiers; 低成本，高速，轨到轨放大器
| 型号： | AD8052ARZ |
| 厂家： | 
ADI |
| 描述： | Low Cost, High Speed, Rail-to-Rail Amplifiers |
| 文件： | 总24页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, High Speed,
Rail-to-Rail Amplifiers
AD8051/AD8052/AD8054
FEATURES
PIN CONNECTIONS (TOP VIEWS)
High speed and fast settling on 5 V
110 MHz, −3 dB bandwidth (G = +1) (AD8051/AD8052)
150 MHz, −3 dB bandwidth (G = +1) (AD8054)
145 V/μs slew rate
AD8051
1
2
3
4
8
NC
NC
–IN
+IN
AD8051
V
1
2
5
+V
OUT
S
7
6
5
+V
S
–V
S
V
+ –
OUT
–V
S
NC
+IN
3
4
–IN
50 ns settling time to 0.1%
NC = NO CONNECT
Single-supply operation
Figure 1. SOIC-8 (R)
Figure 2. SOT-23-5 (RJ)
Output swings to within 25 mV of either rail
Input voltage range: −0.2 V to +4 V; VS = 5 V
Video specifications (G = +2)
0.1 dB gain flatness: 20 MHz; RL = 150 Ω
Differential gain/phase: 0.03%/0.03°
Low distortion
1
2
3
4
5
6
7
14
13
OUT D
–IN D
OUT A
–IN A
AD8052
1
2
3
4
+V
S
8
7
6
5
OUT1
–IN1
12 +IN D
+IN A
V+
–
+
OUT
–IN2
+IN2
11
AD8054
V–
+IN1
–
+
10
9
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
−80 dBc total harmonic @ 1 MHz, RL = 100 Ω
Outstanding load drive capability
–V
S
8
Drives 45 mA, 0.5 V from supply rails (AD8051/AD8052)
Drives 50 pF capacitive load (G = +1) (AD8051/AD8052)
Low power: 2.75 mA/amplifier (AD8054)
Low power: 4.4 mA/amplifier (AD8051/AD8052)
Figure 3. SOIC (R-8) and MSOP (RM-8) Figure 4. SOIC (R-14) and TSSOP (RU-14)
5.0
4.5
APPLICATIONS
V
= 5V
S
G = –1
Active filters
Analog-to-digital drivers
Clock buffer
Consumer video
Professional cameras
CCD imaging systems
CD/DVD ROMs
4.0
3.5
3.0
2.5
2.0
R
R
= 2kΩ
= 2kΩ
F
L
1.5
1.0
0.5
0
0.1
1
10
50
FREQUENCY (MHz)
Figure 5. Low Distortion Rail-to-Rail Output Swing
GENERAL DESCRIPTION
The AD8051 (single), AD8052 (dual), and AD8054 (quad) are
low cost, high speed, voltage feedback amplifiers. The amplifiers
operate on +3 V, +5 V, or 5 V supplies at low supply current.
They have true single-supply capability with an input voltage
range extending 200 mV below the negative rail and within 1 V
of the positive rail.
The AD8051/AD8052/AD8054 are well suited for video
electronics, cameras, video switchers, or any high speed portable
equipment. Low distortion and fast settling make them ideal for
active filter applications.
The AD8051/AD8052 in the 8-lead SOIC, the AD8052 in the
MSOP, the AD8054 in the 14-lead SOIC, and the 14-lead TSSOP
packages are available in the extended temperature range of
−40°C to +125°C.
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage
swings to within 25 mV of each rail, providing maximum output
dynamic range with excellent overdrive recovery.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8051/AD8052/AD8054
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description .................................................................... 16
Application Information................................................................ 17
Overdrive Recovery ................................................................... 17
Driving Capacitive Loads.......................................................... 17
Layout Considerations............................................................... 18
Active Filters ............................................................................... 18
Analog-to-Digital and Digital-to-Analog Applications........ 19
Sync Stripper............................................................................... 20
Single-Supply Composite Video Line Driver ......................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Pin Connections (Top Views)......................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Maximum Power Dissipation ..................................................... 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
REVISION HISTORY
12/07—Rev. G to Rev. H
2/03—Rev. C to Rev. D
Changes to Applications .................................................................. 1
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 23
Changes to General Description .....................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................6
5/06—Rev. F to Rev. G
1/03—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Features, Applications, and General Description.....1
Changes to Figure 15...................................................................... 12
Changes to the Ordering Guide.................................................... 22
Changes to General Description .....................................................1
Changes to Pin Connections............................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................9
Changes to Figure 2...........................................................................9
Changes to Ordering Guide.............................................................9
Updated Outline Dimensions........................................................20
9/04—Rev. E to Rev. F
Changes to Ordering Guide .............................................................7
Changes to Figure 15...................................................................... 15
3/04—Rev. D to Rev. E
Changes to General Description .....................................................2
Changes to Specifications.................................................................3
Changes to Ordering Guide .............................................................6
Rev. H | Page 2 of 24
AD8051/AD8052/AD8054
SPECIFICATIONS
@ TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
AD8051A/AD8052A
AD8054A
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, VOUT = 0.2 V p-p
G = −1, +2, VOUT = 0.2 V p-p
70
110
50
80
150
60
MHz
MHz
Bandwidth for 0.1 dB Flatness
G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω to 2.5 V
RF = 806 Ω (AD8051A/
AD8052A)
20
MHz
RF = 200 Ω (AD8054A)
G = −1, VOUT = 2 V step
G = +1, VOUT = 2 V p-p
G = −1, VOUT = 2 V step
12
170
45
MHz
V/μs
MHz
MHz
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
100
145
35
50
140
40
fC = 5 MHz, VOUT = 2 V p-p,
G = +2
−67
−68
dB
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
f = 10 kHz
f = 10 kHz
16
16
nV/√Hz
fA/√Hz
%
850
0.09
0.03
0.19
0.03
−60
850
0.07
0.02
0.26
0.05
−60
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
f = 5 MHz, G = +2
%
Differential Phase Error (NTSC)
Degrees
Degrees
dB
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.7
10
25
1.7
12
30
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
TMIN − TMAX
Offset Drift
Input Bias Current
10
1.4
15
2
2.5
3.25
0.75
4.5
4.5
1.2
TMIN − TMAX
Input Offset Current
Open-Loop Gain
0.1
98
96
82
78
0.2
98
96
82
78
RL = 2 kΩ to 2.5 V
TMIN − TMAX
RL = 150 Ω to 2.5 V
TMIN − TMAX
86
76
82
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
290
1.4
−0.2 to
+4
300
1.5
−0.2 to
+4
kΩ
pF
V
Input Common-ModeVoltage Range
Common-Mode Rejection Ratio
VCM = 0 V to 3.5 V
72
88
70
86
dB
Rev. H | Page 3 of 24
AD8051/AD8052/AD8054
AD8051A/AD8052A
AD8054A
Typ
Parameter
Conditions
Min
Typ
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ to 2.5 V
RL = 2 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
0.015 to
4.985
0.1 to 0.025 to
4.9 4.975
0.3 to 0.2 to
4.625 4.8
0.03 to
4.975
0.125 to 0.05 to
V
V
V
4.875
0.55 to
4.4
4.95
0.25 to
4.65
Output Current
VOUT = 0.5 V to 4.5 V
TMIN − TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
45
45
80
130
50
30
30
45
85
mA
mA
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
40
pF
POWER SUPPLY
Operating Range
3
12
5
3
12
3.275
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
4.4
80
2.75
80
mA
dB
°C
°C
ΔVS = 1 V
70
68
−40
RJ-5
−40
−40
+85
+125
RM-8, R-8, RU-14, R-14
+125
1 Refer to Figure 19.
Rev. H | Page 4 of 24
AD8051/AD8052/AD8054
@ TA = 25°C, VS = 3 V, RL = 2 kΩ to 1.5 V, unless otherwise noted.
Table 2.
AD8051A/AD8052A
AD8054A
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, VOUT = 0.2 V p-p
70
110
50
80
135
65
MHz
MHz
G = −1, +2, VOUT
0.2 V p-p
=
Bandwidth for 0.1 dB Flatness
G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω to 2.5 V
RF = 402 Ω (AD8051A/
AD8052A)
17
MHz
RF = 200 Ω (AD8054A)
G = −1, VOUT = 2 V step
G = +1, VOUT = 1 V p-p
G = −1, VOUT = 2 V step
10
150
85
MHz
V/μs
MHz
ns
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
90
135
65
55
110
55
fC = 5 MHz, VOUT = 2 V p-p,
G = −1, RL = 100 Ω to 1.5 V
−47
−48
dB
Input Voltage Noise
Input Current Noise
f = 10 kHz
f = 10 kHz
16
600
16
600
nV/√Hz
fA/√Hz
Differential Gain Error (NTSC)
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
f = 5 MHz, G = +2
0.11
0.09
0.13
0.09
%
%
Differential Phase Error (NTSC)
0.24
0.10
−60
0.3
0.1
−60
Degrees
Degrees
dB
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.6
10
25
1.6
12
30
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
TMIN − TMAX
Offset Drift
Input Bias Current
10
1.3
15
2
2.6
3.25
0.8
4.5
4.5
1.2
TMIN − TMAX
Input Offset Current
Open-Loop Gain
0.15
96
94
82
76
0.2
96
94
80
76
RL = 2 kΩ
TMIN − TMAX
RL = 150 Ω
TMIN − TMAX
80
74
80
72
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
290
1.4
−0.2 to
+2
300
1.5
−0.2 to
+2
kΩ
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
VCM = 0 V to 1.5 V
72
88
70
86
dB
Rev. H | Page 5 of 24
AD8051/AD8052/AD8054
AD8051A/AD8052A
AD8054A
Typ
Parameter
Conditions
Min
Typ
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ to 1.5 V
RL = 2 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
0.01 to
2.99
0.0.75 to 0.02 to
0.025 to
2.98
0.35 to
2.965
V
V
V
0.1 to
2.9
2.9
0.2 to
2.75
2.98
0.125 to
2.875
0.35 to 0.15 to
2.55
2.75
Output Current
VOUT = 0.5 V to 2.5 V
TMIN − TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
45
45
60
90
45
25
25
30
50
mA
mA
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
35
pF
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
4.2
80
4.8
2.625
80
3.125 mA
ΔVS = 0.5 V
68
68
−40
dB
°C
RJ-5
−40
−40
+85
+125
RM-8, R-8, RU-14, R-14
+125
°C
1 Refer to Figure 19.
Rev. H | Page 6 of 24
AD8051/AD8052/AD8054
@ TA = 25°C, VS = 5 V, RL = 2 kΩ to ground, unless otherwise noted.
Table 3.
AD8051A/AD8052A
AD8054A
Parameter
Conditions
Min
Typ
Max Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = +1, VOUT = 0.2 V p-p
G = −1, +2, VOUT = 0.2 V p-p
70
110
50
85
160
65
MHz
MHz
Bandwidth for 0.1 dB Flatness
G = +2, VOUT = 0.2 V p-p,
RL = 150 Ω,
RF = 1.1 kΩ (AD8051A/
AD8052A)
20
MHz
RF = 200 Ω (AD8054A)
G = −1, VOUT = 2 V step
G = +1, VOUT = 2 V p-p
G = −1, VOUT = 2 V step
15
190
50
MHz
V/μs
MHz
MHz
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
105
170
40
50
150
40
fC = 5 MHz, VOUT = 2 V p-p,
G = +2
−71
−72
dB
Input Voltage Noise
f = 10 kHz
16
16
nV/√Hz
Input Current Noise
Differential Gain Error (NTSC)
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
f = 5 MHz, G = +2
900
0.02
0.02
0.11
0.02
−60
900
0.06
0.02
0.15
0.03
−60
fA/√Hz
%
%
Degrees
Degrees
dB
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.8
11
27
1.8
13
32
mV
mV
μV/°C
μA
μA
μA
dB
dB
dB
dB
TMIN − TMAX
Offset Drift
Input Bias Current
10
1.4
15
2
2.6
3.5
0.75
4.5
4.5
1.2
TMIN − TMAX
Input Offset Current
Open-Loop Gain
0.1
96
96
82
80
0.2
96
96
82
80
RL = 2 kΩ
TMIN − TMAX
RL = 150 Ω
TMIN − TMAX
88
78
84
76
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
290
1.4
−5.2 to
+4
300
1.5
−5.2 to
+4
kΩ
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
VCM = −5 V to +3.5 V
72
88
70
86
dB
RL = 10 kΩ
RL = 2 kΩ
RL = 150 Ω
−4.98 to
+4.98
−4.97 to
+4.97
V
V
V
−4.85 to −4.97 to
+4.85 +4.97
−4.45 to −4.6 to
−4.8 to −4.9 to
+4.8 +4.9
−4.0 to −4.5 to
+4.3
+4.6
+3.8
+4.5
Output Current
VOUT = −4.5 V to +4.5 V
TMIN − TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
45
45
100
160
50
30
30
60
100
mA
mA
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
40
pF
Rev. H | Page 7 of 24
AD8051/AD8052/AD8054
AD8051A/AD8052A
AD8054A
Typ
Parameter
Conditions
Min
Typ
Max Min
Max Unit
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
4.8
80
5.5
2.875
80
3.4
mA
dB
°C
ΔVS =
RJ-5
RM-8, R-8, RU-14, R-14
1
68
68
−40
−40
+85
+125 −40
+125 °C
Rev. H | Page 8 of 24
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS
Table 4.
MAXIMUM POWER DISSIPATION
Parameter
Ratings
The maximum power that can be safely dissipated by the
AD8051/AD8052/AD8054 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
Supply Voltage
Internal Power Dissipation1
SOIC Packages
12.6 V
Observe power
derating curves
Observe power
derating curves
Observe power
derating curves
Observe power
derating curves
VS
2.5 V
Observe power
derating curves
−65°C to +150°C
SOT-23 Package
MSOP Package
TSSOP Package
While the AD8051/AD8052/AD8054 are internally short-
circuit protected, this cannot be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves.
2.5
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range (R)
Operating Temperature Range (A Grade) −40°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
SOIC-14
SOIC-8
2.0
1.5
1.0
1 See Table 5.
TSSOP-14
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MSOP-8
0.5
0
SOT-23-5
THERMAL RESISTANCE
–55 –35 –15
5
15
35
55
75
95
115
AMBIENT TEMPERATURE (°C)
Specification is for device in free air.
Figure 6. Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
Table 5. Thermal Resistance
ESD CAUTION
Package Type
θJA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
8-Lead SOIC
125
180
150
90
5-Lead SOT-23
8-Lead MSOP
14-Lead SOIC
14-Lead TSSOP
120
Rev. H | Page 9 of 24
AD8051/AD8052/AD8054
TYPICAL PERFORMANCE CHARACTERISTICS
3
5
4
3
2
1
G = +1
= 0
V
= 5V
S
G = +2
= 2kΩ
2
R
G = +2
F
GAIN AS SHOWN
R
R
R
F
R
= 2kΩ
AS SHOWN
= 5kΩ
F
F
1
L
V
= 0.2V p-p
OUT
0
–1
–2
G = +5
= 2kΩ
R
F
0
–1
–2
–3
G = +1
= 0
G = +10
= 2kΩ
R
F
R
F
G = +10
= 2kΩ
–3
–4
–5
R
F
V
= 5V
S
GAIN AS SHOWN
R
R
–4
–5
–6
–7
AS SHOWN
= 2kΩ
F
L
G = +5
= 2kΩ
V
= 0.2V p-p
OUT
–6
–7
R
F
0.1
1
10
FREQUENCY (MHz)
100
500
100k
1M
10M
FREQUENCY (Hz)
100M
500M
Figure 7. AD8051/AD8052 Normalized Gain vs. Frequency; VS = 5 V
Figure 10. AD8054 Normalized Gain vs. Frequency; VS = 5 V
3
6
V
AS SHOWN
S
G = +1
5
2
1
G = +1
= 2kΩ
+3V
+5V
±5V
R
C
= 2kΩ
L
L
V
= +5V
V
= +3V
S
S
R
L
= 5pF
4
V
= 0.2V p-p
OUT
V
= 0.2V p-p
OUT
0
3
2
–1
V
= ±5V
S
–2
–3
–4
–5
1
0
±5V
–1
–2
–3
–4
+3V
+5V
–6
–7
100k
1M
10M
100M
500M
0.1
1
10
FREQUENCY (MHz)
100
500
FREQUENCY (Hz)
Figure 8. AD8051/AD8052 Gain vs. Frequency vs. Supply
Figure 11. AD8054 Gain vs. Frequency vs. Supply
4
3
3
V
R
C
= 5V
= 2kΩ TO 2.5V
= 5pF
S
+85°C
+25°C
2
1
L
–40°C
L
2
G = +1
= 0.2V p-p
–40°C
V
OUT
0
1
+85°C
+25°C
–1
0
–2
–1
–2
–3
–4
–5
V
= 5V
S
G = +1
R
–3
–4
–5
= 2kΩ
= 0.2V p-p
L
V
OUT
–6 TEMPERATURE AS SHOWN
–7
1
10
FREQUENCY (MHz)
100
500
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 12. AD8054 Gain vs. Frequency vs. Temperature
Figure 9. AD8051/AD8052 Gain vs. Frequency vs. Temperature
Rev. H | Page 10 of 24
AD8051/AD8052/AD8054
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
V
= 5V
V
R
R
= 5V
= 200Ω
= 150Ω
S
S
G = +2
F
L
R
R
V
= 150Ω
L
F
5.5
= 806Ω
= 0.2V p-p
G = +2
V = 0.2V p-p
OUT
5.4
5.3
OUT
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. AD8054 0.1 dB Gain Flatness vs. Frequency; G = +2
Figure 13. AD8051/AD8052 0.1 dB Gain Flatness vs. Frequency; G = +2
9
9
V
V
= +5V
S
8
7
6
V
V
= +5V
8
7
6
S
= 2V p-p
OUT
= 2V p-p
OUT
5
4
3
5
4
3
V
V
= ±5V
S
= 4V p-p
OUT
V
V
= ±5V
S
= 4V p-p
OUT
V
AS SHOWN
V
AS SHOWN
S
S
2
1
2
1
G = +2
G = +2
R
R
V
= 2kΩ
= 2kΩ
AS SHOWN
R
R
V
= 2kΩ
= 2kΩ
AS SHOWN
F
L
F
L
OUT
OUT
0
0
–1
–1
0.1
1
10
FREQUENCY (MHz)
100
500
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 17. AD8054 Large Signal Frequency Response; G = +2
Figure 14. AD8051/AD8052 Large Signal Frequency Response; G = +2
80
70
80
V
R
C
= 5V
= 2kΩ
= 5pF
V
R
= 5V
= 2kΩ
S
S
70
60
50
40
30
20
L
L
L
60
50
40
30
20
GAIN
GAIN
180
0
50° PHASE
MARGIN
135
90
–45
–90
–135
–180
PHASE
45° PHASE
MARGIN
PHASE
10
0
10
0
45
0
–10
–20
–10
–20
30k
100k
1M
10M
100M
500M
0.01
0.1
1
10
100
500
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 18. AD8054 Open-Loop Gain and Phase Margin vs. Frequency
Figure 15. AD8051/AD8052 Open-Loop Gain and Phase vs. Frequency
Rev. H | Page 11 of 24
AD8051/AD8052/AD8054
–20
1000
100
V
= 2V p-p
V = 3V, G = –1
S
V
= 5V
OUT
S
R
= 2kΩ, R = 100Ω
L
F
–30
–40
V
R
= 5V, G = +2
S
= 2kΩ, R = 100Ω
F
L
V
R
= 5V, G = +1
S
–50
–60
= 100Ω
L
–70
V
R
= 5V, G = +1
= 2kΩ
S
–80
10
L
V
R
= 5V, G = +2
= 2kΩ, R = 2kΩ
L
S
–90
F
–100
–110
1
10
100
1k
10k
100k
1M
10M
1
2
3
4
5
6
7
8
9 10
FUNDAMENTAL FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 22. Input Voltage Noise vs. Frequency
Figure 19. Total Harmonic Distortion
100
10
–30
–40
V
= 5V
S
10MHz
–50
–60
–70
–80
5MHz
1MHz
–90
–100
–110
–120
–130
–140
1
V
= 5V
S
R
= 2kΩ
L
G = +2
0.1
10
100
1k
10k
100k
1M
10M
0
0.5 1.0
1.5 2.0
2.5 3.0 3.5
OUTPUT VOLTAGE (V p-p)
4.0
4.5
5.0
FREQUENCY (Hz)
Figure 23. Input Current Noise vs. Frequency
Figure 20. Worst Harmonic vs. Output Voltage
0.10
0.05
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
NTSC SUBSCRIBER (3.58MHz)
R
= 150Ω
= 1kΩ
NTSC SUBSCRIBER (3.58MHz)
L
R
= 1kΩ
L
0.00
–0.05
R
V = 5V, G = +2
S
L
V
= 5V, G = +2
S
R
= 2kΩ, R AS SHOWN
R
= 150Ω
R
= 2kΩ, R AS SHOWN
F
L
L
F
L
–0.10
ST
ND
RD
TH
TH
TH
TH
TH
TH TH
10
TH
11
1
2
3
4
5
6
7
8
9
0
10
20
30
40
50
60
70
80
90 100
0.3
0.2
0.1
0.10
0.05
R
= 1kΩ
L
0.00
R
= 1kΩ
L
–0.05
–0.10
–0.15
–0.20
–0.25
0.0
–0.1
–0.2
R
= 150Ω
L
R
= 150Ω
L
V = 5V, G = +2
S
V
R
= 5V, G = +2
S
R
= 2kΩ, R AS SHOWN
L
= 2kΩ, R AS SHOWN
F
F
L
–0.3
ST
ND
RD
TH
TH
TH
6
TH
TH
TH
TH
TH
11
1
2
3
4
5
7
8
9
10
0
10
20
30
40
50
60
70
80
90 100
MODULATING RAMP LEVEL (IRE)
MODULATING RAMP LEVEL (IRE)
Figure 24. AD8054 Differential Gain and Phase Errors
Figure 21. AD8051/AD8052 Differential Gain and Phase Errors
Rev. H | Page 12 of 24
AD8051/AD8052/AD8054
–10
–20
–10
–20
V
= ±5V
= 1kΩ
S
V
R
R
= 5V
= 2kΩ
= 2kΩ
S
R
R
V
F
L
F
L
= AS SHOWN
= 2V p-p
–30
–40
–30
–40
–50
–60
–70
–80
OUT
V
= 2V p-p
OUT
R
= 100Ω
L
–50
–60
–70
–80
–90
R
= 1kΩ
L
–90
–100
–110
–100
0.1
1
10
FREQUENCY (MHz)
100
500
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 25. AD8052 Crosstalk (Output-to-Output) vs. Frequency
Figure 28. AD8054 Crosstalk (Output-to-Output) vs. Frequency
0
20
V
= 5V
V
= 5V
S
S
–10
–20
–30
–40
–50
–60
10
0
–10
–PSRR
+PSRR
–20
–30
–40
–50
–70
–80
–60
–70
–90
–100
–80
0.01
0.1
1
10
100
500
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. PSRR vs. Frequency
Figure 26. CMRR vs. Frequency
100.000
31.000
10.000
3.100
70
V
=5V
V
= 5V
S
S
G = +1
G = –1
= 2kΩ
60
50
R
L
AD8051/AD8052
AD8054
40
1.000
0.310
0.100
30
20
10
0
0.031
0.010
0.1
1
10
100
500
0.5
1.0
1.5
2.0
FREQUENCY (MHz)
INPUT STEP (V p-p)
Figure 27. Closed-Loop Output Resistance vs. Frequency
Figure 30. Settling Time vs. Input Step
Rev. H | Page 13 of 24
AD8051/AD8052/AD8054
1.0
1.000
V
= 5V
V
= 5V
V
= +85°C
S
S
OH
0.9
0.8
+5V – V
(+125°C)
OH
0.875
0.750
0.625
0.500
V
= +25°C
OH
+5V – V
(+25°C)
0.7
0.6
0.5
0.4
OH
V
= –40°C
OH
V
= +85°C
OL
+5V – V
(–40°C)
OH
0.375
0.250
0.125
0
0.3
0.2
V
= +25°C
OL
V
(+125°C)
27
OL
V
= –40°C
OL
V
(+25°C)
0.1
0
OL
V
(–40°C)
15
OL
0
3
6
9
12
18
21
24
30
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 31. AD8051/AD8052 Output Saturation Voltage vs. Load Current
Figure 33. AD8054 Output Saturation Voltage vs. Load Current
100
R
= 2kΩ
L
90
R
= 150Ω
L
80
70
V
= 5V
S
60
0
0.5
1.0 1.5
2.0 2.5 3.0 3.5 4.0
4.5 5.0
OUTPUT VOLTAGE (V)
Figure 32. Open-Loop Gain vs. Output Voltage
Rev. H | Page 14 of 24
AD8051/AD8052/AD8054
V
= 5V
V
= 0.1V p-p
S
IN
G = –1
G = +1
R
= 2kΩ
R
= 2kΩ
F
L
L
5.0
2.5
R
= 2kΩ
V
= 3V
S
1.5
20ns
2µs
20mV
1V
Figure 34. 100 mV Step Response, G = +1
Figure 37. Output Swing; G = −1, RL = 2 kΩ
V
= 5V
V
= 5V
S
S
G = +1
= 2kΩ
G = +1
= 2kΩ
R
R
L
L
2.55
2.50
2.45
2.6
2.5
2.4
20ns
50mV
40ns
50mV
Figure 35. AD8051/AD8052 200 mV Step Response; VS = 5 V, G = +1
Figure 38. AD8054 100 mV Step Response; VS = 5 V, G = +1
V
= ±5V
V
= 1V p-p
S
IN
4.5
3.5
2.5
1.5
0.5
4
3
2
1
G = +1
= 2kΩ
G = +2
R
R
= 2kΩ
= 5V
L
L
S
V
–1
–2
–3
–4
1V
20ns
20ns
500mV
Figure 36. Large Signal Step Response; VS = 5 V, G = +2
Figure 39. Large Signal Step Response; VS = 5 V, G = +1
Rev. H | Page 15 of 24
AD8051/AD8052/AD8054
THEORY OF OPERATION
The inputs of the device can handle voltages from −0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values do not cause phase reversal; however, the input
ESD devices begin to conduct if the input voltages exceed the
rails by greater than 0.5 V. During this overdrive condition, the
output stays at the rail.
CIRCUIT DESCRIPTION
The AD8051/AD8052/AD8054 are fabricated on the Analog
Devices, Inc. proprietary eXtra-Fast Complementary Bipolar
(XFCB) process, which enables the construction of PNP and
NPN transistors with similar fTs in the 2 GHz to 4 GHz region.
The process is dielectrically isolated to eliminate the parasitic
and latch-up problems caused by junction isolation. These
features allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a differential
output input stage to maximize bandwidth and headroom (see
Figure 40). The smaller signal swings required on the first stage
outputs (nodes SIP, SIN) reduce the effect of nonlinear currents
due to junction capacitances and improve the distortion per-
formance. This design achieves harmonic distortion of −80 dBc
@ 1 MHz into 100 Ω with VOUT = 2 V p-p (gain = +1) on a
single 5 V supply.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to
drive 45 mA of output current and allows the AD8054 to drive
30 mA of output current with the outputs within 0.5 V of the
supply rails.
V
CC
I9
Q25
Q50
Q39
R26
Q4
R39
Q5
I10
I2
I3
Q36
I5
Q51
Q23
V
Q40
EE
R2
R15
Q13
Q22
R27
R23
Q21
V
EE
C3
C9
Q31
Q7
V
P
Q1
IN
V
OUT
Q27
V
N
IN
SIN
SIP
Q8
Q2
Q11
R3
Q3
Q24
I7
Q47
I8
CC
I11
V
C7
R21
R5
V
EE
Figure 40. AD8051/AD8052 Simplified Schematic
Rev. H | Page 16 of 24
AD8051/AD8052/AD8054
APPLICATION INFORMATION
OVERDRIVE RECOVERY
V
= 5V
S
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 41, the AD8051/AD8052/
AD8054 recover within 60 ns from negative overdrive and
within 45 ns from positive overdrive.
G = +1
R
= 2kΩ
L
L
C
= 50pF
2.60
2.55
2.50
2.45
V
= ±5V
S
2.40
G = +5
INPUT 1V/DIV
OUTPUT 2V/DIV
R
R
= 2kΩ
= 2kΩ
F
L
100ns
50mV
Figure 43. AD8051/AD8052 200 mV Step Response; CL = 50 pF
10000
1000
100
10
V
= 5V
S
≤ 30%
OVERSHOOT
R
= 3Ω
S
100ns
V/DIV AS SHOWN
R
= 0Ω
S
Figure 41. Overdrive Recovery
DRIVING CAPACITIVE LOADS
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figure 42
and Figure 43 show their frequency and time domain responses,
respectively, to a small-signal excitation. The capacitive load
drive of the AD8051/AD8052/AD8054 can be increased by
adding a low value resistor in series with the load. Figure 44
and Figure 45 show the effect of a series resistor on the capaci-
tive drive for varying voltage gains. As the closed-loop gain is
increased, the larger phase margin allows for larger capacitive
loads with less peaking. Adding a series resistor with lower
closed-loop gains accomplishes the same effect. For large
capacitive loads, the frequency response of the amplifier is
dominated by the roll-off of the series resistor and the load
capacitance.
R
R
F
G
R
S
V
IN
V
OUT
100mV
STEP
C
L
50Ω
1
1
2
3
4
5
6
A
(V/V)
CL
Figure 44. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain
1000
V
= 5V
S
≤ 30%
OVERSHOOT
R
= 10Ω
S
8
R = 0Ω
S
6
4
100
R
R
F
G
2
R
S
V
IN
V
0
OUT
100mV
STEP
C
L
50Ω
–2
–4
10
V
= 5V
1
2
3
4
5
6
S
–6
–8
G = +1
A
(V/V)
CL
R
C
= 2kΩ
= 50pF
L
L
Figure 45. AD8054 Capacitive Load Drive vs. Closed-Loop Gain
V
= 200mV p-p
OUT
–10
–12
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 42. AD8051/AD8052 Closed-Loop Frequency Response; CL = 50 pF
Rev. H | Page 17 of 24
AD8051/AD8052/AD8054
noise bandwidth of the analog signal before analog-to-digital
conversion.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and component
selection. Proper RF design techniques and low parasitic
component selection are necessary.
Note that the unused amplifier’s inputs should be tied to ground.
R6
1kΩ
C1
50pF
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from the
area near the input pins to reduce parasitic capacitance.
R2
2kΩ
13
12
R4
2kΩ
C2
50pF
14
R1
3kΩ
R3
2
3
V
IN
R5
2kΩ
2kΩ
1
6
5
7
9
8
Chip capacitors should be used for supply bypassing. One end
should be connected to the ground plane and the other within
3 mm of each power pin. An additional large (4.7 μF to 10 μF)
tantalum electrolytic capacitor should be connected in parallel,
but not necessarily so close, to supply current for fast, large
signal changes at the output.
AD8054
10
AD8054
AD8054
BAND-PASS
FILTER OUTPUT
Figure 46. 2 MHz Biquad Band-Pass Filter Using AD8054
The frequency response of the circuit is shown in Figure 47.
0
The feedback resistor should be located close to the inverting
input pin to keep the parasitic capacitance at this node to a
minimum. Parasitic capacitance of less than 1 pF at the inverting
input can significantly affect high speed performance.
–10
–20
–30
–40
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end.
ACTIVE FILTERS
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly affect active filter
performance.
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 47. Frequency Response of 2 MHz Band-Pass Biquad Filter
Figure 46 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
Rev. H | Page 18 of 24
AD8051/AD8052/AD8054
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
10
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
Figure 50 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
PART#
0
FUND
0
–10
–20
–30
–40
–50
–60
–70
–80
FFTSIZE 8192
FCLK 20.0MHz
998.5kHz
–0.51dB
–68.13
FUND
VIN
THD
SNR
54.97
SINAD 54.76
8.80
ENOB
SFDR 71.66
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the ADC.
2ND
3RD
4TH
5TH
6TH
7TH
–74.53
–76.06
–76.35
–79.05
–80.36
–75.08
–88.12
–77.87
2ND
7TH
3RD
4TH
9TH
8TH
5TH
6TH
–90
–100
8TH
9TH
–110
–120
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
10
0
PART#
FUND
0
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
FFTSIZE 8192
FCLK 20.0MHz
FUND 9.5MHz
–10
–20
–30
–40
–50
VIN
–0.44dB
–57.08
54.65
THD
SNR
SINAD 52.69
ENOB 8.46
2ND
3RD
60.18
SFDR
2ND
3RD
4TH
5TH
6TH
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
–60
–70
–80
–60.18
–60.23
–82.01
–78.83
–81.28
–77.28
–84.54
7TH
5TH
4TH
8TH
6TH
–90
–100
7TH
8TH
9TH
–110
–120
–92.78
Figure 48 shows the FFT response of the ADC for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
14
13
CLOCK
15
16
SLEEP
INA-I
0.33µF
22Ω
+V
SELECT
DD
+5V
10pF
1kΩ
22Ω
INB-I
17
0.01µF
22Ω
10pF
0.1µF
6
10µF
AD9201
DATA OUT
18 REFT-I
12
11
10
9
D9
D8
D7
D6
7
3
2
0.1µF
10µF
0.1µF
19
REFB-I
50Ω
AD8051
0.1µF
20 AVSS
1kΩ
4
21
22
REFSENSE
VREF
D5
D4
8
7
6
5
4
3
2
1
10µF
0.1µF
0.1µF
10µF
–5V
23
AVDD
+5V
D3
10µF
0.1µF
1kΩ
D2
24 REFB-Q
25 REFT-Q
0.1µF
10µF
0.1µF
D1
0.1µF
D0
22Ω
DVDD
DVSS
+5V
26 INB-Q
0.1µF
10µF
10pF
22Ω
INA-Q
27
28
10pF
CHIP–SELECT
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
Rev. H | Page 19 of 24
AD8051/AD8052/AD8054
dynamic swing requirements are a signal that is mostly low but
goes high with a duty cycle that is a small fraction of a percent,
and the other extreme defined by the opposite condition.
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as analog-to-
digital conversion, it is not desirable to have the sync pulses on
the video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video specifications.
The combination of horizontal and vertical blanking intervals
limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 51
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
As a result of the duty cycles between the two extremes
previously presented, a 1 V p-p composite video signal that is
multiplied by a gain of 2 requires about 3.2 V p-p of dynamic
voltage swing at the output for an op amp to pass a composite
video signal of arbitrarily varying duty cycle without distortion.
V
GROUND
0.4V
BLANK
GROUND
3V OR 5V
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts, such
as sync tip compression, unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single 5 V
supply to handle an ac-coupled composite video signal.
+
10µF
0.1µF
7
V
3
2
IN
TO A/D
6
AD8051
100Ω
4
R2
1kΩ
R1
1kΩ
The input to the circuit in Figure 52 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
0.8V
(OR 2 × V
)
BLANK
Figure 51. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kꢀ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync
pulses stripped at the proper level.
The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The blanking level of the input video pulse is the desired place to
remove the sync information. This level is multiplied by 2 by the
amplifier. This level must be at ground at the output for the sync
stripping action to take place. Since the gain of the amplifier from
the input of R1 to the output is −1, a voltage equal to 2 × VBLANK
must be applied to make the blanking level come out at ground.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of five with minimum visible degradation in the picture.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
5V
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
can arise from such techniques.
4.99kΩ
+
10µF
4.99kΩ
+
0.1µF
10µF
COMPOSITE
VIDEO
IN
47µF
+
7
R
BT
75Ω
3
1000µF
+
R
T
V
6
10kΩ
OUT
AD8051
75Ω
R
L
2
75Ω
4
0.1µF
R
1kΩ
F
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst
case, the dynamic signal swing will approach twice the peak-to-
peak value. The two conditions that define the maximum
R
1kΩ
G
220µF
Figure 52. Single-Supply Composite Video Line Driver
Rev. H | Page 20 of 24
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
2.90 BSC
5
1
4
3
2.80 BSC
1.60 BSC
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 54. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. H | Page 21 of 24
AD8051/AD8052/AD8054
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 55. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. H | Page 22 of 24
AD8051/AD8052/AD8054
ORDERING GUIDE
Model
AD8051AR
AD8051AR-REEL
AD8051AR-REEL7
AD8051ARZ1
AD8051ARZ-REEL1
AD8051ARZ-REEL71
AD8051ART-R2
AD8051ART-REEL
AD8051ART-REEL7
AD8051ARTZ-R21
AD8051ARTZ-REEL1
AD8051ARTZ-REEL71
AD8052AR
AD8052AR-REEL
AD8052AR-REEL7
AD8052ARZ1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
Branding
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 13" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
5-Lead SOT-23, 13" Tape and Reel
5-Lead SOT-23, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 7" Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 13" Tape and Reel
14-Lead SOIC_N, 7" Tape and Reel
14-Lead SOIC_N
14-Lead SOIC_N, 13" Tape and Reel
14-Lead SOIC_N, 7" Tape and Reel
14-Lead TSSOP
H2A
H2A
H2A
H06
H06
H06
R-8
R-8
R-8
R-8
R-8
R-8
AD8052ARZ-REEL1
AD8052ARZ-REEL71
AD8052ARM
RM-8
RM-8
RM-8
RM-8
RM-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
H4A
H4A
H4A
H4A#
H4A#
AD8052ARM-REEL
AD8052ARM-REEL7
AD8052ARMZ1
AD8052ARMZ-REEL71
AD8054AR
AD8054AR-REEL
AD8054AR-REEL7
AD8054ARZ1
AD8054ARZ-REEL1
AD8054ARZ-REEL71
AD8054ARU
AD8054ARU-REEL
AD8054ARU-REEL7
AD8054ARUZ1
AD8054ARUZ-REEL1
AD8054ARUZ-REEL71
14-Lead TSSOP, 13" Tape and Reel
14-Lead TSSOP, 7" Tape and Reel
14-Lead TSSOP
14-Lead TSSOP, 13" Tape and Reel
14-Lead TSSOP, 7" Tape and Reel
1 Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked.
Rev. H | Page 23 of 24
AD8051/AD8052/AD8054
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01062-0-12/07(H)
Rev. H | Page 24 of 24
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