AD8062ARMZ-REEL7 [ADI]
IC DUAL OP-AMP, 6000 uV OFFSET-MAX, PDSO8, MO-187AA, MSOP-8, Operational Amplifier;
| 型号： | AD8062ARMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC DUAL OP-AMP, 6000 uV OFFSET-MAX, PDSO8, MO-187AA, MSOP-8, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, 300 MHz
Rail-to-Rail Amplifiers
AD8061/AD8062/AD8063
Data Sheet
FEATURES
CONNECTION DIAGRAMS
Low cost
AD8062
V
+V
V
1
2
3
4
8
7
6
5
OUT1
IN1
+IN1
S
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Low offset voltage: 6 mV
High speed
AD8061/
AD8063
DISABLE
1
2
3
4
8
7
6
5
NC
–IN
+IN
–
(AD8063 ONLY)
OUT2
IN2
+V
S
–
V
OUT
–V
S
NC
+IN2
–V
S
(Not to Scale)
(Not to Scale)
300 MHz, −3 dB bandwidth (G = 1)
650 V/µs slew rate
NC = NO CONNECT
Figure 1. 8-Lead SOIC (R)
Figure 2. 8-Lead SOIC (R)/MSOP (RM)
8.5 nV/√Hz at 5 V
AD8063
AD8061
35 ns settling time to 0.1% with 1 V step
Operates on 2.7 V to 8 V supplies
Input voltage range = −0.2 V to +3.2 V with VS = 5 V
Excellent video specifications (RL = 150 Ω, G = 2)
Gain flatness: 0.1 dB to 30 MHz
0.01% differential gain error
0.04° differential phase error
35 ns overload recovery
V
+V
S
1
2
3
6
5
4
OUT
V
5
+V
S
1
2
3
OUT
–
V
DISABLE
IN
S
–
V
S
–
+IN
4
–IN
+IN
(Not to Scale)
(Not to Scale)
Figure 3. 6-Lead SOT-23 (RJ)
Figure 4. 5-Lead SOT-23 (RJ)
3
0
Low power
6.8 mA/amplifier typical supply current
AD8063 400 µA when disabled
R
= 50Ω
F
V
= 0.2V p-p
O
R
= 1kΩ
R
= 0Ω
L
F
V
= 1V
BIAS
–3
–6
APPLICATIONS
R
F
Imaging
Photodiode preamps
Professional video and cameras
Handsets
OUT
IN
R
L
50Ω
–9
DVDs/CDs
V
BIAS
Base stations
Filters
–12
1
10
100
1k
ADC drivers
FREQUENCY (MHz)
Clock buffers
Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω
GENERAL DESCRIPTION
The AD8061/AD8062/AD8063 are rail-to-rail output voltage
feedback amplifiers offering ease of use and low cost. They have
a bandwidth and slew rate typically found in current feedback
amplifiers. All have a wide input common-mode voltage range
and output voltage swing, making them easy to use on single
supplies as low as 2.7 V.
150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi-
tionally, they offer wide bandwidth to 300 MHz along with
650 V/µs slew rate.
The AD8061/AD8062/AD8063 offer a typical low power of
6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 µA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
Despite being low cost, the AD8061/AD8062/AD8063 provide
excellent overall performance. For video applications, their
differential gain and phase errors are 0.01% and 0.04° into a
Rev. J
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8061/AD8062/AD8063
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Headroom Considerations........................................................ 14
Overload Behavior and Recovery ............................................ 15
Capacitive Load Drive ............................................................... 16
Disable Operation ...................................................................... 16
Board Layout Considerations ................................................... 16
Applications Information .............................................................. 17
Single-Supply Sync Stripper...................................................... 17
RGB Amplifier............................................................................ 17
Multiplexer.................................................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description......................................................................... 14
REVISION HISTORY
5/13—Rev. I to Rev. J
Added Output Voltage Swing Parameters; Table 1 ...................... 3
Added Output Voltage Swing Parameters; Table 2 ...................... 4
Added Output Voltage Swing Parameters; Table 3 ...................... 5
Changes to Ordering Guide .......................................................... 20
5/13—Rev. H to Rev. I
Changes to Figure 15........................................................................ 8
Changes to Ordering Guide .......................................................... 20
1/13—Rev. G to Rev. H
Changes to Figure 12........................................................................ 7
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/10—Rev. F to Rev. G
Changes to Table 4............................................................................ 6
11/09—Rev. E to Rev. F
Changed Input Common-Mode Voltage Range Parameter........ 4
Updated Outline Dimensions....................................................... 19
10/07—Rev. D to Rev. E
Changes to Applications .................................................................. 1
Updated Outline Dimensions....................................................... 19
12/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Change to Features and General Description............................... 1
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
5/01—Rev. B to Rev. C
Replaced TPC 9 with new graph .................................................... 7
11/00—Rev. A to Rev. B
2/00—Rev. 0 to Rev. A
11/99—Revision 0: Initial Version
Rev. J | Page 2 of 20
Data Sheet
AD8061/AD8062/AD8063
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 1.
Parameter
Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
320
115
280
30
650
500
35
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step
500
300
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2, AD8062
f = 100 kHz
f = 100 kHz
G = 2, RL = 150 Ω
G = 2, RL = 150 Ω
f = 10 MHz
f = 5 MHz
−77
−50
−90
8.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dBc
dB
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Third-Order Intercept
SFDR
1.2
0.01
0.04
28
62
DC PERFORMANCE
Input Offset Voltage
1
2
3.5
3.5
4
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
9
9
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
0.3
70
90
4.5 µA
VO = 0.5 V to 4.5 V, RL = 150 Ω
VO = 0.5 V to 4.5 V, RL = 2 kΩ
68
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
13
1
MΩ
pF
V
−0.2 to +3.2
80
VCM = –0.2 V to +3.2 V
62
dB
RL = 150 Ω
0.3
0.1
V
RL = 2 kΩ
RL = 150 Ω
RL = 2 kΩ
0.25 0.1
4.75 4.86
4.85 4.9
V
V
V
Output Voltage Swing High
Output Current
Capacitive Load Drive, VOUT = 0.8 V
VO = 0.5 V to 4.5 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
25
50
25
300
mA
pF
pF
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
40
ns
ns
V
300
2.8
3.2
DISABLE Voltage (Off)
DISABLE Voltage (On)
V
POWER SUPPLY
Operating Range
2.7
72
5
8
9.5
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
mA
mA
dB
∆VS = 2.7 V to 5 V
Rev. J | Page 3 of 20
AD8061/AD8062/AD8063
Data Sheet
TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
300
115
250
30
280
230
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
–3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 1 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
190
180
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
−60
−44
−90
8.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
1.2
DC PERFORMANCE
Input Offset Voltage
1
2
3.5
3.5
4
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
8.5
8.5
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
0.3
70
90
4.5 µA
VO = 0.5 V to 2.5 V, RL = 150 Ω
VO = 0.5 V to 2.5 V, RL = 2 kΩ
66
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
13
1
MΩ
pF
V
−0.2 to +1.2
80
VCM = –0.2 V to +1.2 V
dB
RL = 150 Ω
RL = 2 kΩ
0.3
0.3
0.1
0.1
V
V
Output Voltage Swing High
RL = 150 Ω
2.85 2.87
V
RL = 2 kΩ
2.9
2.9
25
25
V
Output Current
Capacitive Load Drive, VOUT = 0.8 V
VO = 0.5 V to 2.5 V
30% overshoot, G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
mA
pF
pF
300
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
40
ns
ns
V
300
0.8
1.2
DISABLE Voltage—Off
DISABLE Voltage—On
V
POWER SUPPLY
Operating Range
2.7
72
3
9
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
mA
mA
dB
Rev. J | Page 4 of 20
Data Sheet
AD8061/AD8062/AD8063
TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 3.
Parameter
Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p, VO dc = 1 V
G = 1, VO = 0.7 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
150
60
300
115
230
30
150
130
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
110
95
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
–60
–44
–90
8.5
dBc
dBc
dBc
Crosstalk, Output to Output
Input Voltage Noise
f = 100 kHz
nV/√Hz
Input Current Noise
f = 100 kHz
1.2
pA/√Hz
DC PERFORMANCE
Input Offset Voltage
1
2
3.5
3.5
4
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
8.5
µA
Input Offset Current
Open-Loop Gain
0.3
70
90
4.5 µA
VO = 0.5 V to 2.2 V, RL = 150 Ω
VO = 0.5 V to 2.2 V, RL = 2 kΩ
63
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
13
1
MΩ
pF
V
–0.2 to +0.9
0.8
VCM = –0.2 V to +0.9 V
dB
RL = 150 Ω
0.3
0.1
V
RL = 2 kΩ
0.25 0.1
V
Output Voltage Swing High
RL = 150 Ω
2.55 2.55
V
RL = 2 kΩ
2.6
2.6
25
25
V
Output Current
Capacitive Load Drive, VOUT = 0.8 V
VO = 0.5 V to 2.2 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
mA
pF
pF
300
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
40
300
0.5
ns
ns
V
DISABLE
DISABLE
Voltage (Off)
Voltage (On)
0.9
V
POWER SUPPLY
Operating Range
2.7
8
V
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6.8
0.4
80
8.5
mA
mA
dB
Rev. J | Page 5 of 20
AD8061/AD8062/AD8063
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8061/AD8062/AD8063 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure. While the
AD8061/AD8062/AD8063 is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature (150°C) is not exceeded under all
conditions.
Parameter
Rating
Supply Voltage
Internal Power Dissipation1
8-lead SOIC (R)
5-lead SOT-23 (RJ)
6-lead SOT-23 (RJ)
8 V
0.8 W
0.5 W
0.5 W
0.6 W
8-lead MSOP (RM)
Input Voltage (Common-Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
R-8, RM-8, SOT-23-5, SOT-23-6
(−VS − 0.2 V) to (+VS + 0.2 V)
VS
Observe power derating curves
−65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering,
10 sec)
300°C
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
1 Specification is for device in free air.
8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W.
5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.
T
= 150°C
8-LEAD SOIC
PACKAGE
J
1.5
1.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0.5
0
MSOP
SOT-23-5, SOT-23-6
–50 –40 –30
90
–20 –10
0
10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE (°C)
Figure 6. Maximum Power Dissipation vs. Temperature for
AD8061/AD8062/AD8063
ESD CAUTION
Rev. J | Page 6 of 20
Data Sheet
AD8061/AD8062/AD8063
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
3
G = +1
1.0
+V
@ +85°C
OUT
0
–3
–6
+V
@ +25°C
OUT
0.8
0.6
0.4
0.2
0
G = +2
G = +5
+V
@ –40°C
OUT
–V
@ –40°C
OUT
V
R
= 0.2V p-p
= 1kΩ
= 1V
O
–9
–V
OUT
@ +85°C
80
L
V
BIAS
–V
@ +25°C
60
OUT
–12
10
20
30
40
50
70
90
1
0
10
100
1k
LOAD CURRENT (mA)
FREQUENCY (MHz)
Figure 7. Output Saturation Voltage vs. Load Current
Figure 10. Small Signal Frequency Response
18
16
14
12
10
8
3
V
R
= 1.0V p-p
= 1kΩ
= 1V
O
AD8062
L
G = +1
V
BIAS
0
–3
–6
G = +2
AD8061
G = +5
6
4
–9
2
0
–12
2
3
4
5
6
7
8
1
10
100
1k
SINGLE POWER SUPPLY (V)
FREQUENCY (MHz)
Figure 8. ISUPPLY vs. VSUPPLY
Figure 11. Large Signal Frequency Response
3
3
R
= 50Ω
V
V
= 5V
= 0.2V p-p
F
S
O
R
= 1kΩ
= 1V
L
0
–3
–6
0
–3
–6
V
BIAS
V
R
= 0.2V p-p
= 1kΩ
= 1V
O
R
= 0Ω
L
F
G = –1
G = –2
V
BIAS
G = –5
R
F
OUT
IN
R
L
50Ω
–9
–9
V
BIAS
–12
–12
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω
Figure 12. Small Signal Frequency Response
Rev. J | Page 7 of 20
AD8061/AD8062/AD8063
Data Sheet
0
3
V
V
R
= 5V
= 1V p-p
= 1kΩ
V
= 5V
S
S
–10
R
= 1kΩ
O
L
G = +1
L
–20
–30
0
V
= 1V
BIAS
G = –1
2ND @ 1MHz
–3
–40
–50
3RD @ 10MHz
G = –2
–60
–70
–6
G = –5
–80
–90
–9
3RD @ 1MHz
2.5
INPUT SIGNAL DC BIAS (V)
2ND @ 10MHz
–100
–12
0.5
1.0
3.5
1.5 2.0
3.0
1
10
100
1k
FREQUENCY (MHz)
Figure 13. Large Signal Frequency Response
Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
0.1
0
–40
604Ω
V
R
= 0.2V p-p
= 1kΩ
= 1V
V
= 2.7V
O
S
10µF
5V
+
L
V
–50
BIAS
0.1µF
G = +1
1kΩ
50Ω
1MΩ INPUT
–60
–70
52.3Ω
–0.1
–0.2
0.1µF
1.25V
+
–
V
= 5V
1kΩ
S
dc
(R
)
LOAD
V
= 3V
S
–80
2ND H
–0.3
–0.4
–90
–100
–110
3RD H
–0.5
1
10
100
1k
1
50
0.01
0.1
10
FREQUENCY (MHz)
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
Figure 14. 0.1 dB Flatness
Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias
–30
80
60
200
150
100
50
V
R
= 5V
= 1kΩ
S
L
–40
–50
G = +5
= 1V p-p
V
O
PHASE
2ND
3RD
10MHz
–60
40
GAIN
0
–70
20
–50
–100
–150
–200
–250
–300
–80
2ND
–90
0
3RD
2ND
5MHz
–100
–110
–120
1MHz
– 20
3RD
– 40
0
1
5
2
3
4
0.01
0.1
1
10
100
1k
OUTPUT SIGNAL DC BIAS (V)
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Output Signal DC Bias
Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency,
VS = 5 V, RL = 1 kΩ
Rev. J | Page 8 of 20
Data Sheet
AD8061/AD8062/AD8063
–40
V
= 5V
S
R
= R = 1kΩ
L
F
–50
2ND @ 10MHz
G = +2
0.01
0
–60
–70
–80
–90
5V
+
10µF
–0.01
–0.02
–0.04
–0.06
1MΩ
INPUT
TO
0.1µF
50Ω
50Ω
1kΩ
2ND @ 2MHz
1kΩ
1kΩ
3589A
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
2ND @ 500kHz
3RD @ 2MHz
0.02
0
–100
–110
–0.02
–0.04
–0.06
3RD @ 500kHz
1.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
RTO OUTPUT (V p-p)
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
Figure 19. Harmonic Distortion vs. Output Signal Amplitude
Figure 22. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V
–30
V
= 5V
S
R = R = 1kΩ
I
L
0.010
0.005
0
–40
–50
–60
V
= 2V p-p
O
G = 2
S1 3RD HARMONIC/
DUAL ±2.5V SUPPLY
–0.005
–0.010
S1 2ND HARMONIC/
DUAL ±2.5V SUPPLY
–70
–80
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
0.04
0.03
0.02
0.01
0
–90
–100
–110
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
–0.01
–0.02
0.01
0.1
1
10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
Figure 23. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V
Figure 20. Harmonic Distortion vs. Frequency
1000
1.0
V
= 5V
S
FALLING EDGE
900
800
700
600
500
V
R
= 5V
= 1kΩ
R
= 1kΩ
S
0.9
0.8
L
G = +1
L
G = +1
0.7
0.6
RISING EDGE
0.5
0.4
0.3
0.2
0.1
400
300
200
100
0
0
1.5
OUTPUT STEP AMPLITUDE (V)
3.0
1.0
2.0
2.5
0
0.1
0.2
TIME (µs)
0.3
0.4
0.5
Figure 24. Slew Rate vs. Output Step Amplitude
Figure 21. 400 mV Pulse Response
Rev. J | Page 9 of 20
AD8061/AD8062/AD8063
Data Sheet
1400
V
= ±2.5V
S
G = +1
= 1k
FALLING EDGE
V
R
Ω
IN
L
1200
1000
800
V
= ±4V
S
2.5V
FALLING EDGE
= +5V
V
S
V
OUT
600
400
200
0
RISING EDGE
V
= ±4V
S
0V
RISING EDGE
V
= +5V
S
500mV/DIV
0
20
40
60
80 100
120 140 160
180 200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TIME (ns)
OUTPUT STEP (V)
Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V
Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V
1k
V
= ±2.5V
S
G = +5
= 1k
V
R
= 5V
= 1kΩ
S
R
L
Ω
L
V
OUT
2.5V
1.0V
100
10
1
V
IN
0V
500mV/DIV
0
20
40
60
80 100
120 140 160
180 200
10
100
1k
10k
100k
1M
10M
TIME (ns)
FREQUENCY (Hz)
Figure 26. Voltage Noise vs. Frequency
Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V
100
10
1
0
V
= 0.2V p-p
CM
= 100
V
R
= 5V
= 1kΩ
–10
–20
–30
S
R
V
Ω
L
L
=
±2.5V
SIDE 2
S
SIDE 1
–40
–50
–60
–70
–80
–90
–100
604
Ω
604
Ω
50
Ω
V
154
Ω
IN
200mV p-p
154
Ω
57.6
Ω
0
10
10M
100
1k
10k
100k
1M
0.01
0.1
1
10
100
500
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 27. Current Noise vs. Frequency
Figure 30. CMRR vs. Frequency
Rev. J | Page 10 of 20
Data Sheet
AD8061/AD8062/AD8063
7
6
5
4
3
2
1
0
0
ΔV = 0.2V p-p
S
V
= 5V
S
R
V
= 1kΩ
= 5V
–10
–20
–30
–40
L
S
–PSRR
+PSRR
–50
–60
–70
–80
–90
–100
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.01
0.1
1
10
100
500
5.0
DISABLE VOLTAGE
FREQUENCY (MHz)
Figure 31. PSRR vs. Frequency Delta
DISABLE
Figure 34. AD8063
Voltage vs. Supply Current
6
–20
–30
V
= 5V
S
1kΩ
50Ω
1kΩ
G = +2
f = 10MHz
IN
V
5
4
+2.5V
DISABLE
@ 1.3V
–40
BIAS
= 100Ω
R
L
OUT
1kΩ
–50
IN
–60
–2.5V
3
–70
INPUT = SIDE 2
INPUT = SIDE 1
2
–80
–90
V
V
R
= 5V
1
S
= 400mV rms
= 1kΩ
IN
–100
–110
–120
L
0
G = +2
V
OUT
–1
0.1
1
10
100
500
0.01
0
0.4
0.8
1.2
1.6
2.0
FREQUENCY (MHz)
TIME (µs)
Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V
DISABLE
Figure 35. AD8063
Function, Voltage = 0 V to 5 V
0
1k
V
V
R
= 5V
= 0.2V p-p
= 1kΩ
S
V
V
R
= 5V
S
O
–10
–20
–30
–40
–50
–60
–70
–80
–90
= 0.2V p-p
= 1kΩ
= 1V
O
L
L
V
= 1V
BIAS
100
10
V
BIAS
1
0.1
0.01
1
10
100
1k
0.1
1
10
FREQUENCY (MHz)
100
1k
FREQUENCY (MHz)
Figure 33. AD8063 Disabled Output Isolation Frequency Response
Figure 36. Output Impedance vs. Frequency,
OUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V
V
Rev. J | Page 11 of 20
AD8061/AD8062/AD8063
Data Sheet
V
R
= 5V
= 1kΩ
V
= 5V
S
S
G = +2
L
R
= 1kΩ
L
V
= 1V p-p
IN
3.5V
2.5V
1.5V
+0.1%
–0.1%
1kΩ
1kΩ
R
= 1kΩ
L
50Ω
500mV/DIV
10 20
t = 0
0
30
40
50
60
70
80
90
100
20ns/DIV
TIME (ns)
Figure 37. Output Settling Time to 0.1%
Figure 40. 1 V Step Response
50
45
40
35
30
25
20
15
10
5
V
= 5V
S
FALLING EDGE
G = +2
R
V
= 1kΩ
L
2.6V
= 100mV
IN
RISING EDGE
2.5V
2.4V
V
R
= 5V
= 1kΩ
S
L
G = +1
20mV/DIV
0
0.5
1.0
1.5
OUTPUT VOLTAGE STEP
2.0
2.5
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
Figure 38. Settling Time vs. VOUT
Figure 41. 100 mV Step Response
V
= 5V
S
V
= 5V
S
G = –1
R
R
G = +2
R
V
= 1kΩ
= 1kΩ
F
L
= R = 1kΩ
F
L
= 4V p-p
IN
4.86V
2.43V
0V
0V
1V
2µs
2µs/DIV
1V/DIV
Figure 39. Output Swing
Figure 42. Output Rail-to-Rail Swing
Rev. J | Page 12 of 20
Data Sheet
AD8061/AD8062/AD8063
V
= 5V
S
V
= 5V
S
G = +2
R
V
G = +1
R
= R = 1kΩ
L
F
= 1kΩ
L
= 2V p-p
IN
2.6V
2.5V
2.4V
4.5V
2.5V
0.5V
50mV/DIV
10
1V/DIV
5
0
5
15
20
25
30
35
40
45
50
0
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
Figure 43. 200 mV Step Response
Figure 44. 2 V Step Response
Rev. J | Page 13 of 20
AD8061/AD8062/AD8063
Data Sheet
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family is comprised of high
speed voltage feedback op amps. The high slew rate input stage
is a true, single-supply topology, capable of sensing signals at or
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads
and within 0.3 V when driving 150 Ω. High speed perform-
ance is maintained at supply voltages as low as 2.7 V.
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
–2.8
–3.2
–3.6
–4.0
HEADROOM CONSIDERATIONS
These amplifiers are designed for use in low voltage systems.
To obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
–0.5
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
4.0
CM
The AD8061/AD8062/AD8063 input common-mode voltage
range extends from the negative supply voltage (actually 200 mV
below this), or ground for single-supply operation, to within
1.8 V of the positive supply voltage. Thus, at a gain of 2, the
AD8061/AD8062/AD8063 can provide full rail-to-rail output
swing for supply voltage as low as 3.6 V, assuming the input
signal swings from −VS (or ground) to +VS/2. At a gain of 3,
the AD8061/AD8062/AD8063 can provide a rail-to-rail output
range down to 2.7 V total supply voltage.
Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V
2
0
V
V
V
V
V
= 3.0
CM
CM
CM
CM
CM
= 3.1
= 3.2
= 3.3
= 3.4
–2
–4
–6
–8
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
The input stage is the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 45 shows a typical offset voltage vs. input
common-mode voltage for the AD8061/AD8062/AD8063
amplifier on a 5 V supply. Accurate dc performance is main-
tained from approximately 200 mV below the minus supply
to within 1.8 V of the positive supply. For high speed signals,
however, there are other considerations. Figure 46 shows −3 dB
bandwidth vs. dc input voltage for a unity-gain follower. As
the common-mode voltage approaches the positive supply,
the amplifier holds together well, but the bandwidth begins to
drop at 1.9 V within +VS.
0.1
1
10
100
1k
10k
FREQUENCY (MHz)
Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
Higher frequency signals require more headroom than lower
frequencies to maintain distortion performance. Figure 47
illustrates how the rising edge settling time for the amplifier
configured as a unity-gain follower stretches out as the top of
a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit is
the output stage. The AD8061/AD8062/AD8063 amplifiers use
a common emitter style output stage. This output stage
maximizes the available output range, limited by the saturation
voltage of the output transistors. The saturation voltage
increases with the drive current the output transistor is required
to supply, due to the output transistors’ collector resistance. The
saturation voltage is estimated using the equation
This manifests itself in increased distortion or settling time.
Figure 16 plots the distortion of a 1 V p-p signal with the
AD8061/AD8062/AD8063 amplifier used as a follower on
a 5 V supply vs. signal common-mode voltage. Distortion
performance is maintained until the input signal center voltage
gets beyond 2.5 V, as the peak of the input sine wave begins to
run into the upper common-mode voltage limit.
V
SAT = 25 mV + IO × 8 Ω
where:
IO is the output current.
8 Ω is a typical value for the output transistors’ collector
resistance.
Rev. J | Page 14 of 20
Data Sheet
AD8061/AD8062/AD8063
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
VOLTAGE STEP
FROM 2.4V TO 3.4V
2V TO 3V STEP
2.1V TO 3.1V STEP
VOLTAGE STEP
FROM 2.4V TO 3.6V
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
2.4V TO 3.4V STEP
0
100
200
300
400
500
600
0
4
8
12
16
20
24
28
32
TIME (ns)
TIME (ns)
Figure 48. Pulse Response for G = 1 Follower,
Input Step Overloading the Input Stage
Figure 47. Output Rising Edge for 1 V Step at
Input Headroom Limits, G = 1, VS = 5 V, 0 V
Output
As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals. Figure 16, Figure 17, and Figure 18 illustrate this point,
plotting typical distortion vs. output amplitude and bias for
gains of 2 and 5.
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49
shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
5.0
4.6
OVERLOAD BEHAVIOR AND RECOVERY
Input
OUTPUT VOLTAGE
4.2
5V TO 2.5V
3.8
OUTPUT VOLTAGE
3.4
The specified input common-mode voltage of the AD8061/
AD8062/AD8063 is −200 mV below the negative supply to
within 1.8 V of the positive supply. Exceeding the top limit
results in lower bandwidth and increased settling time as seen
in Figure 46 and Figure 47. Pushing the input voltage of a unity-
gain follower beyond 1.6 V within the positive supply leads to
the behavior shown in Figure 48—an increasing amount of
output error and much increased settling time. Recovery time
from input voltages 1.6 V or closer to the positive supply is
approximately 35 ns, which is limited by the settling artifacts
caused by transistors in the input stage coming out of saturation.
0V TO 2.5V
3.0
2.6
2.2
1.8
1.4
1.0
INPUT VOLTAGE
EDGES
R
5V
R
V
–
IN
2.5V
V
O
–
0.6
0.2
–0.2
0
10
20
30
40
TIME (ns)
50
60
70
Figure 49. Overload Recovery, G = −1, VS = 5 V
The AD8061/AD8062/AD8063 family does not exhibit phase
reversal, even for input voltages beyond the voltage supply rails.
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.
Rev. J | Page 15 of 20
AD8061/AD8062/AD8063
Data Sheet
CAPACITIVE LOAD DRIVE
DISABLE OPERATION
The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:
The internal circuit for the AD8063 disable function is shown
DISABLE
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 µA, and the AD8063 output
in Figure 52. When the
node is pulled below 2 V
DISABLE
enters a high impedance state. If the
node is not
connected and allowed to float, the AD8063 stays biased at
full power.
Use a small resistor in series with the amplifier’s output and the
load capacitance.
VCC
Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
2V
TO AMPLIFIER
BIAS
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
DISABLE
VEE
R
Figure 52. Disable Circuit of the AD8063
SERIES
V
AD8061
O
C
DISABLE
LOAD
Figure 34 shows the AD8063 supply current vs.
voltage. Figure 35 plots the output seen when the AD8063 input
DISABLE
V
IN
Figure 50. Series Resistor Isolating Capacitive Load
is driven with a 10 MHz sine wave, and
is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop. Figure 51 plots the capacitance that
produces 30% overshoot vs. noise gain for a typical amplifier.
10k
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
R
= 4.7
S
1k
100
10
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
R
= 0
S
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
1
2
3
4
5
CLOSED-LOOP GAIN
Figure 51. Capacitive Load vs. Closed-Loop Gain
Rev. J | Page 16 of 20
Data Sheet
AD8061/AD8062/AD8063
APPLICATIONS INFORMATION
The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting RG to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the noninverting input
to the output is 2, which means the black level is amplified by 2
to the output. However, the gain through RG is −1 to the output.
It takes a dc level of twice the input black level to shift the black
level to ground at the output. When this occurs, the sync is
stripped, and the active video is passed as in the ground-
referenced case.
SINGLE-SUPPLY SYNC STRIPPER
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of analog-to-digital conversion,
the sync pulses consume some of the dynamic range, so
removing them increases the converter’s available dynamic
range for the video information.
Figure 53 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the negative
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.
RED
DAC
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
MONITOR
#1
GREEN
DAC
3V
BLUE
DAC
0.1µF
6
10µF
7
3
2
VIDEO IN
1kΩ
75Ω
VIDEO OUT
75Ω
AD8061
3V
75Ω
R
4
F
1kΩ
0.1µF
6
10µF
7
R
1kΩ
G
1kΩ
2
3
PIN NUMBERS ARE
FOR 8-LEAD PACKAGE
75Ω
RED
75Ω
AD8061
4
Figure 53. Single 3 V Sync Stripper Using AD8061
1kΩ
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Because the sync level is
below the black level, it does not show up at the output. However,
all of the active video portion of the waveform is amplified by a
gain of 2 and then normalized to unity gain by the back-
terminated transmission line. Figure 54 is an oscilloscope plot
of the input and output waveforms.
3V
8
MONITOR
#2
0.1µF
10µF
1
1kΩ
1kΩ
2
75Ω
75Ω
GREEN
AD8062
3
5
75Ω
BLUE
7
1
AD8062
75Ω
6
INPUT
4
1kΩ
Figure 55. RGB Cable Driver Using AD8061 and AD8062
2
RGB AMPLIFIER
Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.
OUTPUT
10µs
500mV
Figure 54. Input and Output Waveforms for a Single-Supply
Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at a positive voltage.
However, high speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 accept ground-level input signals and
output ground-level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.
Rev. J | Page 17 of 20
AD8061/AD8062/AD8063
Data Sheet
The select signal and the output waveforms for this circuit are
shown in Figure 57. For synchronization clarity, two different
frequency synthesizers, whose time bases are locked to each
other, generate the signals.
MULTIPLEXER
The AD8063 has a disable pin used to power down the ampli-
fier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gain-
step amplifier or a selectable frequency amplifier.
2µs
OUTPUT
Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.
+4V
SELECT
0.1µF
1
10µF
1V
2V
TIME
BASE
OUT
49.9Ω
AD8063
Figure 57. AD8063 Mux Output
1V p-p
3MHz
0.1µF
10µF
–4V
+4V
1kΩ
V
49.9Ω
OUT
1kΩ
49.9Ω
0.1µF
1
10µF
10µF
49.9Ω
AD8063
–4V
2V p-p
1MHz
TIME
BASE
IN
0.1µF
1kΩ
1kΩ
HCO4
SELECT
Figure 56. Two-to-One Multiplexer Using Two AD8063s
Rev. J | Page 18 of 20
Data Sheet
AD8061/AD8062/AD8063
OUTLINE DIMENSIONS
3.00
2.90
2.80
5
1
4
3
5.00 (0.1968)
4.80 (0.1890)
3.00
2.80
2.60
1.70
1.60
1.50
2
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.95 BSC
1.90
BSC
0.50 (0.0196)
45°
1.27 (0.0500)
BSC
1.30
1.15
0.90
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.55
0.45
0.35
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
(RJ-5)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
3.20
3.00
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
PIN 1
IDENTIFIER
1.30
1.15
0.90
0.65 BSC
0.95
0.85
0.75
0.20 MAX
0.08 MIN
15° MAX
1.45 MAX
0.95 MIN
1.10 MAX
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
0.80
0.55
0.40
0.15
0.05
SEATING
PLANE
0.23
0.09
0.60
BSC
6°
0°
0.50 MAX
0.30 MIN
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-178-AB
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 60. 6-Lead Small Outline Transistor Package [SOT-23]
Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(RJ-6)
Dimensions shown in millimeters
Dimensions shown in millimeters
Rev. J | Page 19 of 20
AD8061/AD8062/AD8063
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
Branding
AD8061AR
AD8061ARZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead SOIC_N
8-Lead SOIC_N
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
AD8061ARZ-REEL
AD8061ARZ-REEL7
AD8061ART-R2
AD8061ART-REEL7
AD8061ARTZ-R2
AD8061ARTZ-REEL
AD8061ARTZ-REEL7
AD8061AR-EBZ
AD8061ART-EBZ
AD8062AR
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
5-Lead SOT-23, 250 Piece Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
5-Lead SOT-23, 250 Piece Tape and Reel
5-Lead SOT-23, 13-Inch Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 5-Lead SOT-23
8-Lead SOIC_N
HGA
HGA
H0D2
H0D2
H0D2
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
–40°C to +85°C
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
AD8062ARZ
8-Lead SOIC_N
AD8062ARZ-RL
AD8062ARZ-R7
AD8062ARM
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
8-Lead MSOP
HCA
AD8062ARMZ
8-Lead MSOP
#HCA
#HCA
#HCA
AD8062ARMZ-RL
AD8062ARMZ-R7
AD8062AR-EBZ
AD8062ARM-EBZ
AD8063ARZ
AD8063ARZ-REEL
AD8063ARZ-REEL7
AD8063ART-R2
AD8063ART-REEL7
AD8063ARTZ-R2
AD8063ARTZ-REEL
AD8063ARTZ-REEL7
AD8063AR-EBZ
AD8063ART-EBZ
8-Lead MSOP, 13-Inch Tape and Reel
8-Lead MSOP, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 13-Inch Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 6-Lead SOT-23
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
RJ-6
RJ-6
HHA
HHA
H0E3
H0E3
H0E3
1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
2 New branding after data code 0542, previously branded HGA.
3 New branding after data code 0542, previously branded HHA.
©1999–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01065-0-5/13(J)
Rev. J | Page 20 of 20
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