AD8065AR-REEL7 [ADI]
High Performance, 145 MHz FastFET⑩ Op Amps; 高性能， 145 MHz的FastFET⑩运算放大器
| 型号： | AD8065AR-REEL7 |
| 厂家： | 
ADI |
| 描述： | High Performance, 145 MHz FastFET⑩ Op Amps |
| 文件： | 总28页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance, 145 MHz
FastFET™ Op Amps
AD8065/AD8066
FEATURES
APPLICATIONS
FET input amplifier
1 pA input bias current
Low cost
Instrumentation
Photodiode preamps
Filters
High speed: 145 MHz, −3 dB bandwidth (G = +1)
180 V/µs slew rate (G = +2)
Low noise
A/D drivers
Level shifting
Buffering
7 nV/√Hz (f = 10 kHz)
0.6 fA/√Hz (f = 10 kHz)
CONNECTION DIAGRAMS
AD8065
AD8065
V
+V
1
2
3
5
Wide supply voltage range: 5 V to 24 V
Single-supply and rail-to-rail output
Low offset voltage 1.5 mV max
High common-mode rejection ratio: −100 dB
Excellent distortion specifications
SFDR −88 dB @ 1 MHz
Low power: 6.4 mA/amplifier typical supply current
No phase reversal
Small packaging: SOIC-8, SOT-23-5, and MSOP
OUT
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
S
–V
S
+V
V
S
4
+IN
–IN
OUT
TOP VIEW
(Not to Scale)
–V
S
NC
TOP VIEW
(Not to Scale)
AD8066
1
2
3
4
8
7
6
5
+V
S
V
OUT1
V
–IN1
+IN1
OUT2
–IN2
+IN2
–V
S
TOP VIEW
(Not to Scale)
Figure 1.
GENERAL DESCRIPTION
The AD8065/AD80661 FastFET amplifiers are voltage feedback
amplifiers with FET inputs offering high performance and ease
of use. The AD8065 is a single amplifier, and the AD8066 is a
dual amplifier. These amplifiers are developed in the Analog
Devices, Inc. proprietary XFCB process and allow exceptionally
low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as
very high input impedance.
operate using only a 6.4 mA/amplifier typical supply current
and are capable of delivering up to 30 mA of load current.
The AD8065/AD8066 are high performance, high speed,
FET input amplifiers available in small packages: SOIC-8,
MSOP-8, and SOT-23-5. They are rated to work over the
industrial temperature range of −40°C to +85°C.
24
With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of
applications. For added versatility, the amplifiers also contain
rail-to-rail outputs.
21
18
15
12
9
G = +10
G = +5
V
= 200mV p-p
O
G = +2
G = +1
Despite the low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02%
and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/µs, excellent distortion
(SFDR of −88 dB @ 1 MHz), extremely high common-mode
rejection of −100 dB, and a low input offset voltage of 1.5 mV
maximum under warmed up conditions. The AD8065/AD8066
6
3
0
–3
–6
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 2. Small Signal Frequency Response
1Protected by U. S. Patent No. 6,262,633.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8065/AD8066
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
2/04—Data Sheet Changed from Rev. D to Rev. E.
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Maximum Power Dissipation ..................................................... 7
Output Short Circuit.................................................................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 15
Theory of Operation ...................................................................... 18
Closed-Loop Frequency Response........................................... 18
Noninverting Closed-Loop Frequency Response.................. 18
Inverting Closed-Loop Frequency Response ......................... 18
Wideband Operation ................................................................. 19
Input Protection.......................................................................... 19
Thermal Considerations............................................................ 20
Input and Output Overload Behavior...................................... 20
Layout, Grounding, and Bypassing Considerations................... 21
Power Supply Bypassing ............................................................ 21
Grounding ................................................................................... 21
Leakage Currents........................................................................ 22
Input Capacitance....................................................................... 22
Output Capacitance ................................................................... 22
Input-to-Output Coupling ........................................................ 23
Wideband Photodiode Preamp ................................................ 23
High Speed JFET Input Instrumentation Amplifier.............. 24
Video Buffer ................................................................................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide........................................................................... 26
Updated Format.................................................................Universal
Updated Figure 56......................................................................... 21
Updated Outline Dimensions...................................................... 25
Updated Ordering Guide.............................................................. 26
11/03—Data Sheet changed from Rev. C to Rev. D.
Changes to Features ........................................................................ 1
Changes to Connection Diagrams................................................ 1
Updated Ordering Guide................................................................ 5
Updated Outline Dimensions...................................................... 22
4/03—Data Sheet changed from Rev. B to Rev. C.
Added SOIC-8 (R) for the AD8065............................................... 4
2/03—Data Sheet changed from Rev. A to Rev. B.
Changes to Absolute Maximum Ratings...................................... 4
Changes to Test Circuit 10 ........................................................... 14
Changes to Test Circuit 11 ........................................................... 15
Changes to Noninverting Closed-Loop Frequency Response 16
Changes to Inverting Closed-Loop Frequency Response ....... 16
Updated Figure 6 .......................................................................... 18
Changes to Figure 7....................................................................... 19
Changes to Figures 10................................................................... 21
Changes to Figure 11..................................................................... 22
Changes to High Speed JFET Instrumentation Amplifier....... 22
Changes to Video Buffer............................................................... 22
8/02—Data Sheet changed from Rev. 0 to Rev. A.
Added AD8066 ..................................................................Universal
Added SOIC-8 (R) and MSOP-8 (RM) ........................................ 1
Edits to General Description ......................................................... 1
Edits to Specifications..................................................................... 2
New Figure 2 .................................................................................... 5
Changes to Ordering Guide........................................................... 5
Edits to TPCs 18, 25, and 28........................................................... 8
New TPC 36 ................................................................................... 11
Added Test Circuits 10 and 11..................................................... 14
MSOP (RM-8) added.................................................................... 23
Rev. E | Page 2 of 28
AD8065/AD8066
SPECIFICATIONS
@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −5.5 V to +5.5 V
G = −1, −5.5 V to +5.5 V
G = +2, VO = 4 V Step
100
100
145
120
50
42
7
175
170
180
55
MHz
MHz
MHz
MHz
MHz
ns
ns
V/µs
ns
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
130
Settling Time to 0.1%
G = +2, VO = 2 V Step
G = +2, VO = 8 V Step
205
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 1 MHz, G = +2, VO = 8 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−88
−67
−73
24
7
0.6
dBc
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.02
0.02
Degree
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VCM = 0 V, SOIC Package
0.4
1
2
25
1
1.5
17
6
mV
µV/°C
pA
pA
pA
SOIC Package
TMIN to TMAX
Input Offset Current
10
TMIN to TMAX
1
pA
Open-Loop Gain
VO = 3 V, RL = 1 kΩ
100
113
dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
−5 to +1.7
−5.0 to +2.4
−5.0 to +5.0
−100
V
V
dB
dB
Usable Range
Common-Mode Rejection Ratio
See the Theory of Operation section
VCM = −1 V to +1 V
VCM = −1 V to +1 V (SOT-23)
−85
−82
−91
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
−4.88 to +4.90 −4.94 to +4.95
V
RL = 150 Ω
−4.8 to +4.7
V
Output Current
VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
35
90
20
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
30% Overshoot G = +1
Operating Range
5
24
V
Quiescent Current per Amplifier
Power Supply Rejection Ratio
6.4
−100
7.2
mA
dB
PSRR
−85
Rev. E | Page 3 of 28
AD8065/AD8066
@ TA = 25°C, VS = 12 V, RL = 1 kΩ, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max Unit
MHz
MHz
MHz
MHz
MHz
MHz
ns
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −12.5 V to +12.5 V
G = −1, −12.5 V to +12.5 V
G = +2, VO = 4 V Step
100
100
145
115
50
40
7
175
170
180
55
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery
Output Overdrive Recovery
Slew Rate
ns
V/µs
ns
130
Settling Time to 0.1%
G = +2, VO = 2 V Step
G = +2, VO = 10 V Step
250
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 1 MHz, G = +2, VO = 10 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−100
−67
−85
24
7
1
dBc
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.04
0.03
Degree
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VCM = 0 V, SOIC Package
0.4
1
3
25
2
1.5
17
7
mV
µV/°C
pA
pA
pA
SOIC Package
TMIN to TMAX
Input Offset Current
10
TMIN to TMAX
2
pA
Open-Loop Gain
VO = 10 V, RL = 1 kΩ
103
114
dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
−12 to +8.5
−12.0 to +9.5
−12.0 to +12.0
−100
V
V
dB
dB
Usable Range
Common-Mode Rejection Ratio
See the Theory of Operation section
VCM = −1 V to +1 V
VCM = −1 V to +1 V (SOT-23)
−85
−82
−91
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
−11.8 to +11.8 −11.9 to +11.9
V
RL = 350 Ω
−11.25 to +11.5
V
Output Current
VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
30
120
25
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
30% Overshoot G = +1
Operating Range
5
24
V
Quiescent Current per Amplifier
Power Supply Rejection Ratio
6.6
−93
7.4
mA
dB
PSRR
−84
Rev. E | Page 4 of 28
AD8065/AD8066
@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −0.5 V to +5.5 V
G = −1, −0.5 V to +5.5 V
G = +2, VO = 2 V Step
125
110
155
130
50
43
6
175
170
160
60
MHz
MHz
MHz
MHz
MHz
ns
ns
V/µs
ns
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
105
G = +2, VO = 2 V Step
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−65
−50
22
7
0.6
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.13
0.16
Degree
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VCM = 1.0 V, SOIC Package
0.4
1
1
25
1
1
1.5
17
5
mV
µV/ºC
pA
pA
pA
pA
dB
dB
SOIC Package
TMIN to TMAX
Input Offset Current
Open-Loop Gain
5
TMIN to TMAX
VO = 1 V to 4 V (AD8065)
VO = 1 V to 4 V (AD8066)
100
90
113
103
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
0 to 1.7
0 to 2.4
0 to 5.0
−100
V
V
dB
dB
Usable Range
Common-Mode Rejection Ratio
See the Theory of Operation section
VCM = 1 V to 4 V
VCM = 1 V to 2 V (SOT-23)
−74
−78
−91
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
0.1 to 4.85
0.03 to 4.95
V
RL = 150 Ω
0.07 to 4.83
V
Output Current
VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
35
75
5
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
30% Overshoot G = +1
Operating Range
5
24
V
Quiescent Current per Amplifier
Power Supply Rejection Ratio
5.8
−78
6.4
−100
7.0
mA
dB
PSRR
Rev. E | Page 5 of 28
AD8065/AD8066
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage
Power Dissipation
26.4 V
See Figure 3
VEE − 0.5 V to VCC + 0.5 V
1.8 V
−65°C to +125°C
−40°C to +85°C
300°C
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering, 10 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 6 of 28
AD8065/AD8066
MAXIMUM POWER DISSIPATION
2.0
1.5
1.0
0.5
0
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction
temperature (TJ) on the die. The plastic encapsulating the die
will locally reach the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic will
change its properties. Even temporarily exceeding this
temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8065/AD8066. Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices, potentially causing failure.
MSOP-8
SOIC-8
SOT-23-5
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and total power dissipated in the
package (PD) determine the junction temperature of the die. The
junction temperature can be calculated as
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as
discussed in the Layout, Grounding, and Bypassing
Considerations section.
TJ =TA +
PD × θJA
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS /2 × IOUT, some of
which is dissipated in the package and some in the load (VOUT
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC
(125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W)
packages on a JEDEC standard 4-layer board. θJA values are
approximations.
×
I
OUT). The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + Total Drive Power − Load Power
OUTPUT SHORT CIRCUIT
2
V
VOUT
RL
V OUT
RL
⎛
⎜
⎞
⎟
S
Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
PD =
(
VS × IS
)
+
×
−
2
⎝
⎠
RMS output voltages should be considered. If RL is referenced to
VS−, as in single-supply operation, then the total drive power is
VS × IOUT
.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply.
2
(
VS/4
RL
)
PD =
(
VS × IS +
)
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
Rev. E | Page 7 of 28
AD8065/AD8066
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: 5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C.
24
21
18
15
12
9
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
R
= 150Ω
L
G = +10
G = +5
G = +2
V
V
= 0.2V p-p
= 0.7V p-p
V
= 200mV p-p
OUT
O
OUT
V
= 1.4V p-p
OUT
G = +2
G = +1
6
3
0
–3
–6
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 4. Small Signal Frequency Response for Various Gains
Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)
6
4
9
8
7
6
5
4
3
V
= 200mV p-p
O
V
= 200mV p-p
O
G = +1
G = +2
V
= +5V
S
V
= +5V
S
2
V
= ±5V
S
V
= ±5V
S
0
V
= ±12V
S
V
= ±12V
S
–2
–4
–6
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42)
Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43)
2
8
V
= 2V p-p
O
G = +1
G = +2
1
0
7
6
5
4
3
2
1
0
V
= +5V
S
V
= ±5V
S
V
= ±12V
S
V
= ±5V
S
–1
–2
–3
–4
–5
V
= ±12V
S
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42)
Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43)
Rev. E | Page 8 of 28
AD8065/AD8066
9
6
8
6
V
= 200mV p-p
O
C
R
= 25pF
L
G = +1
= 20
Ω
SNUB
C
C
= 25pF
= 20pF
C
= 55pF
= 25pF
L
L
L
C
= 5pF
L
4
C
L
3
2
0
0
C
= 5pF
L
–2
–4
–6
–8
–3
–6
–9
V
= 200mV p-p
O
G = +2
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42)
Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43)
8
8
V
= 0.2V p-p
OUT
R
= 100Ω
7
6
5
4
3
2
1
0
6
4
L
V
= 2V p-p
= 4V p-p
G = +2
OUT
R
= 1kΩ
L
2
V
OUT
0
–2
–4
–6
–8
V
= 200mV p-p
O
G = +2
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43)
Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43)
80
60
40
20
0
120
14
V
= 200mV p-p
O
12
10
8
G = +2
PHASE
60
R
R
= R = 1kΩ,
G
F
S
= 500
Ω
R
R
= R = 500
Ω
Ω
,
,
F
S
G
0
= 250Ω
6
GAIN
R
R
C
= R = 500
F
S
F
G
= 250
4
Ω,
–60
–120
–180
R
= R = 1k
Ω
,
,
F
G
= 2.2pF
R
C
= 500
= 3.3pF
Ω
S
2
F
0
–2
–20
0.01
–4
0.1
0.1
1
10
100
1000
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 15. Open-Loop Response
Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)
Rev. E | Page 9 of 28
AD8065/AD8066
–40
–50
–30
–40
–50
G = +2
–60
HD2 G = +2
–60
HD3 G = +2
–70
–70
HD2 R = 150
Ω
L
HD2 R = 1k
Ω
HD2 G = +1
L
–80
–80
HD3 R = 1k
Ω
L
–90
–90
HD3 R = 150
Ω
L
HD3 G = +1
–100
–110
–120
–100
–110
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 19. Harmonic Distortion vs. Frequency for Various Gains
(See Figure 42 and Figure 43)
Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43)
–30
–20
–30
V
= ±12V
S
–40
–50
G = +2
= ±12V
F = 1MHz
G = +2
HD2 V = 20V p-p
V
O
S
–40
HD3 V = 20V p-p
–50
O
–60
–60
HD2 R = 150
Ω
HD2 V = 10V p-p
O
–70
L
–70
HD3 R = 150
Ω
L
–80
HD3 V = 10V p-p
–80
O
–90
HD2 R = 300
Ω
L
–90
–100
–110
–120
HD2 V = 2V p-p
–100
–110
–120
O
HD3 R = 300
Ω
L
HD3 V = 2V p-p
O
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0.1
1.0
10.0
OUTPUT AMPLITUDE (V p-p)
FREQUENCY (MHz)
Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = 12 V
(See Figure 43)
Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 42 and Figure 43)
50
100
R
= 100Ω
L
V
= ±12V
S
45
40
35
30
25
20
15
V
= ±5V
S
10
V
= +5V
S
1
10
1
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage
Figure 21. Voltage Noise
Rev. E | Page 10 of 28
AD8065/AD8066
G = +1
C
= 5pF
G = +1
L
C
= 20pF
L
20ns/DIV
50mV/DIV
20ns/DIV
50mV/DIV
Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52)
Figure 25. Small Signal Transient Response 5 V (See Figure 42)
G = +2
5µs
S
G = +1
V
= ±12V
V
= ±12V
S
V
= 10V p-p
= 2V p-p
OUT
V
= 10V p-p
= 4V p-p
OUT
V
OUT
V
OUT
V
= 2V p-p
OUT
80ns/DIV
80ns/DIV
2V/DIV
2V/DIV
Figure 23. Large Signal Transient Response (See Figure 42)
Figure 26. Large Signal Transient Response (See Figure 43)
IN
–IN
OUT
G = +1
G = –1
= ±5V
V
= ±5V
V
S
S
OUT
1.5V/DIV
1.5V/DIV
100ns/DIV
100ns/DIV
Figure 24. Output Overdrive Recovery (See Figure 44)
Figure 27. Input Overdrive Recovery (See Figure 42)
Rev. E | Page 11 of 28
AD8065/AD8066
V
= 140mV/DIV
IN
V
= 500mV/DIV
IN
V
– 2V
IN
OUT
+0.1%
+0.1%
–0.1%
–0.1%
t = 0
t = 0
V
– 2V
IN
OUT
2mV/DIV
10ns/DIV
2mV/DIV
64µs/DIV
Figure 28. Long-Term Settling Time (See Figure 49)
Figure 31. 0.1% Short-Term Settling Time (See Figure 49)
42
36
30
24
18
12
6
0
–5
+I
b
–I
b
–I
b
–10
–15
–20
–25
–30
0
10
5
–I
b
0
+I
b
–5
–10
–15
+I
b
–20
–25
–30
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12
25
35
45
55
65
75
85
COMMON-MODEVOLTAGE (V)
TEMPERATURE (°C)
Figure 32. Input Bias Current vs. Common-Mode Voltage Range
(see the Input and Output Overload Behavior section)
Figure 29. Input Bias Current vs. Temperature
40
35
30
25
20
15
10
5
0.3
0.2
N = 299
SD = 0.388
MEAN = –0.069
0.1
V
= +5V
S
V
= ±5V
S
0
–0.1
–0.2
–0.3
V
= ±12V
S
0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
INPUT OFFSET VOLTAGE (mV)
COMMON-MODE VOLTAGE (V)
Figure 33. Input Offset Voltage
Figure 30. Input Offset Voltage vs. Common-Mode Voltage
Rev. E | Page 12 of 28
AD8065/AD8066
–30
–40
–50
–60
–70
–80
–90
–100
100
10
1
G = +1
G = +2
V
= ±12V
S
0.1
0.01
0
V
= ±5V
S
0.1
1
10
FREQUENCY (MHz)
100
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)
Figure 34. CMRR vs. Frequency (See Figure 46)
0.30
0.25
0.20
0.15
0.10
0.05
0
80
70
V
– V
OH
CC
V
– V
OH
CC
60
50
40
30
V
– V
EE
OL
V
– V
EE
OL
0
10
20
30
40
25
35
45
55
65
75
85
I
(mA)
LOAD
TEMPERATURE (°C)
Figure 35. Output Saturation Voltage vs. Output Load Current
Figure 38. Output Saturation Voltage vs. Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
= 2V p-p
IN
G = +1
–PSRR
+PSRR
B TO A
A TO B
0.01
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)
Figure 39. Crosstalk vs. Frequency (See Figure 51)
Rev. E | Page 13 of 28
AD8065/AD8066
125
120
115
110
105
100
95
6.60
V
= ±12V
S
6.55
6.50
6.45
6.40
6.35
6.30
6.25
V
= ±5V
S
V
= ±12V
S
V
= +5V
S
V
= +5V
S
V
= ±5V
S
90
85
80
0
10
20
(mA)
30
40
–40
–20
0
20
40
60
80
I
LOAD
TEMPERATURE (°C)
Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages
Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages
Rev. E | Page 14 of 28
AD8065/AD8066
TEST CIRCUITS
SOIC-8 Pinout
+V
CC
+V
CC
4.7µF
0.1µF
4.7µF
0.1µF
2.2pF
24.9Ω
499Ω
499Ω
V
IN
49.9Ω
FET PROBE
FET PROBE
R
SNUB
AD8065
AD8065
V
IN
249Ω
C
LOAD
1kΩ
1kΩ
49.9Ω
0.1µF
4.7µF
0.1µF
4.7µF
–V
–V
EE
EE
Figure 42. G = +1
Figure 44. G = −1
+V
+V
CC
CC
4.7µF
0.1µF
4.7µF
0.1µF
2.2pF
24.9Ω
499Ω
499Ω
FET PROBE
R
SNUB
AD8065
AD8065
NETWORK ANALYZER S22
V
IN
249Ω
C
1kΩ
LOAD
0.1µF
4.7µF
0.1µF
49.9Ω
4.7µF
–V
EE
–V
EE
Figure 45. Output Impedance G = +1
Figure 43. G = +2
Rev. E | Page 15 of 28
AD8065/AD8066
+V
CC
V
IN
1V p-p
4.7µF
0.1µF
+V
CC
49.9Ω
24.9Ω
499Ω
499Ω
V
IN
FET PROBE
FET PROBE
AD8065
AD8065
49.9Ω
499Ω
1kΩ
1kΩ
0.1µF
4.7µF
499Ω
0.1µF
4.7µF
–V
EE
–V
EE
Figure 46. CMRR
Figure 48. Positive PSRR
+V
+V
CC
CC
4.7µF
0.1µF
4.7µF
0.1µF
2.2pF
499Ω
499Ω
499Ω
499Ω
AD8065
249Ω
NETWORK ANALYZER
S22
976Ω
TO SCOPE
AD8065
249Ω
V
IN
0.1µF
49.9Ω
0.1µF
4.7µF
49.9Ω
4.7µF
–V
EE
–V
EE
Figure 47. Output Impedance G = +2
Figure 49. Settling Time
Rev. E | Page 16 of 28
AD8065/AD8066
+V
CC
4.7µF
0.1µF
2.2pF
499Ω
499Ω
24.9Ω
5V
4.7µF
1.5V
0.1µF
FET PROBE
FET PROBE
AD8065
AD8065
249Ω
V
IN
1kΩ
49.9Ω
1kΩ
49.9Ω
V
IN
1V p-p
1.5V
1.5V
–V
EE
Figure 50. Negative PSRR
Figure 52. Single Supply
24.9Ω
FET PROBE
24.9Ω
AD8066
+5V
1kΩ
4.7µF
0.1µF
RECEIVE SIDE
AD8066
V
IN
0.1µF
1kΩ
49.9Ω
4.7µF
–5V
DRIVE SIDE
Figure 51. Crosstalk—AD8066
Rev. E | Page 17 of 28
AD8065/AD8066
THEORY OF OPERATION
The AD8065/AD8066 are voltage feedback operational
amplifiers that combine a laser-trimmed JFET input stage with
the Analog Devices eXtra Fast Complementary Bipolar (XFCB)
process, resulting in an outstanding combination of precision
and speed. The supply voltage range is from 5 V to 24 V. The
amplifiers feature a patented rail-to-rail output stage capable of
driving within 0.5 V of either power supply while sourcing or
sinking up to 30 mA. Also featured is a single-supply input stage
that handles common-mode signals from below the negative
supply to within 3 V of the positive rail. Operation beyond the
JFET input range is possible because of an auxiliary bipolar
input stage that functions with input voltages up to the positive
supply. The amplifiers operate as if they have a rail-to-rail input
and exhibit no phase reversal behavior for common-mode
voltages within the power supply.
NONINVERTING CLOSED-LOOP FREQUENCY
RESPONSE
Solving for the transfer function
2π× fcrossover
RG + RF
VO
VI
=
(
RF + RG s +2π× fcrossover × RG
)
where fcrossover is the frequency where the amplifier’s open-loop
gain equals 0 db
VO RF + RG
At dc
=
VI
RG
Closed-loop −3 dB frequency
RG
RF + RG
f−3dB = fcrossover
×
With voltage noise of 7 nV/√Hz and −88 dBc distortion for
1 MHz 2 V p-p signals, the AD8065/AD8066 are a great choice
for high resolution data acquisition systems. Their low noise,
sub-pA input current, precision offset, and high speed make
them superb preamps for fast photodiode applications. The
speed and output drive capability of the AD8065/AD8066 also
make them useful in video applications.
INVERTING CLOSED-LOOP FREQUENCY
RESPONSE
−2π× fcrossover × RF
RF + RG +2π× fcrossover × RG
VO
VI
=
s
(
)
VO
VI
RF
RG
At dc
= −
CLOSED-LOOP FREQUENCY RESPONSE
The AD8065/AD8066 are classic voltage feedback amplifiers
with an open-loop frequency response that can be approx-
imated as the integrator response shown in Figure 53. Basic
closed-loop frequency response for inverting and noninverting
configurations can be derived from the schematics shown.
Closed-loop −3 dB frequency
RG
f−3dB = fcrossover
×
RF + RG
R
F
R
F
R
G
R
G
V
I
V
V
O
O
V
A
A
V
E
E
V
I
80
A = (2π × fcrossover)/s
60
40
20
0
fcrossover = 65MHz
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 53. Open-Loop Gain vs. Frequency and Basic Connections
Rev. E | Page 18 of 28
AD8065/AD8066
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (RF + RG )/RG. This simple
model is accurate for noise gains above 2. The actual bandwidth
of circuits with noise gains at or below 2 will be higher than
those predicted with this model due to the influence of other
poles in the frequency response of the real op amp.
For the best settling times and the best distortion, the
impedances at the AD8065/AD8066 input terminals should be
matched. This minimizes nonlinear common-mode capacitive
effects that can degrade ac performance.
Actual distortion performance depends on a number of
variables:
R
F
•
•
•
•
•
The closed-loop gain of the application
Whether it is inverting or noninverting
Amplifier loading
Signal frequency and amplitude
Board layout
+V
OS
–
R
G
V
O
I
I
A
b
–
R
S
V
I
b+
Also see Figure 16 to Figure 20. The lowest distortion will be
obtained with the AD8065 used in low gain inverting appli-
cations, since this eliminates common-mode effects. Higher
closed-loop gains result in worse distortion performance.
Figure 54. Voltage Feedback Amplifier DC Errors
Figure 54 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
INPUT PROTECTION
The inputs of the AD8065/AD8066 are protected with back-to-
back diodes between the input terminals as well as ESD diodes
to either power supply. This results in an input stage with
picoamps of input current that can withstand up to 1500 V ESD
events (human body model) with no degradation.
R + R
RG
R + R
RG
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
G
F
G
F
VO
(
error
)
= Ib+ × RS
− I × RF +VOS
b−
⎝
⎠
⎝
⎠
The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG
(though with the AD8065 input currents at less than 20 pA over
temperature, this is likely not a concern). To include common-
mode and power supply rejection effects, total VOS can be
modeled as
Excessive power dissipation through the protection devices will
destroy or degrade the performance of the amplifier. Differ-
ential voltages greater than 0.7 V will result in an input current
of approximately (|V+ − V−| 0.7 V)/RI, where RI is the resistance
in series with the inputs. For input voltages beyond the positive
ΔVS ΔVCM
PSR CMR
VOS =VOS
+
+
nom
supply, the input current will be approximately (VI − VCC
−
VOS
is the offset voltage specified at nominal conditions,
nom
0.7)/RI. Beyond the negative supply, the input current will be
about (VI − VEE + 0.7)/RI. If the inputs of the amplifier are to be
subjected to sustained differential voltages greater than 0.7 V or
to input voltages beyond the amplifier power supply, input
current should be limited to 30 mA by an appropriately sized
input resistor (RI) as shown in Figure 55.
∆VS is the change in power supply from nominal conditions,
PSR is the power supply rejection, ∆VCM is the change in
common-mode voltage from nominal conditions, and CMR
is the common-mode rejection.
WIDEBAND OPERATION
(V – V – 0.7V)
Figure 42 through Figure 44 show the circuits used for
wideband characterization for gains of +1, +2, and −1. Source
impedance at the summing junction (RF || RG) will form a pole
in the amplifier’s loop response with the amplifier’s input
capacitance of 6.6 pF. This can cause peaking and ringing if the
time constant formed is too low. Feedback resistances of 300 Ω
to 1 kΩ are recommended, since they will not unduly load
down the amplifier and the time constant formed will not be
too low. Peaking in the frequency response can be compensated
for with a small capacitor (CF) in parallel with the feedback
resistor, as illustrated in Figure 12. This shows the effect of
different feedback capacitances on the peaking and bandwidth
for a noninverting G = +2 amplifier.
(| V – V | – 0.7V)
I
EE
+
–
R >
I
R >
I
30mA
30mA
(V – V + 0.7V)
I
EE
FOR LARGE | V – V
+
|
R >
I
–
30mA
FOR V BEYOND
AD8065
I
R
SUPPLY VOLTAGES
I
V
I
V
O
Figure 55. Current Limiting Resistor
Rev. E | Page 19 of 28
AD8065/AD8066
The circuit is arranged such that when the input common-
mode voltage exceeds a certain threshold, the input JFET pair’s
bias current will turn OFF, and the bias current of an auxiliary
NPN pair will turn ON, taking over control of the amplifier.
When the input common-mode voltage returns to a viable
operating value, the FET stage turns back ON, the NPN stage
turns OFF, and normal operation resumes.
THERMAL CONSIDERATIONS
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8066
dissipates 312 mW. This can lead to noticeable thermal effects,
especially in the small SOT-23-5 (thermal resistance of
160°C/W). VOS temperature drift is trimmed to guarantee a
maximum drift of 17 µV/°C, so it can change up to 0.425 mV
due to warm-up effects for an AD8065/AD8066 in a SOT-23-5
package on 24 V.
The NPN pair can sustain operation with the input voltage up
to the positive supply, so this is a pseudo rail-to-rail input stage.
For operation beyond the FET stage’s common-mode limit, the
amplifier’s VOS will change to the NPN pair’s offset (mean of
160 µV, standard deviation of 820 µV), and Ib will increase to the
NPN pair’s base current up to 45 µA (see Figure 32).
Ib increases by a factor of 1.7 for every 10°C rise in temperature.
Ib will be close to 5 times higher at 24 V supplies as opposed to a
single 5 V supply.
Heavy loads will increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken to not exceed the
rated power dissipation of the package.
Switchback, or recovery time, is about 100 ns, see Figure 27.
The output transistors of the rail-to-rail output stage have
circuitry to limit the extent of their saturation when the output
is overdriven. This helps output recovery time. Output recovery
from a 0.5 V output overdrive on a 5 V supply is shown in
Figure 24.
INPUT AND OUTPUT OVERLOAD BEHAVIOR
The AD8065/AD8066 have internal circuitry to guard against
phase reversal due to overdriving the input stage. A simplified
schematic of the input stage, including the input-protection
diodes and antiphase reversal circuitry, is shown in Figure 56.
Rev. E | Page 20 of 28
AD8065/AD8066
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
GROUNDING
Power supply pins are actually inputs and care must be taken so
that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.
A ground plane layer is important in densely packed PC boards
to spread the current minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and therefore the high
frequency impedance of the path. High speed currents in an
inductive ground return will create an unwanted voltage noise.
Decoupling schemes are designed to minimize the bypassing
impedance at all frequencies with a parallel combination of
capacitors. 0.1 µF (X7R or NPO) chip capacitors are critical
and should be as close as possible to the amplifier package.
The 4.7 µF tantalum capacitor is less critical for high frequency
bypassing, and, in most cases, only one is needed per board, at
the supply inputs.
V
CC
R1
R5
TO REST OF AMP
Q2
Q5
V
THRESHOLD
VBIAS
D1
D2
R6
R3
Q1
Q6
V
V
N
P
D3
D4
Q3
Q4
S
S
R4
R7
R2
R8
Q7
I
I
T2
T1
–V
EE
Figure 56. Simplified Input Stage
Rev. E | Page 21 of 28
AD8065/AD8066
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding will
work against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents flow from the supplies
as well, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, which are effective at lower frequencies,
the current return path distance is less critical.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance will reduce the input imped-
ance at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations,
if severe enough. It is recommended that the external passive
components connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a small distance from the
input pins on all layers of the board.
LEAKAGE CURRENTS
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8065/AD8066. Any voltage
differential between the inputs and nearby runs will set up
leakage currents through the PC board insulator, for example,
1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board
can create significant leakage (skin oils are a common problem).
To significantly reduce leakage, put a guard ring (shield) around
the inputs and input leads that are driven to the same voltage
potential as the inputs. This way there is no voltage potential
between the inputs and surrounding area to set up any leakage
currents. For the guard ring to be completely effective, it must
be driven by a relatively low impedance source and should
completely surround the input leads on all sides, above and
below, using a multilayer board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking and ringing of the frequency response. There are two
methods to effectively minimize their effect.
•
•
As shown in Figure 57, put a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amp’s output stage. A good value to choose is 20 Ω (see
Figure 10).
Increase the phase margin with higher noise gains or add a
pole with a parallel resistor and capacitor from −IN to the
output.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard ring
will help to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, could be necessary in
some instances.
R
= 20Ω
S
V
AD8065
O
C
V
L
I
Figure 57. Output Isolation Resistor
C
F
R
F
11
= 10 Ω
SH
C
C
I
R
M
PHOTO
C
S
C
D
V
M
O
V
B
C
+ C
S
F
R
F
Figure 58. Wideband Photodiode Preamp
Rev. E | Page 22 of 28
AD8065/AD8066
INPUT-TO-OUTPUT COUPLING
The preamp’s output noise over frequency is shown in Figure 59.
In order to minimize capacitive coupling between the inputs
and output, the output signal traces should not be parallel with
the inputs.
1
f1
=
2πR (C + C + C + 2C
)
F
F
S
M
D
1
WIDEBAND PHOTODIODE PREAMP
f2
f3
=
=
2πR C
F
F
Figure 58 shows an I/V converter with an electrical model of a
photodiode. The basic transfer function is where
fCR
(C + C + 2C + C )/C
F
S
M
D
F
IPHOTO × RF
1+ sCF RF
R
NOISE
F
VOUT
=
f3
f2
VEN (C + C + C + 2C )/C
F
F
S
M
D
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF set the signal bandwidth.
f1
VEN
NOISE DUE TO AMPLIFIER
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS
and the amplifier input capacitance. RF and the total capacitance
produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding CF creates a 0 in the
loop transmission, which compensates for the pole’s effect and
reduces the signal bandwidth. It can be shown that the signal
bandwidth resulting in a 45° phase margin (f(45)) is defined by
the expression
FREQUENCY (Hz)
Figure 59. Photodiode Voltage Noise Contributions
The pole in the loop transmission translates to a 0 in the
amplifier’s noise gain, leading to an amplification of the input
voltage noise over frequency. The loop transmission 0
introduced by CF limits the amplification. The noise gain
bandwidth extends past the preamp signal bandwidth and is
eventually rolled off by the decreasing loop gain of the
amplifier. Keeping the input terminal impedances matched is
recommended to eliminate common-mode noise peaking
effects, which will add to the output noise.
fCR
f(
=
)
45
2π× RF ×CS
Integrating the square of the output voltage noise spectral
density over frequency and then taking the square root allows
users to obtain the total rms output noise of the preamp. Table 5
summarizes approximations for the amplifier and feedback and
source resistances. Noise components for an example preamp
with RF = 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about
1.6 MHz) are also listed.
where fCR is the amplifier crossover frequency, RF is the feedback
resistor, and CS is the total capacitance at the amplifier summing
junction (amplifier + photodiode + board parasitics).
The value of CF that produces f(45) can be shown to be
CS
CF =
2π× RF × fCR
The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half will result in a flat frequency response, with
about 5% transient overshoot.
Table 5. RMS Noise Contributions of Photodiode Preamp
RMS Noise with RF = 50 kΩ,
CS = 15 pF, CS = 15 pF
Contributor
Expression
64.5 µV
2.4 µV
31 µV
RF (×2)
2 × 4 kT × RF × f2 ×1.57
Amp to f1
VEN × f1
Amp (f2 – f1)
CS +CM +CF +2CD
VEN ×
×
f2 − f1
CF
Amp to (past f2)
260 µV
CS +CM +CD +2CF
VEN ×
×
f3 ×1.57
CF
270 µV (Total)
Rev. E | Page 23 of 28
AD8065/AD8066
V
CC
4.7µF
0.1µF
R
S1
1
/
2
V
N
2.2pF
AD8066
4.7µF
R2
0.1µF
500Ω
V
V
CC
EE
4.7µF
0.1µF
R1
500Ω
R
= 500Ω
F
V
O
AD8065
R
G
4.7µF
0.1µF
R3
V
R
= 500Ω
500Ω
EE
F
V
CC
4.7µF
0.1µF
R4
500Ω
2.2pF
1
/
2
AD8066
R
S2
V
P
4.7µF
0.1µF
V
EE
Figure 60. High Speed Instrumentation Amplifier
RF || 0.5(RG). This is the value to be used for matching purposes.
HIGH SPEED JFET INPUT INSTRUMENTATION
AMPLIFIER
VIDEO BUFFER
Figure 60 shows an example of a high speed instrumentation
amplifier with high input impedance using the
AD8065/AD8066. The dc transfer function is
The output current capability and speed of the AD8065 make it
useful as a video buffer, shown in Figure 61.
The G = +2 configuration compensates for the voltage division
of the signal due to the signal termination. This buffer
maintains 0.1 dB flatness for signals up to 7 MHz, from low
amplitudes up to 2 V p-p (Figure 7). Differential gain and phase
have been measured to be 0.02% and 0.028° at 5 V supplies.
1+1000
RG
⎛
⎜
⎞
⎟
VOUT
= VN −VP
( )
⎝
⎠
For G = +1, it is recommended that the feedback resistors for
the two preamps be set to a low value (for instance 50 Ω for 50
Ω source impedance). The bandwidth for G = +1 will be 50
MHz. For higher gains, the bandwidth will be set by the preamp,
equaling
+V
S
4.7µF
4.7µF
0.1µF
249Ω
75Ω
+
AD8065
V
–
I
Inamp−3dB
=
f
CR × RG
/
2 × RF
+
V
75Ω
O
–
0.1µF
Common-mode rejection of the inamp will be primarily
determined by the match of the resistor ratios R1:R2 to R3:R4. It
can be estimated
–V
S
2.2pF
VO
VCM
(
δ1−δ2
)
499Ω
=
499Ω
(
1+ δ1
)
δ2
The summing junction impedance for the preamps is equal to
Figure 61. Video Buffer
Rev. E | Page 24 of 28
AD8065/AD8066
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
3.00
BSC
8
1
5
4
8
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
4.90
BSC
3.00
BSC
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
PIN 1
1.75 (0.0688)
1.35 (0.0532)
0.65 BSC
0.25 (0.0098)
0.10 (0.0040)
1.10 MAX
8°
0.15
0.00
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.80
0.60
0.40
0.40 (0.0157)
8°
0°
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012AA
COPLANARITY
0.10
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 62. 8-Lead Standard Small Outline Package Narrow Body [SOIC]
Figure 64. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(R-8)
Dimensions shown in millimeters (inches)
Dimensions shown in millimeters
2.90 BSC
5
4
3
2.80 BSC
1.60 BSC
2
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
5°
0°
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 63. 5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
Rev. E | Page 25 of 28
AD8065/AD8066
ORDERING GUIDE
Model
AD8065AR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC
8-Lead SOIC
Package Outline
Branding
R-8
R-8
R-8
RT-5
RT-5
RT-5
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
AD8065AR-REEL
AD8065AR-REEL7
AD8065ART-REEL
AD8065ART-R2
AD8065ART-REEL7
AD8066AR
AD8066AR-REEL
AD8066AR-REEL7
AD8066ARZ1
AD8066ARZ-REEL1
AD8066ARZ-REEL71
AD8066ARM
AD8066ARM-REEL
AD8066ARM-REEL7
8-Lead SOIC
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
HRA
HRA
HRA
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
HIB
HIB
HIB
1 Z = Pb-free part.
Rev. E | Page 26 of 28
AD8065/AD8066
NOTES
Rev. E | Page 27 of 28
AD8065/AD8066
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02916-0-2/04(E)
Rev. E | Page 28 of 28
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