AD808-622BR [ADI]
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming; 光纤接收器与量化器和时钟恢复和数据重定时
| 型号： | AD808-622BR |
| 厂家： | 
ADI |
| 描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming |
| 文件： | 总12页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
a
AD808
FEATURES
Meets CCITT G.958 Requirem ents
for STM-4 Regenerator—Type A
frequency acquisition without false lock. T his eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
Meets Bellcore TR-NWT-000253 Requirem ents for OC-12
Output J itter: 2.5 Degrees RMS
622 Mbps Clock Recovery and Data Retim ing
Accepts NRZ Data, No Pream ble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
T he AD808 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. T he frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. T he phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD808.
Quantizer Sensitivity: 4 m V
Level Detect Range: 10 m V to 40 m V, Program m able
Single Supply Operation: +5 V or –5.2 V
Low Pow er: 400 m W
10 KH ECL/ PECL Com patible Output
Package: 16-Lead Narrow 150 m il SOIC
T he device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.5 degrees rms. T his low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. T he device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
P RO D UCT D ESCRIP TIO N
T he AD808 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
622 Mbps NRZ data. T he device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-12 or SDH ST M-4
fiber optic receiver.
T he user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCIT T G.958 T ype A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
T he receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. T he threshold is set with a single external resistor. T he
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
T he AD808 consumes 400 mW and operates from a single
power supply at either +5 V or –5.2 V.
T he PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
FUNCTIO NAL BLO CK D IAGRAM
CF1 CF2
QUANTIZER
PIN
COMPENSATING
ZERO
LOOP
FILTER
⌽
⌺
DET
NIN
PHASE-LOCKED LOOP
VCO
SIGNAL
THRADJ
LEVEL
DETECTOR
CLKOUTP
CLKOUTN
F
DET
LEVEL
DETECT
COMPARATOR/
BUFFER
DATAOUTP
DATAOUTN
RETIMING
DEVICE
AD808
SDOUT
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
AD808–SPECIFICATIONS (T = T to T , V = V to V , C = 0.47 F, unless otherwise noted)
A
MIN
MAX
S
MIN
MAX
D
P aram eter
Condition
Min
Typ
Max
Units
QUANT IZER–DC CHARACT ERIST ICS
Input Voltage Range
Input Sensitivity, VSENSE
Input Overdrive, VOD
Input Offset Voltage
Input Current
Input RMS Noise
Input Peak-to-Peak Noise
@ PIN or N IN
2.5
10
5
VS
V
PIN–NIN, Figure 1, BER = ≤ 1 × 10–10
Figure 1, BER = ≤ 1 × 10–10
4.0
2.0
1.0
10
100
1.5
mV
mV
mV
µA
µV
mV
BER = ≤ 1 × 10–10
BER = ≤ 1 × 10–10
QUANT IZER–AC CHARACT ERIST ICS
Upper –3 dB Bandwidth
Input Resistance
600
800
10
2
MHz
kΩ
pF
Input Capacitance
Pulsewidth Distortion
50
ps
LEVEL DET ECT
Level Detect Range
RT HRESH = 22.1 kΩ
RT HRESH = 6.98 kΩ
RT HRESH = 0 Ω
6.5
13
28.5
0.1
10
18
40
13.5
23
45.5
1.5
mV
mV
mV
µs
Response T ime
DC Coupled
Hysteresis (Electrical)
RT HRESH = 22.1 kΩ (See Figure 8)
RT HRESH = 6.98 kΩ
RT HRESH = 0 Ω
Load = +3.2 mA
Load = –3.2 mA
5
9.0
9.0
10.0
dB
dB
dB
V
3.0
3.0
4.0
5.1
7.0
4.7
0.2
SDOUT Output Logic High
SDOUT Output Logic Low
0.4
V
PHASE-LOCKED LOOP NOMINAL
CENT ER FREQUENCY
622.08
MHz
MHz
MHz
Degrees
ps
CAPT URE RANGE
620
620
624
624
81
T RACKING RANGE
ST AT IC PHASE ERROR (See Figure 7)
27–1 PRN Sequence
Figure 2
22
SET UP T IME (tSU
HOLD T IME (tH)
PHASE DRIFT
JIT T ER
)
550
700
900
1050
50
Figure 2
ps
240 Bits, No T ransitions
Degrees
27–1 PRN Sequence
2.5
2.5
3.6
3.6
Degrees rms
Degrees rms
223–1 PRN Sequence
JIT T ER T OLERANCE
f = 30 Hz
3000
300
3.7
0.56
0.45
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
f = 300 Hz
f = 25 kHz
f = 250 kHz
f = 5 MHz
24
1.7
0.28
0.18
JIT T ER T RANSFER
Peaking (Figure 14)
Bandwidth
CD = 0.47 µF
0.04
333
dB
kHz
450
Acquisition T ime
C D = 0.1 µF
C D = 0.47 µF
223–1 PRN Sequence, TA = +25°C
VCC = 5 V, VEE = GND
2 × 106
8 × 106
3 × 106
Bit Periods
12 × 106 Bit Periods
POWER SUPPLY VOLT AGE
POWER SUPPLY CURRENT
VMIN to VMAX
4.5
55
5.5
Volts
VCC = 5.0 V, VEE = GND,
T A = +25°C
80
100
mA
PECL OUT PUT VOLT AGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
T A = +25°C
Referenced to VCC
–1.2
–2.2
–1.0
–2.0
–0.7
–1.7
Volts
Volts
SYMMET RY (Duty Cycle)
ρ = 1/2, T A = +25°C,
Recovered Clock Output, Pin 5
VCC = 5 V, VEE = GND
45
55
%
OUT PUT RISE / FALL T IMES
Rise T ime (tR)
Fall T ime (tF)
20%–80%
80%–20%
174
136
350
315
500
500
ps
ps
CLOCK SKEW (tRCS
)
Positive Number Indicates Clock
Leading Data
–100
130
250
ps
Specifications subject to change without notice.
–2–
REV. 0
AD808
P IN FUNCTIO N D ESCRIP TIO NS
ABSO LUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V
Maximum Junction T emperature . . . . . . . . . . . . . . . . +165°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . 1500 V
P in
No.
Mnem onic
D escription
1
DAT AOUT N
DAT AOUT P
VCC2
Differential Retimed Data Output
Differential Retimed Data Output
Digital VCC for ECL Outputs
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital VCC for Internal Logic
Loop Damping Capacitor
Loop Damping Capacitor
Analog VEE
2
3
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
T hermal Characteristics:
4
CLKOUT N
CLKOUT P
VCC1
5
6
7
CF1
16-Lead Narrow Body SOIC Package: θJA = 110°C/Watt.
8
CF2
OUTPUT
9
AVEE
NOISE
1
10
11
12
13
14
15
16
T HRADJ
AVCC1
Level Detect T hreshold Adjust
Analog VCC for PLL
NIN
Quantizer Differential Input
Quantizer Differential Input
Analog VCC for Quantizer
Signal Detect Output
0
PIN
INPUT (V)
AVCC2
OFFSET
OVERDRIVE
SENSITIVITY
SDOUT
VEE
Digital VEE for Internal Logic
Figure 1. Input Sensitivity, Input Overdrive
P IN CO NFIGURATIO N
DATAOUT 50%
(PIN 2)
DATAOUTN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HOLD TIME
DATAOUTP
SDOUT
tH
CLKOUT 50%
(PIN 5)
SETUP TIME
tSU
V
AV
CC2
CC2
AD808
TOP VIEW
(Not to Scale)
CLKOUTN
CLKOUTP
PIN
NIN
tRCS
RECOVERED
CLOCK SKEW
V
AV
CC1
CC1
Figure 2. Setup and Hold Tim e
CF1
CF2
THRADJ
AV
EE
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD808-622BR
AD808-622BRRL7
AD808-622BRRL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Pin Narrowbody SOIC
750 Pieces, 7" Reel
2500 Pieces, 13" Reel
R-16A
R-16A
R-16A
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD808 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD808
Tr acking Range
D EFINITIO N O F TERMS
T his is the range of input data rates over which the AD808 will
remain in lock.
Maxim um , Minim um and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. T ypical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. T his procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guard-
banded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Captur e Range
T his is the range of input data rates over which the AD808 will
acquire lock.
Static P hase Er r or
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling in-
stant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals pro-
hibit direct measurement of static phase error.
D ata Tr ansition D ensity, ρ
Input Sensitivity and Input O ver dr ive
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
Sensitivity and Overdrive specifications for the Quantizer in-
volve offset voltage, gain and noise. T he relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
Jitter
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but
occur over a range of input voltages. Within this Zone of Confu-
sion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. T he width of this zone is determined by the
input voltage noise of the quantizer (1.5 mV at the 1 × 10–10
confidence level). T he center of the Zone of Confusion is the
quantizer input offset voltage (1 mV typ). Input Overdrive is the
magnitude of signal required to guarantee correct logic level
with 1 × 10–10 confidence level.
O utput Jitter
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter Toler ance
Jitter T olerance is a measure of the AD808’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
With a single-ended PIN-T IA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some common-
mode potential. Observing the Quantizer input with an oscillo-
scope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instan-
taneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Over-
drive. T he AD808 Quantizer has 4 mV Sensitivity typical.
T he PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. T he modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD808 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. T he AD808
output will have a bit error rate less than 1 × 10–10 when in lock
and retiming input data that has the CCIT T G.958 specified
jitter applied to it.
With a differential T IA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
T his is an illusion caused by the use of a single-ended probe. A
2 mV peak-to-peak signal appears to drive the AD808 Quan-
tizer. However, the single-ended probe measures only half the
signal. T he true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the sig-
nal being observed.
Jitter Tr ansfer (Refer to Figur e 14)
T he AD808 exhibits a low-pass filter response to jitter applied
to its input data.
Response Tim e
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT . T he re-
sponse time of the AD808 (1.5 µs maximum) is much faster
Bandwidth
T his describes the frequency at which the AD808 attenuates
sinusoidal input jitter by 3 dB.
than the SONET /SDH requirement (3 µs
≤ response time ≤
100 µs). In practice, the time constant of the ac coupling at the
Quantizer input determines the LOS response time.
P eaking
T his describes the maximum jitter gain of the AD808 in dB.
Nom inal Center Fr equency
T his is the frequency at which the VCO will oscillate with the
loop damping capacitor, CD, shorted.
–4–
REV. 0
AD808
D am ping Factor , ζ
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.
Damping factor, ζ describes the compensation of the second
order PLL. A larger value of ζ corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition Tim e
T his is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
AV
CC
500⍀
500⍀
PIN
NIN
Sym m etr y—Recover ed Clock D uty Cycle
5k⍀
5k⍀
OUT
Symmetry is calculated as (100 × on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
AV
EE
4mVp-p
V
CM
a. Quantizer Differential Input Stage
SCOPE
PROBE
AD808 QUANTIZER
INPUT
1.2V +V
BE
6k⍀
BINARY
OUTPUT
THRADJ
80k⍀
AV
EE
V
CM
b. Threshold Adjust
a. Single-Ended Input Application
V
CC1
2mVp-p
V
CM
I
OH
OL
30⍀
30⍀
SCOPE
PROBE
SDOUT
AD808 QUANTIZER
+INPUT
–INPUT
I
BINARY
OUTPUT
V
EE
c. Signal Detect Output (SDOUT)
V
CM
V
CC2
b. Differential Input Application
140⍀
140⍀
Figure 3. (a–b) Single-Ended and Differential Input
Applications
DIFFERENTIAL
OUTPUT
T he AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. T his allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. T he internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
7.8mA
V
EE
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 4. (a–d) Sim plified Schem atics
REV. 0
–5–
AD808–Typical Performance Characteristics
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
180
160
140
120
100
80
60
40
20
0
6
8
10
12
14
16
2.00
2.67
3.33
4.00
4.67
5.33
6.00
6.67
4
SIGNAL DETECT VOLTAGE – mV
LOS HYSTERESIS – dB
Figure 5. Signal Detect Voltage vs. RTHRESH
Figure 8. Histogram LOS Hysteresis 22.1 kΩ RTHRESH
(All Tem perature All Supply)
8.0
200
TEST CONDITIONS
WORST CASE:
–40؇C
180
160
140
120
100
80
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
R
= 0
TH
R
= 5k
TH
60
R
= 7k
TH
40
20
0
–40
–20
0
20
40
60
80
95
1.44
1.80
2.16
2.52
2.88
3.24
3.60
3.96
TEMPERATURE – ؇C
JITTER – Degrees
Figure 6. Signal Detect Hysteresis vs. Tem perature
Figure 9. Output J itter Histogram
12
10
8
100
10
25؇C
85؇C
–40؇C
6
SONET MASK
4
1
2
0
0.1
1
0
8
17
25
33
42
50
58
10
100
1k
10k
100k
1M
10M
STATIC PHASE – Degrees
JITTER FREQUENCY – Hz
Figure 7. Histogram of Static Phase –40 @ 4.4 V
Figure 10. J itter Tolerance vs. Frequency
REV. 0
–6–
AD808
TH EO RY O F O P ERATIO N
Q uantizer
1
S
⌽
DATA
INPUT
S + 1
DET
⌺
T he quantizer (comparator) has three gain stages, providing a
net gain of 350. T he quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. T he input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. T he input offset
voltage is factory trimmed and is typically less than 1 mV. XFCB’s
dielectric isolation allows the different blocks within this mixed-
signal IC to be isolated from each other, hence the 4 mV Sensi-
tivity is achieved. T raditionally, high speed comparators are
plagued by crosstalk between outputs and inputs, often resulting
in oscillations when the input signal approaches 10 mV. T he
AD808 quantizer toggles at 2 mV (4.0 mV sensitivity) at the
input without making bit errors. When the input signal is low-
ered below 2 mV, circuit performance is dominated by input
noise, and not crosstalk.
VCO
F
RECOVERED CLOCK
OUTPUT
DET
RETIMING
DEVICE
RETIMED DATA
OUTPUT
Figure 12. PLL Block Diagram
T he frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
T hese pulses occur on the cycle slips between the data fre-
quency and the VCO frequency. With a maximum density data
pattern (1010 . . . ), every cycle slip will produce a pulse at the
frequency detector output. However, with random data, not
every cycle slip produces a pulse. T he density of pulses at the
frequency detector output increases with the density of data
transitions. T he probability that a cycle slip will produce a pulse
increases as the frequency error approaches zero. After the fre-
quency error has been reduced to zero, the frequency detector
output will have no further pulses. At this point the PLL begins
the process of phase acquisition, with a settling time of roughly
2000 bit periods.
Signal D etect
T he input to the signal detect circuit is taken from the first stage
of the quantizer. T he input signal is first processed through a
gain stage. T he output from the gain stage is fed to both a posi-
tive and a negative peak detector. T he threshold value is sub-
tracted from the positive peak signal and added to the negative
peak signal. T he positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT , will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
T he circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
T his means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. T his corresponds to a 3 dB optical hysteresis.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. T he jitter created by a 27–1 pseu-
dorandom code is 1/2 degree, and this is small compared to
random jitter.
T he jitter bandwidth for the PLL is 0.06% of the center fre-
quency. T his figure is chosen so that sinusoidal input jitter at
350 Hz will be attenuated by 3 dB.
T he damping ratio of the PLL is user programmable with a
single external capacitor. At 622 MHz, a damping ratio of 5 is
obtained with a 0.47 µF capacitor. More generally, the damping
THRESHOLD
AD808
BIAS
PIN
IHYS
COMPARATOR STAGES
& CLOCK RECOVERY PLL
+
ratio scales as (fDAT A × CD)1/2
.
+
NIN
ITHR
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisi-
tion time no longer scales directly with capacitor value. T he
acquisition time has two components: frequency acquisition and
phase acquisition. T he frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop band-
width of the PLL and is independent of the damping ratio. In
practice the acquisition time is dominated by the frequency
acquisition. T he fractional loop bandwidth of 0.06% should
give an acquisition time of 2000 bit periods. H owever, the
actual acquisition time is several million bit periods and is
comprised mostly of the time needed to slew the voltage on
the damping capacitor to final value.
POSITIVE
PEAK
DETECTOR
LEVEL
SHIFT
DOWN
SDOUT
NEGATIVE
PEAK
DETECTOR
LEVEL
SHIFT
UP
Figure 11. Signal Level Detect Circuit Block Diagram
P hase-Locked Loop
T he phase-locked loop recovers clock and retimes data from
NRZ data. T he architecture uses a frequency detector to aid
initial frequency acquisition; refer to Figure 12 for a block dia-
gram. Note the frequency detector is always in the circuit. When
the PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is
always in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
REV. 0
–7–
AD808
Center Fr equency Clam p (Figur e 13)
C
PEAK
D
An N-channel FET circuit can be used to bring the AD808
VCO center frequency to within ±10% of 622 MHz when
SDOUT indicates a Loss of Signal (LOS). T his effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. T he N-FET can have “on” resistance as high
as 1 kΩ and still attain effective clamping. However, the chosen
N-FET should have greater than 10 MΩ “off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
0.047
0.10
0.47
0.11
0.07
0.04
1
2
3
DATAOUTN
DATAOUTP
V
16
EE
DIV
20.00m
DIV
36.00m
START
STOP
500.000Hz
100 000.000Hz
SDOUT 15
AV 14
RBW:
30Hz ST: 3.07 min RANGE: R=
0, T=
0dBm
V
CC2
CC2
CLKOUTN
CLKOUTP
PIN 13
NIN 12
4
5
6
7
8
Figure14. J itter Transfer vs. CD
V
AV
CC1
11
10
9
CC1
N_FET
CF1
CF2
THRADJ
C
D
AV
EE
AD808
Figure 13. Center Frequency Clam p Schem atic
C1 0.1F
J5
TP7 TP8
50⍀ STRIP LINE
EQUAL LENGTH
SDOUT
R1
100⍀ 100⍀
C3 0.1F
R2
R9
154⍀
R5 100⍀
R10
154⍀
C12
0.1F
J1
DATAOUTN
DATAOUTN
VEE
1
2
3
16
15
14
R6 100⍀
DATAOUTP
SDOUT
DATAOUTP
J2
R13
R16 3.65k⍀
C4 0.1F
C5 0.1F
301⍀
R14
49.9⍀
R15
49.9⍀
AV
CC2
V
CC2
C9
J6
J7
J3
CLKOUTN
C13 0.1F
R7 100⍀
R8 100⍀
C7
C8
PIN
NIN
4
5
6
7
8
13
12
11
10
PIN
NIN
CLKOUTN
CLKOUTP
CLKOUTP
J4
C6
0.1F
C14 0.1F
AV
CC1
V
CC1
C10
TP1
TP2
VECTOR PINS SPACED FOR RN55C
TYPE RESISTOR; COMPONENT
SHOWN FOR REFERENCE ONLY
R3
R4
TP5
TP6
THRADJ
CF1
CF2
100⍀ 100⍀
CD
R
THRESH
R11
154⍀
R12
154⍀
AV
9
EE
AD808
NOTE:
C2
0.1F
NOTE: INTERCONNECT RUN
UNDER DUT
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
C11
10F
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TP3
+5V
TP4
TPx TEST POINTS ARE VECTORBOARD K24A/M PINS
o
GND
Figure 15. Evaluation Board Schem atic
–8–
REV. 0
AD808
Loop D am ping Capacitor , C D
USING TH E AD 808
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.47 µF, ± 20% capacitor provides < 0.1 dB jitter
peaking.
Acquisition Tim e
T his is the transient time, measured in bit periods, that required
for the AD808 to lock onto the input data from its free running
state.
AD 808 O utput Squelch Cir cuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure
16). T he VCC2 supply pin draws roughly 72 mA (14 mA for each
of 4 ECL loads, plus 16 mA for all 4 ECL output stages). T his
means that selection of a FET with ON RESIST ANCE of
0.5 Ω will affect the common mode of the ECL outputs by
only 36 mV.
Gr ound P lanes
T he use of one ground plane for connections to both analog and
digital grounds is recommended.
P ower Supply Connections
T he use of a 10 µF capacitor between VCC and ground is recom-
mended. T he +5 V power supply connection to VCC2 should be
carefully isolated. T he VCC2 pin is used inside the AD808 to
provide the CLKOUT and DAT AOUT signals.
TO V
, AV , AV
CC CC2
CC1
Use a 0.1 µF decoupling capacitor between IC power supply
input and ground. T his decoupling capacitor should be posi-
tioned as closed to the IC as possible. Refer to the schematic in
Figure 15 for advised connections.
5V
P_FET
1
2
3
DATAOUTN
DATAOUTP
V
16
EE
Tr ansm ission Lines
Use 50 Ω transmission line for PIN, NIN, CLKOUT , and
DAT AOUT signals.
SDOUT 15
AV
V
14
13
CC2
PIN
CC2
BYPASS
CAP
CLKOUTN
CLKOUTP
4
5
6
7
8
Ter m inations
NIN 12
Use metal, thick-film, 1% termination resistors for PIN, NIN,
CLKOUT , and DATAOUT signals. These termination resistors
must be positioned as close to the IC as possible.
V
AV
11
10
9
CC1
CC1
CF1
CF2
THRADJ
AV
EE
AD808
Use individual connections, not daisy chained, for connections
from the +5 V to load resistors for PIN, NIN, CLKOUT , and
DAT AOUT signals.
Figure 16. Squelch Circuit Schem atic
REV. 0
–9–
AD808
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead Sm all O utline IC P ackage
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
1
9
8
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
–10–
REV. 0
–11–
–12–
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